1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#ifndef ATH12K_HAL_RX_H 8#define ATH12K_HAL_RX_H 9 10struct hal_rx_wbm_rel_info { 11 u32 cookie; 12 enum hal_wbm_rel_src_module err_rel_src; 13 enum hal_reo_dest_ring_push_reason push_reason; 14 u32 err_code; 15 bool first_msdu; 16 bool last_msdu; 17 bool continuation; 18 void *rx_desc; 19 bool hw_cc_done; 20}; 21 22#define HAL_INVALID_PEERID 0xffff 23#define VHT_SIG_SU_NSS_MASK 0x7 24 25#define HAL_RX_MAX_MCS 12 26#define HAL_RX_MAX_NSS 8 27 28#define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \ 29 le32_get_bits((__val), GENMASK(7, 0)) 30 31#define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \ 32 le32_get_bits((__val), GENMASK(15, 8)) 33 34#define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \ 35 le32_get_bits((__val), GENMASK(23, 16)) 36 37#define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \ 38 le32_get_bits((__val), GENMASK(31, 24)) 39 40struct hal_rx_mon_status_tlv_hdr { 41 u32 hdr; 42 u8 value[]; 43}; 44 45enum hal_rx_su_mu_coding { 46 HAL_RX_SU_MU_CODING_BCC, 47 HAL_RX_SU_MU_CODING_LDPC, 48 HAL_RX_SU_MU_CODING_MAX, 49}; 50 51enum hal_rx_gi { 52 HAL_RX_GI_0_8_US, 53 HAL_RX_GI_0_4_US, 54 HAL_RX_GI_1_6_US, 55 HAL_RX_GI_3_2_US, 56 HAL_RX_GI_MAX, 57}; 58 59enum hal_rx_bw { 60 HAL_RX_BW_20MHZ, 61 HAL_RX_BW_40MHZ, 62 HAL_RX_BW_80MHZ, 63 HAL_RX_BW_160MHZ, 64 HAL_RX_BW_MAX, 65}; 66 67enum hal_rx_preamble { 68 HAL_RX_PREAMBLE_11A, 69 HAL_RX_PREAMBLE_11B, 70 HAL_RX_PREAMBLE_11N, 71 HAL_RX_PREAMBLE_11AC, 72 HAL_RX_PREAMBLE_11AX, 73 HAL_RX_PREAMBLE_MAX, 74}; 75 76enum hal_rx_reception_type { 77 HAL_RX_RECEPTION_TYPE_SU, 78 HAL_RX_RECEPTION_TYPE_MU_MIMO, 79 HAL_RX_RECEPTION_TYPE_MU_OFDMA, 80 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, 81 HAL_RX_RECEPTION_TYPE_MAX, 82}; 83 84enum hal_rx_legacy_rate { 85 HAL_RX_LEGACY_RATE_1_MBPS, 86 HAL_RX_LEGACY_RATE_2_MBPS, 87 HAL_RX_LEGACY_RATE_5_5_MBPS, 88 HAL_RX_LEGACY_RATE_6_MBPS, 89 HAL_RX_LEGACY_RATE_9_MBPS, 90 HAL_RX_LEGACY_RATE_11_MBPS, 91 HAL_RX_LEGACY_RATE_12_MBPS, 92 HAL_RX_LEGACY_RATE_18_MBPS, 93 HAL_RX_LEGACY_RATE_24_MBPS, 94 HAL_RX_LEGACY_RATE_36_MBPS, 95 HAL_RX_LEGACY_RATE_48_MBPS, 96 HAL_RX_LEGACY_RATE_54_MBPS, 97 HAL_RX_LEGACY_RATE_INVALID, 98}; 99 100#define HAL_TLV_STATUS_PPDU_NOT_DONE 0 101#define HAL_TLV_STATUS_PPDU_DONE 1 102#define HAL_TLV_STATUS_BUF_DONE 2 103#define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 104#define HAL_RX_FCS_LEN 4 105 106enum hal_rx_mon_status { 107 HAL_RX_MON_STATUS_PPDU_NOT_DONE, 108 HAL_RX_MON_STATUS_PPDU_DONE, 109 HAL_RX_MON_STATUS_BUF_DONE, 110}; 111 112#define HAL_RX_MAX_MPDU 256 113#define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 114 115struct hal_rx_user_status { 116 u32 mcs:4, 117 nss:3, 118 ofdma_info_valid:1, 119 ul_ofdma_ru_start_index:7, 120 ul_ofdma_ru_width:7, 121 ul_ofdma_ru_size:8; 122 u32 ul_ofdma_user_v0_word0; 123 u32 ul_ofdma_user_v0_word1; 124 u32 ast_index; 125 u32 tid; 126 u16 tcp_msdu_count; 127 u16 tcp_ack_msdu_count; 128 u16 udp_msdu_count; 129 u16 other_msdu_count; 130 u16 frame_control; 131 u8 frame_control_info_valid; 132 u8 data_sequence_control_info_valid; 133 u16 first_data_seq_ctrl; 134 u32 preamble_type; 135 u16 ht_flags; 136 u16 vht_flags; 137 u16 he_flags; 138 u8 rs_flags; 139 u8 ldpc; 140 u32 mpdu_cnt_fcs_ok; 141 u32 mpdu_cnt_fcs_err; 142 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 143 u32 mpdu_ok_byte_count; 144 u32 mpdu_err_byte_count; 145}; 146 147#define HAL_MAX_UL_MU_USERS 37 148 149struct hal_rx_mon_ppdu_info { 150 u32 ppdu_id; 151 u32 last_ppdu_id; 152 u64 ppdu_ts; 153 u32 num_mpdu_fcs_ok; 154 u32 num_mpdu_fcs_err; 155 u32 preamble_type; 156 u32 mpdu_len; 157 u16 chan_num; 158 u16 tcp_msdu_count; 159 u16 tcp_ack_msdu_count; 160 u16 udp_msdu_count; 161 u16 other_msdu_count; 162 u16 peer_id; 163 u8 rate; 164 u8 mcs; 165 u8 nss; 166 u8 bw; 167 u8 vht_flag_values1; 168 u8 vht_flag_values2; 169 u8 vht_flag_values3[4]; 170 u8 vht_flag_values4; 171 u8 vht_flag_values5; 172 u16 vht_flag_values6; 173 u8 is_stbc; 174 u8 gi; 175 u8 sgi; 176 u8 ldpc; 177 u8 beamformed; 178 u8 rssi_comb; 179 u16 tid; 180 u8 fc_valid; 181 u16 ht_flags; 182 u16 vht_flags; 183 u16 he_flags; 184 u16 he_mu_flags; 185 u8 dcm; 186 u8 ru_alloc; 187 u8 reception_type; 188 u64 tsft; 189 u64 rx_duration; 190 u16 frame_control; 191 u32 ast_index; 192 u8 rs_fcs_err; 193 u8 rs_flags; 194 u8 cck_flag; 195 u8 ofdm_flag; 196 u8 ulofdma_flag; 197 u8 frame_control_info_valid; 198 u16 he_per_user_1; 199 u16 he_per_user_2; 200 u8 he_per_user_position; 201 u8 he_per_user_known; 202 u16 he_flags1; 203 u16 he_flags2; 204 u8 he_RU[4]; 205 u16 he_data1; 206 u16 he_data2; 207 u16 he_data3; 208 u16 he_data4; 209 u16 he_data5; 210 u16 he_data6; 211 u32 ppdu_len; 212 u32 prev_ppdu_id; 213 u32 device_id; 214 u16 first_data_seq_ctrl; 215 u8 monitor_direct_used; 216 u8 data_sequence_control_info_valid; 217 u8 ltf_size; 218 u8 rxpcu_filter_pass; 219 s8 rssi_chain[8][8]; 220 u32 num_users; 221 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 222 u8 addr1[ETH_ALEN]; 223 u8 addr2[ETH_ALEN]; 224 u8 addr3[ETH_ALEN]; 225 u8 addr4[ETH_ALEN]; 226 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS]; 227 u8 userid; 228 u16 ampdu_id[HAL_MAX_UL_MU_USERS]; 229 bool first_msdu_in_mpdu; 230 bool is_ampdu; 231 u8 medium_prot_type; 232}; 233 234#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0) 235 236struct hal_rx_ppdu_start { 237 __le32 info0; 238 __le32 chan_num; 239 __le32 ppdu_start_ts; 240} __packed; 241 242#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16) 243 244#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0) 245#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9) 246#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10) 247#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11) 248#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20) 249 250#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0) 251#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16) 252 253#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16) 254 255#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0) 256#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16) 257 258#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0) 259#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16) 260 261#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0) 262#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16) 263 264#define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT GENMASK(24, 0) 265#define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT GENMASK(24, 0) 266 267struct hal_rx_ppdu_end_user_stats { 268 __le32 rsvd0[2]; 269 __le32 info0; 270 __le32 info1; 271 __le32 info2; 272 __le32 info3; 273 __le32 ht_ctrl; 274 __le32 rsvd1[2]; 275 __le32 info4; 276 __le32 info5; 277 __le32 usr_resp_ref; 278 __le32 info6; 279 __le32 rsvd3[4]; 280 __le32 mpdu_ok_cnt; 281 __le32 rsvd4; 282 __le32 mpdu_err_cnt; 283 __le32 rsvd5[2]; 284 __le32 usr_resp_ref_ext; 285 __le32 rsvd6; 286} __packed; 287 288struct hal_rx_ppdu_end_user_stats_ext { 289 __le32 info0; 290 __le32 info1; 291 __le32 info2; 292 __le32 info3; 293 __le32 info4; 294 __le32 info5; 295 __le32 info6; 296} __packed; 297 298#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0) 299#define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7) 300 301#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4) 302#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6) 303#define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7) 304 305struct hal_rx_ht_sig_info { 306 __le32 info0; 307 __le32 info1; 308} __packed; 309 310#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0) 311#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4) 312 313struct hal_rx_lsig_b_info { 314 __le32 info0; 315} __packed; 316 317#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0) 318#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5) 319#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24) 320 321struct hal_rx_lsig_a_info { 322 __le32 info0; 323} __packed; 324 325#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0) 326#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3) 327#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4) 328#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10) 329 330#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0) 331#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2) 332#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4) 333#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8) 334 335struct hal_rx_vht_sig_a_info { 336 __le32 info0; 337 __le32 info1; 338} __packed; 339 340enum hal_rx_vht_sig_a_gi_setting { 341 HAL_RX_VHT_SIG_A_NORMAL_GI = 0, 342 HAL_RX_VHT_SIG_A_SHORT_GI = 1, 343 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3, 344}; 345 346#define HE_GI_0_8 0 347#define HE_GI_0_4 1 348#define HE_GI_1_6 2 349#define HE_GI_3_2 3 350 351#define HE_LTF_1_X 0 352#define HE_LTF_2_X 1 353#define HE_LTF_4_X 2 354 355#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3) 356#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7) 357#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19) 358#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21) 359#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23) 360#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8) 361#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15) 362#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0) 363#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1) 364#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2) 365 366#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0) 367#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7) 368#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8) 369#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9) 370#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10) 371#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11) 372#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13) 373#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15) 374 375struct hal_rx_he_sig_a_su_info { 376 __le32 info0; 377 __le32 info1; 378} __packed; 379 380#define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1) 381#define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1) 382#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4) 383#define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5) 384#define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11) 385#define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15) 386#define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18) 387#define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22) 388#define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23) 389#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25) 390 391#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0) 392#define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING BIT(7) 393#define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8) 394#define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11) 395#define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12) 396#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF BIT(10) 397#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13) 398#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15) 399 400struct hal_rx_he_sig_a_mu_dl_info { 401 __le32 info0; 402 __le32 info1; 403} __packed; 404 405#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0) 406 407struct hal_rx_he_sig_b1_mu_info { 408 __le32 info0; 409} __packed; 410 411#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0) 412#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15) 413#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20) 414#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29) 415 416struct hal_rx_he_sig_b2_mu_info { 417 __le32 info0; 418} __packed; 419 420#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0) 421#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11) 422#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19) 423#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15) 424#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19) 425#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20) 426 427struct hal_rx_he_sig_b2_ofdma_info { 428 __le32 info0; 429} __packed; 430 431enum hal_rx_ul_reception_type { 432 HAL_RECEPTION_TYPE_ULOFMDA, 433 HAL_RECEPTION_TYPE_ULMIMO, 434 HAL_RECEPTION_TYPE_OTHER, 435 HAL_RECEPTION_TYPE_FRAMELESS 436}; 437 438#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8) 439#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION GENMASK(3, 0) 440 441struct hal_rx_phyrx_rssi_legacy_info { 442 __le32 rsvd[35]; 443 __le32 info0; 444} __packed; 445 446#define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) 447#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16) 448#define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) 449struct hal_rx_mpdu_start { 450 __le32 info0; 451 __le32 info1; 452 __le32 rsvd1[11]; 453 __le32 info2; 454 __le32 rsvd2[9]; 455} __packed; 456 457#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) 458struct hal_rx_ppdu_end_duration { 459 __le32 rsvd0[9]; 460 __le32 info0; 461 __le32 rsvd1[4]; 462} __packed; 463 464struct hal_rx_rxpcu_classification_overview { 465 u32 rsvd0; 466} __packed; 467 468struct hal_rx_msdu_desc_info { 469 u32 msdu_flags; 470 u16 msdu_len; /* 14 bits for length */ 471}; 472 473#define HAL_RX_NUM_MSDU_DESC 6 474struct hal_rx_msdu_list { 475 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 476 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC]; 477 u8 rbm[HAL_RX_NUM_MSDU_DESC]; 478}; 479 480#define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0) 481#define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0) 482#define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16) 483#define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0) 484 485struct hal_rx_frame_bitmap_ack { 486 __le32 reserved; 487 __le32 info0; 488 __le32 info1; 489 __le32 info2; 490 __le32 reserved1[10]; 491} __packed; 492 493#define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0) 494#define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16) 495#define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0) 496#define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21) 497#define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25) 498#define HAL_RX_RESP_REQ_INFO1_STBC BIT(27) 499#define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28) 500#define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29) 501#define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0) 502#define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0) 503#define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0) 504#define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16) 505#define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0) 506 507struct hal_rx_resp_req_info { 508 __le32 info0; 509 __le32 reserved[1]; 510 __le32 info1; 511 __le32 info2; 512 __le32 reserved1[2]; 513 __le32 info3; 514 __le32 info4; 515 __le32 info5; 516 __le32 reserved2[5]; 517} __packed; 518 519#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF 520#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF 521#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF 522#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF 523 524#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30) 525#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31) 526#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0) 527#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3) 528#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7) 529#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8) 530#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9) 531#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16) 532 533/* HE Radiotap data1 Mask */ 534#define HE_SU_FORMAT_TYPE 0x0000 535#define HE_EXT_SU_FORMAT_TYPE 0x0001 536#define HE_MU_FORMAT_TYPE 0x0002 537#define HE_TRIG_FORMAT_TYPE 0x0003 538#define HE_BEAM_CHANGE_KNOWN 0x0008 539#define HE_DL_UL_KNOWN 0x0010 540#define HE_MCS_KNOWN 0x0020 541#define HE_DCM_KNOWN 0x0040 542#define HE_CODING_KNOWN 0x0080 543#define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100 544#define HE_STBC_KNOWN 0x0200 545#define HE_DATA_BW_RU_KNOWN 0x4000 546#define HE_DOPPLER_KNOWN 0x8000 547#define HE_BSS_COLOR_KNOWN 0x0004 548 549/* HE Radiotap data2 Mask */ 550#define HE_GI_KNOWN 0x0002 551#define HE_TXBF_KNOWN 0x0010 552#define HE_PE_DISAMBIGUITY_KNOWN 0x0020 553#define HE_TXOP_KNOWN 0x0040 554#define HE_LTF_SYMBOLS_KNOWN 0x0004 555#define HE_PRE_FEC_PADDING_KNOWN 0x0008 556#define HE_MIDABLE_PERIODICITY_KNOWN 0x0080 557 558/* HE radiotap data3 shift values */ 559#define HE_BEAM_CHANGE_SHIFT 6 560#define HE_DL_UL_SHIFT 7 561#define HE_TRANSMIT_MCS_SHIFT 8 562#define HE_DCM_SHIFT 12 563#define HE_CODING_SHIFT 13 564#define HE_LDPC_EXTRA_SYMBOL_SHIFT 14 565#define HE_STBC_SHIFT 15 566 567/* HE radiotap data4 shift values */ 568#define HE_STA_ID_SHIFT 4 569 570/* HE radiotap data5 */ 571#define HE_GI_SHIFT 4 572#define HE_LTF_SIZE_SHIFT 6 573#define HE_LTF_SYM_SHIFT 8 574#define HE_TXBF_SHIFT 14 575#define HE_PE_DISAMBIGUITY_SHIFT 15 576#define HE_PRE_FEC_PAD_SHIFT 12 577 578/* HE radiotap data6 */ 579#define HE_DOPPLER_SHIFT 4 580#define HE_TXOP_SHIFT 8 581 582/* HE radiotap HE-MU flags1 */ 583#define HE_SIG_B_MCS_KNOWN 0x0010 584#define HE_SIG_B_DCM_KNOWN 0x0040 585#define HE_SIG_B_SYM_NUM_KNOWN 0x8000 586#define HE_RU_0_KNOWN 0x0100 587#define HE_RU_1_KNOWN 0x0200 588#define HE_RU_2_KNOWN 0x0400 589#define HE_RU_3_KNOWN 0x0800 590#define HE_DCM_FLAG_1_SHIFT 5 591#define HE_SPATIAL_REUSE_MU_KNOWN 0x0100 592#define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000 593 594/* HE radiotap HE-MU flags2 */ 595#define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3 596#define HE_BW_KNOWN 0x0004 597#define HE_NUM_SIG_B_SYMBOLS_SHIFT 4 598#define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100 599#define HE_NUM_SIG_B_FLAG_2_SHIFT 9 600#define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12 601#define HE_LTF_KNOWN 0x8000 602 603/* HE radiotap per_user_1 */ 604#define HE_STA_SPATIAL_SHIFT 11 605#define HE_TXBF_SHIFT 14 606#define HE_RESERVED_SET_TO_1_SHIFT 19 607#define HE_STA_CODING_SHIFT 20 608 609/* HE radiotap per_user_2 */ 610#define HE_STA_MCS_SHIFT 4 611#define HE_STA_DCM_SHIFT 5 612 613/* HE radiotap per user known */ 614#define HE_USER_FIELD_POSITION_KNOWN 0x01 615#define HE_STA_ID_PER_USER_KNOWN 0x02 616#define HE_STA_NSTS_KNOWN 0x04 617#define HE_STA_TX_BF_KNOWN 0x08 618#define HE_STA_SPATIAL_CONFIG_KNOWN 0x10 619#define HE_STA_MCS_KNOWN 0x20 620#define HE_STA_DCM_KNOWN 0x40 621#define HE_STA_CODING_KNOWN 0x80 622 623#define HAL_RX_MPDU_ERR_FCS BIT(0) 624#define HAL_RX_MPDU_ERR_DECRYPT BIT(1) 625#define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2) 626#define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3) 627#define HAL_RX_MPDU_ERR_OVERFLOW BIT(4) 628#define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5) 629#define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) 630#define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) 631 632static inline 633enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) 634{ 635 enum nl80211_he_ru_alloc ret; 636 637 switch (ru_tones) { 638 case RU_52: 639 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; 640 break; 641 case RU_106: 642 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; 643 break; 644 case RU_242: 645 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; 646 break; 647 case RU_484: 648 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; 649 break; 650 case RU_996: 651 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; 652 break; 653 case RU_26: 654 fallthrough; 655 default: 656 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; 657 break; 658 } 659 return ret; 660} 661 662void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, 663 struct hal_tlv_64_hdr *tlv, 664 struct hal_reo_status *status); 665void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, 666 struct hal_tlv_64_hdr *tlv, 667 struct hal_reo_status *status); 668void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, 669 struct hal_tlv_64_hdr *tlv, 670 struct hal_reo_status *status); 671void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, 672 struct hal_tlv_64_hdr *tlv, 673 struct hal_reo_status *status); 674void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, 675 struct hal_tlv_64_hdr *tlv, 676 struct hal_reo_status *status); 677void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, 678 struct hal_tlv_64_hdr *tlv, 679 struct hal_reo_status *status); 680void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, 681 struct hal_tlv_64_hdr *tlv, 682 struct hal_reo_status *status); 683void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, 684 u32 *msdu_cookies, 685 enum hal_rx_buf_return_buf_manager *rbm); 686void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, 687 struct hal_wbm_release_ring *dst_desc, 688 struct hal_wbm_release_ring *src_desc, 689 enum hal_wbm_rel_bm_act action); 690void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, 691 dma_addr_t paddr, u32 cookie, u8 manager); 692void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, 693 dma_addr_t *paddr, 694 u32 *cookie, u8 *rbm); 695int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, 696 struct hal_reo_dest_ring *desc, 697 dma_addr_t *paddr, u32 *desc_bank); 698int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, 699 struct hal_rx_wbm_rel_info *rel_info); 700void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, 701 struct ath12k_buffer_addr *buff_addr, 702 dma_addr_t *paddr, u32 *cookie); 703 704#endif 705