1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
6 */
7
8#ifndef _USB_H_
9#define _USB_H_
10
11/* constants */
12#define TX_URB_COUNT               32
13#define RX_URB_COUNT               32
14#define ATH10K_USB_RX_BUFFER_SIZE  4096
15
16#define ATH10K_USB_PIPE_INVALID ATH10K_USB_PIPE_MAX
17
18/* USB endpoint definitions */
19#define ATH10K_USB_EP_ADDR_APP_CTRL_IN          0x81
20#define ATH10K_USB_EP_ADDR_APP_DATA_IN          0x82
21#define ATH10K_USB_EP_ADDR_APP_DATA2_IN         0x83
22#define ATH10K_USB_EP_ADDR_APP_INT_IN           0x84
23
24#define ATH10K_USB_EP_ADDR_APP_CTRL_OUT         0x01
25#define ATH10K_USB_EP_ADDR_APP_DATA_LP_OUT      0x02
26#define ATH10K_USB_EP_ADDR_APP_DATA_MP_OUT      0x03
27#define ATH10K_USB_EP_ADDR_APP_DATA_HP_OUT      0x04
28
29/* diagnostic command definitions */
30#define ATH10K_USB_CONTROL_REQ_SEND_BMI_CMD        1
31#define ATH10K_USB_CONTROL_REQ_RECV_BMI_RESP       2
32#define ATH10K_USB_CONTROL_REQ_DIAG_CMD            3
33#define ATH10K_USB_CONTROL_REQ_DIAG_RESP           4
34
35#define ATH10K_USB_CTRL_DIAG_CC_READ               0
36#define ATH10K_USB_CTRL_DIAG_CC_WRITE              1
37
38#define ATH10K_USB_IS_BULK_EP(attr) (((attr) & 3) == 0x02)
39#define ATH10K_USB_IS_INT_EP(attr)  (((attr) & 3) == 0x03)
40#define ATH10K_USB_IS_ISOC_EP(attr) (((attr) & 3) == 0x01)
41#define ATH10K_USB_IS_DIR_IN(addr)  ((addr) & 0x80)
42
43struct ath10k_usb_ctrl_diag_cmd_write {
44	__le32 cmd;
45	__le32 address;
46	__le32 value;
47	__le32 padding;
48} __packed;
49
50struct ath10k_usb_ctrl_diag_cmd_read {
51	__le32 cmd;
52	__le32 address;
53} __packed;
54
55struct ath10k_usb_ctrl_diag_resp_read {
56	u8 value[4];
57} __packed;
58
59/* tx/rx pipes for usb */
60enum ath10k_usb_pipe_id {
61	ATH10K_USB_PIPE_TX_CTRL = 0,
62	ATH10K_USB_PIPE_TX_DATA_LP,
63	ATH10K_USB_PIPE_TX_DATA_MP,
64	ATH10K_USB_PIPE_TX_DATA_HP,
65	ATH10K_USB_PIPE_RX_CTRL,
66	ATH10K_USB_PIPE_RX_DATA,
67	ATH10K_USB_PIPE_RX_DATA2,
68	ATH10K_USB_PIPE_RX_INT,
69	ATH10K_USB_PIPE_MAX
70};
71
72struct ath10k_usb_pipe {
73	struct list_head urb_list_head;
74	struct usb_anchor urb_submitted;
75	u32 urb_alloc;
76	u32 urb_cnt;
77	u32 urb_cnt_thresh;
78	unsigned int usb_pipe_handle;
79	u32 flags;
80	u8 ep_address;
81	u8 logical_pipe_num;
82	struct ath10k_usb *ar_usb;
83	u16 max_packet_size;
84	struct work_struct io_complete_work;
85	struct sk_buff_head io_comp_queue;
86	struct usb_endpoint_descriptor *ep_desc;
87};
88
89#define ATH10K_USB_PIPE_FLAG_TX BIT(0)
90
91/* usb device object */
92struct ath10k_usb {
93	/* protects pipe->urb_list_head and  pipe->urb_cnt */
94	spinlock_t cs_lock;
95
96	struct usb_device *udev;
97	struct usb_interface *interface;
98	struct ath10k_usb_pipe pipes[ATH10K_USB_PIPE_MAX];
99	u8 *diag_cmd_buffer;
100	u8 *diag_resp_buffer;
101	struct ath10k *ar;
102};
103
104/* usb urb object */
105struct ath10k_urb_context {
106	struct list_head link;
107	struct ath10k_usb_pipe *pipe;
108	struct sk_buff *skb;
109	struct ath10k *ar;
110};
111
112static inline struct ath10k_usb *ath10k_usb_priv(struct ath10k *ar)
113{
114	return (struct ath10k_usb *)ar->drv_priv;
115}
116
117#endif
118