1// SPDX-License-Identifier: GPL-2.0+ 2/* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9#include <linux/module.h> 10#include <linux/bitfield.h> 11#include <linux/hwmon.h> 12#include <linux/mutex.h> 13#include <linux/phy.h> 14#include <linux/polynomial.h> 15#include <linux/property.h> 16#include <linux/netdevice.h> 17 18/* PHY ID */ 19#define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 20#define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 21#define PHY_ID_GPY2xx 0x67C9DC00 22#define PHY_ID_GPY115B 0x67C9DF00 23#define PHY_ID_GPY115C 0x67C9DF10 24#define PHY_ID_GPY211B 0x67C9DE08 25#define PHY_ID_GPY211C 0x67C9DE10 26#define PHY_ID_GPY212B 0x67C9DE09 27#define PHY_ID_GPY212C 0x67C9DE20 28#define PHY_ID_GPY215B 0x67C9DF04 29#define PHY_ID_GPY215C 0x67C9DF20 30#define PHY_ID_GPY241B 0x67C9DE40 31#define PHY_ID_GPY241BM 0x67C9DE80 32#define PHY_ID_GPY245B 0x67C9DEC0 33 34#define PHY_CTL1 0x13 35#define PHY_CTL1_MDICD BIT(3) 36#define PHY_CTL1_MDIAB BIT(2) 37#define PHY_CTL1_AMDIX BIT(0) 38#define PHY_MIISTAT 0x18 /* MII state */ 39#define PHY_IMASK 0x19 /* interrupt mask */ 40#define PHY_ISTAT 0x1A /* interrupt status */ 41#define PHY_FWV 0x1E /* firmware version */ 42 43#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 44#define PHY_MIISTAT_DPX BIT(3) 45#define PHY_MIISTAT_LS BIT(10) 46 47#define PHY_MIISTAT_SPD_10 0 48#define PHY_MIISTAT_SPD_100 1 49#define PHY_MIISTAT_SPD_1000 2 50#define PHY_MIISTAT_SPD_2500 4 51 52#define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 53#define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 54#define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 55#define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 56#define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 57#define PHY_IMASK_LSTC BIT(0) /* Link state change */ 58#define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 59 PHY_IMASK_LSPC | \ 60 PHY_IMASK_DXMC | \ 61 PHY_IMASK_ADSC | \ 62 PHY_IMASK_ANC) 63 64#define PHY_FWV_REL_MASK BIT(15) 65#define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 66#define PHY_FWV_MINOR_MASK GENMASK(7, 0) 67 68#define PHY_PMA_MGBT_POLARITY 0x82 69#define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 70#define PHY_MDI_MDI_X_NORMAL 0x3 71#define PHY_MDI_MDI_X_AB 0x2 72#define PHY_MDI_MDI_X_CD 0x1 73#define PHY_MDI_MDI_X_CROSS 0x0 74 75/* SGMII */ 76#define VSPEC1_SGMII_CTRL 0x08 77#define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 78#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 79#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 80 VSPEC1_SGMII_CTRL_ANRS) 81 82/* Temperature sensor */ 83#define VSPEC1_TEMP_STA 0x0E 84#define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 85 86/* Mailbox */ 87#define VSPEC1_MBOX_DATA 0x5 88#define VSPEC1_MBOX_ADDRLO 0x6 89#define VSPEC1_MBOX_CMD 0x7 90#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 91#define VSPEC1_MBOX_CMD_RD (0 << 8) 92#define VSPEC1_MBOX_CMD_READY BIT(15) 93 94/* WoL */ 95#define VPSPEC2_WOL_CTL 0x0E06 96#define VPSPEC2_WOL_AD01 0x0E08 97#define VPSPEC2_WOL_AD23 0x0E09 98#define VPSPEC2_WOL_AD45 0x0E0A 99#define WOL_EN BIT(0) 100 101/* Internal registers, access via mbox */ 102#define REG_GPIO0_OUT 0xd3ce00 103 104struct gpy_priv { 105 /* serialize mailbox acesses */ 106 struct mutex mbox_lock; 107 108 u8 fw_major; 109 u8 fw_minor; 110 111 /* It takes 3 seconds to fully switch out of loopback mode before 112 * it can safely re-enter loopback mode. Record the time when 113 * loopback is disabled. Check and wait if necessary before loopback 114 * is enabled. 115 */ 116 u64 lb_dis_to; 117}; 118 119static const struct { 120 int major; 121 int minor; 122} ver_need_sgmii_reaneg[] = { 123 {7, 0x6D}, 124 {8, 0x6D}, 125 {9, 0x73}, 126}; 127 128#if IS_ENABLED(CONFIG_HWMON) 129/* The original translation formulae of the temperature (in degrees of Celsius) 130 * are as follows: 131 * 132 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 133 * 3.0762e-1*(N^1) + -5.2156e1 134 * 135 * where [-52.156, 137.961]C and N = [0, 1023]. 136 * 137 * They must be accordingly altered to be suitable for the integer arithmetics. 138 * The technique is called 'factor redistribution', which just makes sure the 139 * multiplications and divisions are made so to have a result of the operations 140 * within the integer numbers limit. In addition we need to translate the 141 * formulae to accept millidegrees of Celsius. Here what it looks like after 142 * the alterations: 143 * 144 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 145 * 307620e-3*(N^1) + -52156 146 * 147 * where T = [-52156, 137961]mC and N = [0, 1023]. 148 */ 149static const struct polynomial poly_N_to_temp = { 150 .terms = { 151 {4, -25761, 1000, 1}, 152 {3, 97332, 1000, 1}, 153 {2, -191650, 1000, 1}, 154 {1, 307620, 1000, 1}, 155 {0, -52156, 1, 1} 156 } 157}; 158 159static int gpy_hwmon_read(struct device *dev, 160 enum hwmon_sensor_types type, 161 u32 attr, int channel, long *value) 162{ 163 struct phy_device *phydev = dev_get_drvdata(dev); 164 int ret; 165 166 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 167 if (ret < 0) 168 return ret; 169 if (!ret) 170 return -ENODATA; 171 172 *value = polynomial_calc(&poly_N_to_temp, 173 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 174 175 return 0; 176} 177 178static umode_t gpy_hwmon_is_visible(const void *data, 179 enum hwmon_sensor_types type, 180 u32 attr, int channel) 181{ 182 return 0444; 183} 184 185static const struct hwmon_channel_info * const gpy_hwmon_info[] = { 186 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 187 NULL 188}; 189 190static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 191 .is_visible = gpy_hwmon_is_visible, 192 .read = gpy_hwmon_read, 193}; 194 195static const struct hwmon_chip_info gpy_hwmon_chip_info = { 196 .ops = &gpy_hwmon_hwmon_ops, 197 .info = gpy_hwmon_info, 198}; 199 200static int gpy_hwmon_register(struct phy_device *phydev) 201{ 202 struct device *dev = &phydev->mdio.dev; 203 struct device *hwmon_dev; 204 char *hwmon_name; 205 206 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev)); 207 if (IS_ERR(hwmon_name)) 208 return PTR_ERR(hwmon_name); 209 210 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, 211 phydev, 212 &gpy_hwmon_chip_info, 213 NULL); 214 215 return PTR_ERR_OR_ZERO(hwmon_dev); 216} 217#else 218static int gpy_hwmon_register(struct phy_device *phydev) 219{ 220 return 0; 221} 222#endif 223 224static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 225{ 226 struct gpy_priv *priv = phydev->priv; 227 int val, ret; 228 u16 cmd; 229 230 mutex_lock(&priv->mbox_lock); 231 232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 233 addr); 234 if (ret) 235 goto out; 236 237 cmd = VSPEC1_MBOX_CMD_RD; 238 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 239 240 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 241 if (ret) 242 goto out; 243 244 /* The mbox read is used in the interrupt workaround. It was observed 245 * that a read might take up to 2.5ms. This is also the time for which 246 * the interrupt line is stuck low. To be on the safe side, poll the 247 * ready bit for 10ms. 248 */ 249 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 250 VSPEC1_MBOX_CMD, val, 251 (val & VSPEC1_MBOX_CMD_READY), 252 500, 10000, false); 253 if (ret) 254 goto out; 255 256 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 257 258out: 259 mutex_unlock(&priv->mbox_lock); 260 return ret; 261} 262 263static int gpy_config_init(struct phy_device *phydev) 264{ 265 int ret; 266 267 /* Mask all interrupts */ 268 ret = phy_write(phydev, PHY_IMASK, 0); 269 if (ret) 270 return ret; 271 272 /* Clear all pending interrupts */ 273 ret = phy_read(phydev, PHY_ISTAT); 274 return ret < 0 ? ret : 0; 275} 276 277static int gpy_probe(struct phy_device *phydev) 278{ 279 struct device *dev = &phydev->mdio.dev; 280 struct gpy_priv *priv; 281 int fw_version; 282 int ret; 283 284 if (!phydev->is_c45) { 285 ret = phy_get_c45_ids(phydev); 286 if (ret < 0) 287 return ret; 288 } 289 290 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 291 if (!priv) 292 return -ENOMEM; 293 phydev->priv = priv; 294 mutex_init(&priv->mbox_lock); 295 296 if (!device_property_present(dev, "maxlinear,use-broken-interrupts")) 297 phydev->dev_flags |= PHY_F_NO_IRQ; 298 299 fw_version = phy_read(phydev, PHY_FWV); 300 if (fw_version < 0) 301 return fw_version; 302 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 303 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 304 305 ret = gpy_hwmon_register(phydev); 306 if (ret) 307 return ret; 308 309 /* Show GPY PHY FW version in dmesg */ 310 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 311 priv->fw_major, priv->fw_minor, fw_version, 312 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 313 314 return 0; 315} 316 317static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 318{ 319 struct gpy_priv *priv = phydev->priv; 320 size_t i; 321 322 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 323 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 324 continue; 325 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 326 return true; 327 break; 328 } 329 330 return false; 331} 332 333static bool gpy_2500basex_chk(struct phy_device *phydev) 334{ 335 int ret; 336 337 ret = phy_read(phydev, PHY_MIISTAT); 338 if (ret < 0) { 339 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 340 ret); 341 return false; 342 } 343 344 if (!(ret & PHY_MIISTAT_LS) || 345 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 346 return false; 347 348 phydev->speed = SPEED_2500; 349 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 350 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 351 VSPEC1_SGMII_CTRL_ANEN, 0); 352 return true; 353} 354 355static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 356{ 357 int ret; 358 359 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 360 if (ret < 0) { 361 phydev_err(phydev, "Error: MMD register access failed: %d\n", 362 ret); 363 return true; 364 } 365 366 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 367} 368 369static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 370{ 371 int ret; 372 u16 val; 373 374 switch (ctrl) { 375 case ETH_TP_MDI_AUTO: 376 val = PHY_CTL1_AMDIX; 377 break; 378 case ETH_TP_MDI_X: 379 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 380 break; 381 case ETH_TP_MDI: 382 val = 0; 383 break; 384 default: 385 return 0; 386 } 387 388 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 389 PHY_CTL1_MDICD, val); 390 if (ret < 0) 391 return ret; 392 393 return genphy_c45_restart_aneg(phydev); 394} 395 396static int gpy_config_aneg(struct phy_device *phydev) 397{ 398 bool changed = false; 399 u32 adv; 400 int ret; 401 402 if (phydev->autoneg == AUTONEG_DISABLE) { 403 /* Configure half duplex with genphy_setup_forced, 404 * because genphy_c45_pma_setup_forced does not support. 405 */ 406 return phydev->duplex != DUPLEX_FULL 407 ? genphy_setup_forced(phydev) 408 : genphy_c45_pma_setup_forced(phydev); 409 } 410 411 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 412 if (ret < 0) 413 return ret; 414 415 ret = genphy_c45_an_config_aneg(phydev); 416 if (ret < 0) 417 return ret; 418 if (ret > 0) 419 changed = true; 420 421 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 422 ret = phy_modify_changed(phydev, MII_CTRL1000, 423 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 424 adv); 425 if (ret < 0) 426 return ret; 427 if (ret > 0) 428 changed = true; 429 430 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 431 if (ret < 0) 432 return ret; 433 434 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 435 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 436 return 0; 437 438 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 439 * disabled. 440 */ 441 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 442 !gpy_sgmii_aneg_en(phydev)) 443 return 0; 444 445 /* There is a design constraint in GPY2xx device where SGMII AN is 446 * only triggered when there is change of speed. If, PHY link 447 * partner`s speed is still same even after PHY TPI is down and up 448 * again, SGMII AN is not triggered and hence no new in-band message 449 * from GPY to MAC side SGMII. 450 * This could cause an issue during power up, when PHY is up prior to 451 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 452 * wouldn`t receive new in-band message from GPY with correct link 453 * status, speed and duplex info. 454 * 455 * 1) If PHY is already up and TPI link status is still down (such as 456 * hard reboot), TPI link status is polled for 4 seconds before 457 * retriggerring SGMII AN. 458 * 2) If PHY is already up and TPI link status is also up (such as soft 459 * reboot), polling of TPI link status is not needed and SGMII AN is 460 * immediately retriggered. 461 * 3) Other conditions such as PHY is down, speed change etc, skip 462 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 463 * initiate SGMII AN. 464 */ 465 466 if (phydev->state != PHY_UP) 467 return 0; 468 469 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 470 20000, 4000000, false); 471 if (ret == -ETIMEDOUT) 472 return 0; 473 else if (ret < 0) 474 return ret; 475 476 /* Trigger SGMII AN. */ 477 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 478 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 479} 480 481static int gpy_update_mdix(struct phy_device *phydev) 482{ 483 int ret; 484 485 ret = phy_read(phydev, PHY_CTL1); 486 if (ret < 0) 487 return ret; 488 489 if (ret & PHY_CTL1_AMDIX) 490 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 491 else 492 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 493 phydev->mdix_ctrl = ETH_TP_MDI_X; 494 else 495 phydev->mdix_ctrl = ETH_TP_MDI; 496 497 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 498 if (ret < 0) 499 return ret; 500 501 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 502 phydev->mdix = ETH_TP_MDI_X; 503 else 504 phydev->mdix = ETH_TP_MDI; 505 506 return 0; 507} 508 509static int gpy_update_interface(struct phy_device *phydev) 510{ 511 int ret; 512 513 /* Interface mode is fixed for USXGMII and integrated PHY */ 514 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 515 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 516 return -EINVAL; 517 518 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 519 * according to speed. Disable ANEG in 2500-BaseX mode. 520 */ 521 switch (phydev->speed) { 522 case SPEED_2500: 523 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 524 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 525 VSPEC1_SGMII_CTRL_ANEN, 0); 526 if (ret < 0) { 527 phydev_err(phydev, 528 "Error: Disable of SGMII ANEG failed: %d\n", 529 ret); 530 return ret; 531 } 532 break; 533 case SPEED_1000: 534 case SPEED_100: 535 case SPEED_10: 536 phydev->interface = PHY_INTERFACE_MODE_SGMII; 537 if (gpy_sgmii_aneg_en(phydev)) 538 break; 539 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 540 * if ANEG is disabled (in 2500-BaseX mode). 541 */ 542 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 543 VSPEC1_SGMII_ANEN_ANRS, 544 VSPEC1_SGMII_ANEN_ANRS); 545 if (ret < 0) { 546 phydev_err(phydev, 547 "Error: Enable of SGMII ANEG failed: %d\n", 548 ret); 549 return ret; 550 } 551 break; 552 } 553 554 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 555 ret = genphy_read_master_slave(phydev); 556 if (ret < 0) 557 return ret; 558 } 559 560 return gpy_update_mdix(phydev); 561} 562 563static int gpy_read_status(struct phy_device *phydev) 564{ 565 int ret; 566 567 ret = genphy_update_link(phydev); 568 if (ret) 569 return ret; 570 571 phydev->speed = SPEED_UNKNOWN; 572 phydev->duplex = DUPLEX_UNKNOWN; 573 phydev->pause = 0; 574 phydev->asym_pause = 0; 575 576 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 577 ret = genphy_c45_read_lpa(phydev); 578 if (ret < 0) 579 return ret; 580 581 /* Read the link partner's 1G advertisement */ 582 ret = phy_read(phydev, MII_STAT1000); 583 if (ret < 0) 584 return ret; 585 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 586 } else if (phydev->autoneg == AUTONEG_DISABLE) { 587 linkmode_zero(phydev->lp_advertising); 588 } 589 590 ret = phy_read(phydev, PHY_MIISTAT); 591 if (ret < 0) 592 return ret; 593 594 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 595 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 596 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 597 case PHY_MIISTAT_SPD_10: 598 phydev->speed = SPEED_10; 599 break; 600 case PHY_MIISTAT_SPD_100: 601 phydev->speed = SPEED_100; 602 break; 603 case PHY_MIISTAT_SPD_1000: 604 phydev->speed = SPEED_1000; 605 break; 606 case PHY_MIISTAT_SPD_2500: 607 phydev->speed = SPEED_2500; 608 break; 609 } 610 611 if (phydev->link) { 612 ret = gpy_update_interface(phydev); 613 if (ret < 0) 614 return ret; 615 } 616 617 return 0; 618} 619 620static int gpy_config_intr(struct phy_device *phydev) 621{ 622 u16 mask = 0; 623 624 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 625 mask = PHY_IMASK_MASK; 626 627 return phy_write(phydev, PHY_IMASK, mask); 628} 629 630static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 631{ 632 int reg; 633 634 reg = phy_read(phydev, PHY_ISTAT); 635 if (reg < 0) { 636 phy_error(phydev); 637 return IRQ_NONE; 638 } 639 640 if (!(reg & PHY_IMASK_MASK)) 641 return IRQ_NONE; 642 643 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 644 * is read. To avoid interrupt storms, delay the interrupt handling as 645 * long as the PHY drives the interrupt line. An internal bus read will 646 * stall as long as the interrupt line is asserted, thus just read a 647 * random register here. 648 * Because we cannot access the internal bus at all while the interrupt 649 * is driven by the PHY, there is no way to make the interrupt line 650 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 651 * frame. Therefore, polling is the best we can do and won't do any more 652 * harm. 653 * It was observed that this bug happens on link state and link speed 654 * changes independent of the firmware version. 655 */ 656 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { 657 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 658 if (reg < 0) { 659 phy_error(phydev); 660 return IRQ_NONE; 661 } 662 } 663 664 phy_trigger_machine(phydev); 665 666 return IRQ_HANDLED; 667} 668 669static int gpy_set_wol(struct phy_device *phydev, 670 struct ethtool_wolinfo *wol) 671{ 672 struct net_device *attach_dev = phydev->attached_dev; 673 int ret; 674 675 if (wol->wolopts & WAKE_MAGIC) { 676 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 677 * VPSPEC2_WOL_AD45 = Byte0:Byte1 678 * VPSPEC2_WOL_AD23 = Byte2:Byte3 679 * VPSPEC2_WOL_AD01 = Byte4:Byte5 680 */ 681 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 682 VPSPEC2_WOL_AD45, 683 ((attach_dev->dev_addr[0] << 8) | 684 attach_dev->dev_addr[1])); 685 if (ret < 0) 686 return ret; 687 688 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 689 VPSPEC2_WOL_AD23, 690 ((attach_dev->dev_addr[2] << 8) | 691 attach_dev->dev_addr[3])); 692 if (ret < 0) 693 return ret; 694 695 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 696 VPSPEC2_WOL_AD01, 697 ((attach_dev->dev_addr[4] << 8) | 698 attach_dev->dev_addr[5])); 699 if (ret < 0) 700 return ret; 701 702 /* Enable the WOL interrupt */ 703 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 704 if (ret < 0) 705 return ret; 706 707 /* Enable magic packet matching */ 708 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 709 VPSPEC2_WOL_CTL, 710 WOL_EN); 711 if (ret < 0) 712 return ret; 713 714 /* Clear the interrupt status register. 715 * Only WoL is enabled so clear all. 716 */ 717 ret = phy_read(phydev, PHY_ISTAT); 718 if (ret < 0) 719 return ret; 720 } else { 721 /* Disable magic packet matching */ 722 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 723 VPSPEC2_WOL_CTL, 724 WOL_EN); 725 if (ret < 0) 726 return ret; 727 } 728 729 if (wol->wolopts & WAKE_PHY) { 730 /* Enable the link state change interrupt */ 731 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 732 if (ret < 0) 733 return ret; 734 735 /* Clear the interrupt status register */ 736 ret = phy_read(phydev, PHY_ISTAT); 737 if (ret < 0) 738 return ret; 739 740 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 741 phy_trigger_machine(phydev); 742 743 return 0; 744 } 745 746 /* Disable the link state change interrupt */ 747 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 748} 749 750static void gpy_get_wol(struct phy_device *phydev, 751 struct ethtool_wolinfo *wol) 752{ 753 int ret; 754 755 wol->supported = WAKE_MAGIC | WAKE_PHY; 756 wol->wolopts = 0; 757 758 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); 759 if (ret & WOL_EN) 760 wol->wolopts |= WAKE_MAGIC; 761 762 ret = phy_read(phydev, PHY_IMASK); 763 if (ret & PHY_IMASK_LSTC) 764 wol->wolopts |= WAKE_PHY; 765} 766 767static int gpy_loopback(struct phy_device *phydev, bool enable) 768{ 769 struct gpy_priv *priv = phydev->priv; 770 u16 set = 0; 771 int ret; 772 773 if (enable) { 774 u64 now = get_jiffies_64(); 775 776 /* wait until 3 seconds from last disable */ 777 if (time_before64(now, priv->lb_dis_to)) 778 msleep(jiffies64_to_msecs(priv->lb_dis_to - now)); 779 780 set = BMCR_LOOPBACK; 781 } 782 783 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); 784 if (ret <= 0) 785 return ret; 786 787 if (enable) { 788 /* It takes some time for PHY device to switch into 789 * loopback mode. 790 */ 791 msleep(100); 792 } else { 793 priv->lb_dis_to = get_jiffies_64() + HZ * 3; 794 } 795 796 return 0; 797} 798 799static int gpy115_loopback(struct phy_device *phydev, bool enable) 800{ 801 struct gpy_priv *priv = phydev->priv; 802 803 if (enable) 804 return gpy_loopback(phydev, enable); 805 806 if (priv->fw_minor > 0x76) 807 return gpy_loopback(phydev, 0); 808 809 return genphy_soft_reset(phydev); 810} 811 812static struct phy_driver gpy_drivers[] = { 813 { 814 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 815 .name = "Maxlinear Ethernet GPY2xx", 816 .get_features = genphy_c45_pma_read_abilities, 817 .config_init = gpy_config_init, 818 .probe = gpy_probe, 819 .suspend = genphy_suspend, 820 .resume = genphy_resume, 821 .config_aneg = gpy_config_aneg, 822 .aneg_done = genphy_c45_aneg_done, 823 .read_status = gpy_read_status, 824 .config_intr = gpy_config_intr, 825 .handle_interrupt = gpy_handle_interrupt, 826 .set_wol = gpy_set_wol, 827 .get_wol = gpy_get_wol, 828 .set_loopback = gpy_loopback, 829 }, 830 { 831 .phy_id = PHY_ID_GPY115B, 832 .phy_id_mask = PHY_ID_GPYx15B_MASK, 833 .name = "Maxlinear Ethernet GPY115B", 834 .get_features = genphy_c45_pma_read_abilities, 835 .config_init = gpy_config_init, 836 .probe = gpy_probe, 837 .suspend = genphy_suspend, 838 .resume = genphy_resume, 839 .config_aneg = gpy_config_aneg, 840 .aneg_done = genphy_c45_aneg_done, 841 .read_status = gpy_read_status, 842 .config_intr = gpy_config_intr, 843 .handle_interrupt = gpy_handle_interrupt, 844 .set_wol = gpy_set_wol, 845 .get_wol = gpy_get_wol, 846 .set_loopback = gpy115_loopback, 847 }, 848 { 849 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 850 .name = "Maxlinear Ethernet GPY115C", 851 .get_features = genphy_c45_pma_read_abilities, 852 .config_init = gpy_config_init, 853 .probe = gpy_probe, 854 .suspend = genphy_suspend, 855 .resume = genphy_resume, 856 .config_aneg = gpy_config_aneg, 857 .aneg_done = genphy_c45_aneg_done, 858 .read_status = gpy_read_status, 859 .config_intr = gpy_config_intr, 860 .handle_interrupt = gpy_handle_interrupt, 861 .set_wol = gpy_set_wol, 862 .get_wol = gpy_get_wol, 863 .set_loopback = gpy115_loopback, 864 }, 865 { 866 .phy_id = PHY_ID_GPY211B, 867 .phy_id_mask = PHY_ID_GPY21xB_MASK, 868 .name = "Maxlinear Ethernet GPY211B", 869 .get_features = genphy_c45_pma_read_abilities, 870 .config_init = gpy_config_init, 871 .probe = gpy_probe, 872 .suspend = genphy_suspend, 873 .resume = genphy_resume, 874 .config_aneg = gpy_config_aneg, 875 .aneg_done = genphy_c45_aneg_done, 876 .read_status = gpy_read_status, 877 .config_intr = gpy_config_intr, 878 .handle_interrupt = gpy_handle_interrupt, 879 .set_wol = gpy_set_wol, 880 .get_wol = gpy_get_wol, 881 .set_loopback = gpy_loopback, 882 }, 883 { 884 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 885 .name = "Maxlinear Ethernet GPY211C", 886 .get_features = genphy_c45_pma_read_abilities, 887 .config_init = gpy_config_init, 888 .probe = gpy_probe, 889 .suspend = genphy_suspend, 890 .resume = genphy_resume, 891 .config_aneg = gpy_config_aneg, 892 .aneg_done = genphy_c45_aneg_done, 893 .read_status = gpy_read_status, 894 .config_intr = gpy_config_intr, 895 .handle_interrupt = gpy_handle_interrupt, 896 .set_wol = gpy_set_wol, 897 .get_wol = gpy_get_wol, 898 .set_loopback = gpy_loopback, 899 }, 900 { 901 .phy_id = PHY_ID_GPY212B, 902 .phy_id_mask = PHY_ID_GPY21xB_MASK, 903 .name = "Maxlinear Ethernet GPY212B", 904 .get_features = genphy_c45_pma_read_abilities, 905 .config_init = gpy_config_init, 906 .probe = gpy_probe, 907 .suspend = genphy_suspend, 908 .resume = genphy_resume, 909 .config_aneg = gpy_config_aneg, 910 .aneg_done = genphy_c45_aneg_done, 911 .read_status = gpy_read_status, 912 .config_intr = gpy_config_intr, 913 .handle_interrupt = gpy_handle_interrupt, 914 .set_wol = gpy_set_wol, 915 .get_wol = gpy_get_wol, 916 .set_loopback = gpy_loopback, 917 }, 918 { 919 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 920 .name = "Maxlinear Ethernet GPY212C", 921 .get_features = genphy_c45_pma_read_abilities, 922 .config_init = gpy_config_init, 923 .probe = gpy_probe, 924 .suspend = genphy_suspend, 925 .resume = genphy_resume, 926 .config_aneg = gpy_config_aneg, 927 .aneg_done = genphy_c45_aneg_done, 928 .read_status = gpy_read_status, 929 .config_intr = gpy_config_intr, 930 .handle_interrupt = gpy_handle_interrupt, 931 .set_wol = gpy_set_wol, 932 .get_wol = gpy_get_wol, 933 .set_loopback = gpy_loopback, 934 }, 935 { 936 .phy_id = PHY_ID_GPY215B, 937 .phy_id_mask = PHY_ID_GPYx15B_MASK, 938 .name = "Maxlinear Ethernet GPY215B", 939 .get_features = genphy_c45_pma_read_abilities, 940 .config_init = gpy_config_init, 941 .probe = gpy_probe, 942 .suspend = genphy_suspend, 943 .resume = genphy_resume, 944 .config_aneg = gpy_config_aneg, 945 .aneg_done = genphy_c45_aneg_done, 946 .read_status = gpy_read_status, 947 .config_intr = gpy_config_intr, 948 .handle_interrupt = gpy_handle_interrupt, 949 .set_wol = gpy_set_wol, 950 .get_wol = gpy_get_wol, 951 .set_loopback = gpy_loopback, 952 }, 953 { 954 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 955 .name = "Maxlinear Ethernet GPY215C", 956 .get_features = genphy_c45_pma_read_abilities, 957 .config_init = gpy_config_init, 958 .probe = gpy_probe, 959 .suspend = genphy_suspend, 960 .resume = genphy_resume, 961 .config_aneg = gpy_config_aneg, 962 .aneg_done = genphy_c45_aneg_done, 963 .read_status = gpy_read_status, 964 .config_intr = gpy_config_intr, 965 .handle_interrupt = gpy_handle_interrupt, 966 .set_wol = gpy_set_wol, 967 .get_wol = gpy_get_wol, 968 .set_loopback = gpy_loopback, 969 }, 970 { 971 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 972 .name = "Maxlinear Ethernet GPY241B", 973 .get_features = genphy_c45_pma_read_abilities, 974 .config_init = gpy_config_init, 975 .probe = gpy_probe, 976 .suspend = genphy_suspend, 977 .resume = genphy_resume, 978 .config_aneg = gpy_config_aneg, 979 .aneg_done = genphy_c45_aneg_done, 980 .read_status = gpy_read_status, 981 .config_intr = gpy_config_intr, 982 .handle_interrupt = gpy_handle_interrupt, 983 .set_wol = gpy_set_wol, 984 .get_wol = gpy_get_wol, 985 .set_loopback = gpy_loopback, 986 }, 987 { 988 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 989 .name = "Maxlinear Ethernet GPY241BM", 990 .get_features = genphy_c45_pma_read_abilities, 991 .config_init = gpy_config_init, 992 .probe = gpy_probe, 993 .suspend = genphy_suspend, 994 .resume = genphy_resume, 995 .config_aneg = gpy_config_aneg, 996 .aneg_done = genphy_c45_aneg_done, 997 .read_status = gpy_read_status, 998 .config_intr = gpy_config_intr, 999 .handle_interrupt = gpy_handle_interrupt, 1000 .set_wol = gpy_set_wol, 1001 .get_wol = gpy_get_wol, 1002 .set_loopback = gpy_loopback, 1003 }, 1004 { 1005 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 1006 .name = "Maxlinear Ethernet GPY245B", 1007 .get_features = genphy_c45_pma_read_abilities, 1008 .config_init = gpy_config_init, 1009 .probe = gpy_probe, 1010 .suspend = genphy_suspend, 1011 .resume = genphy_resume, 1012 .config_aneg = gpy_config_aneg, 1013 .aneg_done = genphy_c45_aneg_done, 1014 .read_status = gpy_read_status, 1015 .config_intr = gpy_config_intr, 1016 .handle_interrupt = gpy_handle_interrupt, 1017 .set_wol = gpy_set_wol, 1018 .get_wol = gpy_get_wol, 1019 .set_loopback = gpy_loopback, 1020 }, 1021}; 1022module_phy_driver(gpy_drivers); 1023 1024static struct mdio_device_id __maybe_unused gpy_tbl[] = { 1025 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1026 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1027 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1028 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1029 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1030 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1031 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1032 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1033 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1034 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1035 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1036 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1037 { } 1038}; 1039MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1040 1041MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1042MODULE_AUTHOR("Xu Liang"); 1043MODULE_LICENSE("GPL"); 1044