1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2022 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../ipa.h"
8#include "../ipa_reg.h"
9
10static const u32 reg_comp_cfg_fmask[] = {
11	[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS]		= BIT(0),
12	[GSI_SNOC_BYPASS_DIS]				= BIT(1),
13	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),
14	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),
15						/* Bit 4 reserved */
16	[IPA_QMB_SELECT_CONS_EN]			= BIT(5),
17	[IPA_QMB_SELECT_PROD_EN]			= BIT(6),
18	[GSI_MULTI_INORDER_RD_DIS]			= BIT(7),
19	[GSI_MULTI_INORDER_WR_DIS]			= BIT(8),
20	[GEN_QMB_0_MULTI_INORDER_RD_DIS]		= BIT(9),
21	[GEN_QMB_1_MULTI_INORDER_RD_DIS]		= BIT(10),
22	[GEN_QMB_0_MULTI_INORDER_WR_DIS]		= BIT(11),
23	[GEN_QMB_1_MULTI_INORDER_WR_DIS]		= BIT(12),
24	[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS]		= BIT(13),
25	[GSI_SNOC_CNOC_LOOP_PROT_DISABLE]		= BIT(14),
26	[GSI_MULTI_AXI_MASTERS_DIS]			= BIT(15),
27	[IPA_QMB_SELECT_GLOBAL_EN]			= BIT(16),
28	[FULL_FLUSH_WAIT_RS_CLOSURE_EN]			= BIT(17),
29						/* Bit 18 reserved */
30	[QMB_RAM_RD_CACHE_DISABLE]			= BIT(19),
31	[GENQMB_AOOOWR]					= BIT(20),
32	[IF_OUT_OF_BUF_STOP_RESET_MASK_EN]		= BIT(21),
33	[ATOMIC_FETCHER_ARB_LOCK_DIS]			= GENMASK(23, 22),
34						/* Bits 24-29 reserved */
35	[GEN_QMB_1_DYNAMIC_ASIZE]			= BIT(30),
36	[GEN_QMB_0_DYNAMIC_ASIZE]			= BIT(31),
37};
38
39REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
40
41static const u32 reg_clkon_cfg_fmask[] = {
42	[CLKON_RX]					= BIT(0),
43	[CLKON_PROC]					= BIT(1),
44	[TX_WRAPPER]					= BIT(2),
45	[CLKON_MISC]					= BIT(3),
46	[RAM_ARB]					= BIT(4),
47	[FTCH_HPS]					= BIT(5),
48	[FTCH_DPS]					= BIT(6),
49	[CLKON_HPS]					= BIT(7),
50	[CLKON_DPS]					= BIT(8),
51	[RX_HPS_CMDQS]					= BIT(9),
52	[HPS_DPS_CMDQS]					= BIT(10),
53	[DPS_TX_CMDQS]					= BIT(11),
54	[RSRC_MNGR]					= BIT(12),
55	[CTX_HANDLER]					= BIT(13),
56	[ACK_MNGR]					= BIT(14),
57	[D_DCPH]					= BIT(15),
58	[H_DCPH]					= BIT(16),
59						/* Bit 17 reserved */
60	[NTF_TX_CMDQS]					= BIT(18),
61	[CLKON_TX_0]					= BIT(19),
62	[CLKON_TX_1]					= BIT(20),
63	[CLKON_FNR]					= BIT(21),
64	[QSB2AXI_CMDQ_L]				= BIT(22),
65	[AGGR_WRAPPER]					= BIT(23),
66	[RAM_SLAVEWAY]					= BIT(24),
67	[CLKON_QMB]					= BIT(25),
68	[WEIGHT_ARB]					= BIT(26),
69	[GSI_IF]					= BIT(27),
70	[CLKON_GLOBAL]					= BIT(28),
71	[GLOBAL_2X_CLK]					= BIT(29),
72	[DPL_FIFO]					= BIT(30),
73	[DRBIP]						= BIT(31),
74};
75
76REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
77
78static const u32 reg_route_fmask[] = {
79	[ROUTE_DIS]					= BIT(0),
80	[ROUTE_DEF_PIPE]				= GENMASK(5, 1),
81	[ROUTE_DEF_HDR_TABLE]				= BIT(6),
82	[ROUTE_DEF_HDR_OFST]				= GENMASK(16, 7),
83	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(21, 17),
84						/* Bits 22-23 reserved */
85	[ROUTE_DEF_RETAIN_HDR]				= BIT(24),
86						/* Bits 25-31 reserved */
87};
88
89REG_FIELDS(ROUTE, route, 0x00000048);
90
91static const u32 reg_shared_mem_size_fmask[] = {
92	[MEM_SIZE]					= GENMASK(15, 0),
93	[MEM_BADDR]					= GENMASK(31, 16),
94};
95
96REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
97
98static const u32 reg_qsb_max_writes_fmask[] = {
99	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
100	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
101						/* Bits 8-31 reserved */
102};
103
104REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
105
106static const u32 reg_qsb_max_reads_fmask[] = {
107	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
108	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
109						/* Bits 8-15 reserved */
110	[GEN_QMB_0_MAX_READS_BEATS]			= GENMASK(23, 16),
111	[GEN_QMB_1_MAX_READS_BEATS]			= GENMASK(31, 24),
112};
113
114REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
115
116static const u32 reg_filt_rout_hash_en_fmask[] = {
117	[IPV6_ROUTER_HASH]				= BIT(0),
118						/* Bits 1-3 reserved */
119	[IPV6_FILTER_HASH]				= BIT(4),
120						/* Bits 5-7 reserved */
121	[IPV4_ROUTER_HASH]				= BIT(8),
122						/* Bits 9-11 reserved */
123	[IPV4_FILTER_HASH]				= BIT(12),
124						/* Bits 13-31 reserved */
125};
126
127REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
128
129static const u32 reg_filt_rout_hash_flush_fmask[] = {
130	[IPV6_ROUTER_HASH]				= BIT(0),
131						/* Bits 1-3 reserved */
132	[IPV6_FILTER_HASH]				= BIT(4),
133						/* Bits 5-7 reserved */
134	[IPV4_ROUTER_HASH]				= BIT(8),
135						/* Bits 9-11 reserved */
136	[IPV4_FILTER_HASH]				= BIT(12),
137						/* Bits 13-31 reserved */
138};
139
140REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
141
142/* Valid bits defined by ipa->available */
143REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
144
145static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
146	[IPA_BASE_ADDR]					= GENMASK(17, 0),
147						/* Bits 18-31 reserved */
148};
149
150/* Offset must be a multiple of 8 */
151REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
152
153/* Valid bits defined by ipa->available */
154REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
155
156static const u32 reg_ipa_tx_cfg_fmask[] = {
157						/* Bits 0-1 reserved */
158	[PREFETCH_ALMOST_EMPTY_SIZE_TX0]		= GENMASK(5, 2),
159	[DMAW_SCND_OUTSD_PRED_THRESHOLD]		= GENMASK(9, 6),
160	[DMAW_SCND_OUTSD_PRED_EN]			= BIT(10),
161	[DMAW_MAX_BEATS_256_DIS]			= BIT(11),
162	[PA_MASK_EN]					= BIT(12),
163	[PREFETCH_ALMOST_EMPTY_SIZE_TX1]		= GENMASK(16, 13),
164	[DUAL_TX_ENABLE]				= BIT(17),
165	[SSPND_PA_NO_START_STATE]			= BIT(18),
166						/* Bits 19-31 reserved */
167};
168
169REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
170
171static const u32 reg_flavor_0_fmask[] = {
172	[MAX_PIPES]					= GENMASK(4, 0),
173						/* Bits 5-7 reserved */
174	[MAX_CONS_PIPES]				= GENMASK(12, 8),
175						/* Bits 13-15 reserved */
176	[MAX_PROD_PIPES]				= GENMASK(20, 16),
177						/* Bits 21-23 reserved */
178	[PROD_LOWEST]					= GENMASK(27, 24),
179						/* Bits 28-31 reserved */
180};
181
182REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
183
184static const u32 reg_idle_indication_cfg_fmask[] = {
185	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
186	[CONST_NON_IDLE_ENABLE]				= BIT(16),
187						/* Bits 17-31 reserved */
188};
189
190REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
191
192static const u32 reg_qtime_timestamp_cfg_fmask[] = {
193	[DPL_TIMESTAMP_LSB]				= GENMASK(4, 0),
194						/* Bits 5-6 reserved */
195	[DPL_TIMESTAMP_SEL]				= BIT(7),
196	[TAG_TIMESTAMP_LSB]				= GENMASK(12, 8),
197						/* Bits 13-15 reserved */
198	[NAT_TIMESTAMP_LSB]				= GENMASK(20, 16),
199						/* Bits 21-31 reserved */
200};
201
202REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
203
204static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
205	[DIV_VALUE]					= GENMASK(8, 0),
206						/* Bits 9-30 reserved */
207	[DIV_ENABLE]					= BIT(31),
208};
209
210REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
211
212static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
213	[PULSE_GRAN_0]					= GENMASK(2, 0),
214	[PULSE_GRAN_1]					= GENMASK(5, 3),
215	[PULSE_GRAN_2]					= GENMASK(8, 6),
216						/* Bits 9-31 reserved */
217};
218
219REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
220
221static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
222	[X_MIN_LIM]					= GENMASK(5, 0),
223						/* Bits 6-7 reserved */
224	[X_MAX_LIM]					= GENMASK(13, 8),
225						/* Bits 14-15 reserved */
226	[Y_MIN_LIM]					= GENMASK(21, 16),
227						/* Bits 22-23 reserved */
228	[Y_MAX_LIM]					= GENMASK(29, 24),
229						/* Bits 30-31 reserved */
230};
231
232REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
233		  0x00000400, 0x0020);
234
235static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
236	[X_MIN_LIM]					= GENMASK(5, 0),
237						/* Bits 6-7 reserved */
238	[X_MAX_LIM]					= GENMASK(13, 8),
239						/* Bits 14-15 reserved */
240	[Y_MIN_LIM]					= GENMASK(21, 16),
241						/* Bits 22-23 reserved */
242	[Y_MAX_LIM]					= GENMASK(29, 24),
243						/* Bits 30-31 reserved */
244};
245
246REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
247		  0x00000404, 0x0020);
248
249static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
250	[X_MIN_LIM]					= GENMASK(5, 0),
251						/* Bits 6-7 reserved */
252	[X_MAX_LIM]					= GENMASK(13, 8),
253						/* Bits 14-15 reserved */
254	[Y_MIN_LIM]					= GENMASK(21, 16),
255						/* Bits 22-23 reserved */
256	[Y_MAX_LIM]					= GENMASK(29, 24),
257						/* Bits 30-31 reserved */
258};
259
260REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
261		  0x00000500, 0x0020);
262
263static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
264	[X_MIN_LIM]					= GENMASK(5, 0),
265						/* Bits 6-7 reserved */
266	[X_MAX_LIM]					= GENMASK(13, 8),
267						/* Bits 14-15 reserved */
268	[Y_MIN_LIM]					= GENMASK(21, 16),
269						/* Bits 22-23 reserved */
270	[Y_MAX_LIM]					= GENMASK(29, 24),
271						/* Bits 30-31 reserved */
272};
273
274REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
275		  0x00000504, 0x0020);
276
277static const u32 reg_endp_init_cfg_fmask[] = {
278	[FRAG_OFFLOAD_EN]				= BIT(0),
279	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
280	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
281						/* Bit 7 reserved */
282	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
283						/* Bits 9-31 reserved */
284};
285
286REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
287
288static const u32 reg_endp_init_nat_fmask[] = {
289	[NAT_EN]					= GENMASK(1, 0),
290						/* Bits 2-31 reserved */
291};
292
293REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
294
295static const u32 reg_endp_init_hdr_fmask[] = {
296	[HDR_LEN]					= GENMASK(5, 0),
297	[HDR_OFST_METADATA_VALID]			= BIT(6),
298	[HDR_OFST_METADATA]				= GENMASK(12, 7),
299	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
300	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
301	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
302						/* Bit 26 reserved */
303	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
304	[HDR_LEN_MSB]					= GENMASK(29, 28),
305	[HDR_OFST_METADATA_MSB]				= GENMASK(31, 30),
306};
307
308REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
309
310static const u32 reg_endp_init_hdr_ext_fmask[] = {
311	[HDR_ENDIANNESS]				= BIT(0),
312	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
313	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
314	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
315	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
316	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
317						/* Bits 14-15 reserved */
318	[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB]		= GENMASK(17, 16),
319	[HDR_OFST_PKT_SIZE_MSB]				= GENMASK(19, 18),
320	[HDR_ADDITIONAL_CONST_LEN_MSB]			= GENMASK(21, 20),
321						/* Bits 22-31 reserved */
322};
323
324REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
325
326REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
327	   0x00000818, 0x0070);
328
329static const u32 reg_endp_init_mode_fmask[] = {
330	[ENDP_MODE]					= GENMASK(2, 0),
331	[DCPH_ENABLE]					= BIT(3),
332	[DEST_PIPE_INDEX]				= GENMASK(8, 4),
333						/* Bits 9-11 reserved */
334	[BYTE_THRESHOLD]				= GENMASK(27, 12),
335	[PIPE_REPLICATION_EN]				= BIT(28),
336	[PAD_EN]					= BIT(29),
337	[DRBIP_ACL_ENABLE]				= BIT(30),
338						/* Bit 31 reserved */
339};
340
341REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
342
343static const u32 reg_endp_init_aggr_fmask[] = {
344	[AGGR_EN]					= GENMASK(1, 0),
345	[AGGR_TYPE]					= GENMASK(4, 2),
346	[BYTE_LIMIT]					= GENMASK(10, 5),
347						/* Bit 11 reserved */
348	[TIME_LIMIT]					= GENMASK(16, 12),
349	[PKT_LIMIT]					= GENMASK(22, 17),
350	[SW_EOF_ACTIVE]					= BIT(23),
351	[FORCE_CLOSE]					= BIT(24),
352						/* Bit 25 reserved */
353	[HARD_BYTE_LIMIT_EN]				= BIT(26),
354	[AGGR_GRAN_SEL]					= BIT(27),
355						/* Bits 28-31 reserved */
356};
357
358REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
359
360static const u32 reg_endp_init_hol_block_en_fmask[] = {
361	[HOL_BLOCK_EN]					= BIT(0),
362						/* Bits 1-31 reserved */
363};
364
365REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
366		  0x0000082c, 0x0070);
367
368static const u32 reg_endp_init_hol_block_timer_fmask[] = {
369	[TIMER_LIMIT]					= GENMASK(4, 0),
370						/* Bits 5-7 reserved */
371	[TIMER_GRAN_SEL]				= BIT(8),
372						/* Bits 9-31 reserved */
373};
374
375REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
376		  0x00000830, 0x0070);
377
378static const u32 reg_endp_init_deaggr_fmask[] = {
379	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
380	[SYSPIPE_ERR_DETECTION]				= BIT(6),
381	[PACKET_OFFSET_VALID]				= BIT(7),
382	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),
383	[IGNORE_MIN_PKT_ERR]				= BIT(14),
384						/* Bit 15 reserved */
385	[MAX_PACKET_LEN]				= GENMASK(31, 16),
386};
387
388REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
389
390static const u32 reg_endp_init_rsrc_grp_fmask[] = {
391	[ENDP_RSRC_GRP]					= GENMASK(1, 0),
392						/* Bits 2-31 reserved */
393};
394
395REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
396
397static const u32 reg_endp_init_seq_fmask[] = {
398	[SEQ_TYPE]					= GENMASK(7, 0),
399						/* Bits 8-31 reserved */
400};
401
402REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
403
404static const u32 reg_endp_status_fmask[] = {
405	[STATUS_EN]					= BIT(0),
406	[STATUS_ENDP]					= GENMASK(5, 1),
407						/* Bits 6-8 reserved */
408	[STATUS_PKT_SUPPRESS]				= BIT(9),
409						/* Bits 10-31 reserved */
410};
411
412REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
413
414static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
415	[FILTER_HASH_MSK_SRC_ID]			= BIT(0),
416	[FILTER_HASH_MSK_SRC_IP]			= BIT(1),
417	[FILTER_HASH_MSK_DST_IP]			= BIT(2),
418	[FILTER_HASH_MSK_SRC_PORT]			= BIT(3),
419	[FILTER_HASH_MSK_DST_PORT]			= BIT(4),
420	[FILTER_HASH_MSK_PROTOCOL]			= BIT(5),
421	[FILTER_HASH_MSK_METADATA]			= BIT(6),
422	[FILTER_HASH_MSK_ALL]				= GENMASK(6, 0),
423						/* Bits 7-15 reserved */
424	[ROUTER_HASH_MSK_SRC_ID]			= BIT(16),
425	[ROUTER_HASH_MSK_SRC_IP]			= BIT(17),
426	[ROUTER_HASH_MSK_DST_IP]			= BIT(18),
427	[ROUTER_HASH_MSK_SRC_PORT]			= BIT(19),
428	[ROUTER_HASH_MSK_DST_PORT]			= BIT(20),
429	[ROUTER_HASH_MSK_PROTOCOL]			= BIT(21),
430	[ROUTER_HASH_MSK_METADATA]			= BIT(22),
431	[ROUTER_HASH_MSK_ALL]				= GENMASK(22, 16),
432						/* Bits 23-31 reserved */
433};
434
435REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
436		  0x0000085c, 0x0070);
437
438/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
439REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
440
441/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
442REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
443
444/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
445REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
446
447static const u32 reg_ipa_irq_uc_fmask[] = {
448	[UC_INTR]					= BIT(0),
449						/* Bits 1-31 reserved */
450};
451
452REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
453
454/* Valid bits defined by ipa->available */
455REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
456	   0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
457
458/* Valid bits defined by ipa->available */
459REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
460	   0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
461
462/* Valid bits defined by ipa->available */
463REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
464	   0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
465
466static const struct reg *reg_array[] = {
467	[COMP_CFG]			= &reg_comp_cfg,
468	[CLKON_CFG]			= &reg_clkon_cfg,
469	[ROUTE]				= &reg_route,
470	[SHARED_MEM_SIZE]		= &reg_shared_mem_size,
471	[QSB_MAX_WRITES]		= &reg_qsb_max_writes,
472	[QSB_MAX_READS]			= &reg_qsb_max_reads,
473	[FILT_ROUT_HASH_EN]		= &reg_filt_rout_hash_en,
474	[FILT_ROUT_HASH_FLUSH]		= &reg_filt_rout_hash_flush,
475	[STATE_AGGR_ACTIVE]		= &reg_state_aggr_active,
476	[LOCAL_PKT_PROC_CNTXT]		= &reg_local_pkt_proc_cntxt,
477	[AGGR_FORCE_CLOSE]		= &reg_aggr_force_close,
478	[IPA_TX_CFG]			= &reg_ipa_tx_cfg,
479	[FLAVOR_0]			= &reg_flavor_0,
480	[IDLE_INDICATION_CFG]		= &reg_idle_indication_cfg,
481	[QTIME_TIMESTAMP_CFG]		= &reg_qtime_timestamp_cfg,
482	[TIMERS_XO_CLK_DIV_CFG]		= &reg_timers_xo_clk_div_cfg,
483	[TIMERS_PULSE_GRAN_CFG]		= &reg_timers_pulse_gran_cfg,
484	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &reg_src_rsrc_grp_01_rsrc_type,
485	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &reg_src_rsrc_grp_23_rsrc_type,
486	[DST_RSRC_GRP_01_RSRC_TYPE]	= &reg_dst_rsrc_grp_01_rsrc_type,
487	[DST_RSRC_GRP_23_RSRC_TYPE]	= &reg_dst_rsrc_grp_23_rsrc_type,
488	[ENDP_INIT_CFG]			= &reg_endp_init_cfg,
489	[ENDP_INIT_NAT]			= &reg_endp_init_nat,
490	[ENDP_INIT_HDR]			= &reg_endp_init_hdr,
491	[ENDP_INIT_HDR_EXT]		= &reg_endp_init_hdr_ext,
492	[ENDP_INIT_HDR_METADATA_MASK]	= &reg_endp_init_hdr_metadata_mask,
493	[ENDP_INIT_MODE]		= &reg_endp_init_mode,
494	[ENDP_INIT_AGGR]		= &reg_endp_init_aggr,
495	[ENDP_INIT_HOL_BLOCK_EN]	= &reg_endp_init_hol_block_en,
496	[ENDP_INIT_HOL_BLOCK_TIMER]	= &reg_endp_init_hol_block_timer,
497	[ENDP_INIT_DEAGGR]		= &reg_endp_init_deaggr,
498	[ENDP_INIT_RSRC_GRP]		= &reg_endp_init_rsrc_grp,
499	[ENDP_INIT_SEQ]			= &reg_endp_init_seq,
500	[ENDP_STATUS]			= &reg_endp_status,
501	[ENDP_FILTER_ROUTER_HSH_CFG]	= &reg_endp_filter_router_hsh_cfg,
502	[IPA_IRQ_STTS]			= &reg_ipa_irq_stts,
503	[IPA_IRQ_EN]			= &reg_ipa_irq_en,
504	[IPA_IRQ_CLR]			= &reg_ipa_irq_clr,
505	[IPA_IRQ_UC]			= &reg_ipa_irq_uc,
506	[IRQ_SUSPEND_INFO]		= &reg_irq_suspend_info,
507	[IRQ_SUSPEND_EN]		= &reg_irq_suspend_en,
508	[IRQ_SUSPEND_CLR]		= &reg_irq_suspend_clr,
509};
510
511const struct regs ipa_regs_v4_11 = {
512	.reg_count	= ARRAY_SIZE(reg_array),
513	.reg		= reg_array,
514};
515