1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../gsi.h"
8#include "../reg.h"
9#include "../gsi_reg.h"
10
11REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12    0x0000c020 + 0x1000 * GSI_EE_AP);
13
14REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15    0x0000c024 + 0x1000 * GSI_EE_AP);
16
17static const u32 reg_ch_c_cntxt_0_fmask[] = {
18	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
19	[CHTYPE_DIR]					= BIT(3),
20	[CH_EE]						= GENMASK(7, 4),
21	[CHID]						= GENMASK(12, 8),
22						/* Bit 13 reserved */
23	[ERINDEX]					= GENMASK(18, 14),
24						/* Bit 19 reserved */
25	[CHSTATE]					= GENMASK(23, 20),
26	[ELEMENT_SIZE]					= GENMASK(31, 24),
27};
28
29REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
31
32static const u32 reg_ch_c_cntxt_1_fmask[] = {
33	[CH_R_LENGTH]					= GENMASK(15, 0),
34						/* Bits 16-31 reserved */
35};
36
37REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
39
40REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
43
44static const u32 reg_ch_c_qos_fmask[] = {
45	[WRR_WEIGHT]					= GENMASK(3, 0),
46						/* Bits 4-7 reserved */
47	[MAX_PREFETCH]					= BIT(8),
48	[USE_DB_ENG]					= BIT(9),
49	[USE_ESCAPE_BUF_ONLY]				= BIT(10),
50						/* Bits 11-31 reserved */
51};
52
53REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
54
55static const u32 reg_error_log_fmask[] = {
56	[ERR_ARG3]					= GENMASK(3, 0),
57	[ERR_ARG2]					= GENMASK(7, 4),
58	[ERR_ARG1]					= GENMASK(11, 8),
59	[ERR_CODE]					= GENMASK(15, 12),
60						/* Bits 16-18 reserved */
61	[ERR_VIRT_IDX]					= GENMASK(23, 19),
62	[ERR_TYPE]					= GENMASK(27, 24),
63	[ERR_EE]					= GENMASK(31, 28),
64};
65
66REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
67	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
68
69REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
70	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
71
72REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
73	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
74
75REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
76	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
77
78static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
79	[EV_CHTYPE]					= GENMASK(3, 0),
80	[EV_EE]						= GENMASK(7, 4),
81	[EV_EVCHID]					= GENMASK(15, 8),
82	[EV_INTYPE]					= BIT(16),
83						/* Bits 17-19 reserved */
84	[EV_CHSTATE]					= GENMASK(23, 20),
85	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
86};
87
88REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
89		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
90
91static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
92	[R_LENGTH]					= GENMASK(15, 0),
93};
94
95REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
96		  0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
97
98REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
99	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
100
101REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
102	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
103
104REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
105	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
106
107static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
108	[EV_MODT]					= GENMASK(15, 0),
109	[EV_MODC]					= GENMASK(23, 16),
110	[EV_MOD_CNT]					= GENMASK(31, 24),
111};
112
113REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
114		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
115
116REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
117	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
118
119REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
120	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
121
122REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
123	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
124
125REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
126	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
127
128REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
129	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
130
131REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
132	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
133
134REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
135	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
136
137REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
138	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
139
140REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
141	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
142
143static const u32 reg_gsi_status_fmask[] = {
144	[ENABLED]					= BIT(0),
145						/* Bits 1-31 reserved */
146};
147
148REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
149
150static const u32 reg_ch_cmd_fmask[] = {
151	[CH_CHID]					= GENMASK(7, 0),
152						/* Bits 8-23 reserved */
153	[CH_OPCODE]					= GENMASK(31, 24),
154};
155
156REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
157
158static const u32 reg_ev_ch_cmd_fmask[] = {
159	[EV_CHID]					= GENMASK(7, 0),
160						/* Bits 8-23 reserved */
161	[EV_OPCODE]					= GENMASK(31, 24),
162};
163
164REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
165
166static const u32 reg_generic_cmd_fmask[] = {
167	[GENERIC_OPCODE]				= GENMASK(4, 0),
168	[GENERIC_CHID]					= GENMASK(9, 5),
169	[GENERIC_EE]					= GENMASK(13, 10),
170						/* Bits 14-31 reserved */
171};
172
173REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
174
175static const u32 reg_hw_param_2_fmask[] = {
176	[IRAM_SIZE]					= GENMASK(2, 0),
177	[NUM_CH_PER_EE]					= GENMASK(7, 3),
178	[NUM_EV_PER_EE]					= GENMASK(12, 8),
179	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
180	[GSI_CH_FULL_LOGIC]				= BIT(14),
181	[GSI_USE_SDMA]					= BIT(15),
182	[GSI_SDMA_N_INT]				= GENMASK(18, 16),
183	[GSI_SDMA_MAX_BURST]				= GENMASK(26, 19),
184	[GSI_SDMA_N_IOVEC]				= GENMASK(29, 27),
185						/* Bits 30-31 reserved */
186};
187
188REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
189
190REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
191
192REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
193
194REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
195
196REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
197
198REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
199    0x0001f098 + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
202    0x0001f09c + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
205    0x0001f0a0 + 0x4000 * GSI_EE_AP);
206
207REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
208    0x0001f0a4 + 0x4000 * GSI_EE_AP);
209
210REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
213    0x0001f0b8 + 0x4000 * GSI_EE_AP);
214
215REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
216    0x0001f0c0 + 0x4000 * GSI_EE_AP);
217
218REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
219
220REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
221
222REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
223
224REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
225
226REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
227
228REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
229
230static const u32 reg_cntxt_intset_fmask[] = {
231	[INTYPE]					= BIT(0)
232						/* Bits 1-31 reserved */
233};
234
235REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
236
237REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
238
239REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
240
241static const u32 reg_cntxt_scratch_0_fmask[] = {
242	[INTER_EE_RESULT]				= GENMASK(2, 0),
243						/* Bits 3-4 reserved */
244	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
245						/* Bits 8-31 reserved */
246};
247
248REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
249
250static const struct reg *reg_array[] = {
251	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
252	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
253	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
254	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
255	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
256	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
257	[CH_C_QOS]			= &reg_ch_c_qos,
258	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
259	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
260	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
261	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
262	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
263	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
264	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
265	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
266	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
267	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
268	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
269	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
270	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
271	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
272	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
273	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
274	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
275	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
276	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
277	[GSI_STATUS]			= &reg_gsi_status,
278	[CH_CMD]			= &reg_ch_cmd,
279	[EV_CH_CMD]			= &reg_ev_ch_cmd,
280	[GENERIC_CMD]			= &reg_generic_cmd,
281	[HW_PARAM_2]			= &reg_hw_param_2,
282	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
283	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
284	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
285	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
286	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
287	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
288	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
289	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
290	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
291	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
292	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
293	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
294	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
295	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
296	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
297	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
298	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
299	[CNTXT_INTSET]			= &reg_cntxt_intset,
300	[ERROR_LOG]			= &reg_error_log,
301	[ERROR_LOG_CLR]			= &reg_error_log_clr,
302	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
303};
304
305const struct regs gsi_regs_v4_0 = {
306	.reg_count	= ARRAY_SIZE(reg_array),
307	.reg		= reg_array,
308};
309