1// SPDX-License-Identifier: GPL-2.0 2 3/* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 */ 8 9#include <linux/bitops.h> 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/dma/ti-cppi5.h> 14#include <linux/etherdevice.h> 15#include <linux/genalloc.h> 16#include <linux/if_vlan.h> 17#include <linux/interrupt.h> 18#include <linux/kernel.h> 19#include <linux/mfd/syscon.h> 20#include <linux/module.h> 21#include <linux/of.h> 22#include <linux/of_irq.h> 23#include <linux/of_mdio.h> 24#include <linux/of_net.h> 25#include <linux/of_platform.h> 26#include <linux/phy.h> 27#include <linux/remoteproc/pruss.h> 28#include <linux/regmap.h> 29#include <linux/remoteproc.h> 30 31#include "icssg_prueth.h" 32#include "icssg_mii_rt.h" 33#include "../k3-cppi-desc-pool.h" 34 35#define PRUETH_MODULE_DESCRIPTION "PRUSS ICSSG Ethernet driver" 36 37/* Netif debug messages possible */ 38#define PRUETH_EMAC_DEBUG (NETIF_MSG_DRV | \ 39 NETIF_MSG_PROBE | \ 40 NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_IFDOWN | \ 43 NETIF_MSG_IFUP | \ 44 NETIF_MSG_RX_ERR | \ 45 NETIF_MSG_TX_ERR | \ 46 NETIF_MSG_TX_QUEUED | \ 47 NETIF_MSG_INTR | \ 48 NETIF_MSG_TX_DONE | \ 49 NETIF_MSG_RX_STATUS | \ 50 NETIF_MSG_PKTDATA | \ 51 NETIF_MSG_HW | \ 52 NETIF_MSG_WOL) 53 54#define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx) 55 56/* CTRLMMR_ICSSG_RGMII_CTRL register bits */ 57#define ICSSG_CTRL_RGMII_ID_MODE BIT(24) 58 59#define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */ 60 61static void prueth_cleanup_rx_chns(struct prueth_emac *emac, 62 struct prueth_rx_chn *rx_chn, 63 int max_rflows) 64{ 65 if (rx_chn->desc_pool) 66 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 67 68 if (rx_chn->rx_chn) 69 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 70} 71 72static void prueth_cleanup_tx_chns(struct prueth_emac *emac) 73{ 74 int i; 75 76 for (i = 0; i < emac->tx_ch_num; i++) { 77 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 78 79 if (tx_chn->desc_pool) 80 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 81 82 if (tx_chn->tx_chn) 83 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 84 85 /* Assume prueth_cleanup_tx_chns() is called at the 86 * end after all channel resources are freed 87 */ 88 memset(tx_chn, 0, sizeof(*tx_chn)); 89 } 90} 91 92static void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num) 93{ 94 int i; 95 96 for (i = 0; i < num; i++) { 97 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 98 99 if (tx_chn->irq) 100 free_irq(tx_chn->irq, tx_chn); 101 netif_napi_del(&tx_chn->napi_tx); 102 } 103} 104 105static void prueth_xmit_free(struct prueth_tx_chn *tx_chn, 106 struct cppi5_host_desc_t *desc) 107{ 108 struct cppi5_host_desc_t *first_desc, *next_desc; 109 dma_addr_t buf_dma, next_desc_dma; 110 u32 buf_dma_len; 111 112 first_desc = desc; 113 next_desc = first_desc; 114 115 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 116 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 117 118 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, 119 DMA_TO_DEVICE); 120 121 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 122 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 123 while (next_desc_dma) { 124 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 125 next_desc_dma); 126 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 127 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 128 129 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 130 DMA_TO_DEVICE); 131 132 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 133 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 134 135 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 136 } 137 138 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 139} 140 141static int emac_tx_complete_packets(struct prueth_emac *emac, int chn, 142 int budget) 143{ 144 struct net_device *ndev = emac->ndev; 145 struct cppi5_host_desc_t *desc_tx; 146 struct netdev_queue *netif_txq; 147 struct prueth_tx_chn *tx_chn; 148 unsigned int total_bytes = 0; 149 struct sk_buff *skb; 150 dma_addr_t desc_dma; 151 int res, num_tx = 0; 152 void **swdata; 153 154 tx_chn = &emac->tx_chns[chn]; 155 156 while (true) { 157 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 158 if (res == -ENODATA) 159 break; 160 161 /* teardown completion */ 162 if (cppi5_desc_is_tdcm(desc_dma)) { 163 if (atomic_dec_and_test(&emac->tdown_cnt)) 164 complete(&emac->tdown_complete); 165 break; 166 } 167 168 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 169 desc_dma); 170 swdata = cppi5_hdesc_get_swdata(desc_tx); 171 172 skb = *(swdata); 173 prueth_xmit_free(tx_chn, desc_tx); 174 175 ndev = skb->dev; 176 ndev->stats.tx_packets++; 177 ndev->stats.tx_bytes += skb->len; 178 total_bytes += skb->len; 179 napi_consume_skb(skb, budget); 180 num_tx++; 181 } 182 183 if (!num_tx) 184 return 0; 185 186 netif_txq = netdev_get_tx_queue(ndev, chn); 187 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 188 189 if (netif_tx_queue_stopped(netif_txq)) { 190 /* If the TX queue was stopped, wake it now 191 * if we have enough room. 192 */ 193 __netif_tx_lock(netif_txq, smp_processor_id()); 194 if (netif_running(ndev) && 195 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 196 MAX_SKB_FRAGS)) 197 netif_tx_wake_queue(netif_txq); 198 __netif_tx_unlock(netif_txq); 199 } 200 201 return num_tx; 202} 203 204static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget) 205{ 206 struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx); 207 struct prueth_emac *emac = tx_chn->emac; 208 int num_tx_packets; 209 210 num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget); 211 212 if (num_tx_packets >= budget) 213 return budget; 214 215 if (napi_complete_done(napi_tx, num_tx_packets)) 216 enable_irq(tx_chn->irq); 217 218 return num_tx_packets; 219} 220 221static irqreturn_t prueth_tx_irq(int irq, void *dev_id) 222{ 223 struct prueth_tx_chn *tx_chn = dev_id; 224 225 disable_irq_nosync(irq); 226 napi_schedule(&tx_chn->napi_tx); 227 228 return IRQ_HANDLED; 229} 230 231static int prueth_ndev_add_tx_napi(struct prueth_emac *emac) 232{ 233 struct prueth *prueth = emac->prueth; 234 int i, ret; 235 236 for (i = 0; i < emac->tx_ch_num; i++) { 237 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 238 239 netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll); 240 ret = request_irq(tx_chn->irq, prueth_tx_irq, 241 IRQF_TRIGGER_HIGH, tx_chn->name, 242 tx_chn); 243 if (ret) { 244 netif_napi_del(&tx_chn->napi_tx); 245 dev_err(prueth->dev, "unable to request TX IRQ %d\n", 246 tx_chn->irq); 247 goto fail; 248 } 249 } 250 251 return 0; 252fail: 253 prueth_ndev_del_tx_napi(emac, i); 254 return ret; 255} 256 257static int prueth_init_tx_chns(struct prueth_emac *emac) 258{ 259 static const struct k3_ring_cfg ring_cfg = { 260 .elm_size = K3_RINGACC_RING_ELSIZE_8, 261 .mode = K3_RINGACC_RING_MODE_RING, 262 .flags = 0, 263 .size = PRUETH_MAX_TX_DESC, 264 }; 265 struct k3_udma_glue_tx_channel_cfg tx_cfg; 266 struct device *dev = emac->prueth->dev; 267 struct net_device *ndev = emac->ndev; 268 int ret, slice, i; 269 u32 hdesc_size; 270 271 slice = prueth_emac_slice(emac); 272 if (slice < 0) 273 return slice; 274 275 init_completion(&emac->tdown_complete); 276 277 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 278 PRUETH_NAV_SW_DATA_SIZE); 279 memset(&tx_cfg, 0, sizeof(tx_cfg)); 280 tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 281 tx_cfg.tx_cfg = ring_cfg; 282 tx_cfg.txcq_cfg = ring_cfg; 283 284 for (i = 0; i < emac->tx_ch_num; i++) { 285 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 286 287 /* To differentiate channels for SLICE0 vs SLICE1 */ 288 snprintf(tx_chn->name, sizeof(tx_chn->name), 289 "tx%d-%d", slice, i); 290 291 tx_chn->emac = emac; 292 tx_chn->id = i; 293 tx_chn->descs_num = PRUETH_MAX_TX_DESC; 294 295 tx_chn->tx_chn = 296 k3_udma_glue_request_tx_chn(dev, tx_chn->name, 297 &tx_cfg); 298 if (IS_ERR(tx_chn->tx_chn)) { 299 ret = PTR_ERR(tx_chn->tx_chn); 300 tx_chn->tx_chn = NULL; 301 netdev_err(ndev, 302 "Failed to request tx dma ch: %d\n", ret); 303 goto fail; 304 } 305 306 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 307 tx_chn->desc_pool = 308 k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 309 tx_chn->descs_num, 310 hdesc_size, 311 tx_chn->name); 312 if (IS_ERR(tx_chn->desc_pool)) { 313 ret = PTR_ERR(tx_chn->desc_pool); 314 tx_chn->desc_pool = NULL; 315 netdev_err(ndev, "Failed to create tx pool: %d\n", ret); 316 goto fail; 317 } 318 319 ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 320 if (ret < 0) { 321 netdev_err(ndev, "failed to get tx irq\n"); 322 goto fail; 323 } 324 tx_chn->irq = ret; 325 326 snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d", 327 dev_name(dev), tx_chn->id); 328 } 329 330 return 0; 331 332fail: 333 prueth_cleanup_tx_chns(emac); 334 return ret; 335} 336 337static int prueth_init_rx_chns(struct prueth_emac *emac, 338 struct prueth_rx_chn *rx_chn, 339 char *name, u32 max_rflows, 340 u32 max_desc_num) 341{ 342 struct k3_udma_glue_rx_channel_cfg rx_cfg; 343 struct device *dev = emac->prueth->dev; 344 struct net_device *ndev = emac->ndev; 345 u32 fdqring_id, hdesc_size; 346 int i, ret = 0, slice; 347 348 slice = prueth_emac_slice(emac); 349 if (slice < 0) 350 return slice; 351 352 /* To differentiate channels for SLICE0 vs SLICE1 */ 353 snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice); 354 355 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 356 PRUETH_NAV_SW_DATA_SIZE); 357 memset(&rx_cfg, 0, sizeof(rx_cfg)); 358 rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 359 rx_cfg.flow_id_num = max_rflows; 360 rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */ 361 362 /* init all flows */ 363 rx_chn->dev = dev; 364 rx_chn->descs_num = max_desc_num; 365 366 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name, 367 &rx_cfg); 368 if (IS_ERR(rx_chn->rx_chn)) { 369 ret = PTR_ERR(rx_chn->rx_chn); 370 rx_chn->rx_chn = NULL; 371 netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret); 372 goto fail; 373 } 374 375 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 376 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 377 rx_chn->descs_num, 378 hdesc_size, 379 rx_chn->name); 380 if (IS_ERR(rx_chn->desc_pool)) { 381 ret = PTR_ERR(rx_chn->desc_pool); 382 rx_chn->desc_pool = NULL; 383 netdev_err(ndev, "Failed to create rx pool: %d\n", ret); 384 goto fail; 385 } 386 387 emac->rx_flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 388 netdev_dbg(ndev, "flow id base = %d\n", emac->rx_flow_id_base); 389 390 fdqring_id = K3_RINGACC_RING_ID_ANY; 391 for (i = 0; i < rx_cfg.flow_id_num; i++) { 392 struct k3_ring_cfg rxring_cfg = { 393 .elm_size = K3_RINGACC_RING_ELSIZE_8, 394 .mode = K3_RINGACC_RING_MODE_RING, 395 .flags = 0, 396 }; 397 struct k3_ring_cfg fdqring_cfg = { 398 .elm_size = K3_RINGACC_RING_ELSIZE_8, 399 .flags = K3_RINGACC_RING_SHARED, 400 }; 401 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 402 .rx_cfg = rxring_cfg, 403 .rxfdq_cfg = fdqring_cfg, 404 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 405 .src_tag_lo_sel = 406 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 407 }; 408 409 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 410 rx_flow_cfg.rx_cfg.size = max_desc_num; 411 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 412 rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode; 413 414 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 415 i, &rx_flow_cfg); 416 if (ret) { 417 netdev_err(ndev, "Failed to init rx flow%d %d\n", 418 i, ret); 419 goto fail; 420 } 421 if (!i) 422 fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 423 i); 424 rx_chn->irq[i] = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 425 if (rx_chn->irq[i] <= 0) { 426 ret = rx_chn->irq[i]; 427 netdev_err(ndev, "Failed to get rx dma irq"); 428 goto fail; 429 } 430 } 431 432 return 0; 433 434fail: 435 prueth_cleanup_rx_chns(emac, rx_chn, max_rflows); 436 return ret; 437} 438 439static int prueth_dma_rx_push(struct prueth_emac *emac, 440 struct sk_buff *skb, 441 struct prueth_rx_chn *rx_chn) 442{ 443 struct net_device *ndev = emac->ndev; 444 struct cppi5_host_desc_t *desc_rx; 445 u32 pkt_len = skb_tailroom(skb); 446 dma_addr_t desc_dma; 447 dma_addr_t buf_dma; 448 void **swdata; 449 450 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 451 if (!desc_rx) { 452 netdev_err(ndev, "rx push: failed to allocate descriptor\n"); 453 return -ENOMEM; 454 } 455 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 456 457 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, DMA_FROM_DEVICE); 458 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 459 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 460 netdev_err(ndev, "rx push: failed to map rx pkt buffer\n"); 461 return -EINVAL; 462 } 463 464 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 465 PRUETH_NAV_PS_DATA_SIZE); 466 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 467 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 468 469 swdata = cppi5_hdesc_get_swdata(desc_rx); 470 *swdata = skb; 471 472 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, 473 desc_rx, desc_dma); 474} 475 476static u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns) 477{ 478 u32 iepcount_lo, iepcount_hi, hi_rollover_count; 479 u64 ns; 480 481 iepcount_lo = lo & GENMASK(19, 0); 482 iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20; 483 hi_rollover_count = hi >> 11; 484 485 ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw); 486 ns = ns * cycle_time_ns + iepcount_lo; 487 488 return ns; 489} 490 491static void emac_rx_timestamp(struct prueth_emac *emac, 492 struct sk_buff *skb, u32 *psdata) 493{ 494 struct skb_shared_hwtstamps *ssh; 495 u64 ns; 496 497 u32 hi_sw = readl(emac->prueth->shram.va + 498 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 499 ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0], 500 IEP_DEFAULT_CYCLE_TIME_NS); 501 502 ssh = skb_hwtstamps(skb); 503 memset(ssh, 0, sizeof(*ssh)); 504 ssh->hwtstamp = ns_to_ktime(ns); 505} 506 507static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id) 508{ 509 struct prueth_rx_chn *rx_chn = &emac->rx_chns; 510 u32 buf_dma_len, pkt_len, port_id = 0; 511 struct net_device *ndev = emac->ndev; 512 struct cppi5_host_desc_t *desc_rx; 513 struct sk_buff *skb, *new_skb; 514 dma_addr_t desc_dma, buf_dma; 515 void **swdata; 516 u32 *psdata; 517 int ret; 518 519 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma); 520 if (ret) { 521 if (ret != -ENODATA) 522 netdev_err(ndev, "rx pop: failed: %d\n", ret); 523 return ret; 524 } 525 526 if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */ 527 return 0; 528 529 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 530 531 swdata = cppi5_hdesc_get_swdata(desc_rx); 532 skb = *swdata; 533 534 psdata = cppi5_hdesc_get_psdata(desc_rx); 535 /* RX HW timestamp */ 536 if (emac->rx_ts_enabled) 537 emac_rx_timestamp(emac, skb, psdata); 538 539 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 540 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 541 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 542 /* firmware adds 4 CRC bytes, strip them */ 543 pkt_len -= 4; 544 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 545 546 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 547 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 548 549 skb->dev = ndev; 550 new_skb = netdev_alloc_skb_ip_align(ndev, PRUETH_MAX_PKT_SIZE); 551 /* if allocation fails we drop the packet but push the 552 * descriptor back to the ring with old skb to prevent a stall 553 */ 554 if (!new_skb) { 555 ndev->stats.rx_dropped++; 556 new_skb = skb; 557 } else { 558 /* send the filled skb up the n/w stack */ 559 skb_put(skb, pkt_len); 560 skb->protocol = eth_type_trans(skb, ndev); 561 napi_gro_receive(&emac->napi_rx, skb); 562 ndev->stats.rx_bytes += pkt_len; 563 ndev->stats.rx_packets++; 564 } 565 566 /* queue another RX DMA */ 567 ret = prueth_dma_rx_push(emac, new_skb, &emac->rx_chns); 568 if (WARN_ON(ret < 0)) { 569 dev_kfree_skb_any(new_skb); 570 ndev->stats.rx_errors++; 571 ndev->stats.rx_dropped++; 572 } 573 574 return ret; 575} 576 577static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma) 578{ 579 struct prueth_rx_chn *rx_chn = data; 580 struct cppi5_host_desc_t *desc_rx; 581 struct sk_buff *skb; 582 dma_addr_t buf_dma; 583 u32 buf_dma_len; 584 void **swdata; 585 586 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 587 swdata = cppi5_hdesc_get_swdata(desc_rx); 588 skb = *swdata; 589 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 590 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 591 592 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, 593 DMA_FROM_DEVICE); 594 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 595 596 dev_kfree_skb_any(skb); 597} 598 599static int emac_get_tx_ts(struct prueth_emac *emac, 600 struct emac_tx_ts_response *rsp) 601{ 602 struct prueth *prueth = emac->prueth; 603 int slice = prueth_emac_slice(emac); 604 int addr; 605 606 addr = icssg_queue_pop(prueth, slice == 0 ? 607 ICSSG_TS_POP_SLICE0 : ICSSG_TS_POP_SLICE1); 608 if (addr < 0) 609 return addr; 610 611 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); 612 /* return buffer back for to pool */ 613 icssg_queue_push(prueth, slice == 0 ? 614 ICSSG_TS_PUSH_SLICE0 : ICSSG_TS_PUSH_SLICE1, addr); 615 616 return 0; 617} 618 619static void tx_ts_work(struct prueth_emac *emac) 620{ 621 struct skb_shared_hwtstamps ssh; 622 struct emac_tx_ts_response tsr; 623 struct sk_buff *skb; 624 int ret = 0; 625 u32 hi_sw; 626 u64 ns; 627 628 /* There may be more than one pending requests */ 629 while (1) { 630 ret = emac_get_tx_ts(emac, &tsr); 631 if (ret) /* nothing more */ 632 break; 633 634 if (tsr.cookie >= PRUETH_MAX_TX_TS_REQUESTS || 635 !emac->tx_ts_skb[tsr.cookie]) { 636 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", 637 tsr.cookie); 638 break; 639 } 640 641 skb = emac->tx_ts_skb[tsr.cookie]; 642 emac->tx_ts_skb[tsr.cookie] = NULL; /* free slot */ 643 if (!skb) { 644 netdev_err(emac->ndev, "Driver Bug! got NULL skb\n"); 645 break; 646 } 647 648 hi_sw = readl(emac->prueth->shram.va + 649 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 650 ns = icssg_ts_to_ns(hi_sw, tsr.hi_ts, tsr.lo_ts, 651 IEP_DEFAULT_CYCLE_TIME_NS); 652 653 memset(&ssh, 0, sizeof(ssh)); 654 ssh.hwtstamp = ns_to_ktime(ns); 655 656 skb_tstamp_tx(skb, &ssh); 657 dev_consume_skb_any(skb); 658 659 if (atomic_dec_and_test(&emac->tx_ts_pending)) /* no more? */ 660 break; 661 } 662} 663 664static int prueth_tx_ts_cookie_get(struct prueth_emac *emac) 665{ 666 int i; 667 668 /* search and get the next free slot */ 669 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 670 if (!emac->tx_ts_skb[i]) { 671 emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */ 672 return i; 673 } 674 } 675 676 return -EBUSY; 677} 678 679/** 680 * emac_ndo_start_xmit - EMAC Transmit function 681 * @skb: SKB pointer 682 * @ndev: EMAC network adapter 683 * 684 * Called by the system to transmit a packet - we queue the packet in 685 * EMAC hardware transmit queue 686 * Doesn't wait for completion we'll check for TX completion in 687 * emac_tx_complete_packets(). 688 * 689 * Return: enum netdev_tx 690 */ 691static enum netdev_tx emac_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev) 692{ 693 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 694 struct prueth_emac *emac = netdev_priv(ndev); 695 struct netdev_queue *netif_txq; 696 struct prueth_tx_chn *tx_chn; 697 dma_addr_t desc_dma, buf_dma; 698 int i, ret = 0, q_idx; 699 bool in_tx_ts = 0; 700 int tx_ts_cookie; 701 void **swdata; 702 u32 pkt_len; 703 u32 *epib; 704 705 pkt_len = skb_headlen(skb); 706 q_idx = skb_get_queue_mapping(skb); 707 708 tx_chn = &emac->tx_chns[q_idx]; 709 netif_txq = netdev_get_tx_queue(ndev, q_idx); 710 711 /* Map the linear buffer */ 712 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE); 713 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 714 netdev_err(ndev, "tx: failed to map skb buffer\n"); 715 ret = NETDEV_TX_OK; 716 goto drop_free_skb; 717 } 718 719 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 720 if (!first_desc) { 721 netdev_dbg(ndev, "tx: failed to allocate descriptor\n"); 722 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE); 723 goto drop_stop_q_busy; 724 } 725 726 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 727 PRUETH_NAV_PS_DATA_SIZE); 728 cppi5_hdesc_set_pkttype(first_desc, 0); 729 epib = first_desc->epib; 730 epib[0] = 0; 731 epib[1] = 0; 732 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 733 emac->tx_ts_enabled) { 734 tx_ts_cookie = prueth_tx_ts_cookie_get(emac); 735 if (tx_ts_cookie >= 0) { 736 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 737 /* Request TX timestamp */ 738 epib[0] = (u32)tx_ts_cookie; 739 epib[1] = 0x80000000; /* TX TS request */ 740 emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb); 741 in_tx_ts = 1; 742 } 743 } 744 745 /* set dst tag to indicate internal qid at the firmware which is at 746 * bit8..bit15. bit0..bit7 indicates port num for directed 747 * packets in case of switch mode operation 748 */ 749 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8))); 750 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 751 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 752 swdata = cppi5_hdesc_get_swdata(first_desc); 753 *swdata = skb; 754 755 /* Handle the case where skb is fragmented in pages */ 756 cur_desc = first_desc; 757 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 758 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 759 u32 frag_size = skb_frag_size(frag); 760 761 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 762 if (!next_desc) { 763 netdev_err(ndev, 764 "tx: failed to allocate frag. descriptor\n"); 765 goto free_desc_stop_q_busy_cleanup_tx_ts; 766 } 767 768 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 769 DMA_TO_DEVICE); 770 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 771 netdev_err(ndev, "tx: Failed to map skb page\n"); 772 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 773 ret = NETDEV_TX_OK; 774 goto cleanup_tx_ts; 775 } 776 777 cppi5_hdesc_reset_hbdesc(next_desc); 778 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 779 cppi5_hdesc_attach_buf(next_desc, 780 buf_dma, frag_size, buf_dma, frag_size); 781 782 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 783 next_desc); 784 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 785 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 786 787 pkt_len += frag_size; 788 cur_desc = next_desc; 789 } 790 WARN_ON_ONCE(pkt_len != skb->len); 791 792 /* report bql before sending packet */ 793 netdev_tx_sent_queue(netif_txq, pkt_len); 794 795 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 796 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 797 /* cppi5_desc_dump(first_desc, 64); */ 798 799 skb_tx_timestamp(skb); /* SW timestamp if SKBTX_IN_PROGRESS not set */ 800 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 801 if (ret) { 802 netdev_err(ndev, "tx: push failed: %d\n", ret); 803 goto drop_free_descs; 804 } 805 806 if (in_tx_ts) 807 atomic_inc(&emac->tx_ts_pending); 808 809 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 810 netif_tx_stop_queue(netif_txq); 811 /* Barrier, so that stop_queue visible to other cpus */ 812 smp_mb__after_atomic(); 813 814 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 815 MAX_SKB_FRAGS) 816 netif_tx_wake_queue(netif_txq); 817 } 818 819 return NETDEV_TX_OK; 820 821cleanup_tx_ts: 822 if (in_tx_ts) { 823 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 824 emac->tx_ts_skb[tx_ts_cookie] = NULL; 825 } 826 827drop_free_descs: 828 prueth_xmit_free(tx_chn, first_desc); 829 830drop_free_skb: 831 dev_kfree_skb_any(skb); 832 833 /* error */ 834 ndev->stats.tx_dropped++; 835 netdev_err(ndev, "tx: error: %d\n", ret); 836 837 return ret; 838 839free_desc_stop_q_busy_cleanup_tx_ts: 840 if (in_tx_ts) { 841 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 842 emac->tx_ts_skb[tx_ts_cookie] = NULL; 843 } 844 prueth_xmit_free(tx_chn, first_desc); 845 846drop_stop_q_busy: 847 netif_tx_stop_queue(netif_txq); 848 return NETDEV_TX_BUSY; 849} 850 851static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma) 852{ 853 struct prueth_tx_chn *tx_chn = data; 854 struct cppi5_host_desc_t *desc_tx; 855 struct sk_buff *skb; 856 void **swdata; 857 858 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 859 swdata = cppi5_hdesc_get_swdata(desc_tx); 860 skb = *(swdata); 861 prueth_xmit_free(tx_chn, desc_tx); 862 863 dev_kfree_skb_any(skb); 864} 865 866static irqreturn_t prueth_tx_ts_irq(int irq, void *dev_id) 867{ 868 struct prueth_emac *emac = dev_id; 869 870 /* currently only TX timestamp is being returned */ 871 tx_ts_work(emac); 872 873 return IRQ_HANDLED; 874} 875 876static irqreturn_t prueth_rx_irq(int irq, void *dev_id) 877{ 878 struct prueth_emac *emac = dev_id; 879 880 disable_irq_nosync(irq); 881 napi_schedule(&emac->napi_rx); 882 883 return IRQ_HANDLED; 884} 885 886struct icssg_firmwares { 887 char *pru; 888 char *rtu; 889 char *txpru; 890}; 891 892static struct icssg_firmwares icssg_emac_firmwares[] = { 893 { 894 .pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 895 .rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 896 .txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 897 }, 898 { 899 .pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 900 .rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 901 .txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", 902 } 903}; 904 905static int prueth_emac_start(struct prueth *prueth, struct prueth_emac *emac) 906{ 907 struct icssg_firmwares *firmwares; 908 struct device *dev = prueth->dev; 909 int slice, ret; 910 911 firmwares = icssg_emac_firmwares; 912 913 slice = prueth_emac_slice(emac); 914 if (slice < 0) { 915 netdev_err(emac->ndev, "invalid port\n"); 916 return -EINVAL; 917 } 918 919 ret = icssg_config(prueth, emac, slice); 920 if (ret) 921 return ret; 922 923 ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru); 924 ret = rproc_boot(prueth->pru[slice]); 925 if (ret) { 926 dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); 927 return -EINVAL; 928 } 929 930 ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu); 931 ret = rproc_boot(prueth->rtu[slice]); 932 if (ret) { 933 dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); 934 goto halt_pru; 935 } 936 937 ret = rproc_set_firmware(prueth->txpru[slice], firmwares[slice].txpru); 938 ret = rproc_boot(prueth->txpru[slice]); 939 if (ret) { 940 dev_err(dev, "failed to boot TX_PRU%d: %d\n", slice, ret); 941 goto halt_rtu; 942 } 943 944 emac->fw_running = 1; 945 return 0; 946 947halt_rtu: 948 rproc_shutdown(prueth->rtu[slice]); 949 950halt_pru: 951 rproc_shutdown(prueth->pru[slice]); 952 953 return ret; 954} 955 956static void prueth_emac_stop(struct prueth_emac *emac) 957{ 958 struct prueth *prueth = emac->prueth; 959 int slice; 960 961 switch (emac->port_id) { 962 case PRUETH_PORT_MII0: 963 slice = ICSS_SLICE0; 964 break; 965 case PRUETH_PORT_MII1: 966 slice = ICSS_SLICE1; 967 break; 968 default: 969 netdev_err(emac->ndev, "invalid port\n"); 970 return; 971 } 972 973 emac->fw_running = 0; 974 rproc_shutdown(prueth->txpru[slice]); 975 rproc_shutdown(prueth->rtu[slice]); 976 rproc_shutdown(prueth->pru[slice]); 977} 978 979static void prueth_cleanup_tx_ts(struct prueth_emac *emac) 980{ 981 int i; 982 983 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 984 if (emac->tx_ts_skb[i]) { 985 dev_kfree_skb_any(emac->tx_ts_skb[i]); 986 emac->tx_ts_skb[i] = NULL; 987 } 988 } 989} 990 991/* called back by PHY layer if there is change in link state of hw port*/ 992static void emac_adjust_link(struct net_device *ndev) 993{ 994 struct prueth_emac *emac = netdev_priv(ndev); 995 struct phy_device *phydev = ndev->phydev; 996 struct prueth *prueth = emac->prueth; 997 bool new_state = false; 998 unsigned long flags; 999 1000 if (phydev->link) { 1001 /* check the mode of operation - full/half duplex */ 1002 if (phydev->duplex != emac->duplex) { 1003 new_state = true; 1004 emac->duplex = phydev->duplex; 1005 } 1006 if (phydev->speed != emac->speed) { 1007 new_state = true; 1008 emac->speed = phydev->speed; 1009 } 1010 if (!emac->link) { 1011 new_state = true; 1012 emac->link = 1; 1013 } 1014 } else if (emac->link) { 1015 new_state = true; 1016 emac->link = 0; 1017 1018 /* f/w should support 100 & 1000 */ 1019 emac->speed = SPEED_1000; 1020 1021 /* half duplex may not be supported by f/w */ 1022 emac->duplex = DUPLEX_FULL; 1023 } 1024 1025 if (new_state) { 1026 phy_print_status(phydev); 1027 1028 /* update RGMII and MII configuration based on PHY negotiated 1029 * values 1030 */ 1031 if (emac->link) { 1032 /* Set the RGMII cfg for gig en and full duplex */ 1033 icssg_update_rgmii_cfg(prueth->miig_rt, emac); 1034 1035 /* update the Tx IPG based on 100M/1G speed */ 1036 spin_lock_irqsave(&emac->lock, flags); 1037 icssg_config_ipg(emac); 1038 spin_unlock_irqrestore(&emac->lock, flags); 1039 icssg_config_set_speed(emac); 1040 emac_set_port_state(emac, ICSSG_EMAC_PORT_FORWARD); 1041 1042 } else { 1043 emac_set_port_state(emac, ICSSG_EMAC_PORT_DISABLE); 1044 } 1045 } 1046 1047 if (emac->link) { 1048 /* reactivate the transmit queue */ 1049 netif_tx_wake_all_queues(ndev); 1050 } else { 1051 netif_tx_stop_all_queues(ndev); 1052 prueth_cleanup_tx_ts(emac); 1053 } 1054} 1055 1056static int emac_napi_rx_poll(struct napi_struct *napi_rx, int budget) 1057{ 1058 struct prueth_emac *emac = prueth_napi_to_emac(napi_rx); 1059 int rx_flow = PRUETH_RX_FLOW_DATA; 1060 int flow = PRUETH_MAX_RX_FLOWS; 1061 int num_rx = 0; 1062 int cur_budget; 1063 int ret; 1064 1065 while (flow--) { 1066 cur_budget = budget - num_rx; 1067 1068 while (cur_budget--) { 1069 ret = emac_rx_packet(emac, flow); 1070 if (ret) 1071 break; 1072 num_rx++; 1073 } 1074 1075 if (num_rx >= budget) 1076 break; 1077 } 1078 1079 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 1080 enable_irq(emac->rx_chns.irq[rx_flow]); 1081 1082 return num_rx; 1083} 1084 1085static int prueth_prepare_rx_chan(struct prueth_emac *emac, 1086 struct prueth_rx_chn *chn, 1087 int buf_size) 1088{ 1089 struct sk_buff *skb; 1090 int i, ret; 1091 1092 for (i = 0; i < chn->descs_num; i++) { 1093 skb = __netdev_alloc_skb_ip_align(NULL, buf_size, GFP_KERNEL); 1094 if (!skb) 1095 return -ENOMEM; 1096 1097 ret = prueth_dma_rx_push(emac, skb, chn); 1098 if (ret < 0) { 1099 netdev_err(emac->ndev, 1100 "cannot submit skb for rx chan %s ret %d\n", 1101 chn->name, ret); 1102 kfree_skb(skb); 1103 return ret; 1104 } 1105 } 1106 1107 return 0; 1108} 1109 1110static void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num, 1111 bool free_skb) 1112{ 1113 int i; 1114 1115 for (i = 0; i < ch_num; i++) { 1116 if (free_skb) 1117 k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn, 1118 &emac->tx_chns[i], 1119 prueth_tx_cleanup); 1120 k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn); 1121 } 1122} 1123 1124static void prueth_reset_rx_chan(struct prueth_rx_chn *chn, 1125 int num_flows, bool disable) 1126{ 1127 int i; 1128 1129 for (i = 0; i < num_flows; i++) 1130 k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn, 1131 prueth_rx_cleanup, !!i); 1132 if (disable) 1133 k3_udma_glue_disable_rx_chn(chn->rx_chn); 1134} 1135 1136static int emac_phy_connect(struct prueth_emac *emac) 1137{ 1138 struct prueth *prueth = emac->prueth; 1139 struct net_device *ndev = emac->ndev; 1140 /* connect PHY */ 1141 ndev->phydev = of_phy_connect(emac->ndev, emac->phy_node, 1142 &emac_adjust_link, 0, 1143 emac->phy_if); 1144 if (!ndev->phydev) { 1145 dev_err(prueth->dev, "couldn't connect to phy %s\n", 1146 emac->phy_node->full_name); 1147 return -ENODEV; 1148 } 1149 1150 /* remove unsupported modes */ 1151 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1152 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1153 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1154 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1155 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1156 1157 if (emac->phy_if == PHY_INTERFACE_MODE_MII) 1158 phy_set_max_speed(ndev->phydev, SPEED_100); 1159 1160 return 0; 1161} 1162 1163static u64 prueth_iep_gettime(void *clockops_data, struct ptp_system_timestamp *sts) 1164{ 1165 u32 hi_rollover_count, hi_rollover_count_r; 1166 struct prueth_emac *emac = clockops_data; 1167 struct prueth *prueth = emac->prueth; 1168 void __iomem *fw_hi_r_count_addr; 1169 void __iomem *fw_count_hi_addr; 1170 u32 iepcount_hi, iepcount_hi_r; 1171 unsigned long flags; 1172 u32 iepcount_lo; 1173 u64 ts = 0; 1174 1175 fw_count_hi_addr = prueth->shram.va + TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET; 1176 fw_hi_r_count_addr = prueth->shram.va + TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET; 1177 1178 local_irq_save(flags); 1179 do { 1180 iepcount_hi = icss_iep_get_count_hi(emac->iep); 1181 iepcount_hi += readl(fw_count_hi_addr); 1182 hi_rollover_count = readl(fw_hi_r_count_addr); 1183 ptp_read_system_prets(sts); 1184 iepcount_lo = icss_iep_get_count_low(emac->iep); 1185 ptp_read_system_postts(sts); 1186 1187 iepcount_hi_r = icss_iep_get_count_hi(emac->iep); 1188 iepcount_hi_r += readl(fw_count_hi_addr); 1189 hi_rollover_count_r = readl(fw_hi_r_count_addr); 1190 } while ((iepcount_hi_r != iepcount_hi) || 1191 (hi_rollover_count != hi_rollover_count_r)); 1192 local_irq_restore(flags); 1193 1194 ts = ((u64)hi_rollover_count) << 23 | iepcount_hi; 1195 ts = ts * (u64)IEP_DEFAULT_CYCLE_TIME_NS + iepcount_lo; 1196 1197 return ts; 1198} 1199 1200static void prueth_iep_settime(void *clockops_data, u64 ns) 1201{ 1202 struct icssg_setclock_desc __iomem *sc_descp; 1203 struct prueth_emac *emac = clockops_data; 1204 struct icssg_setclock_desc sc_desc; 1205 u64 cyclecount; 1206 u32 cycletime; 1207 int timeout; 1208 1209 if (!emac->fw_running) 1210 return; 1211 1212 sc_descp = emac->prueth->shram.va + TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET; 1213 1214 cycletime = IEP_DEFAULT_CYCLE_TIME_NS; 1215 cyclecount = ns / cycletime; 1216 1217 memset(&sc_desc, 0, sizeof(sc_desc)); 1218 sc_desc.margin = cycletime - 1000; 1219 sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0); 1220 sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32; 1221 sc_desc.iepcount_set = ns % cycletime; 1222 sc_desc.CMP0_current = cycletime - 4; //Count from 0 to (cycle time)-4 1223 1224 memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc)); 1225 1226 writeb(1, &sc_descp->request); 1227 1228 timeout = 5; /* fw should take 2-3 ms */ 1229 while (timeout--) { 1230 if (readb(&sc_descp->acknowledgment)) 1231 return; 1232 1233 usleep_range(500, 1000); 1234 } 1235 1236 dev_err(emac->prueth->dev, "settime timeout\n"); 1237} 1238 1239static int prueth_perout_enable(void *clockops_data, 1240 struct ptp_perout_request *req, int on, 1241 u64 *cmp) 1242{ 1243 struct prueth_emac *emac = clockops_data; 1244 u32 reduction_factor = 0, offset = 0; 1245 struct timespec64 ts; 1246 u64 ns_period; 1247 1248 if (!on) 1249 return 0; 1250 1251 /* Any firmware specific stuff for PPS/PEROUT handling */ 1252 ts.tv_sec = req->period.sec; 1253 ts.tv_nsec = req->period.nsec; 1254 ns_period = timespec64_to_ns(&ts); 1255 1256 /* f/w doesn't support period less than cycle time */ 1257 if (ns_period < IEP_DEFAULT_CYCLE_TIME_NS) 1258 return -ENXIO; 1259 1260 reduction_factor = ns_period / IEP_DEFAULT_CYCLE_TIME_NS; 1261 offset = ns_period % IEP_DEFAULT_CYCLE_TIME_NS; 1262 1263 /* f/w requires at least 1uS within a cycle so CMP 1264 * can trigger after SYNC is enabled 1265 */ 1266 if (offset < 5 * NSEC_PER_USEC) 1267 offset = 5 * NSEC_PER_USEC; 1268 1269 /* if offset is close to cycle time then we will miss 1270 * the CMP event for last tick when IEP rolls over. 1271 * In normal mode, IEP tick is 4ns. 1272 * In slow compensation it could be 0ns or 8ns at 1273 * every slow compensation cycle. 1274 */ 1275 if (offset > IEP_DEFAULT_CYCLE_TIME_NS - 8) 1276 offset = IEP_DEFAULT_CYCLE_TIME_NS - 8; 1277 1278 /* we're in shadow mode so need to set upper 32-bits */ 1279 *cmp = (u64)offset << 32; 1280 1281 writel(reduction_factor, emac->prueth->shram.va + 1282 TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET); 1283 1284 writel(0, emac->prueth->shram.va + 1285 TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); 1286 1287 return 0; 1288} 1289 1290const struct icss_iep_clockops prueth_iep_clockops = { 1291 .settime = prueth_iep_settime, 1292 .gettime = prueth_iep_gettime, 1293 .perout_enable = prueth_perout_enable, 1294}; 1295 1296/** 1297 * emac_ndo_open - EMAC device open 1298 * @ndev: network adapter device 1299 * 1300 * Called when system wants to start the interface. 1301 * 1302 * Return: 0 for a successful open, or appropriate error code 1303 */ 1304static int emac_ndo_open(struct net_device *ndev) 1305{ 1306 struct prueth_emac *emac = netdev_priv(ndev); 1307 int ret, i, num_data_chn = emac->tx_ch_num; 1308 struct prueth *prueth = emac->prueth; 1309 int slice = prueth_emac_slice(emac); 1310 struct device *dev = prueth->dev; 1311 int max_rx_flows; 1312 int rx_flow; 1313 1314 /* clear SMEM and MSMC settings for all slices */ 1315 if (!prueth->emacs_initialized) { 1316 memset_io(prueth->msmcram.va, 0, prueth->msmcram.size); 1317 memset_io(prueth->shram.va, 0, ICSSG_CONFIG_OFFSET_SLICE1 * PRUETH_NUM_MACS); 1318 } 1319 1320 /* set h/w MAC as user might have re-configured */ 1321 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1322 1323 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1324 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 1325 1326 icssg_class_default(prueth->miig_rt, slice, 0); 1327 1328 /* Notify the stack of the actual queue counts. */ 1329 ret = netif_set_real_num_tx_queues(ndev, num_data_chn); 1330 if (ret) { 1331 dev_err(dev, "cannot set real number of tx queues\n"); 1332 return ret; 1333 } 1334 1335 init_completion(&emac->cmd_complete); 1336 ret = prueth_init_tx_chns(emac); 1337 if (ret) { 1338 dev_err(dev, "failed to init tx channel: %d\n", ret); 1339 return ret; 1340 } 1341 1342 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1343 ret = prueth_init_rx_chns(emac, &emac->rx_chns, "rx", 1344 max_rx_flows, PRUETH_MAX_RX_DESC); 1345 if (ret) { 1346 dev_err(dev, "failed to init rx channel: %d\n", ret); 1347 goto cleanup_tx; 1348 } 1349 1350 ret = prueth_ndev_add_tx_napi(emac); 1351 if (ret) 1352 goto cleanup_rx; 1353 1354 /* we use only the highest priority flow for now i.e. @irq[3] */ 1355 rx_flow = PRUETH_RX_FLOW_DATA; 1356 ret = request_irq(emac->rx_chns.irq[rx_flow], prueth_rx_irq, 1357 IRQF_TRIGGER_HIGH, dev_name(dev), emac); 1358 if (ret) { 1359 dev_err(dev, "unable to request RX IRQ\n"); 1360 goto cleanup_napi; 1361 } 1362 1363 /* reset and start PRU firmware */ 1364 ret = prueth_emac_start(prueth, emac); 1365 if (ret) 1366 goto free_rx_irq; 1367 1368 icssg_mii_update_mtu(prueth->mii_rt, slice, ndev->max_mtu); 1369 1370 if (!prueth->emacs_initialized) { 1371 ret = icss_iep_init(emac->iep, &prueth_iep_clockops, 1372 emac, IEP_DEFAULT_CYCLE_TIME_NS); 1373 } 1374 1375 ret = request_threaded_irq(emac->tx_ts_irq, NULL, prueth_tx_ts_irq, 1376 IRQF_ONESHOT, dev_name(dev), emac); 1377 if (ret) 1378 goto stop; 1379 1380 /* Prepare RX */ 1381 ret = prueth_prepare_rx_chan(emac, &emac->rx_chns, PRUETH_MAX_PKT_SIZE); 1382 if (ret) 1383 goto free_tx_ts_irq; 1384 1385 ret = k3_udma_glue_enable_rx_chn(emac->rx_chns.rx_chn); 1386 if (ret) 1387 goto reset_rx_chn; 1388 1389 for (i = 0; i < emac->tx_ch_num; i++) { 1390 ret = k3_udma_glue_enable_tx_chn(emac->tx_chns[i].tx_chn); 1391 if (ret) 1392 goto reset_tx_chan; 1393 } 1394 1395 /* Enable NAPI in Tx and Rx direction */ 1396 for (i = 0; i < emac->tx_ch_num; i++) 1397 napi_enable(&emac->tx_chns[i].napi_tx); 1398 napi_enable(&emac->napi_rx); 1399 1400 /* start PHY */ 1401 phy_start(ndev->phydev); 1402 1403 prueth->emacs_initialized++; 1404 1405 queue_work(system_long_wq, &emac->stats_work.work); 1406 1407 return 0; 1408 1409reset_tx_chan: 1410 /* Since interface is not yet up, there is wouldn't be 1411 * any SKB for completion. So set false to free_skb 1412 */ 1413 prueth_reset_tx_chan(emac, i, false); 1414reset_rx_chn: 1415 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, false); 1416free_tx_ts_irq: 1417 free_irq(emac->tx_ts_irq, emac); 1418stop: 1419 prueth_emac_stop(emac); 1420free_rx_irq: 1421 free_irq(emac->rx_chns.irq[rx_flow], emac); 1422cleanup_napi: 1423 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1424cleanup_rx: 1425 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1426cleanup_tx: 1427 prueth_cleanup_tx_chns(emac); 1428 1429 return ret; 1430} 1431 1432/** 1433 * emac_ndo_stop - EMAC device stop 1434 * @ndev: network adapter device 1435 * 1436 * Called when system wants to stop or down the interface. 1437 * 1438 * Return: Always 0 (Success) 1439 */ 1440static int emac_ndo_stop(struct net_device *ndev) 1441{ 1442 struct prueth_emac *emac = netdev_priv(ndev); 1443 struct prueth *prueth = emac->prueth; 1444 int rx_flow = PRUETH_RX_FLOW_DATA; 1445 int max_rx_flows; 1446 int ret, i; 1447 1448 /* inform the upper layers. */ 1449 netif_tx_stop_all_queues(ndev); 1450 1451 /* block packets from wire */ 1452 if (ndev->phydev) 1453 phy_stop(ndev->phydev); 1454 1455 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); 1456 1457 atomic_set(&emac->tdown_cnt, emac->tx_ch_num); 1458 /* ensure new tdown_cnt value is visible */ 1459 smp_mb__after_atomic(); 1460 /* tear down and disable UDMA channels */ 1461 reinit_completion(&emac->tdown_complete); 1462 for (i = 0; i < emac->tx_ch_num; i++) 1463 k3_udma_glue_tdown_tx_chn(emac->tx_chns[i].tx_chn, false); 1464 1465 ret = wait_for_completion_timeout(&emac->tdown_complete, 1466 msecs_to_jiffies(1000)); 1467 if (!ret) 1468 netdev_err(ndev, "tx teardown timeout\n"); 1469 1470 prueth_reset_tx_chan(emac, emac->tx_ch_num, true); 1471 for (i = 0; i < emac->tx_ch_num; i++) 1472 napi_disable(&emac->tx_chns[i].napi_tx); 1473 1474 max_rx_flows = PRUETH_MAX_RX_FLOWS; 1475 k3_udma_glue_tdown_rx_chn(emac->rx_chns.rx_chn, true); 1476 1477 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, true); 1478 1479 napi_disable(&emac->napi_rx); 1480 1481 cancel_work_sync(&emac->rx_mode_work); 1482 1483 /* Destroying the queued work in ndo_stop() */ 1484 cancel_delayed_work_sync(&emac->stats_work); 1485 1486 /* stop PRUs */ 1487 prueth_emac_stop(emac); 1488 1489 if (prueth->emacs_initialized == 1) 1490 icss_iep_exit(emac->iep); 1491 1492 /* stop PRUs */ 1493 prueth_emac_stop(emac); 1494 1495 free_irq(emac->tx_ts_irq, emac); 1496 1497 free_irq(emac->rx_chns.irq[rx_flow], emac); 1498 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 1499 prueth_cleanup_tx_chns(emac); 1500 1501 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 1502 prueth_cleanup_tx_chns(emac); 1503 1504 prueth->emacs_initialized--; 1505 1506 return 0; 1507} 1508 1509static void emac_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1510{ 1511 ndev->stats.tx_errors++; 1512} 1513 1514static void emac_ndo_set_rx_mode_work(struct work_struct *work) 1515{ 1516 struct prueth_emac *emac = container_of(work, struct prueth_emac, rx_mode_work); 1517 struct net_device *ndev = emac->ndev; 1518 bool promisc, allmulti; 1519 1520 if (!netif_running(ndev)) 1521 return; 1522 1523 promisc = ndev->flags & IFF_PROMISC; 1524 allmulti = ndev->flags & IFF_ALLMULTI; 1525 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_DISABLE); 1526 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_DISABLE); 1527 1528 if (promisc) { 1529 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_ENABLE); 1530 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1531 return; 1532 } 1533 1534 if (allmulti) { 1535 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1536 return; 1537 } 1538 1539 if (!netdev_mc_empty(ndev)) { 1540 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 1541 return; 1542 } 1543} 1544 1545/** 1546 * emac_ndo_set_rx_mode - EMAC set receive mode function 1547 * @ndev: The EMAC network adapter 1548 * 1549 * Called when system wants to set the receive mode of the device. 1550 * 1551 */ 1552static void emac_ndo_set_rx_mode(struct net_device *ndev) 1553{ 1554 struct prueth_emac *emac = netdev_priv(ndev); 1555 1556 queue_work(emac->cmd_wq, &emac->rx_mode_work); 1557} 1558 1559static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr) 1560{ 1561 struct prueth_emac *emac = netdev_priv(ndev); 1562 struct hwtstamp_config config; 1563 1564 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1565 return -EFAULT; 1566 1567 switch (config.tx_type) { 1568 case HWTSTAMP_TX_OFF: 1569 emac->tx_ts_enabled = 0; 1570 break; 1571 case HWTSTAMP_TX_ON: 1572 emac->tx_ts_enabled = 1; 1573 break; 1574 default: 1575 return -ERANGE; 1576 } 1577 1578 switch (config.rx_filter) { 1579 case HWTSTAMP_FILTER_NONE: 1580 emac->rx_ts_enabled = 0; 1581 break; 1582 case HWTSTAMP_FILTER_ALL: 1583 case HWTSTAMP_FILTER_SOME: 1584 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1585 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1586 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1587 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1588 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1589 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1590 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1591 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1592 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1593 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1594 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1595 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1596 case HWTSTAMP_FILTER_NTP_ALL: 1597 emac->rx_ts_enabled = 1; 1598 config.rx_filter = HWTSTAMP_FILTER_ALL; 1599 break; 1600 default: 1601 return -ERANGE; 1602 } 1603 1604 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1605 -EFAULT : 0; 1606} 1607 1608static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr) 1609{ 1610 struct prueth_emac *emac = netdev_priv(ndev); 1611 struct hwtstamp_config config; 1612 1613 config.flags = 0; 1614 config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1615 config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1616 1617 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1618 -EFAULT : 0; 1619} 1620 1621static int emac_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1622{ 1623 switch (cmd) { 1624 case SIOCGHWTSTAMP: 1625 return emac_get_ts_config(ndev, ifr); 1626 case SIOCSHWTSTAMP: 1627 return emac_set_ts_config(ndev, ifr); 1628 default: 1629 break; 1630 } 1631 1632 return phy_do_ioctl(ndev, ifr, cmd); 1633} 1634 1635static void emac_ndo_get_stats64(struct net_device *ndev, 1636 struct rtnl_link_stats64 *stats) 1637{ 1638 struct prueth_emac *emac = netdev_priv(ndev); 1639 1640 emac_update_hardware_stats(emac); 1641 1642 stats->rx_packets = emac_get_stat_by_name(emac, "rx_packets"); 1643 stats->rx_bytes = emac_get_stat_by_name(emac, "rx_bytes"); 1644 stats->tx_packets = emac_get_stat_by_name(emac, "tx_packets"); 1645 stats->tx_bytes = emac_get_stat_by_name(emac, "tx_bytes"); 1646 stats->rx_crc_errors = emac_get_stat_by_name(emac, "rx_crc_errors"); 1647 stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors"); 1648 stats->multicast = emac_get_stat_by_name(emac, "rx_multicast_frames"); 1649 1650 stats->rx_errors = ndev->stats.rx_errors; 1651 stats->rx_dropped = ndev->stats.rx_dropped; 1652 stats->tx_errors = ndev->stats.tx_errors; 1653 stats->tx_dropped = ndev->stats.tx_dropped; 1654} 1655 1656static const struct net_device_ops emac_netdev_ops = { 1657 .ndo_open = emac_ndo_open, 1658 .ndo_stop = emac_ndo_stop, 1659 .ndo_start_xmit = emac_ndo_start_xmit, 1660 .ndo_set_mac_address = eth_mac_addr, 1661 .ndo_validate_addr = eth_validate_addr, 1662 .ndo_tx_timeout = emac_ndo_tx_timeout, 1663 .ndo_set_rx_mode = emac_ndo_set_rx_mode, 1664 .ndo_eth_ioctl = emac_ndo_ioctl, 1665 .ndo_get_stats64 = emac_ndo_get_stats64, 1666}; 1667 1668/* get emac_port corresponding to eth_node name */ 1669static int prueth_node_port(struct device_node *eth_node) 1670{ 1671 u32 port_id; 1672 int ret; 1673 1674 ret = of_property_read_u32(eth_node, "reg", &port_id); 1675 if (ret) 1676 return ret; 1677 1678 if (port_id == 0) 1679 return PRUETH_PORT_MII0; 1680 else if (port_id == 1) 1681 return PRUETH_PORT_MII1; 1682 else 1683 return PRUETH_PORT_INVALID; 1684} 1685 1686/* get MAC instance corresponding to eth_node name */ 1687static int prueth_node_mac(struct device_node *eth_node) 1688{ 1689 u32 port_id; 1690 int ret; 1691 1692 ret = of_property_read_u32(eth_node, "reg", &port_id); 1693 if (ret) 1694 return ret; 1695 1696 if (port_id == 0) 1697 return PRUETH_MAC0; 1698 else if (port_id == 1) 1699 return PRUETH_MAC1; 1700 else 1701 return PRUETH_MAC_INVALID; 1702} 1703 1704static int prueth_netdev_init(struct prueth *prueth, 1705 struct device_node *eth_node) 1706{ 1707 int ret, num_tx_chn = PRUETH_MAX_TX_QUEUES; 1708 struct prueth_emac *emac; 1709 struct net_device *ndev; 1710 enum prueth_port port; 1711 const char *irq_name; 1712 enum prueth_mac mac; 1713 1714 port = prueth_node_port(eth_node); 1715 if (port == PRUETH_PORT_INVALID) 1716 return -EINVAL; 1717 1718 mac = prueth_node_mac(eth_node); 1719 if (mac == PRUETH_MAC_INVALID) 1720 return -EINVAL; 1721 1722 ndev = alloc_etherdev_mq(sizeof(*emac), num_tx_chn); 1723 if (!ndev) 1724 return -ENOMEM; 1725 1726 emac = netdev_priv(ndev); 1727 emac->prueth = prueth; 1728 emac->ndev = ndev; 1729 emac->port_id = port; 1730 emac->cmd_wq = create_singlethread_workqueue("icssg_cmd_wq"); 1731 if (!emac->cmd_wq) { 1732 ret = -ENOMEM; 1733 goto free_ndev; 1734 } 1735 INIT_WORK(&emac->rx_mode_work, emac_ndo_set_rx_mode_work); 1736 1737 INIT_DELAYED_WORK(&emac->stats_work, emac_stats_work_handler); 1738 1739 ret = pruss_request_mem_region(prueth->pruss, 1740 port == PRUETH_PORT_MII0 ? 1741 PRUSS_MEM_DRAM0 : PRUSS_MEM_DRAM1, 1742 &emac->dram); 1743 if (ret) { 1744 dev_err(prueth->dev, "unable to get DRAM: %d\n", ret); 1745 ret = -ENOMEM; 1746 goto free_wq; 1747 } 1748 1749 emac->tx_ch_num = 1; 1750 1751 irq_name = "tx_ts0"; 1752 if (emac->port_id == PRUETH_PORT_MII1) 1753 irq_name = "tx_ts1"; 1754 emac->tx_ts_irq = platform_get_irq_byname_optional(prueth->pdev, irq_name); 1755 if (emac->tx_ts_irq < 0) { 1756 ret = dev_err_probe(prueth->dev, emac->tx_ts_irq, "could not get tx_ts_irq\n"); 1757 goto free; 1758 } 1759 1760 SET_NETDEV_DEV(ndev, prueth->dev); 1761 spin_lock_init(&emac->lock); 1762 mutex_init(&emac->cmd_lock); 1763 1764 emac->phy_node = of_parse_phandle(eth_node, "phy-handle", 0); 1765 if (!emac->phy_node && !of_phy_is_fixed_link(eth_node)) { 1766 dev_err(prueth->dev, "couldn't find phy-handle\n"); 1767 ret = -ENODEV; 1768 goto free; 1769 } else if (of_phy_is_fixed_link(eth_node)) { 1770 ret = of_phy_register_fixed_link(eth_node); 1771 if (ret) { 1772 ret = dev_err_probe(prueth->dev, ret, 1773 "failed to register fixed-link phy\n"); 1774 goto free; 1775 } 1776 1777 emac->phy_node = eth_node; 1778 } 1779 1780 ret = of_get_phy_mode(eth_node, &emac->phy_if); 1781 if (ret) { 1782 dev_err(prueth->dev, "could not get phy-mode property\n"); 1783 goto free; 1784 } 1785 1786 if (emac->phy_if != PHY_INTERFACE_MODE_MII && 1787 !phy_interface_mode_is_rgmii(emac->phy_if)) { 1788 dev_err(prueth->dev, "PHY mode unsupported %s\n", phy_modes(emac->phy_if)); 1789 ret = -EINVAL; 1790 goto free; 1791 } 1792 1793 /* AM65 SR2.0 has TX Internal delay always enabled by hardware 1794 * and it is not possible to disable TX Internal delay. The below 1795 * switch case block describes how we handle different phy modes 1796 * based on hardware restriction. 1797 */ 1798 switch (emac->phy_if) { 1799 case PHY_INTERFACE_MODE_RGMII_ID: 1800 emac->phy_if = PHY_INTERFACE_MODE_RGMII_RXID; 1801 break; 1802 case PHY_INTERFACE_MODE_RGMII_TXID: 1803 emac->phy_if = PHY_INTERFACE_MODE_RGMII; 1804 break; 1805 case PHY_INTERFACE_MODE_RGMII: 1806 case PHY_INTERFACE_MODE_RGMII_RXID: 1807 dev_err(prueth->dev, "RGMII mode without TX delay is not supported"); 1808 ret = -EINVAL; 1809 goto free; 1810 default: 1811 break; 1812 } 1813 1814 /* get mac address from DT and set private and netdev addr */ 1815 ret = of_get_ethdev_address(eth_node, ndev); 1816 if (!is_valid_ether_addr(ndev->dev_addr)) { 1817 eth_hw_addr_random(ndev); 1818 dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n", 1819 port, ndev->dev_addr); 1820 } 1821 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 1822 1823 ndev->min_mtu = PRUETH_MIN_PKT_SIZE; 1824 ndev->max_mtu = PRUETH_MAX_MTU; 1825 ndev->netdev_ops = &emac_netdev_ops; 1826 ndev->ethtool_ops = &icssg_ethtool_ops; 1827 ndev->hw_features = NETIF_F_SG; 1828 ndev->features = ndev->hw_features; 1829 1830 netif_napi_add(ndev, &emac->napi_rx, emac_napi_rx_poll); 1831 prueth->emac[mac] = emac; 1832 1833 return 0; 1834 1835free: 1836 pruss_release_mem_region(prueth->pruss, &emac->dram); 1837free_wq: 1838 destroy_workqueue(emac->cmd_wq); 1839free_ndev: 1840 emac->ndev = NULL; 1841 prueth->emac[mac] = NULL; 1842 free_netdev(ndev); 1843 1844 return ret; 1845} 1846 1847static void prueth_netdev_exit(struct prueth *prueth, 1848 struct device_node *eth_node) 1849{ 1850 struct prueth_emac *emac; 1851 enum prueth_mac mac; 1852 1853 mac = prueth_node_mac(eth_node); 1854 if (mac == PRUETH_MAC_INVALID) 1855 return; 1856 1857 emac = prueth->emac[mac]; 1858 if (!emac) 1859 return; 1860 1861 if (of_phy_is_fixed_link(emac->phy_node)) 1862 of_phy_deregister_fixed_link(emac->phy_node); 1863 1864 netif_napi_del(&emac->napi_rx); 1865 1866 pruss_release_mem_region(prueth->pruss, &emac->dram); 1867 destroy_workqueue(emac->cmd_wq); 1868 free_netdev(emac->ndev); 1869 prueth->emac[mac] = NULL; 1870} 1871 1872static int prueth_get_cores(struct prueth *prueth, int slice) 1873{ 1874 struct device *dev = prueth->dev; 1875 enum pruss_pru_id pruss_id; 1876 struct device_node *np; 1877 int idx = -1, ret; 1878 1879 np = dev->of_node; 1880 1881 switch (slice) { 1882 case ICSS_SLICE0: 1883 idx = 0; 1884 break; 1885 case ICSS_SLICE1: 1886 idx = 3; 1887 break; 1888 default: 1889 return -EINVAL; 1890 } 1891 1892 prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id); 1893 if (IS_ERR(prueth->pru[slice])) { 1894 ret = PTR_ERR(prueth->pru[slice]); 1895 prueth->pru[slice] = NULL; 1896 return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice); 1897 } 1898 prueth->pru_id[slice] = pruss_id; 1899 1900 idx++; 1901 prueth->rtu[slice] = pru_rproc_get(np, idx, NULL); 1902 if (IS_ERR(prueth->rtu[slice])) { 1903 ret = PTR_ERR(prueth->rtu[slice]); 1904 prueth->rtu[slice] = NULL; 1905 return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice); 1906 } 1907 1908 idx++; 1909 prueth->txpru[slice] = pru_rproc_get(np, idx, NULL); 1910 if (IS_ERR(prueth->txpru[slice])) { 1911 ret = PTR_ERR(prueth->txpru[slice]); 1912 prueth->txpru[slice] = NULL; 1913 return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice); 1914 } 1915 1916 return 0; 1917} 1918 1919static void prueth_put_cores(struct prueth *prueth, int slice) 1920{ 1921 if (prueth->txpru[slice]) 1922 pru_rproc_put(prueth->txpru[slice]); 1923 1924 if (prueth->rtu[slice]) 1925 pru_rproc_put(prueth->rtu[slice]); 1926 1927 if (prueth->pru[slice]) 1928 pru_rproc_put(prueth->pru[slice]); 1929} 1930 1931static const struct of_device_id prueth_dt_match[]; 1932 1933static int prueth_probe(struct platform_device *pdev) 1934{ 1935 struct device_node *eth_node, *eth_ports_node; 1936 struct device_node *eth0_node = NULL; 1937 struct device_node *eth1_node = NULL; 1938 struct genpool_data_align gp_data = { 1939 .align = SZ_64K, 1940 }; 1941 const struct of_device_id *match; 1942 struct device *dev = &pdev->dev; 1943 struct device_node *np; 1944 struct prueth *prueth; 1945 struct pruss *pruss; 1946 u32 msmc_ram_size; 1947 int i, ret; 1948 1949 np = dev->of_node; 1950 1951 match = of_match_device(prueth_dt_match, dev); 1952 if (!match) 1953 return -ENODEV; 1954 1955 prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL); 1956 if (!prueth) 1957 return -ENOMEM; 1958 1959 dev_set_drvdata(dev, prueth); 1960 prueth->pdev = pdev; 1961 prueth->pdata = *(const struct prueth_pdata *)match->data; 1962 1963 prueth->dev = dev; 1964 eth_ports_node = of_get_child_by_name(np, "ethernet-ports"); 1965 if (!eth_ports_node) 1966 return -ENOENT; 1967 1968 for_each_child_of_node(eth_ports_node, eth_node) { 1969 u32 reg; 1970 1971 if (strcmp(eth_node->name, "port")) 1972 continue; 1973 ret = of_property_read_u32(eth_node, "reg", ®); 1974 if (ret < 0) { 1975 dev_err(dev, "%pOF error reading port_id %d\n", 1976 eth_node, ret); 1977 } 1978 1979 of_node_get(eth_node); 1980 1981 if (reg == 0) { 1982 eth0_node = eth_node; 1983 if (!of_device_is_available(eth0_node)) { 1984 of_node_put(eth0_node); 1985 eth0_node = NULL; 1986 } 1987 } else if (reg == 1) { 1988 eth1_node = eth_node; 1989 if (!of_device_is_available(eth1_node)) { 1990 of_node_put(eth1_node); 1991 eth1_node = NULL; 1992 } 1993 } else { 1994 dev_err(dev, "port reg should be 0 or 1\n"); 1995 } 1996 } 1997 1998 of_node_put(eth_ports_node); 1999 2000 /* At least one node must be present and available else we fail */ 2001 if (!eth0_node && !eth1_node) { 2002 dev_err(dev, "neither port0 nor port1 node available\n"); 2003 return -ENODEV; 2004 } 2005 2006 if (eth0_node == eth1_node) { 2007 dev_err(dev, "port0 and port1 can't have same reg\n"); 2008 of_node_put(eth0_node); 2009 return -ENODEV; 2010 } 2011 2012 prueth->eth_node[PRUETH_MAC0] = eth0_node; 2013 prueth->eth_node[PRUETH_MAC1] = eth1_node; 2014 2015 prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt"); 2016 if (IS_ERR(prueth->miig_rt)) { 2017 dev_err(dev, "couldn't get ti,mii-g-rt syscon regmap\n"); 2018 return -ENODEV; 2019 } 2020 2021 prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt"); 2022 if (IS_ERR(prueth->mii_rt)) { 2023 dev_err(dev, "couldn't get ti,mii-rt syscon regmap\n"); 2024 return -ENODEV; 2025 } 2026 2027 if (eth0_node) { 2028 ret = prueth_get_cores(prueth, ICSS_SLICE0); 2029 if (ret) 2030 goto put_cores; 2031 } 2032 2033 if (eth1_node) { 2034 ret = prueth_get_cores(prueth, ICSS_SLICE1); 2035 if (ret) 2036 goto put_cores; 2037 } 2038 2039 pruss = pruss_get(eth0_node ? 2040 prueth->pru[ICSS_SLICE0] : prueth->pru[ICSS_SLICE1]); 2041 if (IS_ERR(pruss)) { 2042 ret = PTR_ERR(pruss); 2043 dev_err(dev, "unable to get pruss handle\n"); 2044 goto put_cores; 2045 } 2046 2047 prueth->pruss = pruss; 2048 2049 ret = pruss_request_mem_region(pruss, PRUSS_MEM_SHRD_RAM2, 2050 &prueth->shram); 2051 if (ret) { 2052 dev_err(dev, "unable to get PRUSS SHRD RAM2: %d\n", ret); 2053 goto put_pruss; 2054 } 2055 2056 prueth->sram_pool = of_gen_pool_get(np, "sram", 0); 2057 if (!prueth->sram_pool) { 2058 dev_err(dev, "unable to get SRAM pool\n"); 2059 ret = -ENODEV; 2060 2061 goto put_mem; 2062 } 2063 2064 msmc_ram_size = MSMC_RAM_SIZE; 2065 2066 /* NOTE: FW bug needs buffer base to be 64KB aligned */ 2067 prueth->msmcram.va = 2068 (void __iomem *)gen_pool_alloc_algo(prueth->sram_pool, 2069 msmc_ram_size, 2070 gen_pool_first_fit_align, 2071 &gp_data); 2072 2073 if (!prueth->msmcram.va) { 2074 ret = -ENOMEM; 2075 dev_err(dev, "unable to allocate MSMC resource\n"); 2076 goto put_mem; 2077 } 2078 prueth->msmcram.pa = gen_pool_virt_to_phys(prueth->sram_pool, 2079 (unsigned long)prueth->msmcram.va); 2080 prueth->msmcram.size = msmc_ram_size; 2081 memset_io(prueth->msmcram.va, 0, msmc_ram_size); 2082 dev_dbg(dev, "sram: pa %llx va %p size %zx\n", prueth->msmcram.pa, 2083 prueth->msmcram.va, prueth->msmcram.size); 2084 2085 prueth->iep0 = icss_iep_get_idx(np, 0); 2086 if (IS_ERR(prueth->iep0)) { 2087 ret = dev_err_probe(dev, PTR_ERR(prueth->iep0), "iep0 get failed\n"); 2088 prueth->iep0 = NULL; 2089 goto free_pool; 2090 } 2091 2092 prueth->iep1 = icss_iep_get_idx(np, 1); 2093 if (IS_ERR(prueth->iep1)) { 2094 ret = dev_err_probe(dev, PTR_ERR(prueth->iep1), "iep1 get failed\n"); 2095 goto put_iep0; 2096 } 2097 2098 if (prueth->pdata.quirk_10m_link_issue) { 2099 /* Enable IEP1 for FW in 64bit mode as W/A for 10M FD link detect issue under TX 2100 * traffic. 2101 */ 2102 icss_iep_init_fw(prueth->iep1); 2103 } 2104 2105 /* setup netdev interfaces */ 2106 if (eth0_node) { 2107 ret = prueth_netdev_init(prueth, eth0_node); 2108 if (ret) { 2109 dev_err_probe(dev, ret, "netdev init %s failed\n", 2110 eth0_node->name); 2111 goto exit_iep; 2112 } 2113 prueth->emac[PRUETH_MAC0]->iep = prueth->iep0; 2114 } 2115 2116 if (eth1_node) { 2117 ret = prueth_netdev_init(prueth, eth1_node); 2118 if (ret) { 2119 dev_err_probe(dev, ret, "netdev init %s failed\n", 2120 eth1_node->name); 2121 goto netdev_exit; 2122 } 2123 2124 prueth->emac[PRUETH_MAC1]->iep = prueth->iep0; 2125 } 2126 2127 /* register the network devices */ 2128 if (eth0_node) { 2129 ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev); 2130 if (ret) { 2131 dev_err(dev, "can't register netdev for port MII0"); 2132 goto netdev_exit; 2133 } 2134 2135 prueth->registered_netdevs[PRUETH_MAC0] = prueth->emac[PRUETH_MAC0]->ndev; 2136 2137 emac_phy_connect(prueth->emac[PRUETH_MAC0]); 2138 phy_attached_info(prueth->emac[PRUETH_MAC0]->ndev->phydev); 2139 } 2140 2141 if (eth1_node) { 2142 ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev); 2143 if (ret) { 2144 dev_err(dev, "can't register netdev for port MII1"); 2145 goto netdev_unregister; 2146 } 2147 2148 prueth->registered_netdevs[PRUETH_MAC1] = prueth->emac[PRUETH_MAC1]->ndev; 2149 emac_phy_connect(prueth->emac[PRUETH_MAC1]); 2150 phy_attached_info(prueth->emac[PRUETH_MAC1]->ndev->phydev); 2151 } 2152 2153 dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n", 2154 (!eth0_node || !eth1_node) ? "single" : "dual"); 2155 2156 if (eth1_node) 2157 of_node_put(eth1_node); 2158 if (eth0_node) 2159 of_node_put(eth0_node); 2160 return 0; 2161 2162netdev_unregister: 2163 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2164 if (!prueth->registered_netdevs[i]) 2165 continue; 2166 if (prueth->emac[i]->ndev->phydev) { 2167 phy_disconnect(prueth->emac[i]->ndev->phydev); 2168 prueth->emac[i]->ndev->phydev = NULL; 2169 } 2170 unregister_netdev(prueth->registered_netdevs[i]); 2171 } 2172 2173netdev_exit: 2174 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2175 eth_node = prueth->eth_node[i]; 2176 if (!eth_node) 2177 continue; 2178 2179 prueth_netdev_exit(prueth, eth_node); 2180 } 2181 2182exit_iep: 2183 if (prueth->pdata.quirk_10m_link_issue) 2184 icss_iep_exit_fw(prueth->iep1); 2185 icss_iep_put(prueth->iep1); 2186 2187put_iep0: 2188 icss_iep_put(prueth->iep0); 2189 prueth->iep0 = NULL; 2190 prueth->iep1 = NULL; 2191 2192free_pool: 2193 gen_pool_free(prueth->sram_pool, 2194 (unsigned long)prueth->msmcram.va, msmc_ram_size); 2195 2196put_mem: 2197 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2198 2199put_pruss: 2200 pruss_put(prueth->pruss); 2201 2202put_cores: 2203 if (eth1_node) { 2204 prueth_put_cores(prueth, ICSS_SLICE1); 2205 of_node_put(eth1_node); 2206 } 2207 2208 if (eth0_node) { 2209 prueth_put_cores(prueth, ICSS_SLICE0); 2210 of_node_put(eth0_node); 2211 } 2212 2213 return ret; 2214} 2215 2216static void prueth_remove(struct platform_device *pdev) 2217{ 2218 struct prueth *prueth = platform_get_drvdata(pdev); 2219 struct device_node *eth_node; 2220 int i; 2221 2222 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2223 if (!prueth->registered_netdevs[i]) 2224 continue; 2225 phy_stop(prueth->emac[i]->ndev->phydev); 2226 phy_disconnect(prueth->emac[i]->ndev->phydev); 2227 prueth->emac[i]->ndev->phydev = NULL; 2228 unregister_netdev(prueth->registered_netdevs[i]); 2229 } 2230 2231 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2232 eth_node = prueth->eth_node[i]; 2233 if (!eth_node) 2234 continue; 2235 2236 prueth_netdev_exit(prueth, eth_node); 2237 } 2238 2239 if (prueth->pdata.quirk_10m_link_issue) 2240 icss_iep_exit_fw(prueth->iep1); 2241 2242 icss_iep_put(prueth->iep1); 2243 icss_iep_put(prueth->iep0); 2244 2245 gen_pool_free(prueth->sram_pool, 2246 (unsigned long)prueth->msmcram.va, 2247 MSMC_RAM_SIZE); 2248 2249 pruss_release_mem_region(prueth->pruss, &prueth->shram); 2250 2251 pruss_put(prueth->pruss); 2252 2253 if (prueth->eth_node[PRUETH_MAC1]) 2254 prueth_put_cores(prueth, ICSS_SLICE1); 2255 2256 if (prueth->eth_node[PRUETH_MAC0]) 2257 prueth_put_cores(prueth, ICSS_SLICE0); 2258} 2259 2260#ifdef CONFIG_PM_SLEEP 2261static int prueth_suspend(struct device *dev) 2262{ 2263 struct prueth *prueth = dev_get_drvdata(dev); 2264 struct net_device *ndev; 2265 int i, ret; 2266 2267 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2268 ndev = prueth->registered_netdevs[i]; 2269 2270 if (!ndev) 2271 continue; 2272 2273 if (netif_running(ndev)) { 2274 netif_device_detach(ndev); 2275 ret = emac_ndo_stop(ndev); 2276 if (ret < 0) { 2277 netdev_err(ndev, "failed to stop: %d", ret); 2278 return ret; 2279 } 2280 } 2281 } 2282 2283 return 0; 2284} 2285 2286static int prueth_resume(struct device *dev) 2287{ 2288 struct prueth *prueth = dev_get_drvdata(dev); 2289 struct net_device *ndev; 2290 int i, ret; 2291 2292 for (i = 0; i < PRUETH_NUM_MACS; i++) { 2293 ndev = prueth->registered_netdevs[i]; 2294 2295 if (!ndev) 2296 continue; 2297 2298 if (netif_running(ndev)) { 2299 ret = emac_ndo_open(ndev); 2300 if (ret < 0) { 2301 netdev_err(ndev, "failed to start: %d", ret); 2302 return ret; 2303 } 2304 netif_device_attach(ndev); 2305 } 2306 } 2307 2308 return 0; 2309} 2310#endif /* CONFIG_PM_SLEEP */ 2311 2312static const struct dev_pm_ops prueth_dev_pm_ops = { 2313 SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume) 2314}; 2315 2316static const struct prueth_pdata am654_icssg_pdata = { 2317 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2318 .quirk_10m_link_issue = 1, 2319}; 2320 2321static const struct of_device_id prueth_dt_match[] = { 2322 { .compatible = "ti,am654-icssg-prueth", .data = &am654_icssg_pdata }, 2323 { /* sentinel */ } 2324}; 2325MODULE_DEVICE_TABLE(of, prueth_dt_match); 2326 2327static struct platform_driver prueth_driver = { 2328 .probe = prueth_probe, 2329 .remove_new = prueth_remove, 2330 .driver = { 2331 .name = "icssg-prueth", 2332 .of_match_table = prueth_dt_match, 2333 .pm = &prueth_dev_pm_ops, 2334 }, 2335}; 2336module_platform_driver(prueth_driver); 2337 2338MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 2339MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 2340MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver"); 2341MODULE_LICENSE("GPL"); 2342