1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 */
5
6#ifndef AM65_CPSW_NUSS_H_
7#define AM65_CPSW_NUSS_H_
8
9#include <linux/if_ether.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/phylink.h>
14#include <linux/platform_device.h>
15#include <linux/soc/ti/k3-ringacc.h>
16#include <net/devlink.h>
17#include "am65-cpsw-qos.h"
18
19struct am65_cpts;
20
21#define HOST_PORT_NUM		0
22
23#define AM65_CPSW_MAX_TX_QUEUES	8
24#define AM65_CPSW_MAX_RX_QUEUES	1
25#define AM65_CPSW_MAX_RX_FLOWS	1
26
27#define AM65_CPSW_PORT_VLAN_REG_OFFSET	0x014
28
29struct am65_cpsw_slave_data {
30	bool				mac_only;
31	struct cpsw_sl			*mac_sl;
32	struct device_node		*phy_node;
33	phy_interface_t			phy_if;
34	struct phy			*ifphy;
35	struct phy			*serdes_phy;
36	bool				rx_pause;
37	bool				tx_pause;
38	u8				mac_addr[ETH_ALEN];
39	int				port_vlan;
40	struct phylink			*phylink;
41	struct phylink_config		phylink_config;
42};
43
44struct am65_cpsw_port {
45	struct am65_cpsw_common		*common;
46	struct net_device		*ndev;
47	const char			*name;
48	u32				port_id;
49	void __iomem			*port_base;
50	void __iomem			*sgmii_base;
51	void __iomem			*stat_base;
52	void __iomem			*fetch_ram_base;
53	bool				disabled;
54	struct am65_cpsw_slave_data	slave;
55	bool				tx_ts_enabled;
56	bool				rx_ts_enabled;
57	struct am65_cpsw_qos		qos;
58	struct devlink_port		devlink_port;
59	/* Only for suspend resume context */
60	u32				vid_context;
61};
62
63struct am65_cpsw_host {
64	struct am65_cpsw_common		*common;
65	void __iomem			*port_base;
66	void __iomem			*stat_base;
67	/* Only for suspend resume context */
68	u32				vid_context;
69};
70
71struct am65_cpsw_tx_chn {
72	struct device *dma_dev;
73	struct napi_struct napi_tx;
74	struct am65_cpsw_common	*common;
75	struct k3_cppi_desc_pool *desc_pool;
76	struct k3_udma_glue_tx_channel *tx_chn;
77	spinlock_t lock; /* protect TX rings in multi-port mode */
78	int irq;
79	u32 id;
80	u32 descs_num;
81	char tx_chn_name[128];
82	u32 rate_mbps;
83};
84
85struct am65_cpsw_rx_chn {
86	struct device *dev;
87	struct device *dma_dev;
88	struct k3_cppi_desc_pool *desc_pool;
89	struct k3_udma_glue_rx_channel *rx_chn;
90	u32 descs_num;
91	int irq;
92};
93
94#define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
95#define AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ BIT(1)
96
97struct am65_cpsw_pdata {
98	u32	quirks;
99	u64	extra_modes;
100	enum k3_ring_mode fdqring_mode;
101	const char	*ale_dev_id;
102};
103
104enum cpsw_devlink_param_id {
105	AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
106	AM65_CPSW_DL_PARAM_SWITCH_MODE,
107};
108
109struct am65_cpsw_devlink {
110	struct am65_cpsw_common *common;
111};
112
113struct am65_cpsw_common {
114	struct device		*dev;
115	struct device		*mdio_dev;
116	struct am65_cpsw_pdata	pdata;
117
118	void __iomem		*ss_base;
119	void __iomem		*cpsw_base;
120
121	u32			port_num;
122	struct am65_cpsw_host   host;
123	struct am65_cpsw_port	*ports;
124	u32			disabled_ports_mask;
125	struct net_device	*dma_ndev;
126
127	int			usage_count; /* number of opened ports */
128	struct cpsw_ale		*ale;
129	int			tx_ch_num;
130	u32			tx_ch_rate_msk;
131	u32			rx_flow_id_base;
132
133	struct am65_cpsw_tx_chn	tx_chns[AM65_CPSW_MAX_TX_QUEUES];
134	struct completion	tdown_complete;
135	atomic_t		tdown_cnt;
136
137	struct am65_cpsw_rx_chn	rx_chns;
138	struct napi_struct	napi_rx;
139
140	bool			rx_irq_disabled;
141
142	u32			nuss_ver;
143	u32			cpsw_ver;
144	unsigned long		bus_freq;
145	bool			pf_p0_rx_ptype_rrobin;
146	struct am65_cpts	*cpts;
147	int			est_enabled;
148
149	bool		is_emac_mode;
150	u16			br_members;
151	int			default_vlan;
152	struct devlink *devlink;
153	struct net_device *hw_bridge_dev;
154	struct notifier_block am65_cpsw_netdevice_nb;
155	unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
156	/* only for suspend/resume context restore */
157	u32			*ale_context;
158};
159
160struct am65_cpsw_ndev_stats {
161	u64 tx_packets;
162	u64 tx_bytes;
163	u64 rx_packets;
164	u64 rx_bytes;
165	struct u64_stats_sync syncp;
166};
167
168struct am65_cpsw_ndev_priv {
169	u32			msg_enable;
170	struct am65_cpsw_port	*port;
171	struct am65_cpsw_ndev_stats __percpu *stats;
172	bool offload_fwd_mark;
173};
174
175#define am65_ndev_to_priv(ndev) \
176	((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
177#define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
178#define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
179#define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
180
181#define am65_common_get_host(common) (&(common)->host)
182#define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
183
184#define am65_cpsw_napi_to_common(pnapi) \
185	container_of(pnapi, struct am65_cpsw_common, napi_rx)
186#define am65_cpsw_napi_to_tx_chn(pnapi) \
187	container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
188
189#define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
190
191#define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
192
193extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
194
195void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
196void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
197int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
198
199bool am65_cpsw_port_dev_check(const struct net_device *dev);
200
201#endif /* AM65_CPSW_NUSS_H_ */
202