1// SPDX-License-Identifier: GPL-2.0 2/* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11#include <linux/cache.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/etherdevice.h> 17#include <linux/ethtool.h> 18#include <linux/if_vlan.h> 19#include <linux/kernel.h> 20#include <linux/list.h> 21#include <linux/module.h> 22#include <linux/net_tstamp.h> 23#include <linux/of.h> 24#include <linux/of_mdio.h> 25#include <linux/of_net.h> 26#include <linux/platform_device.h> 27#include <linux/pm_runtime.h> 28#include <linux/slab.h> 29#include <linux/spinlock.h> 30#include <linux/reset.h> 31#include <linux/math64.h> 32 33#include "ravb.h" 34 35#define RAVB_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 41static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 42 "ch0", /* RAVB_BE */ 43 "ch1", /* RAVB_NC */ 44}; 45 46static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 47 "ch18", /* RAVB_BE */ 48 "ch19", /* RAVB_NC */ 49}; 50 51void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 52 u32 set) 53{ 54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 55} 56 57int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 58{ 59 int i; 60 61 for (i = 0; i < 10000; i++) { 62 if ((ravb_read(ndev, reg) & mask) == value) 63 return 0; 64 udelay(10); 65 } 66 return -ETIMEDOUT; 67} 68 69static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 70{ 71 u32 csr_ops = 1U << (opmode & CCC_OPC); 72 u32 ccc_mask = CCC_OPC; 73 int error; 74 75 /* If gPTP active in config mode is supported it needs to be configured 76 * along with CSEL and operating mode in the same access. This is a 77 * hardware limitation. 78 */ 79 if (opmode & CCC_GAC) 80 ccc_mask |= CCC_GAC | CCC_CSEL; 81 82 /* Set operating mode */ 83 ravb_modify(ndev, CCC, ccc_mask, opmode); 84 /* Check if the operating mode is changed to the requested one */ 85 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 86 if (error) { 87 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 88 opmode & CCC_OPC); 89 } 90 91 return error; 92} 93 94static void ravb_set_rate_gbeth(struct net_device *ndev) 95{ 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 10: /* 10BASE */ 100 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 101 break; 102 case 100: /* 100BASE */ 103 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 104 break; 105 case 1000: /* 1000BASE */ 106 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 107 break; 108 } 109} 110 111static void ravb_set_rate_rcar(struct net_device *ndev) 112{ 113 struct ravb_private *priv = netdev_priv(ndev); 114 115 switch (priv->speed) { 116 case 100: /* 100BASE */ 117 ravb_write(ndev, GECMR_SPEED_100, GECMR); 118 break; 119 case 1000: /* 1000BASE */ 120 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 121 break; 122 } 123} 124 125static void ravb_set_buffer_align(struct sk_buff *skb) 126{ 127 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 128 129 if (reserve) 130 skb_reserve(skb, RAVB_ALIGN - reserve); 131} 132 133/* Get MAC address from the MAC address registers 134 * 135 * Ethernet AVB device doesn't have ROM for MAC address. 136 * This function gets the MAC address that was used by a bootloader. 137 */ 138static void ravb_read_mac_address(struct device_node *np, 139 struct net_device *ndev) 140{ 141 int ret; 142 143 ret = of_get_ethdev_address(np, ndev); 144 if (ret) { 145 u32 mahr = ravb_read(ndev, MAHR); 146 u32 malr = ravb_read(ndev, MALR); 147 u8 addr[ETH_ALEN]; 148 149 addr[0] = (mahr >> 24) & 0xFF; 150 addr[1] = (mahr >> 16) & 0xFF; 151 addr[2] = (mahr >> 8) & 0xFF; 152 addr[3] = (mahr >> 0) & 0xFF; 153 addr[4] = (malr >> 8) & 0xFF; 154 addr[5] = (malr >> 0) & 0xFF; 155 eth_hw_addr_set(ndev, addr); 156 } 157} 158 159static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 160{ 161 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 162 mdiobb); 163 164 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 165} 166 167/* MDC pin control */ 168static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 169{ 170 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 171} 172 173/* Data I/O pin control */ 174static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 175{ 176 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 177} 178 179/* Set data bit */ 180static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 181{ 182 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 183} 184 185/* Get data bit */ 186static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 187{ 188 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 189 mdiobb); 190 191 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 192} 193 194/* MDIO bus control struct */ 195static const struct mdiobb_ops bb_ops = { 196 .owner = THIS_MODULE, 197 .set_mdc = ravb_set_mdc, 198 .set_mdio_dir = ravb_set_mdio_dir, 199 .set_mdio_data = ravb_set_mdio_data, 200 .get_mdio_data = ravb_get_mdio_data, 201}; 202 203/* Free TX skb function for AVB-IP */ 204static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 205{ 206 struct ravb_private *priv = netdev_priv(ndev); 207 struct net_device_stats *stats = &priv->stats[q]; 208 unsigned int num_tx_desc = priv->num_tx_desc; 209 struct ravb_tx_desc *desc; 210 unsigned int entry; 211 int free_num = 0; 212 u32 size; 213 214 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 215 bool txed; 216 217 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 218 num_tx_desc); 219 desc = &priv->tx_ring[q][entry]; 220 txed = desc->die_dt == DT_FEMPTY; 221 if (free_txed_only && !txed) 222 break; 223 /* Descriptor type must be checked before all other reads */ 224 dma_rmb(); 225 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 226 /* Free the original skb. */ 227 if (priv->tx_skb[q][entry / num_tx_desc]) { 228 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 229 size, DMA_TO_DEVICE); 230 /* Last packet descriptor? */ 231 if (entry % num_tx_desc == num_tx_desc - 1) { 232 entry /= num_tx_desc; 233 dev_kfree_skb_any(priv->tx_skb[q][entry]); 234 priv->tx_skb[q][entry] = NULL; 235 if (txed) 236 stats->tx_packets++; 237 } 238 free_num++; 239 } 240 if (txed) 241 stats->tx_bytes += size; 242 desc->die_dt = DT_EEMPTY; 243 } 244 return free_num; 245} 246 247static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 248{ 249 struct ravb_private *priv = netdev_priv(ndev); 250 unsigned int ring_size; 251 unsigned int i; 252 253 if (!priv->gbeth_rx_ring) 254 return; 255 256 for (i = 0; i < priv->num_rx_ring[q]; i++) { 257 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 258 259 if (!dma_mapping_error(ndev->dev.parent, 260 le32_to_cpu(desc->dptr))) 261 dma_unmap_single(ndev->dev.parent, 262 le32_to_cpu(desc->dptr), 263 GBETH_RX_BUFF_MAX, 264 DMA_FROM_DEVICE); 265 } 266 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 268 priv->rx_desc_dma[q]); 269 priv->gbeth_rx_ring = NULL; 270} 271 272static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 273{ 274 struct ravb_private *priv = netdev_priv(ndev); 275 unsigned int ring_size; 276 unsigned int i; 277 278 if (!priv->rx_ring[q]) 279 return; 280 281 for (i = 0; i < priv->num_rx_ring[q]; i++) { 282 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 283 284 if (!dma_mapping_error(ndev->dev.parent, 285 le32_to_cpu(desc->dptr))) 286 dma_unmap_single(ndev->dev.parent, 287 le32_to_cpu(desc->dptr), 288 RX_BUF_SZ, 289 DMA_FROM_DEVICE); 290 } 291 ring_size = sizeof(struct ravb_ex_rx_desc) * 292 (priv->num_rx_ring[q] + 1); 293 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 294 priv->rx_desc_dma[q]); 295 priv->rx_ring[q] = NULL; 296} 297 298/* Free skb's and DMA buffers for Ethernet AVB */ 299static void ravb_ring_free(struct net_device *ndev, int q) 300{ 301 struct ravb_private *priv = netdev_priv(ndev); 302 const struct ravb_hw_info *info = priv->info; 303 unsigned int num_tx_desc = priv->num_tx_desc; 304 unsigned int ring_size; 305 unsigned int i; 306 307 info->rx_ring_free(ndev, q); 308 309 if (priv->tx_ring[q]) { 310 ravb_tx_free(ndev, q, false); 311 312 ring_size = sizeof(struct ravb_tx_desc) * 313 (priv->num_tx_ring[q] * num_tx_desc + 1); 314 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 315 priv->tx_desc_dma[q]); 316 priv->tx_ring[q] = NULL; 317 } 318 319 /* Free RX skb ringbuffer */ 320 if (priv->rx_skb[q]) { 321 for (i = 0; i < priv->num_rx_ring[q]; i++) 322 dev_kfree_skb(priv->rx_skb[q][i]); 323 } 324 kfree(priv->rx_skb[q]); 325 priv->rx_skb[q] = NULL; 326 327 /* Free aligned TX buffers */ 328 kfree(priv->tx_align[q]); 329 priv->tx_align[q] = NULL; 330 331 /* Free TX skb ringbuffer. 332 * SKBs are freed by ravb_tx_free() call above. 333 */ 334 kfree(priv->tx_skb[q]); 335 priv->tx_skb[q] = NULL; 336} 337 338static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 339{ 340 struct ravb_private *priv = netdev_priv(ndev); 341 struct ravb_rx_desc *rx_desc; 342 unsigned int rx_ring_size; 343 dma_addr_t dma_addr; 344 unsigned int i; 345 346 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 347 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 348 /* Build RX ring buffer */ 349 for (i = 0; i < priv->num_rx_ring[q]; i++) { 350 /* RX descriptor */ 351 rx_desc = &priv->gbeth_rx_ring[i]; 352 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 353 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 354 GBETH_RX_BUFF_MAX, 355 DMA_FROM_DEVICE); 356 /* We just set the data size to 0 for a failed mapping which 357 * should prevent DMA from happening... 358 */ 359 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 360 rx_desc->ds_cc = cpu_to_le16(0); 361 rx_desc->dptr = cpu_to_le32(dma_addr); 362 rx_desc->die_dt = DT_FEMPTY; 363 } 364 rx_desc = &priv->gbeth_rx_ring[i]; 365 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 366 rx_desc->die_dt = DT_LINKFIX; /* type */ 367} 368 369static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 370{ 371 struct ravb_private *priv = netdev_priv(ndev); 372 struct ravb_ex_rx_desc *rx_desc; 373 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 374 dma_addr_t dma_addr; 375 unsigned int i; 376 377 memset(priv->rx_ring[q], 0, rx_ring_size); 378 /* Build RX ring buffer */ 379 for (i = 0; i < priv->num_rx_ring[q]; i++) { 380 /* RX descriptor */ 381 rx_desc = &priv->rx_ring[q][i]; 382 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 383 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 384 RX_BUF_SZ, 385 DMA_FROM_DEVICE); 386 /* We just set the data size to 0 for a failed mapping which 387 * should prevent DMA from happening... 388 */ 389 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 390 rx_desc->ds_cc = cpu_to_le16(0); 391 rx_desc->dptr = cpu_to_le32(dma_addr); 392 rx_desc->die_dt = DT_FEMPTY; 393 } 394 rx_desc = &priv->rx_ring[q][i]; 395 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 rx_desc->die_dt = DT_LINKFIX; /* type */ 397} 398 399/* Format skb and descriptor buffer for Ethernet AVB */ 400static void ravb_ring_format(struct net_device *ndev, int q) 401{ 402 struct ravb_private *priv = netdev_priv(ndev); 403 const struct ravb_hw_info *info = priv->info; 404 unsigned int num_tx_desc = priv->num_tx_desc; 405 struct ravb_tx_desc *tx_desc; 406 struct ravb_desc *desc; 407 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 408 num_tx_desc; 409 unsigned int i; 410 411 priv->cur_rx[q] = 0; 412 priv->cur_tx[q] = 0; 413 priv->dirty_rx[q] = 0; 414 priv->dirty_tx[q] = 0; 415 416 info->rx_ring_format(ndev, q); 417 418 memset(priv->tx_ring[q], 0, tx_ring_size); 419 /* Build TX ring buffer */ 420 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 421 i++, tx_desc++) { 422 tx_desc->die_dt = DT_EEMPTY; 423 if (num_tx_desc > 1) { 424 tx_desc++; 425 tx_desc->die_dt = DT_EEMPTY; 426 } 427 } 428 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 429 tx_desc->die_dt = DT_LINKFIX; /* type */ 430 431 /* RX descriptor base address for best effort */ 432 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 433 desc->die_dt = DT_LINKFIX; /* type */ 434 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 435 436 /* TX descriptor base address for best effort */ 437 desc = &priv->desc_bat[q]; 438 desc->die_dt = DT_LINKFIX; /* type */ 439 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 440} 441 442static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 443{ 444 struct ravb_private *priv = netdev_priv(ndev); 445 unsigned int ring_size; 446 447 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 448 449 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 450 &priv->rx_desc_dma[q], 451 GFP_KERNEL); 452 return priv->gbeth_rx_ring; 453} 454 455static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 456{ 457 struct ravb_private *priv = netdev_priv(ndev); 458 unsigned int ring_size; 459 460 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 461 462 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 463 &priv->rx_desc_dma[q], 464 GFP_KERNEL); 465 return priv->rx_ring[q]; 466} 467 468/* Init skb and descriptor buffer for Ethernet AVB */ 469static int ravb_ring_init(struct net_device *ndev, int q) 470{ 471 struct ravb_private *priv = netdev_priv(ndev); 472 const struct ravb_hw_info *info = priv->info; 473 unsigned int num_tx_desc = priv->num_tx_desc; 474 unsigned int ring_size; 475 struct sk_buff *skb; 476 unsigned int i; 477 478 /* Allocate RX and TX skb rings */ 479 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 480 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 481 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 482 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 483 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 484 goto error; 485 486 for (i = 0; i < priv->num_rx_ring[q]; i++) { 487 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 488 if (!skb) 489 goto error; 490 ravb_set_buffer_align(skb); 491 priv->rx_skb[q][i] = skb; 492 } 493 494 if (num_tx_desc > 1) { 495 /* Allocate rings for the aligned buffers */ 496 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 497 DPTR_ALIGN - 1, GFP_KERNEL); 498 if (!priv->tx_align[q]) 499 goto error; 500 } 501 502 /* Allocate all RX descriptors. */ 503 if (!info->alloc_rx_desc(ndev, q)) 504 goto error; 505 506 priv->dirty_rx[q] = 0; 507 508 /* Allocate all TX descriptors. */ 509 ring_size = sizeof(struct ravb_tx_desc) * 510 (priv->num_tx_ring[q] * num_tx_desc + 1); 511 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 512 &priv->tx_desc_dma[q], 513 GFP_KERNEL); 514 if (!priv->tx_ring[q]) 515 goto error; 516 517 return 0; 518 519error: 520 ravb_ring_free(ndev, q); 521 522 return -ENOMEM; 523} 524 525static void ravb_emac_init_gbeth(struct net_device *ndev) 526{ 527 struct ravb_private *priv = netdev_priv(ndev); 528 529 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 530 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 531 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 532 } else { 533 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 534 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 535 CXR31_SEL_LINK0); 536 } 537 538 /* Receive frame limit set register */ 539 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 540 541 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 542 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 543 ECMR_TE | ECMR_RE | ECMR_RCPT | 544 ECMR_TXF | ECMR_RXF, ECMR); 545 546 ravb_set_rate_gbeth(ndev); 547 548 /* Set MAC address */ 549 ravb_write(ndev, 550 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 551 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 552 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 553 554 /* E-MAC status register clear */ 555 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 556 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 557 558 /* E-MAC interrupt enable register */ 559 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 560} 561 562static void ravb_emac_init_rcar(struct net_device *ndev) 563{ 564 /* Receive frame limit set register */ 565 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 566 567 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 568 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 569 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 570 ECMR_TE | ECMR_RE, ECMR); 571 572 ravb_set_rate_rcar(ndev); 573 574 /* Set MAC address */ 575 ravb_write(ndev, 576 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 577 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 578 ravb_write(ndev, 579 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 580 581 /* E-MAC status register clear */ 582 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 583 584 /* E-MAC interrupt enable register */ 585 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 586} 587 588/* E-MAC init function */ 589static void ravb_emac_init(struct net_device *ndev) 590{ 591 struct ravb_private *priv = netdev_priv(ndev); 592 const struct ravb_hw_info *info = priv->info; 593 594 info->emac_init(ndev); 595} 596 597static int ravb_dmac_init_gbeth(struct net_device *ndev) 598{ 599 int error; 600 601 error = ravb_ring_init(ndev, RAVB_BE); 602 if (error) 603 return error; 604 605 /* Descriptor format */ 606 ravb_ring_format(ndev, RAVB_BE); 607 608 /* Set DMAC RX */ 609 ravb_write(ndev, 0x60000000, RCR); 610 611 /* Set Max Frame Length (RTC) */ 612 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 613 614 /* Set FIFO size */ 615 ravb_write(ndev, 0x00222200, TGC); 616 617 ravb_write(ndev, 0, TCCR); 618 619 /* Frame receive */ 620 ravb_write(ndev, RIC0_FRE0, RIC0); 621 /* Disable FIFO full warning */ 622 ravb_write(ndev, 0x0, RIC1); 623 /* Receive FIFO full error, descriptor empty */ 624 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 625 626 ravb_write(ndev, TIC_FTE0, TIC); 627 628 return 0; 629} 630 631static int ravb_dmac_init_rcar(struct net_device *ndev) 632{ 633 struct ravb_private *priv = netdev_priv(ndev); 634 const struct ravb_hw_info *info = priv->info; 635 int error; 636 637 error = ravb_ring_init(ndev, RAVB_BE); 638 if (error) 639 return error; 640 error = ravb_ring_init(ndev, RAVB_NC); 641 if (error) { 642 ravb_ring_free(ndev, RAVB_BE); 643 return error; 644 } 645 646 /* Descriptor format */ 647 ravb_ring_format(ndev, RAVB_BE); 648 ravb_ring_format(ndev, RAVB_NC); 649 650 /* Set AVB RX */ 651 ravb_write(ndev, 652 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 653 654 /* Set FIFO size */ 655 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 656 657 /* Timestamp enable */ 658 ravb_write(ndev, TCCR_TFEN, TCCR); 659 660 /* Interrupt init: */ 661 if (info->multi_irqs) { 662 /* Clear DIL.DPLx */ 663 ravb_write(ndev, 0, DIL); 664 /* Set queue specific interrupt */ 665 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 666 } 667 /* Frame receive */ 668 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 669 /* Disable FIFO full warning */ 670 ravb_write(ndev, 0, RIC1); 671 /* Receive FIFO full error, descriptor empty */ 672 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 673 /* Frame transmitted, timestamp FIFO updated */ 674 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 675 676 return 0; 677} 678 679/* Device init function for Ethernet AVB */ 680static int ravb_dmac_init(struct net_device *ndev) 681{ 682 struct ravb_private *priv = netdev_priv(ndev); 683 const struct ravb_hw_info *info = priv->info; 684 int error; 685 686 /* Set CONFIG mode */ 687 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 688 if (error) 689 return error; 690 691 error = info->dmac_init(ndev); 692 if (error) 693 return error; 694 695 /* Setting the control will start the AVB-DMAC process. */ 696 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 697} 698 699static void ravb_get_tx_tstamp(struct net_device *ndev) 700{ 701 struct ravb_private *priv = netdev_priv(ndev); 702 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 703 struct skb_shared_hwtstamps shhwtstamps; 704 struct sk_buff *skb; 705 struct timespec64 ts; 706 u16 tag, tfa_tag; 707 int count; 708 u32 tfa2; 709 710 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 711 while (count--) { 712 tfa2 = ravb_read(ndev, TFA2); 713 tfa_tag = (tfa2 & TFA2_TST) >> 16; 714 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 715 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 716 ravb_read(ndev, TFA1); 717 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 718 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 719 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 720 list) { 721 skb = ts_skb->skb; 722 tag = ts_skb->tag; 723 list_del(&ts_skb->list); 724 kfree(ts_skb); 725 if (tag == tfa_tag) { 726 skb_tstamp_tx(skb, &shhwtstamps); 727 dev_consume_skb_any(skb); 728 break; 729 } else { 730 dev_kfree_skb_any(skb); 731 } 732 } 733 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 734 } 735} 736 737static void ravb_rx_csum(struct sk_buff *skb) 738{ 739 u8 *hw_csum; 740 741 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 742 * appended to packet data 743 */ 744 if (unlikely(skb->len < sizeof(__sum16))) 745 return; 746 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 747 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 748 skb->ip_summed = CHECKSUM_COMPLETE; 749 skb_trim(skb, skb->len - sizeof(__sum16)); 750} 751 752static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 753 struct ravb_rx_desc *desc) 754{ 755 struct ravb_private *priv = netdev_priv(ndev); 756 struct sk_buff *skb; 757 758 skb = priv->rx_skb[RAVB_BE][entry]; 759 priv->rx_skb[RAVB_BE][entry] = NULL; 760 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 761 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 762 763 return skb; 764} 765 766/* Packet receive function for Gigabit Ethernet */ 767static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 768{ 769 struct ravb_private *priv = netdev_priv(ndev); 770 const struct ravb_hw_info *info = priv->info; 771 struct net_device_stats *stats; 772 struct ravb_rx_desc *desc; 773 struct sk_buff *skb; 774 dma_addr_t dma_addr; 775 u8 desc_status; 776 int boguscnt; 777 u16 pkt_len; 778 u8 die_dt; 779 int entry; 780 int limit; 781 782 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 783 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 784 stats = &priv->stats[q]; 785 786 boguscnt = min(boguscnt, *quota); 787 limit = boguscnt; 788 desc = &priv->gbeth_rx_ring[entry]; 789 while (desc->die_dt != DT_FEMPTY) { 790 /* Descriptor type must be checked before all other reads */ 791 dma_rmb(); 792 desc_status = desc->msc; 793 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 794 795 if (--boguscnt < 0) 796 break; 797 798 /* We use 0-byte descriptors to mark the DMA mapping errors */ 799 if (!pkt_len) 800 continue; 801 802 if (desc_status & MSC_MC) 803 stats->multicast++; 804 805 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 806 stats->rx_errors++; 807 if (desc_status & MSC_CRC) 808 stats->rx_crc_errors++; 809 if (desc_status & MSC_RFE) 810 stats->rx_frame_errors++; 811 if (desc_status & (MSC_RTLF | MSC_RTSF)) 812 stats->rx_length_errors++; 813 if (desc_status & MSC_CEEF) 814 stats->rx_missed_errors++; 815 } else { 816 die_dt = desc->die_dt & 0xF0; 817 switch (die_dt) { 818 case DT_FSINGLE: 819 skb = ravb_get_skb_gbeth(ndev, entry, desc); 820 skb_put(skb, pkt_len); 821 skb->protocol = eth_type_trans(skb, ndev); 822 napi_gro_receive(&priv->napi[q], skb); 823 stats->rx_packets++; 824 stats->rx_bytes += pkt_len; 825 break; 826 case DT_FSTART: 827 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 828 skb_put(priv->rx_1st_skb, pkt_len); 829 break; 830 case DT_FMID: 831 skb = ravb_get_skb_gbeth(ndev, entry, desc); 832 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 833 priv->rx_1st_skb->len, 834 skb->data, 835 pkt_len); 836 skb_put(priv->rx_1st_skb, pkt_len); 837 dev_kfree_skb(skb); 838 break; 839 case DT_FEND: 840 skb = ravb_get_skb_gbeth(ndev, entry, desc); 841 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 842 priv->rx_1st_skb->len, 843 skb->data, 844 pkt_len); 845 skb_put(priv->rx_1st_skb, pkt_len); 846 dev_kfree_skb(skb); 847 priv->rx_1st_skb->protocol = 848 eth_type_trans(priv->rx_1st_skb, ndev); 849 napi_gro_receive(&priv->napi[q], 850 priv->rx_1st_skb); 851 stats->rx_packets++; 852 stats->rx_bytes += pkt_len; 853 break; 854 } 855 } 856 857 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 858 desc = &priv->gbeth_rx_ring[entry]; 859 } 860 861 /* Refill the RX ring buffers. */ 862 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 863 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 864 desc = &priv->gbeth_rx_ring[entry]; 865 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 866 867 if (!priv->rx_skb[q][entry]) { 868 skb = netdev_alloc_skb(ndev, info->max_rx_len); 869 if (!skb) 870 break; 871 ravb_set_buffer_align(skb); 872 dma_addr = dma_map_single(ndev->dev.parent, 873 skb->data, 874 GBETH_RX_BUFF_MAX, 875 DMA_FROM_DEVICE); 876 skb_checksum_none_assert(skb); 877 /* We just set the data size to 0 for a failed mapping 878 * which should prevent DMA from happening... 879 */ 880 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 881 desc->ds_cc = cpu_to_le16(0); 882 desc->dptr = cpu_to_le32(dma_addr); 883 priv->rx_skb[q][entry] = skb; 884 } 885 /* Descriptor type must be set after all the above writes */ 886 dma_wmb(); 887 desc->die_dt = DT_FEMPTY; 888 } 889 890 *quota -= limit - (++boguscnt); 891 892 return boguscnt <= 0; 893} 894 895/* Packet receive function for Ethernet AVB */ 896static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 897{ 898 struct ravb_private *priv = netdev_priv(ndev); 899 const struct ravb_hw_info *info = priv->info; 900 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 901 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 902 priv->cur_rx[q]; 903 struct net_device_stats *stats = &priv->stats[q]; 904 struct ravb_ex_rx_desc *desc; 905 struct sk_buff *skb; 906 dma_addr_t dma_addr; 907 struct timespec64 ts; 908 u8 desc_status; 909 u16 pkt_len; 910 int limit; 911 912 boguscnt = min(boguscnt, *quota); 913 limit = boguscnt; 914 desc = &priv->rx_ring[q][entry]; 915 while (desc->die_dt != DT_FEMPTY) { 916 /* Descriptor type must be checked before all other reads */ 917 dma_rmb(); 918 desc_status = desc->msc; 919 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 920 921 if (--boguscnt < 0) 922 break; 923 924 /* We use 0-byte descriptors to mark the DMA mapping errors */ 925 if (!pkt_len) 926 continue; 927 928 if (desc_status & MSC_MC) 929 stats->multicast++; 930 931 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 932 MSC_CEEF)) { 933 stats->rx_errors++; 934 if (desc_status & MSC_CRC) 935 stats->rx_crc_errors++; 936 if (desc_status & MSC_RFE) 937 stats->rx_frame_errors++; 938 if (desc_status & (MSC_RTLF | MSC_RTSF)) 939 stats->rx_length_errors++; 940 if (desc_status & MSC_CEEF) 941 stats->rx_missed_errors++; 942 } else { 943 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 944 945 skb = priv->rx_skb[q][entry]; 946 priv->rx_skb[q][entry] = NULL; 947 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 948 RX_BUF_SZ, 949 DMA_FROM_DEVICE); 950 get_ts &= (q == RAVB_NC) ? 951 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 952 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 953 if (get_ts) { 954 struct skb_shared_hwtstamps *shhwtstamps; 955 956 shhwtstamps = skb_hwtstamps(skb); 957 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 958 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 959 32) | le32_to_cpu(desc->ts_sl); 960 ts.tv_nsec = le32_to_cpu(desc->ts_n); 961 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 962 } 963 964 skb_put(skb, pkt_len); 965 skb->protocol = eth_type_trans(skb, ndev); 966 if (ndev->features & NETIF_F_RXCSUM) 967 ravb_rx_csum(skb); 968 napi_gro_receive(&priv->napi[q], skb); 969 stats->rx_packets++; 970 stats->rx_bytes += pkt_len; 971 } 972 973 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 974 desc = &priv->rx_ring[q][entry]; 975 } 976 977 /* Refill the RX ring buffers. */ 978 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 979 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 980 desc = &priv->rx_ring[q][entry]; 981 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 982 983 if (!priv->rx_skb[q][entry]) { 984 skb = netdev_alloc_skb(ndev, info->max_rx_len); 985 if (!skb) 986 break; /* Better luck next round. */ 987 ravb_set_buffer_align(skb); 988 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 989 le16_to_cpu(desc->ds_cc), 990 DMA_FROM_DEVICE); 991 skb_checksum_none_assert(skb); 992 /* We just set the data size to 0 for a failed mapping 993 * which should prevent DMA from happening... 994 */ 995 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 996 desc->ds_cc = cpu_to_le16(0); 997 desc->dptr = cpu_to_le32(dma_addr); 998 priv->rx_skb[q][entry] = skb; 999 } 1000 /* Descriptor type must be set after all the above writes */ 1001 dma_wmb(); 1002 desc->die_dt = DT_FEMPTY; 1003 } 1004 1005 *quota -= limit - (++boguscnt); 1006 1007 return boguscnt <= 0; 1008} 1009 1010/* Packet receive function for Ethernet AVB */ 1011static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1012{ 1013 struct ravb_private *priv = netdev_priv(ndev); 1014 const struct ravb_hw_info *info = priv->info; 1015 1016 return info->receive(ndev, quota, q); 1017} 1018 1019static void ravb_rcv_snd_disable(struct net_device *ndev) 1020{ 1021 /* Disable TX and RX */ 1022 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1023} 1024 1025static void ravb_rcv_snd_enable(struct net_device *ndev) 1026{ 1027 /* Enable TX and RX */ 1028 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1029} 1030 1031/* function for waiting dma process finished */ 1032static int ravb_stop_dma(struct net_device *ndev) 1033{ 1034 struct ravb_private *priv = netdev_priv(ndev); 1035 const struct ravb_hw_info *info = priv->info; 1036 int error; 1037 1038 /* Wait for stopping the hardware TX process */ 1039 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1040 1041 if (error) 1042 return error; 1043 1044 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1045 0); 1046 if (error) 1047 return error; 1048 1049 /* Stop the E-MAC's RX/TX processes. */ 1050 ravb_rcv_snd_disable(ndev); 1051 1052 /* Wait for stopping the RX DMA process */ 1053 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1054 if (error) 1055 return error; 1056 1057 /* Stop AVB-DMAC process */ 1058 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1059} 1060 1061/* E-MAC interrupt handler */ 1062static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1063{ 1064 struct ravb_private *priv = netdev_priv(ndev); 1065 u32 ecsr, psr; 1066 1067 ecsr = ravb_read(ndev, ECSR); 1068 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1069 1070 if (ecsr & ECSR_MPD) 1071 pm_wakeup_event(&priv->pdev->dev, 0); 1072 if (ecsr & ECSR_ICD) 1073 ndev->stats.tx_carrier_errors++; 1074 if (ecsr & ECSR_LCHNG) { 1075 /* Link changed */ 1076 if (priv->no_avb_link) 1077 return; 1078 psr = ravb_read(ndev, PSR); 1079 if (priv->avb_link_active_low) 1080 psr ^= PSR_LMON; 1081 if (!(psr & PSR_LMON)) { 1082 /* DIsable RX and TX */ 1083 ravb_rcv_snd_disable(ndev); 1084 } else { 1085 /* Enable RX and TX */ 1086 ravb_rcv_snd_enable(ndev); 1087 } 1088 } 1089} 1090 1091static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1092{ 1093 struct net_device *ndev = dev_id; 1094 struct ravb_private *priv = netdev_priv(ndev); 1095 1096 spin_lock(&priv->lock); 1097 ravb_emac_interrupt_unlocked(ndev); 1098 spin_unlock(&priv->lock); 1099 return IRQ_HANDLED; 1100} 1101 1102/* Error interrupt handler */ 1103static void ravb_error_interrupt(struct net_device *ndev) 1104{ 1105 struct ravb_private *priv = netdev_priv(ndev); 1106 u32 eis, ris2; 1107 1108 eis = ravb_read(ndev, EIS); 1109 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1110 if (eis & EIS_QFS) { 1111 ris2 = ravb_read(ndev, RIS2); 1112 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1113 RIS2); 1114 1115 /* Receive Descriptor Empty int */ 1116 if (ris2 & RIS2_QFF0) 1117 priv->stats[RAVB_BE].rx_over_errors++; 1118 1119 /* Receive Descriptor Empty int */ 1120 if (ris2 & RIS2_QFF1) 1121 priv->stats[RAVB_NC].rx_over_errors++; 1122 1123 /* Receive FIFO Overflow int */ 1124 if (ris2 & RIS2_RFFF) 1125 priv->rx_fifo_errors++; 1126 } 1127} 1128 1129static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1130{ 1131 struct ravb_private *priv = netdev_priv(ndev); 1132 const struct ravb_hw_info *info = priv->info; 1133 u32 ris0 = ravb_read(ndev, RIS0); 1134 u32 ric0 = ravb_read(ndev, RIC0); 1135 u32 tis = ravb_read(ndev, TIS); 1136 u32 tic = ravb_read(ndev, TIC); 1137 1138 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1139 if (napi_schedule_prep(&priv->napi[q])) { 1140 /* Mask RX and TX interrupts */ 1141 if (!info->irq_en_dis) { 1142 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1143 ravb_write(ndev, tic & ~BIT(q), TIC); 1144 } else { 1145 ravb_write(ndev, BIT(q), RID0); 1146 ravb_write(ndev, BIT(q), TID); 1147 } 1148 __napi_schedule(&priv->napi[q]); 1149 } else { 1150 netdev_warn(ndev, 1151 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1152 ris0, ric0); 1153 netdev_warn(ndev, 1154 " tx status 0x%08x, tx mask 0x%08x.\n", 1155 tis, tic); 1156 } 1157 return true; 1158 } 1159 return false; 1160} 1161 1162static bool ravb_timestamp_interrupt(struct net_device *ndev) 1163{ 1164 u32 tis = ravb_read(ndev, TIS); 1165 1166 if (tis & TIS_TFUF) { 1167 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1168 ravb_get_tx_tstamp(ndev); 1169 return true; 1170 } 1171 return false; 1172} 1173 1174static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1175{ 1176 struct net_device *ndev = dev_id; 1177 struct ravb_private *priv = netdev_priv(ndev); 1178 const struct ravb_hw_info *info = priv->info; 1179 irqreturn_t result = IRQ_NONE; 1180 u32 iss; 1181 1182 spin_lock(&priv->lock); 1183 /* Get interrupt status */ 1184 iss = ravb_read(ndev, ISS); 1185 1186 /* Received and transmitted interrupts */ 1187 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1188 int q; 1189 1190 /* Timestamp updated */ 1191 if (ravb_timestamp_interrupt(ndev)) 1192 result = IRQ_HANDLED; 1193 1194 /* Network control and best effort queue RX/TX */ 1195 if (info->nc_queues) { 1196 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1197 if (ravb_queue_interrupt(ndev, q)) 1198 result = IRQ_HANDLED; 1199 } 1200 } else { 1201 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1202 result = IRQ_HANDLED; 1203 } 1204 } 1205 1206 /* E-MAC status summary */ 1207 if (iss & ISS_MS) { 1208 ravb_emac_interrupt_unlocked(ndev); 1209 result = IRQ_HANDLED; 1210 } 1211 1212 /* Error status summary */ 1213 if (iss & ISS_ES) { 1214 ravb_error_interrupt(ndev); 1215 result = IRQ_HANDLED; 1216 } 1217 1218 /* gPTP interrupt status summary */ 1219 if (iss & ISS_CGIS) { 1220 ravb_ptp_interrupt(ndev); 1221 result = IRQ_HANDLED; 1222 } 1223 1224 spin_unlock(&priv->lock); 1225 return result; 1226} 1227 1228/* Timestamp/Error/gPTP interrupt handler */ 1229static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1230{ 1231 struct net_device *ndev = dev_id; 1232 struct ravb_private *priv = netdev_priv(ndev); 1233 irqreturn_t result = IRQ_NONE; 1234 u32 iss; 1235 1236 spin_lock(&priv->lock); 1237 /* Get interrupt status */ 1238 iss = ravb_read(ndev, ISS); 1239 1240 /* Timestamp updated */ 1241 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1242 result = IRQ_HANDLED; 1243 1244 /* Error status summary */ 1245 if (iss & ISS_ES) { 1246 ravb_error_interrupt(ndev); 1247 result = IRQ_HANDLED; 1248 } 1249 1250 /* gPTP interrupt status summary */ 1251 if (iss & ISS_CGIS) { 1252 ravb_ptp_interrupt(ndev); 1253 result = IRQ_HANDLED; 1254 } 1255 1256 spin_unlock(&priv->lock); 1257 return result; 1258} 1259 1260static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1261{ 1262 struct net_device *ndev = dev_id; 1263 struct ravb_private *priv = netdev_priv(ndev); 1264 irqreturn_t result = IRQ_NONE; 1265 1266 spin_lock(&priv->lock); 1267 1268 /* Network control/Best effort queue RX/TX */ 1269 if (ravb_queue_interrupt(ndev, q)) 1270 result = IRQ_HANDLED; 1271 1272 spin_unlock(&priv->lock); 1273 return result; 1274} 1275 1276static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1277{ 1278 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1279} 1280 1281static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1282{ 1283 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1284} 1285 1286static int ravb_poll(struct napi_struct *napi, int budget) 1287{ 1288 struct net_device *ndev = napi->dev; 1289 struct ravb_private *priv = netdev_priv(ndev); 1290 const struct ravb_hw_info *info = priv->info; 1291 bool gptp = info->gptp || info->ccc_gac; 1292 struct ravb_rx_desc *desc; 1293 unsigned long flags; 1294 int q = napi - priv->napi; 1295 int mask = BIT(q); 1296 int quota = budget; 1297 unsigned int entry; 1298 1299 if (!gptp) { 1300 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1301 desc = &priv->gbeth_rx_ring[entry]; 1302 } 1303 /* Processing RX Descriptor Ring */ 1304 /* Clear RX interrupt */ 1305 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1306 if (gptp || desc->die_dt != DT_FEMPTY) { 1307 if (ravb_rx(ndev, "a, q)) 1308 goto out; 1309 } 1310 1311 /* Processing TX Descriptor Ring */ 1312 spin_lock_irqsave(&priv->lock, flags); 1313 /* Clear TX interrupt */ 1314 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1315 ravb_tx_free(ndev, q, true); 1316 netif_wake_subqueue(ndev, q); 1317 spin_unlock_irqrestore(&priv->lock, flags); 1318 1319 napi_complete(napi); 1320 1321 /* Re-enable RX/TX interrupts */ 1322 spin_lock_irqsave(&priv->lock, flags); 1323 if (!info->irq_en_dis) { 1324 ravb_modify(ndev, RIC0, mask, mask); 1325 ravb_modify(ndev, TIC, mask, mask); 1326 } else { 1327 ravb_write(ndev, mask, RIE0); 1328 ravb_write(ndev, mask, TIE); 1329 } 1330 spin_unlock_irqrestore(&priv->lock, flags); 1331 1332 /* Receive error message handling */ 1333 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1334 if (info->nc_queues) 1335 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1336 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1337 ndev->stats.rx_over_errors = priv->rx_over_errors; 1338 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1339 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1340out: 1341 return budget - quota; 1342} 1343 1344static void ravb_set_duplex_gbeth(struct net_device *ndev) 1345{ 1346 struct ravb_private *priv = netdev_priv(ndev); 1347 1348 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1349} 1350 1351/* PHY state control function */ 1352static void ravb_adjust_link(struct net_device *ndev) 1353{ 1354 struct ravb_private *priv = netdev_priv(ndev); 1355 const struct ravb_hw_info *info = priv->info; 1356 struct phy_device *phydev = ndev->phydev; 1357 bool new_state = false; 1358 unsigned long flags; 1359 1360 spin_lock_irqsave(&priv->lock, flags); 1361 1362 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1363 if (priv->no_avb_link) 1364 ravb_rcv_snd_disable(ndev); 1365 1366 if (phydev->link) { 1367 if (info->half_duplex && phydev->duplex != priv->duplex) { 1368 new_state = true; 1369 priv->duplex = phydev->duplex; 1370 ravb_set_duplex_gbeth(ndev); 1371 } 1372 1373 if (phydev->speed != priv->speed) { 1374 new_state = true; 1375 priv->speed = phydev->speed; 1376 info->set_rate(ndev); 1377 } 1378 if (!priv->link) { 1379 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1380 new_state = true; 1381 priv->link = phydev->link; 1382 } 1383 } else if (priv->link) { 1384 new_state = true; 1385 priv->link = 0; 1386 priv->speed = 0; 1387 if (info->half_duplex) 1388 priv->duplex = -1; 1389 } 1390 1391 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1392 if (priv->no_avb_link && phydev->link) 1393 ravb_rcv_snd_enable(ndev); 1394 1395 spin_unlock_irqrestore(&priv->lock, flags); 1396 1397 if (new_state && netif_msg_link(priv)) 1398 phy_print_status(phydev); 1399} 1400 1401/* PHY init function */ 1402static int ravb_phy_init(struct net_device *ndev) 1403{ 1404 struct device_node *np = ndev->dev.parent->of_node; 1405 struct ravb_private *priv = netdev_priv(ndev); 1406 const struct ravb_hw_info *info = priv->info; 1407 struct phy_device *phydev; 1408 struct device_node *pn; 1409 phy_interface_t iface; 1410 int err; 1411 1412 priv->link = 0; 1413 priv->speed = 0; 1414 priv->duplex = -1; 1415 1416 /* Try connecting to PHY */ 1417 pn = of_parse_phandle(np, "phy-handle", 0); 1418 if (!pn) { 1419 /* In the case of a fixed PHY, the DT node associated 1420 * to the PHY is the Ethernet MAC DT node. 1421 */ 1422 if (of_phy_is_fixed_link(np)) { 1423 err = of_phy_register_fixed_link(np); 1424 if (err) 1425 return err; 1426 } 1427 pn = of_node_get(np); 1428 } 1429 1430 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1431 : priv->phy_interface; 1432 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1433 of_node_put(pn); 1434 if (!phydev) { 1435 netdev_err(ndev, "failed to connect PHY\n"); 1436 err = -ENOENT; 1437 goto err_deregister_fixed_link; 1438 } 1439 1440 if (!info->half_duplex) { 1441 /* 10BASE, Pause and Asym Pause is not supported */ 1442 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1443 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1444 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1445 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1446 1447 /* Half Duplex is not supported */ 1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1449 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1450 } 1451 1452 phy_attached_info(phydev); 1453 1454 return 0; 1455 1456err_deregister_fixed_link: 1457 if (of_phy_is_fixed_link(np)) 1458 of_phy_deregister_fixed_link(np); 1459 1460 return err; 1461} 1462 1463/* PHY control start function */ 1464static int ravb_phy_start(struct net_device *ndev) 1465{ 1466 int error; 1467 1468 error = ravb_phy_init(ndev); 1469 if (error) 1470 return error; 1471 1472 phy_start(ndev->phydev); 1473 1474 return 0; 1475} 1476 1477static u32 ravb_get_msglevel(struct net_device *ndev) 1478{ 1479 struct ravb_private *priv = netdev_priv(ndev); 1480 1481 return priv->msg_enable; 1482} 1483 1484static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1485{ 1486 struct ravb_private *priv = netdev_priv(ndev); 1487 1488 priv->msg_enable = value; 1489} 1490 1491static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1492 "rx_queue_0_current", 1493 "tx_queue_0_current", 1494 "rx_queue_0_dirty", 1495 "tx_queue_0_dirty", 1496 "rx_queue_0_packets", 1497 "tx_queue_0_packets", 1498 "rx_queue_0_bytes", 1499 "tx_queue_0_bytes", 1500 "rx_queue_0_mcast_packets", 1501 "rx_queue_0_errors", 1502 "rx_queue_0_crc_errors", 1503 "rx_queue_0_frame_errors", 1504 "rx_queue_0_length_errors", 1505 "rx_queue_0_csum_offload_errors", 1506 "rx_queue_0_over_errors", 1507}; 1508 1509static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1510 "rx_queue_0_current", 1511 "tx_queue_0_current", 1512 "rx_queue_0_dirty", 1513 "tx_queue_0_dirty", 1514 "rx_queue_0_packets", 1515 "tx_queue_0_packets", 1516 "rx_queue_0_bytes", 1517 "tx_queue_0_bytes", 1518 "rx_queue_0_mcast_packets", 1519 "rx_queue_0_errors", 1520 "rx_queue_0_crc_errors", 1521 "rx_queue_0_frame_errors", 1522 "rx_queue_0_length_errors", 1523 "rx_queue_0_missed_errors", 1524 "rx_queue_0_over_errors", 1525 1526 "rx_queue_1_current", 1527 "tx_queue_1_current", 1528 "rx_queue_1_dirty", 1529 "tx_queue_1_dirty", 1530 "rx_queue_1_packets", 1531 "tx_queue_1_packets", 1532 "rx_queue_1_bytes", 1533 "tx_queue_1_bytes", 1534 "rx_queue_1_mcast_packets", 1535 "rx_queue_1_errors", 1536 "rx_queue_1_crc_errors", 1537 "rx_queue_1_frame_errors", 1538 "rx_queue_1_length_errors", 1539 "rx_queue_1_missed_errors", 1540 "rx_queue_1_over_errors", 1541}; 1542 1543static int ravb_get_sset_count(struct net_device *netdev, int sset) 1544{ 1545 struct ravb_private *priv = netdev_priv(netdev); 1546 const struct ravb_hw_info *info = priv->info; 1547 1548 switch (sset) { 1549 case ETH_SS_STATS: 1550 return info->stats_len; 1551 default: 1552 return -EOPNOTSUPP; 1553 } 1554} 1555 1556static void ravb_get_ethtool_stats(struct net_device *ndev, 1557 struct ethtool_stats *estats, u64 *data) 1558{ 1559 struct ravb_private *priv = netdev_priv(ndev); 1560 const struct ravb_hw_info *info = priv->info; 1561 int num_rx_q; 1562 int i = 0; 1563 int q; 1564 1565 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1566 /* Device-specific stats */ 1567 for (q = RAVB_BE; q < num_rx_q; q++) { 1568 struct net_device_stats *stats = &priv->stats[q]; 1569 1570 data[i++] = priv->cur_rx[q]; 1571 data[i++] = priv->cur_tx[q]; 1572 data[i++] = priv->dirty_rx[q]; 1573 data[i++] = priv->dirty_tx[q]; 1574 data[i++] = stats->rx_packets; 1575 data[i++] = stats->tx_packets; 1576 data[i++] = stats->rx_bytes; 1577 data[i++] = stats->tx_bytes; 1578 data[i++] = stats->multicast; 1579 data[i++] = stats->rx_errors; 1580 data[i++] = stats->rx_crc_errors; 1581 data[i++] = stats->rx_frame_errors; 1582 data[i++] = stats->rx_length_errors; 1583 data[i++] = stats->rx_missed_errors; 1584 data[i++] = stats->rx_over_errors; 1585 } 1586} 1587 1588static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1589{ 1590 struct ravb_private *priv = netdev_priv(ndev); 1591 const struct ravb_hw_info *info = priv->info; 1592 1593 switch (stringset) { 1594 case ETH_SS_STATS: 1595 memcpy(data, info->gstrings_stats, info->gstrings_size); 1596 break; 1597 } 1598} 1599 1600static void ravb_get_ringparam(struct net_device *ndev, 1601 struct ethtool_ringparam *ring, 1602 struct kernel_ethtool_ringparam *kernel_ring, 1603 struct netlink_ext_ack *extack) 1604{ 1605 struct ravb_private *priv = netdev_priv(ndev); 1606 1607 ring->rx_max_pending = BE_RX_RING_MAX; 1608 ring->tx_max_pending = BE_TX_RING_MAX; 1609 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1610 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1611} 1612 1613static int ravb_set_ringparam(struct net_device *ndev, 1614 struct ethtool_ringparam *ring, 1615 struct kernel_ethtool_ringparam *kernel_ring, 1616 struct netlink_ext_ack *extack) 1617{ 1618 struct ravb_private *priv = netdev_priv(ndev); 1619 const struct ravb_hw_info *info = priv->info; 1620 int error; 1621 1622 if (ring->tx_pending > BE_TX_RING_MAX || 1623 ring->rx_pending > BE_RX_RING_MAX || 1624 ring->tx_pending < BE_TX_RING_MIN || 1625 ring->rx_pending < BE_RX_RING_MIN) 1626 return -EINVAL; 1627 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1628 return -EINVAL; 1629 1630 if (netif_running(ndev)) { 1631 netif_device_detach(ndev); 1632 /* Stop PTP Clock driver */ 1633 if (info->gptp) 1634 ravb_ptp_stop(ndev); 1635 /* Wait for DMA stopping */ 1636 error = ravb_stop_dma(ndev); 1637 if (error) { 1638 netdev_err(ndev, 1639 "cannot set ringparam! Any AVB processes are still running?\n"); 1640 return error; 1641 } 1642 synchronize_irq(ndev->irq); 1643 1644 /* Free all the skb's in the RX queue and the DMA buffers. */ 1645 ravb_ring_free(ndev, RAVB_BE); 1646 if (info->nc_queues) 1647 ravb_ring_free(ndev, RAVB_NC); 1648 } 1649 1650 /* Set new parameters */ 1651 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1652 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1653 1654 if (netif_running(ndev)) { 1655 error = ravb_dmac_init(ndev); 1656 if (error) { 1657 netdev_err(ndev, 1658 "%s: ravb_dmac_init() failed, error %d\n", 1659 __func__, error); 1660 return error; 1661 } 1662 1663 ravb_emac_init(ndev); 1664 1665 /* Initialise PTP Clock driver */ 1666 if (info->gptp) 1667 ravb_ptp_init(ndev, priv->pdev); 1668 1669 netif_device_attach(ndev); 1670 } 1671 1672 return 0; 1673} 1674 1675static int ravb_get_ts_info(struct net_device *ndev, 1676 struct ethtool_ts_info *info) 1677{ 1678 struct ravb_private *priv = netdev_priv(ndev); 1679 const struct ravb_hw_info *hw_info = priv->info; 1680 1681 info->so_timestamping = 1682 SOF_TIMESTAMPING_TX_SOFTWARE | 1683 SOF_TIMESTAMPING_RX_SOFTWARE | 1684 SOF_TIMESTAMPING_SOFTWARE | 1685 SOF_TIMESTAMPING_TX_HARDWARE | 1686 SOF_TIMESTAMPING_RX_HARDWARE | 1687 SOF_TIMESTAMPING_RAW_HARDWARE; 1688 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1689 info->rx_filters = 1690 (1 << HWTSTAMP_FILTER_NONE) | 1691 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1692 (1 << HWTSTAMP_FILTER_ALL); 1693 if (hw_info->gptp || hw_info->ccc_gac) 1694 info->phc_index = ptp_clock_index(priv->ptp.clock); 1695 1696 return 0; 1697} 1698 1699static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1700{ 1701 struct ravb_private *priv = netdev_priv(ndev); 1702 1703 wol->supported = WAKE_MAGIC; 1704 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1705} 1706 1707static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1708{ 1709 struct ravb_private *priv = netdev_priv(ndev); 1710 const struct ravb_hw_info *info = priv->info; 1711 1712 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1713 return -EOPNOTSUPP; 1714 1715 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1716 1717 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1718 1719 return 0; 1720} 1721 1722static const struct ethtool_ops ravb_ethtool_ops = { 1723 .nway_reset = phy_ethtool_nway_reset, 1724 .get_msglevel = ravb_get_msglevel, 1725 .set_msglevel = ravb_set_msglevel, 1726 .get_link = ethtool_op_get_link, 1727 .get_strings = ravb_get_strings, 1728 .get_ethtool_stats = ravb_get_ethtool_stats, 1729 .get_sset_count = ravb_get_sset_count, 1730 .get_ringparam = ravb_get_ringparam, 1731 .set_ringparam = ravb_set_ringparam, 1732 .get_ts_info = ravb_get_ts_info, 1733 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1734 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1735 .get_wol = ravb_get_wol, 1736 .set_wol = ravb_set_wol, 1737}; 1738 1739static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1740 struct net_device *ndev, struct device *dev, 1741 const char *ch) 1742{ 1743 char *name; 1744 int error; 1745 1746 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1747 if (!name) 1748 return -ENOMEM; 1749 error = request_irq(irq, handler, 0, name, ndev); 1750 if (error) 1751 netdev_err(ndev, "cannot request IRQ %s\n", name); 1752 1753 return error; 1754} 1755 1756/* Network device open function for Ethernet AVB */ 1757static int ravb_open(struct net_device *ndev) 1758{ 1759 struct ravb_private *priv = netdev_priv(ndev); 1760 const struct ravb_hw_info *info = priv->info; 1761 struct platform_device *pdev = priv->pdev; 1762 struct device *dev = &pdev->dev; 1763 int error; 1764 1765 napi_enable(&priv->napi[RAVB_BE]); 1766 if (info->nc_queues) 1767 napi_enable(&priv->napi[RAVB_NC]); 1768 1769 if (!info->multi_irqs) { 1770 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1771 ndev->name, ndev); 1772 if (error) { 1773 netdev_err(ndev, "cannot request IRQ\n"); 1774 goto out_napi_off; 1775 } 1776 } else { 1777 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1778 dev, "ch22:multi"); 1779 if (error) 1780 goto out_napi_off; 1781 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1782 dev, "ch24:emac"); 1783 if (error) 1784 goto out_free_irq; 1785 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1786 ndev, dev, "ch0:rx_be"); 1787 if (error) 1788 goto out_free_irq_emac; 1789 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1790 ndev, dev, "ch18:tx_be"); 1791 if (error) 1792 goto out_free_irq_be_rx; 1793 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1794 ndev, dev, "ch1:rx_nc"); 1795 if (error) 1796 goto out_free_irq_be_tx; 1797 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1798 ndev, dev, "ch19:tx_nc"); 1799 if (error) 1800 goto out_free_irq_nc_rx; 1801 1802 if (info->err_mgmt_irqs) { 1803 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1804 ndev, dev, "err_a"); 1805 if (error) 1806 goto out_free_irq_nc_tx; 1807 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1808 ndev, dev, "mgmt_a"); 1809 if (error) 1810 goto out_free_irq_erra; 1811 } 1812 } 1813 1814 /* Device init */ 1815 error = ravb_dmac_init(ndev); 1816 if (error) 1817 goto out_free_irq_mgmta; 1818 ravb_emac_init(ndev); 1819 1820 /* Initialise PTP Clock driver */ 1821 if (info->gptp) 1822 ravb_ptp_init(ndev, priv->pdev); 1823 1824 /* PHY control start */ 1825 error = ravb_phy_start(ndev); 1826 if (error) 1827 goto out_ptp_stop; 1828 1829 netif_tx_start_all_queues(ndev); 1830 1831 return 0; 1832 1833out_ptp_stop: 1834 /* Stop PTP Clock driver */ 1835 if (info->gptp) 1836 ravb_ptp_stop(ndev); 1837 ravb_stop_dma(ndev); 1838out_free_irq_mgmta: 1839 if (!info->multi_irqs) 1840 goto out_free_irq; 1841 if (info->err_mgmt_irqs) 1842 free_irq(priv->mgmta_irq, ndev); 1843out_free_irq_erra: 1844 if (info->err_mgmt_irqs) 1845 free_irq(priv->erra_irq, ndev); 1846out_free_irq_nc_tx: 1847 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1848out_free_irq_nc_rx: 1849 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1850out_free_irq_be_tx: 1851 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1852out_free_irq_be_rx: 1853 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1854out_free_irq_emac: 1855 free_irq(priv->emac_irq, ndev); 1856out_free_irq: 1857 free_irq(ndev->irq, ndev); 1858out_napi_off: 1859 if (info->nc_queues) 1860 napi_disable(&priv->napi[RAVB_NC]); 1861 napi_disable(&priv->napi[RAVB_BE]); 1862 return error; 1863} 1864 1865/* Timeout function for Ethernet AVB */ 1866static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1867{ 1868 struct ravb_private *priv = netdev_priv(ndev); 1869 1870 netif_err(priv, tx_err, ndev, 1871 "transmit timed out, status %08x, resetting...\n", 1872 ravb_read(ndev, ISS)); 1873 1874 /* tx_errors count up */ 1875 ndev->stats.tx_errors++; 1876 1877 schedule_work(&priv->work); 1878} 1879 1880static void ravb_tx_timeout_work(struct work_struct *work) 1881{ 1882 struct ravb_private *priv = container_of(work, struct ravb_private, 1883 work); 1884 const struct ravb_hw_info *info = priv->info; 1885 struct net_device *ndev = priv->ndev; 1886 int error; 1887 1888 if (!rtnl_trylock()) { 1889 usleep_range(1000, 2000); 1890 schedule_work(&priv->work); 1891 return; 1892 } 1893 1894 netif_tx_stop_all_queues(ndev); 1895 1896 /* Stop PTP Clock driver */ 1897 if (info->gptp) 1898 ravb_ptp_stop(ndev); 1899 1900 /* Wait for DMA stopping */ 1901 if (ravb_stop_dma(ndev)) { 1902 /* If ravb_stop_dma() fails, the hardware is still operating 1903 * for TX and/or RX. So, this should not call the following 1904 * functions because ravb_dmac_init() is possible to fail too. 1905 * Also, this should not retry ravb_stop_dma() again and again 1906 * here because it's possible to wait forever. So, this just 1907 * re-enables the TX and RX and skip the following 1908 * re-initialization procedure. 1909 */ 1910 ravb_rcv_snd_enable(ndev); 1911 goto out; 1912 } 1913 1914 ravb_ring_free(ndev, RAVB_BE); 1915 if (info->nc_queues) 1916 ravb_ring_free(ndev, RAVB_NC); 1917 1918 /* Device init */ 1919 error = ravb_dmac_init(ndev); 1920 if (error) { 1921 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1922 * should return here to avoid re-enabling the TX and RX in 1923 * ravb_emac_init(). 1924 */ 1925 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1926 __func__, error); 1927 goto out_unlock; 1928 } 1929 ravb_emac_init(ndev); 1930 1931out: 1932 /* Initialise PTP Clock driver */ 1933 if (info->gptp) 1934 ravb_ptp_init(ndev, priv->pdev); 1935 1936 netif_tx_start_all_queues(ndev); 1937 1938out_unlock: 1939 rtnl_unlock(); 1940} 1941 1942/* Packet transmit function for Ethernet AVB */ 1943static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1944{ 1945 struct ravb_private *priv = netdev_priv(ndev); 1946 const struct ravb_hw_info *info = priv->info; 1947 unsigned int num_tx_desc = priv->num_tx_desc; 1948 u16 q = skb_get_queue_mapping(skb); 1949 struct ravb_tstamp_skb *ts_skb; 1950 struct ravb_tx_desc *desc; 1951 unsigned long flags; 1952 dma_addr_t dma_addr; 1953 void *buffer; 1954 u32 entry; 1955 u32 len; 1956 1957 spin_lock_irqsave(&priv->lock, flags); 1958 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1959 num_tx_desc) { 1960 netif_err(priv, tx_queued, ndev, 1961 "still transmitting with the full ring!\n"); 1962 netif_stop_subqueue(ndev, q); 1963 spin_unlock_irqrestore(&priv->lock, flags); 1964 return NETDEV_TX_BUSY; 1965 } 1966 1967 if (skb_put_padto(skb, ETH_ZLEN)) 1968 goto exit; 1969 1970 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1971 priv->tx_skb[q][entry / num_tx_desc] = skb; 1972 1973 if (num_tx_desc > 1) { 1974 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1975 entry / num_tx_desc * DPTR_ALIGN; 1976 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1977 1978 /* Zero length DMA descriptors are problematic as they seem 1979 * to terminate DMA transfers. Avoid them by simply using a 1980 * length of DPTR_ALIGN (4) when skb data is aligned to 1981 * DPTR_ALIGN. 1982 * 1983 * As skb is guaranteed to have at least ETH_ZLEN (60) 1984 * bytes of data by the call to skb_put_padto() above this 1985 * is safe with respect to both the length of the first DMA 1986 * descriptor (len) overflowing the available data and the 1987 * length of the second DMA descriptor (skb->len - len) 1988 * being negative. 1989 */ 1990 if (len == 0) 1991 len = DPTR_ALIGN; 1992 1993 memcpy(buffer, skb->data, len); 1994 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1995 DMA_TO_DEVICE); 1996 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1997 goto drop; 1998 1999 desc = &priv->tx_ring[q][entry]; 2000 desc->ds_tagl = cpu_to_le16(len); 2001 desc->dptr = cpu_to_le32(dma_addr); 2002 2003 buffer = skb->data + len; 2004 len = skb->len - len; 2005 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2006 DMA_TO_DEVICE); 2007 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2008 goto unmap; 2009 2010 desc++; 2011 } else { 2012 desc = &priv->tx_ring[q][entry]; 2013 len = skb->len; 2014 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2015 DMA_TO_DEVICE); 2016 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2017 goto drop; 2018 } 2019 desc->ds_tagl = cpu_to_le16(len); 2020 desc->dptr = cpu_to_le32(dma_addr); 2021 2022 /* TX timestamp required */ 2023 if (info->gptp || info->ccc_gac) { 2024 if (q == RAVB_NC) { 2025 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2026 if (!ts_skb) { 2027 if (num_tx_desc > 1) { 2028 desc--; 2029 dma_unmap_single(ndev->dev.parent, dma_addr, 2030 len, DMA_TO_DEVICE); 2031 } 2032 goto unmap; 2033 } 2034 ts_skb->skb = skb_get(skb); 2035 ts_skb->tag = priv->ts_skb_tag++; 2036 priv->ts_skb_tag &= 0x3ff; 2037 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2038 2039 /* TAG and timestamp required flag */ 2040 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2041 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2042 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2043 } 2044 2045 skb_tx_timestamp(skb); 2046 } 2047 /* Descriptor type must be set after all the above writes */ 2048 dma_wmb(); 2049 if (num_tx_desc > 1) { 2050 desc->die_dt = DT_FEND; 2051 desc--; 2052 desc->die_dt = DT_FSTART; 2053 } else { 2054 desc->die_dt = DT_FSINGLE; 2055 } 2056 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2057 2058 priv->cur_tx[q] += num_tx_desc; 2059 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2060 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2061 !ravb_tx_free(ndev, q, true)) 2062 netif_stop_subqueue(ndev, q); 2063 2064exit: 2065 spin_unlock_irqrestore(&priv->lock, flags); 2066 return NETDEV_TX_OK; 2067 2068unmap: 2069 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2070 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2071drop: 2072 dev_kfree_skb_any(skb); 2073 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2074 goto exit; 2075} 2076 2077static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2078 struct net_device *sb_dev) 2079{ 2080 /* If skb needs TX timestamp, it is handled in network control queue */ 2081 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2082 RAVB_BE; 2083 2084} 2085 2086static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2087{ 2088 struct ravb_private *priv = netdev_priv(ndev); 2089 const struct ravb_hw_info *info = priv->info; 2090 struct net_device_stats *nstats, *stats0, *stats1; 2091 2092 nstats = &ndev->stats; 2093 stats0 = &priv->stats[RAVB_BE]; 2094 2095 if (info->tx_counters) { 2096 nstats->tx_dropped += ravb_read(ndev, TROCR); 2097 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2098 } 2099 2100 if (info->carrier_counters) { 2101 nstats->collisions += ravb_read(ndev, CXR41); 2102 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2103 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2104 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2105 } 2106 2107 nstats->rx_packets = stats0->rx_packets; 2108 nstats->tx_packets = stats0->tx_packets; 2109 nstats->rx_bytes = stats0->rx_bytes; 2110 nstats->tx_bytes = stats0->tx_bytes; 2111 nstats->multicast = stats0->multicast; 2112 nstats->rx_errors = stats0->rx_errors; 2113 nstats->rx_crc_errors = stats0->rx_crc_errors; 2114 nstats->rx_frame_errors = stats0->rx_frame_errors; 2115 nstats->rx_length_errors = stats0->rx_length_errors; 2116 nstats->rx_missed_errors = stats0->rx_missed_errors; 2117 nstats->rx_over_errors = stats0->rx_over_errors; 2118 if (info->nc_queues) { 2119 stats1 = &priv->stats[RAVB_NC]; 2120 2121 nstats->rx_packets += stats1->rx_packets; 2122 nstats->tx_packets += stats1->tx_packets; 2123 nstats->rx_bytes += stats1->rx_bytes; 2124 nstats->tx_bytes += stats1->tx_bytes; 2125 nstats->multicast += stats1->multicast; 2126 nstats->rx_errors += stats1->rx_errors; 2127 nstats->rx_crc_errors += stats1->rx_crc_errors; 2128 nstats->rx_frame_errors += stats1->rx_frame_errors; 2129 nstats->rx_length_errors += stats1->rx_length_errors; 2130 nstats->rx_missed_errors += stats1->rx_missed_errors; 2131 nstats->rx_over_errors += stats1->rx_over_errors; 2132 } 2133 2134 return nstats; 2135} 2136 2137/* Update promiscuous bit */ 2138static void ravb_set_rx_mode(struct net_device *ndev) 2139{ 2140 struct ravb_private *priv = netdev_priv(ndev); 2141 unsigned long flags; 2142 2143 spin_lock_irqsave(&priv->lock, flags); 2144 ravb_modify(ndev, ECMR, ECMR_PRM, 2145 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2146 spin_unlock_irqrestore(&priv->lock, flags); 2147} 2148 2149/* Device close function for Ethernet AVB */ 2150static int ravb_close(struct net_device *ndev) 2151{ 2152 struct device_node *np = ndev->dev.parent->of_node; 2153 struct ravb_private *priv = netdev_priv(ndev); 2154 const struct ravb_hw_info *info = priv->info; 2155 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2156 2157 netif_tx_stop_all_queues(ndev); 2158 2159 /* Disable interrupts by clearing the interrupt masks. */ 2160 ravb_write(ndev, 0, RIC0); 2161 ravb_write(ndev, 0, RIC2); 2162 ravb_write(ndev, 0, TIC); 2163 2164 /* Stop PTP Clock driver */ 2165 if (info->gptp) 2166 ravb_ptp_stop(ndev); 2167 2168 /* Set the config mode to stop the AVB-DMAC's processes */ 2169 if (ravb_stop_dma(ndev) < 0) 2170 netdev_err(ndev, 2171 "device will be stopped after h/w processes are done.\n"); 2172 2173 /* Clear the timestamp list */ 2174 if (info->gptp || info->ccc_gac) { 2175 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2176 list_del(&ts_skb->list); 2177 kfree_skb(ts_skb->skb); 2178 kfree(ts_skb); 2179 } 2180 } 2181 2182 /* PHY disconnect */ 2183 if (ndev->phydev) { 2184 phy_stop(ndev->phydev); 2185 phy_disconnect(ndev->phydev); 2186 if (of_phy_is_fixed_link(np)) 2187 of_phy_deregister_fixed_link(np); 2188 } 2189 2190 cancel_work_sync(&priv->work); 2191 2192 if (info->multi_irqs) { 2193 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2194 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2195 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2196 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2197 free_irq(priv->emac_irq, ndev); 2198 if (info->err_mgmt_irqs) { 2199 free_irq(priv->erra_irq, ndev); 2200 free_irq(priv->mgmta_irq, ndev); 2201 } 2202 } 2203 free_irq(ndev->irq, ndev); 2204 2205 if (info->nc_queues) 2206 napi_disable(&priv->napi[RAVB_NC]); 2207 napi_disable(&priv->napi[RAVB_BE]); 2208 2209 /* Free all the skb's in the RX queue and the DMA buffers. */ 2210 ravb_ring_free(ndev, RAVB_BE); 2211 if (info->nc_queues) 2212 ravb_ring_free(ndev, RAVB_NC); 2213 2214 return 0; 2215} 2216 2217static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2218{ 2219 struct ravb_private *priv = netdev_priv(ndev); 2220 struct hwtstamp_config config; 2221 2222 config.flags = 0; 2223 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2224 HWTSTAMP_TX_OFF; 2225 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2226 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2227 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2228 break; 2229 case RAVB_RXTSTAMP_TYPE_ALL: 2230 config.rx_filter = HWTSTAMP_FILTER_ALL; 2231 break; 2232 default: 2233 config.rx_filter = HWTSTAMP_FILTER_NONE; 2234 } 2235 2236 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2237 -EFAULT : 0; 2238} 2239 2240/* Control hardware time stamping */ 2241static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2242{ 2243 struct ravb_private *priv = netdev_priv(ndev); 2244 struct hwtstamp_config config; 2245 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2246 u32 tstamp_tx_ctrl; 2247 2248 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2249 return -EFAULT; 2250 2251 switch (config.tx_type) { 2252 case HWTSTAMP_TX_OFF: 2253 tstamp_tx_ctrl = 0; 2254 break; 2255 case HWTSTAMP_TX_ON: 2256 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2257 break; 2258 default: 2259 return -ERANGE; 2260 } 2261 2262 switch (config.rx_filter) { 2263 case HWTSTAMP_FILTER_NONE: 2264 tstamp_rx_ctrl = 0; 2265 break; 2266 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2267 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2268 break; 2269 default: 2270 config.rx_filter = HWTSTAMP_FILTER_ALL; 2271 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2272 } 2273 2274 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2275 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2276 2277 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2278 -EFAULT : 0; 2279} 2280 2281/* ioctl to device function */ 2282static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2283{ 2284 struct phy_device *phydev = ndev->phydev; 2285 2286 if (!netif_running(ndev)) 2287 return -EINVAL; 2288 2289 if (!phydev) 2290 return -ENODEV; 2291 2292 switch (cmd) { 2293 case SIOCGHWTSTAMP: 2294 return ravb_hwtstamp_get(ndev, req); 2295 case SIOCSHWTSTAMP: 2296 return ravb_hwtstamp_set(ndev, req); 2297 } 2298 2299 return phy_mii_ioctl(phydev, req, cmd); 2300} 2301 2302static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2303{ 2304 struct ravb_private *priv = netdev_priv(ndev); 2305 2306 ndev->mtu = new_mtu; 2307 2308 if (netif_running(ndev)) { 2309 synchronize_irq(priv->emac_irq); 2310 ravb_emac_init(ndev); 2311 } 2312 2313 netdev_update_features(ndev); 2314 2315 return 0; 2316} 2317 2318static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2319{ 2320 struct ravb_private *priv = netdev_priv(ndev); 2321 unsigned long flags; 2322 2323 spin_lock_irqsave(&priv->lock, flags); 2324 2325 /* Disable TX and RX */ 2326 ravb_rcv_snd_disable(ndev); 2327 2328 /* Modify RX Checksum setting */ 2329 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2330 2331 /* Enable TX and RX */ 2332 ravb_rcv_snd_enable(ndev); 2333 2334 spin_unlock_irqrestore(&priv->lock, flags); 2335} 2336 2337static int ravb_set_features_gbeth(struct net_device *ndev, 2338 netdev_features_t features) 2339{ 2340 /* Place holder */ 2341 return 0; 2342} 2343 2344static int ravb_set_features_rcar(struct net_device *ndev, 2345 netdev_features_t features) 2346{ 2347 netdev_features_t changed = ndev->features ^ features; 2348 2349 if (changed & NETIF_F_RXCSUM) 2350 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2351 2352 ndev->features = features; 2353 2354 return 0; 2355} 2356 2357static int ravb_set_features(struct net_device *ndev, 2358 netdev_features_t features) 2359{ 2360 struct ravb_private *priv = netdev_priv(ndev); 2361 const struct ravb_hw_info *info = priv->info; 2362 2363 return info->set_feature(ndev, features); 2364} 2365 2366static const struct net_device_ops ravb_netdev_ops = { 2367 .ndo_open = ravb_open, 2368 .ndo_stop = ravb_close, 2369 .ndo_start_xmit = ravb_start_xmit, 2370 .ndo_select_queue = ravb_select_queue, 2371 .ndo_get_stats = ravb_get_stats, 2372 .ndo_set_rx_mode = ravb_set_rx_mode, 2373 .ndo_tx_timeout = ravb_tx_timeout, 2374 .ndo_eth_ioctl = ravb_do_ioctl, 2375 .ndo_change_mtu = ravb_change_mtu, 2376 .ndo_validate_addr = eth_validate_addr, 2377 .ndo_set_mac_address = eth_mac_addr, 2378 .ndo_set_features = ravb_set_features, 2379}; 2380 2381/* MDIO bus init function */ 2382static int ravb_mdio_init(struct ravb_private *priv) 2383{ 2384 struct platform_device *pdev = priv->pdev; 2385 struct device *dev = &pdev->dev; 2386 struct phy_device *phydev; 2387 struct device_node *pn; 2388 int error; 2389 2390 /* Bitbang init */ 2391 priv->mdiobb.ops = &bb_ops; 2392 2393 /* MII controller setting */ 2394 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2395 if (!priv->mii_bus) 2396 return -ENOMEM; 2397 2398 /* Hook up MII support for ethtool */ 2399 priv->mii_bus->name = "ravb_mii"; 2400 priv->mii_bus->parent = dev; 2401 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2402 pdev->name, pdev->id); 2403 2404 /* Register MDIO bus */ 2405 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2406 if (error) 2407 goto out_free_bus; 2408 2409 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2410 phydev = of_phy_find_device(pn); 2411 if (phydev) { 2412 phydev->mac_managed_pm = true; 2413 put_device(&phydev->mdio.dev); 2414 } 2415 of_node_put(pn); 2416 2417 return 0; 2418 2419out_free_bus: 2420 free_mdio_bitbang(priv->mii_bus); 2421 return error; 2422} 2423 2424/* MDIO bus release function */ 2425static int ravb_mdio_release(struct ravb_private *priv) 2426{ 2427 /* Unregister mdio bus */ 2428 mdiobus_unregister(priv->mii_bus); 2429 2430 /* Free bitbang info */ 2431 free_mdio_bitbang(priv->mii_bus); 2432 2433 return 0; 2434} 2435 2436static const struct ravb_hw_info ravb_gen3_hw_info = { 2437 .rx_ring_free = ravb_rx_ring_free_rcar, 2438 .rx_ring_format = ravb_rx_ring_format_rcar, 2439 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2440 .receive = ravb_rx_rcar, 2441 .set_rate = ravb_set_rate_rcar, 2442 .set_feature = ravb_set_features_rcar, 2443 .dmac_init = ravb_dmac_init_rcar, 2444 .emac_init = ravb_emac_init_rcar, 2445 .gstrings_stats = ravb_gstrings_stats, 2446 .gstrings_size = sizeof(ravb_gstrings_stats), 2447 .net_hw_features = NETIF_F_RXCSUM, 2448 .net_features = NETIF_F_RXCSUM, 2449 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2450 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2451 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2452 .rx_max_buf_size = SZ_2K, 2453 .internal_delay = 1, 2454 .tx_counters = 1, 2455 .multi_irqs = 1, 2456 .irq_en_dis = 1, 2457 .ccc_gac = 1, 2458 .nc_queues = 1, 2459 .magic_pkt = 1, 2460}; 2461 2462static const struct ravb_hw_info ravb_gen2_hw_info = { 2463 .rx_ring_free = ravb_rx_ring_free_rcar, 2464 .rx_ring_format = ravb_rx_ring_format_rcar, 2465 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2466 .receive = ravb_rx_rcar, 2467 .set_rate = ravb_set_rate_rcar, 2468 .set_feature = ravb_set_features_rcar, 2469 .dmac_init = ravb_dmac_init_rcar, 2470 .emac_init = ravb_emac_init_rcar, 2471 .gstrings_stats = ravb_gstrings_stats, 2472 .gstrings_size = sizeof(ravb_gstrings_stats), 2473 .net_hw_features = NETIF_F_RXCSUM, 2474 .net_features = NETIF_F_RXCSUM, 2475 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2476 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2477 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2478 .rx_max_buf_size = SZ_2K, 2479 .aligned_tx = 1, 2480 .gptp = 1, 2481 .nc_queues = 1, 2482 .magic_pkt = 1, 2483}; 2484 2485static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2486 .rx_ring_free = ravb_rx_ring_free_rcar, 2487 .rx_ring_format = ravb_rx_ring_format_rcar, 2488 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2489 .receive = ravb_rx_rcar, 2490 .set_rate = ravb_set_rate_rcar, 2491 .set_feature = ravb_set_features_rcar, 2492 .dmac_init = ravb_dmac_init_rcar, 2493 .emac_init = ravb_emac_init_rcar, 2494 .gstrings_stats = ravb_gstrings_stats, 2495 .gstrings_size = sizeof(ravb_gstrings_stats), 2496 .net_hw_features = NETIF_F_RXCSUM, 2497 .net_features = NETIF_F_RXCSUM, 2498 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2499 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2500 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2501 .rx_max_buf_size = SZ_2K, 2502 .multi_irqs = 1, 2503 .err_mgmt_irqs = 1, 2504 .gptp = 1, 2505 .gptp_ref_clk = 1, 2506 .nc_queues = 1, 2507 .magic_pkt = 1, 2508}; 2509 2510static const struct ravb_hw_info gbeth_hw_info = { 2511 .rx_ring_free = ravb_rx_ring_free_gbeth, 2512 .rx_ring_format = ravb_rx_ring_format_gbeth, 2513 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2514 .receive = ravb_rx_gbeth, 2515 .set_rate = ravb_set_rate_gbeth, 2516 .set_feature = ravb_set_features_gbeth, 2517 .dmac_init = ravb_dmac_init_gbeth, 2518 .emac_init = ravb_emac_init_gbeth, 2519 .gstrings_stats = ravb_gstrings_stats_gbeth, 2520 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2521 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2522 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2523 .tccr_mask = TCCR_TSRQ0, 2524 .rx_max_buf_size = SZ_8K, 2525 .aligned_tx = 1, 2526 .tx_counters = 1, 2527 .carrier_counters = 1, 2528 .half_duplex = 1, 2529}; 2530 2531static const struct of_device_id ravb_match_table[] = { 2532 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2533 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2534 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2535 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2536 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2537 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2538 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2539 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2540 { } 2541}; 2542MODULE_DEVICE_TABLE(of, ravb_match_table); 2543 2544static int ravb_set_gti(struct net_device *ndev) 2545{ 2546 struct ravb_private *priv = netdev_priv(ndev); 2547 const struct ravb_hw_info *info = priv->info; 2548 struct device *dev = ndev->dev.parent; 2549 unsigned long rate; 2550 uint64_t inc; 2551 2552 if (info->gptp_ref_clk) 2553 rate = clk_get_rate(priv->gptp_clk); 2554 else 2555 rate = clk_get_rate(priv->clk); 2556 if (!rate) 2557 return -EINVAL; 2558 2559 inc = div64_ul(1000000000ULL << 20, rate); 2560 2561 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2562 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2563 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2564 return -EINVAL; 2565 } 2566 2567 ravb_write(ndev, inc, GTI); 2568 2569 return 0; 2570} 2571 2572static int ravb_set_config_mode(struct net_device *ndev) 2573{ 2574 struct ravb_private *priv = netdev_priv(ndev); 2575 const struct ravb_hw_info *info = priv->info; 2576 int error; 2577 2578 if (info->gptp) { 2579 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2580 if (error) 2581 return error; 2582 /* Set CSEL value */ 2583 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2584 } else if (info->ccc_gac) { 2585 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 2586 } else { 2587 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2588 } 2589 2590 return error; 2591} 2592 2593/* Set tx and rx clock internal delay modes */ 2594static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2595{ 2596 struct ravb_private *priv = netdev_priv(ndev); 2597 bool explicit_delay = false; 2598 u32 delay; 2599 2600 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2601 /* Valid values are 0 and 1800, according to DT bindings */ 2602 priv->rxcidm = !!delay; 2603 explicit_delay = true; 2604 } 2605 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2606 /* Valid values are 0 and 2000, according to DT bindings */ 2607 priv->txcidm = !!delay; 2608 explicit_delay = true; 2609 } 2610 2611 if (explicit_delay) 2612 return; 2613 2614 /* Fall back to legacy rgmii-*id behavior */ 2615 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2616 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2617 priv->rxcidm = 1; 2618 priv->rgmii_override = 1; 2619 } 2620 2621 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2622 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2623 priv->txcidm = 1; 2624 priv->rgmii_override = 1; 2625 } 2626} 2627 2628static void ravb_set_delay_mode(struct net_device *ndev) 2629{ 2630 struct ravb_private *priv = netdev_priv(ndev); 2631 u32 set = 0; 2632 2633 if (priv->rxcidm) 2634 set |= APSR_RDM; 2635 if (priv->txcidm) 2636 set |= APSR_TDM; 2637 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2638} 2639 2640static int ravb_probe(struct platform_device *pdev) 2641{ 2642 struct device_node *np = pdev->dev.of_node; 2643 const struct ravb_hw_info *info; 2644 struct reset_control *rstc; 2645 struct ravb_private *priv; 2646 struct net_device *ndev; 2647 int error, irq, q; 2648 struct resource *res; 2649 int i; 2650 2651 if (!np) { 2652 dev_err(&pdev->dev, 2653 "this driver is required to be instantiated from device tree\n"); 2654 return -EINVAL; 2655 } 2656 2657 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2658 if (IS_ERR(rstc)) 2659 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2660 "failed to get cpg reset\n"); 2661 2662 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2663 NUM_TX_QUEUE, NUM_RX_QUEUE); 2664 if (!ndev) 2665 return -ENOMEM; 2666 2667 info = of_device_get_match_data(&pdev->dev); 2668 2669 ndev->features = info->net_features; 2670 ndev->hw_features = info->net_hw_features; 2671 2672 error = reset_control_deassert(rstc); 2673 if (error) 2674 goto out_free_netdev; 2675 2676 pm_runtime_enable(&pdev->dev); 2677 error = pm_runtime_resume_and_get(&pdev->dev); 2678 if (error < 0) 2679 goto out_rpm_disable; 2680 2681 if (info->multi_irqs) { 2682 if (info->err_mgmt_irqs) 2683 irq = platform_get_irq_byname(pdev, "dia"); 2684 else 2685 irq = platform_get_irq_byname(pdev, "ch22"); 2686 } else { 2687 irq = platform_get_irq(pdev, 0); 2688 } 2689 if (irq < 0) { 2690 error = irq; 2691 goto out_release; 2692 } 2693 ndev->irq = irq; 2694 2695 SET_NETDEV_DEV(ndev, &pdev->dev); 2696 2697 priv = netdev_priv(ndev); 2698 priv->info = info; 2699 priv->rstc = rstc; 2700 priv->ndev = ndev; 2701 priv->pdev = pdev; 2702 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2703 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2704 if (info->nc_queues) { 2705 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2706 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2707 } 2708 2709 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2710 if (IS_ERR(priv->addr)) { 2711 error = PTR_ERR(priv->addr); 2712 goto out_release; 2713 } 2714 2715 /* The Ether-specific entries in the device structure. */ 2716 ndev->base_addr = res->start; 2717 2718 spin_lock_init(&priv->lock); 2719 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2720 2721 error = of_get_phy_mode(np, &priv->phy_interface); 2722 if (error && error != -ENODEV) 2723 goto out_release; 2724 2725 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2726 priv->avb_link_active_low = 2727 of_property_read_bool(np, "renesas,ether-link-active-low"); 2728 2729 if (info->multi_irqs) { 2730 if (info->err_mgmt_irqs) 2731 irq = platform_get_irq_byname(pdev, "line3"); 2732 else 2733 irq = platform_get_irq_byname(pdev, "ch24"); 2734 if (irq < 0) { 2735 error = irq; 2736 goto out_release; 2737 } 2738 priv->emac_irq = irq; 2739 for (i = 0; i < NUM_RX_QUEUE; i++) { 2740 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2741 if (irq < 0) { 2742 error = irq; 2743 goto out_release; 2744 } 2745 priv->rx_irqs[i] = irq; 2746 } 2747 for (i = 0; i < NUM_TX_QUEUE; i++) { 2748 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2749 if (irq < 0) { 2750 error = irq; 2751 goto out_release; 2752 } 2753 priv->tx_irqs[i] = irq; 2754 } 2755 2756 if (info->err_mgmt_irqs) { 2757 irq = platform_get_irq_byname(pdev, "err_a"); 2758 if (irq < 0) { 2759 error = irq; 2760 goto out_release; 2761 } 2762 priv->erra_irq = irq; 2763 2764 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2765 if (irq < 0) { 2766 error = irq; 2767 goto out_release; 2768 } 2769 priv->mgmta_irq = irq; 2770 } 2771 } 2772 2773 priv->clk = devm_clk_get(&pdev->dev, NULL); 2774 if (IS_ERR(priv->clk)) { 2775 error = PTR_ERR(priv->clk); 2776 goto out_release; 2777 } 2778 2779 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2780 if (IS_ERR(priv->refclk)) { 2781 error = PTR_ERR(priv->refclk); 2782 goto out_release; 2783 } 2784 clk_prepare_enable(priv->refclk); 2785 2786 if (info->gptp_ref_clk) { 2787 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2788 if (IS_ERR(priv->gptp_clk)) { 2789 error = PTR_ERR(priv->gptp_clk); 2790 goto out_disable_refclk; 2791 } 2792 clk_prepare_enable(priv->gptp_clk); 2793 } 2794 2795 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2796 ndev->min_mtu = ETH_MIN_MTU; 2797 2798 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2799 * Use two descriptor to handle such situation. First descriptor to 2800 * handle aligned data buffer and second descriptor to handle the 2801 * overflow data because of alignment. 2802 */ 2803 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2804 2805 /* Set function */ 2806 ndev->netdev_ops = &ravb_netdev_ops; 2807 ndev->ethtool_ops = &ravb_ethtool_ops; 2808 2809 /* Set AVB config mode */ 2810 error = ravb_set_config_mode(ndev); 2811 if (error) 2812 goto out_disable_gptp_clk; 2813 2814 if (info->gptp || info->ccc_gac) { 2815 /* Set GTI value */ 2816 error = ravb_set_gti(ndev); 2817 if (error) 2818 goto out_disable_gptp_clk; 2819 2820 /* Request GTI loading */ 2821 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2822 } 2823 2824 if (info->internal_delay) { 2825 ravb_parse_delay_mode(np, ndev); 2826 ravb_set_delay_mode(ndev); 2827 } 2828 2829 /* Allocate descriptor base address table */ 2830 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2831 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2832 &priv->desc_bat_dma, GFP_KERNEL); 2833 if (!priv->desc_bat) { 2834 dev_err(&pdev->dev, 2835 "Cannot allocate desc base address table (size %d bytes)\n", 2836 priv->desc_bat_size); 2837 error = -ENOMEM; 2838 goto out_disable_gptp_clk; 2839 } 2840 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2841 priv->desc_bat[q].die_dt = DT_EOS; 2842 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2843 2844 /* Initialise HW timestamp list */ 2845 INIT_LIST_HEAD(&priv->ts_skb_list); 2846 2847 /* Initialise PTP Clock driver */ 2848 if (info->ccc_gac) 2849 ravb_ptp_init(ndev, pdev); 2850 2851 /* Debug message level */ 2852 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2853 2854 /* Read and set MAC address */ 2855 ravb_read_mac_address(np, ndev); 2856 if (!is_valid_ether_addr(ndev->dev_addr)) { 2857 dev_warn(&pdev->dev, 2858 "no valid MAC address supplied, using a random one\n"); 2859 eth_hw_addr_random(ndev); 2860 } 2861 2862 /* MDIO bus init */ 2863 error = ravb_mdio_init(priv); 2864 if (error) { 2865 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2866 goto out_dma_free; 2867 } 2868 2869 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2870 if (info->nc_queues) 2871 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2872 2873 /* Network device register */ 2874 error = register_netdev(ndev); 2875 if (error) 2876 goto out_napi_del; 2877 2878 device_set_wakeup_capable(&pdev->dev, 1); 2879 2880 /* Print device information */ 2881 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2882 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2883 2884 platform_set_drvdata(pdev, ndev); 2885 2886 return 0; 2887 2888out_napi_del: 2889 if (info->nc_queues) 2890 netif_napi_del(&priv->napi[RAVB_NC]); 2891 2892 netif_napi_del(&priv->napi[RAVB_BE]); 2893 ravb_mdio_release(priv); 2894out_dma_free: 2895 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2896 priv->desc_bat_dma); 2897 2898 /* Stop PTP Clock driver */ 2899 if (info->ccc_gac) 2900 ravb_ptp_stop(ndev); 2901out_disable_gptp_clk: 2902 clk_disable_unprepare(priv->gptp_clk); 2903out_disable_refclk: 2904 clk_disable_unprepare(priv->refclk); 2905out_release: 2906 pm_runtime_put(&pdev->dev); 2907out_rpm_disable: 2908 pm_runtime_disable(&pdev->dev); 2909 reset_control_assert(rstc); 2910out_free_netdev: 2911 free_netdev(ndev); 2912 return error; 2913} 2914 2915static int ravb_remove(struct platform_device *pdev) 2916{ 2917 struct net_device *ndev = platform_get_drvdata(pdev); 2918 struct ravb_private *priv = netdev_priv(ndev); 2919 const struct ravb_hw_info *info = priv->info; 2920 2921 unregister_netdev(ndev); 2922 if (info->nc_queues) 2923 netif_napi_del(&priv->napi[RAVB_NC]); 2924 netif_napi_del(&priv->napi[RAVB_BE]); 2925 2926 ravb_mdio_release(priv); 2927 2928 /* Stop PTP Clock driver */ 2929 if (info->ccc_gac) 2930 ravb_ptp_stop(ndev); 2931 2932 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2933 priv->desc_bat_dma); 2934 2935 ravb_set_opmode(ndev, CCC_OPC_RESET); 2936 2937 clk_disable_unprepare(priv->gptp_clk); 2938 clk_disable_unprepare(priv->refclk); 2939 2940 pm_runtime_put_sync(&pdev->dev); 2941 pm_runtime_disable(&pdev->dev); 2942 reset_control_assert(priv->rstc); 2943 free_netdev(ndev); 2944 platform_set_drvdata(pdev, NULL); 2945 2946 return 0; 2947} 2948 2949static int ravb_wol_setup(struct net_device *ndev) 2950{ 2951 struct ravb_private *priv = netdev_priv(ndev); 2952 const struct ravb_hw_info *info = priv->info; 2953 2954 /* Disable interrupts by clearing the interrupt masks. */ 2955 ravb_write(ndev, 0, RIC0); 2956 ravb_write(ndev, 0, RIC2); 2957 ravb_write(ndev, 0, TIC); 2958 2959 /* Only allow ECI interrupts */ 2960 synchronize_irq(priv->emac_irq); 2961 if (info->nc_queues) 2962 napi_disable(&priv->napi[RAVB_NC]); 2963 napi_disable(&priv->napi[RAVB_BE]); 2964 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2965 2966 /* Enable MagicPacket */ 2967 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2968 2969 return enable_irq_wake(priv->emac_irq); 2970} 2971 2972static int ravb_wol_restore(struct net_device *ndev) 2973{ 2974 struct ravb_private *priv = netdev_priv(ndev); 2975 const struct ravb_hw_info *info = priv->info; 2976 2977 if (info->nc_queues) 2978 napi_enable(&priv->napi[RAVB_NC]); 2979 napi_enable(&priv->napi[RAVB_BE]); 2980 2981 /* Disable MagicPacket */ 2982 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2983 2984 ravb_close(ndev); 2985 2986 return disable_irq_wake(priv->emac_irq); 2987} 2988 2989static int __maybe_unused ravb_suspend(struct device *dev) 2990{ 2991 struct net_device *ndev = dev_get_drvdata(dev); 2992 struct ravb_private *priv = netdev_priv(ndev); 2993 int ret; 2994 2995 if (!netif_running(ndev)) 2996 return 0; 2997 2998 netif_device_detach(ndev); 2999 3000 if (priv->wol_enabled) 3001 ret = ravb_wol_setup(ndev); 3002 else 3003 ret = ravb_close(ndev); 3004 3005 if (priv->info->ccc_gac) 3006 ravb_ptp_stop(ndev); 3007 3008 return ret; 3009} 3010 3011static int __maybe_unused ravb_resume(struct device *dev) 3012{ 3013 struct net_device *ndev = dev_get_drvdata(dev); 3014 struct ravb_private *priv = netdev_priv(ndev); 3015 const struct ravb_hw_info *info = priv->info; 3016 int ret = 0; 3017 3018 /* If WoL is enabled set reset mode to rearm the WoL logic */ 3019 if (priv->wol_enabled) { 3020 ret = ravb_set_opmode(ndev, CCC_OPC_RESET); 3021 if (ret) 3022 return ret; 3023 } 3024 3025 /* All register have been reset to default values. 3026 * Restore all registers which where setup at probe time and 3027 * reopen device if it was running before system suspended. 3028 */ 3029 3030 /* Set AVB config mode */ 3031 ret = ravb_set_config_mode(ndev); 3032 if (ret) 3033 return ret; 3034 3035 if (info->gptp || info->ccc_gac) { 3036 /* Set GTI value */ 3037 ret = ravb_set_gti(ndev); 3038 if (ret) 3039 return ret; 3040 3041 /* Request GTI loading */ 3042 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 3043 } 3044 3045 if (info->internal_delay) 3046 ravb_set_delay_mode(ndev); 3047 3048 /* Restore descriptor base address table */ 3049 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3050 3051 if (priv->info->ccc_gac) 3052 ravb_ptp_init(ndev, priv->pdev); 3053 3054 if (netif_running(ndev)) { 3055 if (priv->wol_enabled) { 3056 ret = ravb_wol_restore(ndev); 3057 if (ret) 3058 return ret; 3059 } 3060 ret = ravb_open(ndev); 3061 if (ret < 0) 3062 return ret; 3063 ravb_set_rx_mode(ndev); 3064 netif_device_attach(ndev); 3065 } 3066 3067 return ret; 3068} 3069 3070static int __maybe_unused ravb_runtime_nop(struct device *dev) 3071{ 3072 /* Runtime PM callback shared between ->runtime_suspend() 3073 * and ->runtime_resume(). Simply returns success. 3074 * 3075 * This driver re-initializes all registers after 3076 * pm_runtime_get_sync() anyway so there is no need 3077 * to save and restore registers here. 3078 */ 3079 return 0; 3080} 3081 3082static const struct dev_pm_ops ravb_dev_pm_ops = { 3083 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3084 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3085}; 3086 3087static struct platform_driver ravb_driver = { 3088 .probe = ravb_probe, 3089 .remove = ravb_remove, 3090 .driver = { 3091 .name = "ravb", 3092 .pm = &ravb_dev_pm_ops, 3093 .of_match_table = ravb_match_table, 3094 }, 3095}; 3096 3097module_platform_driver(ravb_driver); 3098 3099MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3100MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3101MODULE_LICENSE("GPL v2"); 3102