1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
5 */
6
7#ifndef __SPARX5_QOS_H__
8#define __SPARX5_QOS_H__
9
10#include <linux/netdevice.h>
11
12/* Number of Layers */
13#define SPX5_HSCH_LAYER_CNT 3
14
15/* Scheduling elements per layer */
16#define SPX5_HSCH_L0_SE_CNT 5040
17#define SPX5_HSCH_L1_SE_CNT 64
18#define SPX5_HSCH_L2_SE_CNT 64
19
20/* Calculate Layer 0 Scheduler Element when using normal hierarchy */
21#define SPX5_HSCH_L0_GET_IDX(port, queue) ((64 * (port)) + (8 * (queue)))
22
23/* Number of leak groups */
24#define SPX5_HSCH_LEAK_GRP_CNT 4
25
26/* Scheduler modes */
27#define SPX5_SE_MODE_LINERATE 0
28#define SPX5_SE_MODE_DATARATE 1
29
30/* Rate and burst */
31#define SPX5_SE_RATE_MAX 262143
32#define SPX5_SE_BURST_MAX 127
33#define SPX5_SE_RATE_MIN 1
34#define SPX5_SE_BURST_MIN 1
35#define SPX5_SE_BURST_UNIT 4096
36
37/* Dwrr */
38#define SPX5_DWRR_COST_MAX 63
39
40struct sparx5_shaper {
41	u32 mode;
42	u32 rate;
43	u32 burst;
44};
45
46struct sparx5_lg {
47	u32 max_rate;
48	u32 resolution;
49	u32 leak_time;
50	u32 max_ses;
51};
52
53struct sparx5_layer {
54	struct sparx5_lg leak_groups[SPX5_HSCH_LEAK_GRP_CNT];
55};
56
57struct sparx5_dwrr {
58	u32 count; /* Number of inputs running dwrr */
59	u8 cost[SPX5_PRIOS];
60};
61
62int sparx5_qos_init(struct sparx5 *sparx5);
63
64/* Multi-Queue Priority */
65int sparx5_tc_mqprio_add(struct net_device *ndev, u8 num_tc);
66int sparx5_tc_mqprio_del(struct net_device *ndev);
67
68/* Token Bucket Filter */
69struct tc_tbf_qopt_offload_replace_params;
70int sparx5_tc_tbf_add(struct sparx5_port *port,
71		      struct tc_tbf_qopt_offload_replace_params *params,
72		      u32 layer, u32 idx);
73int sparx5_tc_tbf_del(struct sparx5_port *port, u32 layer, u32 idx);
74
75/* Enhanced Transmission Selection */
76struct tc_ets_qopt_offload_replace_params;
77int sparx5_tc_ets_add(struct sparx5_port *port,
78		      struct tc_ets_qopt_offload_replace_params *params);
79
80int sparx5_tc_ets_del(struct sparx5_port *port);
81
82#endif	/* __SPARX5_QOS_H__ */
83