1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/export.h> 7#include <linux/err.h> 8#include <linux/device.h> 9#include <linux/pci.h> 10#include <linux/interrupt.h> 11#include <linux/wait.h> 12#include <linux/types.h> 13#include <linux/skbuff.h> 14#include <linux/if_vlan.h> 15#include <linux/log2.h> 16#include <linux/string.h> 17 18#include "pci_hw.h" 19#include "pci.h" 20#include "core.h" 21#include "cmd.h" 22#include "port.h" 23#include "resources.h" 24 25#define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27#define mlxsw_pci_read32(mlxsw_pci, reg) \ 28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29 30enum mlxsw_pci_queue_type { 31 MLXSW_PCI_QUEUE_TYPE_SDQ, 32 MLXSW_PCI_QUEUE_TYPE_RDQ, 33 MLXSW_PCI_QUEUE_TYPE_CQ, 34 MLXSW_PCI_QUEUE_TYPE_EQ, 35}; 36 37#define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38 39static const u16 mlxsw_pci_doorbell_type_offset[] = { 40 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 41 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 42 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 43 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 44}; 45 46static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 47 0, /* unused */ 48 0, /* unused */ 49 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 50 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 51}; 52 53struct mlxsw_pci_mem_item { 54 char *buf; 55 dma_addr_t mapaddr; 56 size_t size; 57}; 58 59struct mlxsw_pci_queue_elem_info { 60 char *elem; /* pointer to actual dma mapped element mem chunk */ 61 union { 62 struct { 63 struct sk_buff *skb; 64 } sdq; 65 struct { 66 struct sk_buff *skb; 67 } rdq; 68 } u; 69}; 70 71struct mlxsw_pci_queue { 72 spinlock_t lock; /* for queue accesses */ 73 struct mlxsw_pci_mem_item mem_item; 74 struct mlxsw_pci_queue_elem_info *elem_info; 75 u16 producer_counter; 76 u16 consumer_counter; 77 u16 count; /* number of elements in queue */ 78 u8 num; /* queue number */ 79 u8 elem_size; /* size of one element */ 80 enum mlxsw_pci_queue_type type; 81 struct tasklet_struct tasklet; /* queue processing tasklet */ 82 struct mlxsw_pci *pci; 83 union { 84 struct { 85 u32 comp_sdq_count; 86 u32 comp_rdq_count; 87 enum mlxsw_pci_cqe_v v; 88 } cq; 89 struct { 90 u32 ev_cmd_count; 91 u32 ev_comp_count; 92 u32 ev_other_count; 93 } eq; 94 } u; 95}; 96 97struct mlxsw_pci_queue_type_group { 98 struct mlxsw_pci_queue *q; 99 u8 count; /* number of queues in group */ 100}; 101 102struct mlxsw_pci { 103 struct pci_dev *pdev; 104 u8 __iomem *hw_addr; 105 u64 free_running_clock_offset; 106 u64 utc_sec_offset; 107 u64 utc_nsec_offset; 108 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 109 u32 doorbell_offset; 110 struct mlxsw_core *core; 111 struct { 112 struct mlxsw_pci_mem_item *items; 113 unsigned int count; 114 } fw_area; 115 struct { 116 struct mlxsw_pci_mem_item out_mbox; 117 struct mlxsw_pci_mem_item in_mbox; 118 struct mutex lock; /* Lock access to command registers */ 119 bool nopoll; 120 wait_queue_head_t wait; 121 bool wait_done; 122 struct { 123 u8 status; 124 u64 out_param; 125 } comp; 126 } cmd; 127 struct mlxsw_bus_info bus_info; 128 const struct pci_device_id *id; 129 enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 130 u8 num_sdq_cqs; /* Number of CQs used for SDQs */ 131}; 132 133static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 134{ 135 tasklet_schedule(&q->tasklet); 136} 137 138static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 139 size_t elem_size, int elem_index) 140{ 141 return q->mem_item.buf + (elem_size * elem_index); 142} 143 144static struct mlxsw_pci_queue_elem_info * 145mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 146{ 147 return &q->elem_info[elem_index]; 148} 149 150static struct mlxsw_pci_queue_elem_info * 151mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 152{ 153 int index = q->producer_counter & (q->count - 1); 154 155 if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 156 return NULL; 157 return mlxsw_pci_queue_elem_info_get(q, index); 158} 159 160static struct mlxsw_pci_queue_elem_info * 161mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 162{ 163 int index = q->consumer_counter & (q->count - 1); 164 165 return mlxsw_pci_queue_elem_info_get(q, index); 166} 167 168static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 169{ 170 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 171} 172 173static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 174{ 175 return owner_bit != !!(q->consumer_counter & q->count); 176} 177 178static struct mlxsw_pci_queue_type_group * 179mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 180 enum mlxsw_pci_queue_type q_type) 181{ 182 return &mlxsw_pci->queues[q_type]; 183} 184 185static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 186 enum mlxsw_pci_queue_type q_type) 187{ 188 struct mlxsw_pci_queue_type_group *queue_group; 189 190 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 191 return queue_group->count; 192} 193 194static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 195{ 196 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 197} 198 199static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 200{ 201 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 202} 203 204static struct mlxsw_pci_queue * 205__mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 206 enum mlxsw_pci_queue_type q_type, u8 q_num) 207{ 208 return &mlxsw_pci->queues[q_type].q[q_num]; 209} 210 211static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 212 u8 q_num) 213{ 214 return __mlxsw_pci_queue_get(mlxsw_pci, 215 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 216} 217 218static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 219 u8 q_num) 220{ 221 return __mlxsw_pci_queue_get(mlxsw_pci, 222 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 223} 224 225static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 226 u8 q_num) 227{ 228 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 229} 230 231static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 232 u8 q_num) 233{ 234 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 235} 236 237static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 238 struct mlxsw_pci_queue *q, 239 u16 val) 240{ 241 mlxsw_pci_write32(mlxsw_pci, 242 DOORBELL(mlxsw_pci->doorbell_offset, 243 mlxsw_pci_doorbell_type_offset[q->type], 244 q->num), val); 245} 246 247static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 248 struct mlxsw_pci_queue *q, 249 u16 val) 250{ 251 mlxsw_pci_write32(mlxsw_pci, 252 DOORBELL(mlxsw_pci->doorbell_offset, 253 mlxsw_pci_doorbell_arm_type_offset[q->type], 254 q->num), val); 255} 256 257static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 258 struct mlxsw_pci_queue *q) 259{ 260 wmb(); /* ensure all writes are done before we ring a bell */ 261 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 262} 263 264static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 265 struct mlxsw_pci_queue *q) 266{ 267 wmb(); /* ensure all writes are done before we ring a bell */ 268 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 269 q->consumer_counter + q->count); 270} 271 272static void 273mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 274 struct mlxsw_pci_queue *q) 275{ 276 wmb(); /* ensure all writes are done before we ring a bell */ 277 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 278} 279 280static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 281 int page_index) 282{ 283 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 284} 285 286static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 287 struct mlxsw_pci_queue *q) 288{ 289 int tclass; 290 int lp; 291 int i; 292 int err; 293 294 q->producer_counter = 0; 295 q->consumer_counter = 0; 296 tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC : 297 MLXSW_PCI_SDQ_CTL_TC; 298 lp = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE : 299 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE; 300 301 /* Set CQ of same number of this SDQ. */ 302 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 303 mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp); 304 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); 305 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 306 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 307 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 308 309 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 310 } 311 312 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 313 if (err) 314 return err; 315 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 316 return 0; 317} 318 319static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 320 struct mlxsw_pci_queue *q) 321{ 322 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 323} 324 325static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 326 int index, char *frag_data, size_t frag_len, 327 int direction) 328{ 329 struct pci_dev *pdev = mlxsw_pci->pdev; 330 dma_addr_t mapaddr; 331 332 mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction); 333 if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) { 334 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 335 return -EIO; 336 } 337 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 338 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 339 return 0; 340} 341 342static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 343 int index, int direction) 344{ 345 struct pci_dev *pdev = mlxsw_pci->pdev; 346 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 347 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 348 349 if (!frag_len) 350 return; 351 dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); 352} 353 354static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 355 struct mlxsw_pci_queue_elem_info *elem_info) 356{ 357 size_t buf_len = MLXSW_PORT_MAX_MTU; 358 char *wqe = elem_info->elem; 359 struct sk_buff *skb; 360 int err; 361 362 skb = netdev_alloc_skb_ip_align(NULL, buf_len); 363 if (!skb) 364 return -ENOMEM; 365 366 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 367 buf_len, DMA_FROM_DEVICE); 368 if (err) 369 goto err_frag_map; 370 371 elem_info->u.rdq.skb = skb; 372 return 0; 373 374err_frag_map: 375 dev_kfree_skb_any(skb); 376 return err; 377} 378 379static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 380 struct mlxsw_pci_queue_elem_info *elem_info) 381{ 382 struct sk_buff *skb; 383 char *wqe; 384 385 skb = elem_info->u.rdq.skb; 386 wqe = elem_info->elem; 387 388 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 389 dev_kfree_skb_any(skb); 390} 391 392static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 393 struct mlxsw_pci_queue *q) 394{ 395 struct mlxsw_pci_queue_elem_info *elem_info; 396 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 397 int i; 398 int err; 399 400 q->producer_counter = 0; 401 q->consumer_counter = 0; 402 403 /* Set CQ of same number of this RDQ with base 404 * above SDQ count as the lower ones are assigned to SDQs. 405 */ 406 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 407 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 408 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 409 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 410 411 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 412 } 413 414 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 415 if (err) 416 return err; 417 418 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 419 420 for (i = 0; i < q->count; i++) { 421 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 422 BUG_ON(!elem_info); 423 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 424 if (err) 425 goto rollback; 426 /* Everything is set up, ring doorbell to pass elem to HW */ 427 q->producer_counter++; 428 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 429 } 430 431 return 0; 432 433rollback: 434 for (i--; i >= 0; i--) { 435 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 436 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 437 } 438 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 439 440 return err; 441} 442 443static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 444 struct mlxsw_pci_queue *q) 445{ 446 struct mlxsw_pci_queue_elem_info *elem_info; 447 int i; 448 449 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 450 for (i = 0; i < q->count; i++) { 451 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 452 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 453 } 454} 455 456static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 457 struct mlxsw_pci_queue *q) 458{ 459 q->u.cq.v = mlxsw_pci->max_cqe_ver; 460 461 if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 462 q->num < mlxsw_pci->num_sdq_cqs && 463 !mlxsw_core_sdq_supports_cqe_v2(mlxsw_pci->core)) 464 q->u.cq.v = MLXSW_PCI_CQE_V1; 465} 466 467static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 468 struct mlxsw_pci_queue *q) 469{ 470 int i; 471 int err; 472 473 q->consumer_counter = 0; 474 475 for (i = 0; i < q->count; i++) { 476 char *elem = mlxsw_pci_queue_elem_get(q, i); 477 478 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 479 } 480 481 if (q->u.cq.v == MLXSW_PCI_CQE_V1) 482 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 483 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 484 else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 485 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 486 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 487 488 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 489 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 490 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 491 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 492 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 493 494 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 495 } 496 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 497 if (err) 498 return err; 499 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 500 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 501 return 0; 502} 503 504static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 505 struct mlxsw_pci_queue *q) 506{ 507 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 508} 509 510static unsigned int mlxsw_pci_read32_off(struct mlxsw_pci *mlxsw_pci, 511 ptrdiff_t off) 512{ 513 return ioread32be(mlxsw_pci->hw_addr + off); 514} 515 516static void mlxsw_pci_skb_cb_ts_set(struct mlxsw_pci *mlxsw_pci, 517 struct sk_buff *skb, 518 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 519{ 520 u8 ts_type; 521 522 if (cqe_v != MLXSW_PCI_CQE_V2) 523 return; 524 525 ts_type = mlxsw_pci_cqe2_time_stamp_type_get(cqe); 526 527 if (ts_type != MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC && 528 ts_type != MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC) 529 return; 530 531 mlxsw_skb_cb(skb)->cqe_ts.sec = mlxsw_pci_cqe2_time_stamp_sec_get(cqe); 532 mlxsw_skb_cb(skb)->cqe_ts.nsec = 533 mlxsw_pci_cqe2_time_stamp_nsec_get(cqe); 534} 535 536static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 537 struct mlxsw_pci_queue *q, 538 u16 consumer_counter_limit, 539 enum mlxsw_pci_cqe_v cqe_v, 540 char *cqe) 541{ 542 struct pci_dev *pdev = mlxsw_pci->pdev; 543 struct mlxsw_pci_queue_elem_info *elem_info; 544 struct mlxsw_tx_info tx_info; 545 char *wqe; 546 struct sk_buff *skb; 547 int i; 548 549 spin_lock(&q->lock); 550 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 551 tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; 552 skb = elem_info->u.sdq.skb; 553 wqe = elem_info->elem; 554 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 555 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 556 557 if (unlikely(!tx_info.is_emad && 558 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 559 mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe); 560 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 561 tx_info.local_port); 562 skb = NULL; 563 } 564 565 if (skb) 566 dev_kfree_skb_any(skb); 567 elem_info->u.sdq.skb = NULL; 568 569 if (q->consumer_counter++ != consumer_counter_limit) 570 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 571 spin_unlock(&q->lock); 572} 573 574static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb, 575 const char *cqe) 576{ 577 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 578 579 if (mlxsw_pci_cqe2_tx_lag_get(cqe)) { 580 cb->rx_md_info.tx_port_is_lag = true; 581 cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe); 582 cb->rx_md_info.tx_lag_port_index = 583 mlxsw_pci_cqe2_tx_lag_subport_get(cqe); 584 } else { 585 cb->rx_md_info.tx_port_is_lag = false; 586 cb->rx_md_info.tx_sys_port = 587 mlxsw_pci_cqe2_tx_system_port_get(cqe); 588 } 589 590 if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT && 591 cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID) 592 cb->rx_md_info.tx_port_valid = 1; 593 else 594 cb->rx_md_info.tx_port_valid = 0; 595} 596 597static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe) 598{ 599 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 600 601 cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe); 602 if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID) 603 cb->rx_md_info.tx_congestion_valid = 1; 604 else 605 cb->rx_md_info.tx_congestion_valid = 0; 606 cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT; 607 608 cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe); 609 if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID) 610 cb->rx_md_info.latency_valid = 1; 611 else 612 cb->rx_md_info.latency_valid = 0; 613 614 cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe); 615 if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID) 616 cb->rx_md_info.tx_tc_valid = 1; 617 else 618 cb->rx_md_info.tx_tc_valid = 0; 619 620 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 621} 622 623static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 624 struct mlxsw_pci_queue *q, 625 u16 consumer_counter_limit, 626 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 627{ 628 struct pci_dev *pdev = mlxsw_pci->pdev; 629 struct mlxsw_pci_queue_elem_info *elem_info; 630 struct mlxsw_rx_info rx_info = {}; 631 char wqe[MLXSW_PCI_WQE_SIZE]; 632 struct sk_buff *skb; 633 u16 byte_count; 634 int err; 635 636 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 637 skb = elem_info->u.rdq.skb; 638 memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE); 639 640 if (q->consumer_counter++ != consumer_counter_limit) 641 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 642 643 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 644 if (err) { 645 dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 646 goto out; 647 } 648 649 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 650 651 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 652 rx_info.is_lag = true; 653 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 654 rx_info.lag_port_index = 655 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 656 } else { 657 rx_info.is_lag = false; 658 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 659 } 660 661 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 662 663 if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || 664 rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) { 665 u32 cookie_index = 0; 666 667 if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) 668 cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe); 669 mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index; 670 } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 && 671 rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 && 672 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 673 rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe); 674 mlxsw_pci_cqe_rdq_md_init(skb, cqe); 675 } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE && 676 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 677 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 678 } 679 680 mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe); 681 682 byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 683 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 684 byte_count -= ETH_FCS_LEN; 685 skb_put(skb, byte_count); 686 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 687 688out: 689 /* Everything is set up, ring doorbell to pass elem to HW */ 690 q->producer_counter++; 691 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 692 return; 693} 694 695static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 696{ 697 struct mlxsw_pci_queue_elem_info *elem_info; 698 char *elem; 699 bool owner_bit; 700 701 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 702 elem = elem_info->elem; 703 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 704 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 705 return NULL; 706 q->consumer_counter++; 707 rmb(); /* make sure we read owned bit before the rest of elem */ 708 return elem; 709} 710 711static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t) 712{ 713 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 714 struct mlxsw_pci *mlxsw_pci = q->pci; 715 char *cqe; 716 int items = 0; 717 int credits = q->count >> 1; 718 719 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 720 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 721 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 722 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 723 char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 724 725 memcpy(ncqe, cqe, q->elem_size); 726 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 727 728 if (sendq) { 729 struct mlxsw_pci_queue *sdq; 730 731 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 732 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 733 wqe_counter, q->u.cq.v, ncqe); 734 q->u.cq.comp_sdq_count++; 735 } else { 736 struct mlxsw_pci_queue *rdq; 737 738 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 739 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 740 wqe_counter, q->u.cq.v, ncqe); 741 q->u.cq.comp_rdq_count++; 742 } 743 if (++items == credits) 744 break; 745 } 746 if (items) 747 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 748} 749 750static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 751{ 752 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 753 MLXSW_PCI_CQE01_COUNT; 754} 755 756static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 757{ 758 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 759 MLXSW_PCI_CQE01_SIZE; 760} 761 762static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 763 struct mlxsw_pci_queue *q) 764{ 765 int i; 766 int err; 767 768 q->consumer_counter = 0; 769 770 for (i = 0; i < q->count; i++) { 771 char *elem = mlxsw_pci_queue_elem_get(q, i); 772 773 mlxsw_pci_eqe_owner_set(elem, 1); 774 } 775 776 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 777 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 778 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 779 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 780 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 781 782 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 783 } 784 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 785 if (err) 786 return err; 787 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 788 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 789 return 0; 790} 791 792static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 793 struct mlxsw_pci_queue *q) 794{ 795 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 796} 797 798static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 799{ 800 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 801 mlxsw_pci->cmd.comp.out_param = 802 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 803 mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 804 mlxsw_pci->cmd.wait_done = true; 805 wake_up(&mlxsw_pci->cmd.wait); 806} 807 808static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 809{ 810 struct mlxsw_pci_queue_elem_info *elem_info; 811 char *elem; 812 bool owner_bit; 813 814 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 815 elem = elem_info->elem; 816 owner_bit = mlxsw_pci_eqe_owner_get(elem); 817 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 818 return NULL; 819 q->consumer_counter++; 820 rmb(); /* make sure we read owned bit before the rest of elem */ 821 return elem; 822} 823 824static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t) 825{ 826 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 827 struct mlxsw_pci *mlxsw_pci = q->pci; 828 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 829 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 830 char *eqe; 831 u8 cqn; 832 bool cq_handle = false; 833 int items = 0; 834 int credits = q->count >> 1; 835 836 memset(&active_cqns, 0, sizeof(active_cqns)); 837 838 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 839 840 /* Command interface completion events are always received on 841 * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events 842 * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1). 843 */ 844 switch (q->num) { 845 case MLXSW_PCI_EQ_ASYNC_NUM: 846 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 847 q->u.eq.ev_cmd_count++; 848 break; 849 case MLXSW_PCI_EQ_COMP_NUM: 850 cqn = mlxsw_pci_eqe_cqn_get(eqe); 851 set_bit(cqn, active_cqns); 852 cq_handle = true; 853 q->u.eq.ev_comp_count++; 854 break; 855 default: 856 q->u.eq.ev_other_count++; 857 } 858 if (++items == credits) 859 break; 860 } 861 if (items) { 862 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 863 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 864 } 865 866 if (!cq_handle) 867 return; 868 for_each_set_bit(cqn, active_cqns, cq_count) { 869 q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 870 mlxsw_pci_queue_tasklet_schedule(q); 871 } 872} 873 874struct mlxsw_pci_queue_ops { 875 const char *name; 876 enum mlxsw_pci_queue_type type; 877 void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 878 struct mlxsw_pci_queue *q); 879 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 880 struct mlxsw_pci_queue *q); 881 void (*fini)(struct mlxsw_pci *mlxsw_pci, 882 struct mlxsw_pci_queue *q); 883 void (*tasklet)(struct tasklet_struct *t); 884 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 885 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 886 u16 elem_count; 887 u8 elem_size; 888}; 889 890static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 891 .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 892 .init = mlxsw_pci_sdq_init, 893 .fini = mlxsw_pci_sdq_fini, 894 .elem_count = MLXSW_PCI_WQE_COUNT, 895 .elem_size = MLXSW_PCI_WQE_SIZE, 896}; 897 898static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 899 .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 900 .init = mlxsw_pci_rdq_init, 901 .fini = mlxsw_pci_rdq_fini, 902 .elem_count = MLXSW_PCI_WQE_COUNT, 903 .elem_size = MLXSW_PCI_WQE_SIZE 904}; 905 906static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 907 .type = MLXSW_PCI_QUEUE_TYPE_CQ, 908 .pre_init = mlxsw_pci_cq_pre_init, 909 .init = mlxsw_pci_cq_init, 910 .fini = mlxsw_pci_cq_fini, 911 .tasklet = mlxsw_pci_cq_tasklet, 912 .elem_count_f = mlxsw_pci_cq_elem_count, 913 .elem_size_f = mlxsw_pci_cq_elem_size 914}; 915 916static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 917 .type = MLXSW_PCI_QUEUE_TYPE_EQ, 918 .init = mlxsw_pci_eq_init, 919 .fini = mlxsw_pci_eq_fini, 920 .tasklet = mlxsw_pci_eq_tasklet, 921 .elem_count = MLXSW_PCI_EQE_COUNT, 922 .elem_size = MLXSW_PCI_EQE_SIZE 923}; 924 925static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 926 const struct mlxsw_pci_queue_ops *q_ops, 927 struct mlxsw_pci_queue *q, u8 q_num) 928{ 929 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 930 int i; 931 int err; 932 933 q->num = q_num; 934 if (q_ops->pre_init) 935 q_ops->pre_init(mlxsw_pci, q); 936 937 spin_lock_init(&q->lock); 938 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 939 q_ops->elem_count; 940 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 941 q_ops->elem_size; 942 q->type = q_ops->type; 943 q->pci = mlxsw_pci; 944 945 if (q_ops->tasklet) 946 tasklet_setup(&q->tasklet, q_ops->tasklet); 947 948 mem_item->size = MLXSW_PCI_AQ_SIZE; 949 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 950 mem_item->size, &mem_item->mapaddr, 951 GFP_KERNEL); 952 if (!mem_item->buf) 953 return -ENOMEM; 954 955 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 956 if (!q->elem_info) { 957 err = -ENOMEM; 958 goto err_elem_info_alloc; 959 } 960 961 /* Initialize dma mapped elements info elem_info for 962 * future easy access. 963 */ 964 for (i = 0; i < q->count; i++) { 965 struct mlxsw_pci_queue_elem_info *elem_info; 966 967 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 968 elem_info->elem = 969 __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 970 } 971 972 mlxsw_cmd_mbox_zero(mbox); 973 err = q_ops->init(mlxsw_pci, mbox, q); 974 if (err) 975 goto err_q_ops_init; 976 return 0; 977 978err_q_ops_init: 979 kfree(q->elem_info); 980err_elem_info_alloc: 981 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 982 mem_item->buf, mem_item->mapaddr); 983 return err; 984} 985 986static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 987 const struct mlxsw_pci_queue_ops *q_ops, 988 struct mlxsw_pci_queue *q) 989{ 990 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 991 992 q_ops->fini(mlxsw_pci, q); 993 kfree(q->elem_info); 994 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 995 mem_item->buf, mem_item->mapaddr); 996} 997 998static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 999 const struct mlxsw_pci_queue_ops *q_ops, 1000 u8 num_qs) 1001{ 1002 struct mlxsw_pci_queue_type_group *queue_group; 1003 int i; 1004 int err; 1005 1006 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1007 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 1008 if (!queue_group->q) 1009 return -ENOMEM; 1010 1011 for (i = 0; i < num_qs; i++) { 1012 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 1013 &queue_group->q[i], i); 1014 if (err) 1015 goto err_queue_init; 1016 } 1017 queue_group->count = num_qs; 1018 1019 return 0; 1020 1021err_queue_init: 1022 for (i--; i >= 0; i--) 1023 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1024 kfree(queue_group->q); 1025 return err; 1026} 1027 1028static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 1029 const struct mlxsw_pci_queue_ops *q_ops) 1030{ 1031 struct mlxsw_pci_queue_type_group *queue_group; 1032 int i; 1033 1034 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1035 for (i = 0; i < queue_group->count; i++) 1036 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1037 kfree(queue_group->q); 1038} 1039 1040static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1041{ 1042 struct pci_dev *pdev = mlxsw_pci->pdev; 1043 u8 num_sdqs; 1044 u8 sdq_log2sz; 1045 u8 num_rdqs; 1046 u8 rdq_log2sz; 1047 u8 num_cqs; 1048 u8 cq_log2sz; 1049 u8 cqv2_log2sz; 1050 u8 num_eqs; 1051 u8 eq_log2sz; 1052 int err; 1053 1054 mlxsw_cmd_mbox_zero(mbox); 1055 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1056 if (err) 1057 return err; 1058 1059 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1060 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1061 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1062 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1063 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1064 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1065 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 1066 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1067 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1068 1069 if (num_sdqs + num_rdqs > num_cqs || 1070 num_sdqs < MLXSW_PCI_SDQS_MIN || 1071 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1072 dev_err(&pdev->dev, "Unsupported number of queues\n"); 1073 return -EINVAL; 1074 } 1075 1076 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1077 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1078 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 1079 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 1080 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 1081 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1082 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1083 return -EINVAL; 1084 } 1085 1086 mlxsw_pci->num_sdq_cqs = num_sdqs; 1087 1088 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1089 num_eqs); 1090 if (err) { 1091 dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1092 return err; 1093 } 1094 1095 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1096 num_cqs); 1097 if (err) { 1098 dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1099 goto err_cqs_init; 1100 } 1101 1102 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1103 num_sdqs); 1104 if (err) { 1105 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1106 goto err_sdqs_init; 1107 } 1108 1109 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1110 num_rdqs); 1111 if (err) { 1112 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1113 goto err_rdqs_init; 1114 } 1115 1116 /* We have to poll in command interface until queues are initialized */ 1117 mlxsw_pci->cmd.nopoll = true; 1118 return 0; 1119 1120err_rdqs_init: 1121 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1122err_sdqs_init: 1123 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1124err_cqs_init: 1125 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1126 return err; 1127} 1128 1129static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1130{ 1131 mlxsw_pci->cmd.nopoll = false; 1132 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1133 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1134 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1135 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1136} 1137 1138static void 1139mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1140 char *mbox, int index, 1141 const struct mlxsw_swid_config *swid) 1142{ 1143 u8 mask = 0; 1144 1145 if (swid->used_type) { 1146 mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1147 mbox, index, swid->type); 1148 mask |= 1; 1149 } 1150 if (swid->used_properties) { 1151 mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1152 mbox, index, swid->properties); 1153 mask |= 2; 1154 } 1155 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1156} 1157 1158static int 1159mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1160 const struct mlxsw_config_profile *profile, 1161 struct mlxsw_res *res) 1162{ 1163 u64 single_size, double_size, linear_size; 1164 int err; 1165 1166 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1167 &single_size, &double_size, 1168 &linear_size); 1169 if (err) 1170 return err; 1171 1172 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1173 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1174 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1175 1176 return 0; 1177} 1178 1179static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1180 const struct mlxsw_config_profile *profile, 1181 struct mlxsw_res *res) 1182{ 1183 int i; 1184 int err; 1185 1186 mlxsw_cmd_mbox_zero(mbox); 1187 1188 if (profile->used_max_vepa_channels) { 1189 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1190 mbox, 1); 1191 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1192 mbox, profile->max_vepa_channels); 1193 } 1194 if (profile->used_max_lag) { 1195 mlxsw_cmd_mbox_config_profile_set_max_lag_set(mbox, 1); 1196 mlxsw_cmd_mbox_config_profile_max_lag_set(mbox, 1197 profile->max_lag); 1198 } 1199 if (profile->used_max_mid) { 1200 mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1201 mbox, 1); 1202 mlxsw_cmd_mbox_config_profile_max_mid_set( 1203 mbox, profile->max_mid); 1204 } 1205 if (profile->used_max_pgt) { 1206 mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1207 mbox, 1); 1208 mlxsw_cmd_mbox_config_profile_max_pgt_set( 1209 mbox, profile->max_pgt); 1210 } 1211 if (profile->used_max_system_port) { 1212 mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1213 mbox, 1); 1214 mlxsw_cmd_mbox_config_profile_max_system_port_set( 1215 mbox, profile->max_system_port); 1216 } 1217 if (profile->used_max_vlan_groups) { 1218 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1219 mbox, 1); 1220 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1221 mbox, profile->max_vlan_groups); 1222 } 1223 if (profile->used_max_regions) { 1224 mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1225 mbox, 1); 1226 mlxsw_cmd_mbox_config_profile_max_regions_set( 1227 mbox, profile->max_regions); 1228 } 1229 if (profile->used_flood_tables) { 1230 mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1231 mbox, 1); 1232 mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1233 mbox, profile->max_flood_tables); 1234 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1235 mbox, profile->max_vid_flood_tables); 1236 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 1237 mbox, profile->max_fid_offset_flood_tables); 1238 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 1239 mbox, profile->fid_offset_flood_table_size); 1240 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1241 mbox, profile->max_fid_flood_tables); 1242 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1243 mbox, profile->fid_flood_table_size); 1244 } 1245 if (profile->used_flood_mode) { 1246 mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1247 mbox, 1); 1248 mlxsw_cmd_mbox_config_profile_flood_mode_set( 1249 mbox, profile->flood_mode); 1250 } 1251 if (profile->used_max_ib_mc) { 1252 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1253 mbox, 1); 1254 mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1255 mbox, profile->max_ib_mc); 1256 } 1257 if (profile->used_max_pkey) { 1258 mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1259 mbox, 1); 1260 mlxsw_cmd_mbox_config_profile_max_pkey_set( 1261 mbox, profile->max_pkey); 1262 } 1263 if (profile->used_ar_sec) { 1264 mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1265 mbox, 1); 1266 mlxsw_cmd_mbox_config_profile_ar_sec_set( 1267 mbox, profile->ar_sec); 1268 } 1269 if (profile->used_adaptive_routing_group_cap) { 1270 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1271 mbox, 1); 1272 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1273 mbox, profile->adaptive_routing_group_cap); 1274 } 1275 if (profile->used_ubridge) { 1276 mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1); 1277 mlxsw_cmd_mbox_config_profile_ubridge_set(mbox, 1278 profile->ubridge); 1279 } 1280 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1281 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1282 if (err) 1283 return err; 1284 1285 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1286 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1287 MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1288 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1289 1); 1290 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1291 MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1292 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1293 mbox, 1); 1294 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1295 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1296 } 1297 1298 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1299 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1300 &profile->swid_config[i]); 1301 1302 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 1303 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 1304 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 1305 } 1306 1307 if (profile->used_cqe_time_stamp_type) { 1308 mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox, 1309 1); 1310 mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox, 1311 profile->cqe_time_stamp_type); 1312 } 1313 1314 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1315} 1316 1317static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1318{ 1319 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1320 int err; 1321 1322 mlxsw_cmd_mbox_zero(mbox); 1323 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1324 if (err) 1325 return err; 1326 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1327 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1328 return 0; 1329} 1330 1331static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1332 u16 num_pages) 1333{ 1334 struct mlxsw_pci_mem_item *mem_item; 1335 int nent = 0; 1336 int i; 1337 int err; 1338 1339 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1340 GFP_KERNEL); 1341 if (!mlxsw_pci->fw_area.items) 1342 return -ENOMEM; 1343 mlxsw_pci->fw_area.count = num_pages; 1344 1345 mlxsw_cmd_mbox_zero(mbox); 1346 for (i = 0; i < num_pages; i++) { 1347 mem_item = &mlxsw_pci->fw_area.items[i]; 1348 1349 mem_item->size = MLXSW_PCI_PAGE_SIZE; 1350 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1351 mem_item->size, 1352 &mem_item->mapaddr, GFP_KERNEL); 1353 if (!mem_item->buf) { 1354 err = -ENOMEM; 1355 goto err_alloc; 1356 } 1357 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 1358 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 1359 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 1360 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1361 if (err) 1362 goto err_cmd_map_fa; 1363 nent = 0; 1364 mlxsw_cmd_mbox_zero(mbox); 1365 } 1366 } 1367 1368 if (nent) { 1369 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1370 if (err) 1371 goto err_cmd_map_fa; 1372 } 1373 1374 return 0; 1375 1376err_cmd_map_fa: 1377err_alloc: 1378 for (i--; i >= 0; i--) { 1379 mem_item = &mlxsw_pci->fw_area.items[i]; 1380 1381 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1382 mem_item->buf, mem_item->mapaddr); 1383 } 1384 kfree(mlxsw_pci->fw_area.items); 1385 return err; 1386} 1387 1388static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1389{ 1390 struct mlxsw_pci_mem_item *mem_item; 1391 int i; 1392 1393 mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1394 1395 for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1396 mem_item = &mlxsw_pci->fw_area.items[i]; 1397 1398 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1399 mem_item->buf, mem_item->mapaddr); 1400 } 1401 kfree(mlxsw_pci->fw_area.items); 1402} 1403 1404static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1405{ 1406 struct mlxsw_pci *mlxsw_pci = dev_id; 1407 struct mlxsw_pci_queue *q; 1408 int i; 1409 1410 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1411 q = mlxsw_pci_eq_get(mlxsw_pci, i); 1412 mlxsw_pci_queue_tasklet_schedule(q); 1413 } 1414 return IRQ_HANDLED; 1415} 1416 1417static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 1418 struct mlxsw_pci_mem_item *mbox) 1419{ 1420 struct pci_dev *pdev = mlxsw_pci->pdev; 1421 int err = 0; 1422 1423 mbox->size = MLXSW_CMD_MBOX_SIZE; 1424 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, 1425 &mbox->mapaddr, GFP_KERNEL); 1426 if (!mbox->buf) { 1427 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 1428 err = -ENOMEM; 1429 } 1430 1431 return err; 1432} 1433 1434static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 1435 struct mlxsw_pci_mem_item *mbox) 1436{ 1437 struct pci_dev *pdev = mlxsw_pci->pdev; 1438 1439 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 1440 mbox->mapaddr); 1441} 1442 1443static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, 1444 const struct pci_device_id *id, 1445 u32 *p_sys_status) 1446{ 1447 unsigned long end; 1448 u32 val; 1449 1450 /* We must wait for the HW to become responsive. */ 1451 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1452 1453 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1454 do { 1455 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1456 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 1457 return 0; 1458 cond_resched(); 1459 } while (time_before(jiffies, end)); 1460 1461 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; 1462 1463 return -EBUSY; 1464} 1465 1466static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, 1467 const struct pci_device_id *id) 1468{ 1469 struct pci_dev *pdev = mlxsw_pci->pdev; 1470 char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1471 u32 sys_status; 1472 int err; 1473 1474 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1475 if (err) { 1476 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n", 1477 sys_status); 1478 return err; 1479 } 1480 1481 mlxsw_reg_mrsr_pack(mrsr_pl); 1482 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1483 if (err) 1484 return err; 1485 1486 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1487 if (err) { 1488 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", 1489 sys_status); 1490 return err; 1491 } 1492 1493 return 0; 1494} 1495 1496static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1497{ 1498 int err; 1499 1500 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1501 if (err < 0) 1502 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1503 return err; 1504} 1505 1506static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1507{ 1508 pci_free_irq_vectors(mlxsw_pci->pdev); 1509} 1510 1511static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1512 const struct mlxsw_config_profile *profile, 1513 struct mlxsw_res *res) 1514{ 1515 struct mlxsw_pci *mlxsw_pci = bus_priv; 1516 struct pci_dev *pdev = mlxsw_pci->pdev; 1517 char *mbox; 1518 u16 num_pages; 1519 int err; 1520 1521 mlxsw_pci->core = mlxsw_core; 1522 1523 mbox = mlxsw_cmd_mbox_alloc(); 1524 if (!mbox) 1525 return -ENOMEM; 1526 1527 err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); 1528 if (err) 1529 goto err_sw_reset; 1530 1531 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1532 if (err < 0) { 1533 dev_err(&pdev->dev, "MSI-X init failed\n"); 1534 goto err_alloc_irq; 1535 } 1536 1537 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1538 if (err) 1539 goto err_query_fw; 1540 1541 mlxsw_pci->bus_info.fw_rev.major = 1542 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1543 mlxsw_pci->bus_info.fw_rev.minor = 1544 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1545 mlxsw_pci->bus_info.fw_rev.subminor = 1546 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1547 1548 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1549 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1550 err = -EINVAL; 1551 goto err_iface_rev; 1552 } 1553 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1554 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1555 err = -EINVAL; 1556 goto err_doorbell_page_bar; 1557 } 1558 1559 mlxsw_pci->doorbell_offset = 1560 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1561 1562 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 1563 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 1564 err = -EINVAL; 1565 goto err_fr_rn_clk_bar; 1566 } 1567 1568 mlxsw_pci->free_running_clock_offset = 1569 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 1570 1571 if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) { 1572 dev_err(&pdev->dev, "Unsupported UTC sec BAR queried from hw\n"); 1573 err = -EINVAL; 1574 goto err_utc_sec_bar; 1575 } 1576 1577 mlxsw_pci->utc_sec_offset = 1578 mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox); 1579 1580 if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) { 1581 dev_err(&pdev->dev, "Unsupported UTC nsec BAR queried from hw\n"); 1582 err = -EINVAL; 1583 goto err_utc_nsec_bar; 1584 } 1585 1586 mlxsw_pci->utc_nsec_offset = 1587 mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox); 1588 1589 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1590 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1591 if (err) 1592 goto err_fw_area_init; 1593 1594 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1595 if (err) 1596 goto err_boardinfo; 1597 1598 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1599 if (err) 1600 goto err_query_resources; 1601 1602 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 1603 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 1604 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 1605 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 1606 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 1607 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 1608 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 1609 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 1610 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 1611 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 1612 } else { 1613 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 1614 goto err_cqe_v_check; 1615 } 1616 1617 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1618 if (err) 1619 goto err_config_profile; 1620 1621 /* Some resources depend on unified bridge model, which is configured 1622 * as part of config_profile. Query the resources again to get correct 1623 * values. 1624 */ 1625 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1626 if (err) 1627 goto err_requery_resources; 1628 1629 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1630 if (err) 1631 goto err_aqs_init; 1632 1633 err = request_irq(pci_irq_vector(pdev, 0), 1634 mlxsw_pci_eq_irq_handler, 0, 1635 mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1636 if (err) { 1637 dev_err(&pdev->dev, "IRQ request failed\n"); 1638 goto err_request_eq_irq; 1639 } 1640 1641 goto mbox_put; 1642 1643err_request_eq_irq: 1644 mlxsw_pci_aqs_fini(mlxsw_pci); 1645err_aqs_init: 1646err_requery_resources: 1647err_config_profile: 1648err_cqe_v_check: 1649err_query_resources: 1650err_boardinfo: 1651 mlxsw_pci_fw_area_fini(mlxsw_pci); 1652err_fw_area_init: 1653err_utc_nsec_bar: 1654err_utc_sec_bar: 1655err_fr_rn_clk_bar: 1656err_doorbell_page_bar: 1657err_iface_rev: 1658err_query_fw: 1659 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1660err_alloc_irq: 1661err_sw_reset: 1662mbox_put: 1663 mlxsw_cmd_mbox_free(mbox); 1664 return err; 1665} 1666 1667static void mlxsw_pci_fini(void *bus_priv) 1668{ 1669 struct mlxsw_pci *mlxsw_pci = bus_priv; 1670 1671 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1672 mlxsw_pci_aqs_fini(mlxsw_pci); 1673 mlxsw_pci_fw_area_fini(mlxsw_pci); 1674 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1675} 1676 1677static struct mlxsw_pci_queue * 1678mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1679 const struct mlxsw_tx_info *tx_info) 1680{ 1681 u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1; 1682 u8 sdqn; 1683 1684 if (tx_info->is_emad) { 1685 sdqn = MLXSW_PCI_SDQ_EMAD_INDEX; 1686 } else { 1687 BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0); 1688 sdqn = 1 + (tx_info->local_port % ctl_sdq_count); 1689 } 1690 1691 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1692} 1693 1694static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1695 const struct mlxsw_tx_info *tx_info) 1696{ 1697 struct mlxsw_pci *mlxsw_pci = bus_priv; 1698 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1699 1700 return !mlxsw_pci_queue_elem_info_producer_get(q); 1701} 1702 1703static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1704 const struct mlxsw_tx_info *tx_info) 1705{ 1706 struct mlxsw_pci *mlxsw_pci = bus_priv; 1707 struct mlxsw_pci_queue *q; 1708 struct mlxsw_pci_queue_elem_info *elem_info; 1709 char *wqe; 1710 int i; 1711 int err; 1712 1713 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1714 err = skb_linearize(skb); 1715 if (err) 1716 return err; 1717 } 1718 1719 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1720 spin_lock_bh(&q->lock); 1721 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1722 if (!elem_info) { 1723 /* queue is full */ 1724 err = -EAGAIN; 1725 goto unlock; 1726 } 1727 mlxsw_skb_cb(skb)->tx_info = *tx_info; 1728 elem_info->u.sdq.skb = skb; 1729 1730 wqe = elem_info->elem; 1731 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1732 mlxsw_pci_wqe_lp_set(wqe, 0); 1733 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1734 1735 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1736 skb_headlen(skb), DMA_TO_DEVICE); 1737 if (err) 1738 goto unlock; 1739 1740 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1741 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1742 1743 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1744 skb_frag_address(frag), 1745 skb_frag_size(frag), 1746 DMA_TO_DEVICE); 1747 if (err) 1748 goto unmap_frags; 1749 } 1750 1751 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 1752 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1753 1754 /* Set unused sq entries byte count to zero. */ 1755 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1756 mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1757 1758 /* Everything is set up, ring producer doorbell to get HW going */ 1759 q->producer_counter++; 1760 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1761 1762 goto unlock; 1763 1764unmap_frags: 1765 for (; i >= 0; i--) 1766 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1767unlock: 1768 spin_unlock_bh(&q->lock); 1769 return err; 1770} 1771 1772static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1773 u32 in_mod, bool out_mbox_direct, 1774 char *in_mbox, size_t in_mbox_size, 1775 char *out_mbox, size_t out_mbox_size, 1776 u8 *p_status) 1777{ 1778 struct mlxsw_pci *mlxsw_pci = bus_priv; 1779 dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 1780 bool evreq = mlxsw_pci->cmd.nopoll; 1781 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1782 bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1783 int err; 1784 1785 *p_status = MLXSW_CMD_STATUS_OK; 1786 1787 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1788 if (err) 1789 return err; 1790 1791 if (in_mbox) { 1792 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1793 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1794 } 1795 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1796 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1797 1798 if (out_mbox) 1799 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1800 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1801 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1802 1803 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1804 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1805 1806 *p_wait_done = false; 1807 1808 wmb(); /* all needs to be written before we write control register */ 1809 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1810 MLXSW_PCI_CIR_CTRL_GO_BIT | 1811 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1812 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1813 opcode); 1814 1815 if (!evreq) { 1816 unsigned long end; 1817 1818 end = jiffies + timeout; 1819 do { 1820 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1821 1822 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1823 *p_wait_done = true; 1824 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1825 break; 1826 } 1827 cond_resched(); 1828 } while (time_before(jiffies, end)); 1829 } else { 1830 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1831 *p_status = mlxsw_pci->cmd.comp.status; 1832 } 1833 1834 err = 0; 1835 if (*p_wait_done) { 1836 if (*p_status) 1837 err = -EIO; 1838 } else { 1839 err = -ETIMEDOUT; 1840 } 1841 1842 if (!err && out_mbox && out_mbox_direct) { 1843 /* Some commands don't use output param as address to mailbox 1844 * but they store output directly into registers. In that case, 1845 * copy registers into mbox buffer. 1846 */ 1847 __be32 tmp; 1848 1849 if (!evreq) { 1850 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1851 CIR_OUT_PARAM_HI)); 1852 memcpy(out_mbox, &tmp, sizeof(tmp)); 1853 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1854 CIR_OUT_PARAM_LO)); 1855 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1856 } 1857 } else if (!err && out_mbox) { 1858 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1859 } 1860 1861 mutex_unlock(&mlxsw_pci->cmd.lock); 1862 1863 return err; 1864} 1865 1866static u32 mlxsw_pci_read_frc_h(void *bus_priv) 1867{ 1868 struct mlxsw_pci *mlxsw_pci = bus_priv; 1869 u64 frc_offset_h; 1870 1871 frc_offset_h = mlxsw_pci->free_running_clock_offset; 1872 return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_h); 1873} 1874 1875static u32 mlxsw_pci_read_frc_l(void *bus_priv) 1876{ 1877 struct mlxsw_pci *mlxsw_pci = bus_priv; 1878 u64 frc_offset_l; 1879 1880 frc_offset_l = mlxsw_pci->free_running_clock_offset + 4; 1881 return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_l); 1882} 1883 1884static u32 mlxsw_pci_read_utc_sec(void *bus_priv) 1885{ 1886 struct mlxsw_pci *mlxsw_pci = bus_priv; 1887 1888 return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_sec_offset); 1889} 1890 1891static u32 mlxsw_pci_read_utc_nsec(void *bus_priv) 1892{ 1893 struct mlxsw_pci *mlxsw_pci = bus_priv; 1894 1895 return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_nsec_offset); 1896} 1897 1898static const struct mlxsw_bus mlxsw_pci_bus = { 1899 .kind = "pci", 1900 .init = mlxsw_pci_init, 1901 .fini = mlxsw_pci_fini, 1902 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1903 .skb_transmit = mlxsw_pci_skb_transmit, 1904 .cmd_exec = mlxsw_pci_cmd_exec, 1905 .read_frc_h = mlxsw_pci_read_frc_h, 1906 .read_frc_l = mlxsw_pci_read_frc_l, 1907 .read_utc_sec = mlxsw_pci_read_utc_sec, 1908 .read_utc_nsec = mlxsw_pci_read_utc_nsec, 1909 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 1910}; 1911 1912static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) 1913{ 1914 int err; 1915 1916 mutex_init(&mlxsw_pci->cmd.lock); 1917 init_waitqueue_head(&mlxsw_pci->cmd.wait); 1918 1919 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1920 if (err) 1921 goto err_in_mbox_alloc; 1922 1923 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1924 if (err) 1925 goto err_out_mbox_alloc; 1926 1927 return 0; 1928 1929err_out_mbox_alloc: 1930 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1931err_in_mbox_alloc: 1932 mutex_destroy(&mlxsw_pci->cmd.lock); 1933 return err; 1934} 1935 1936static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci) 1937{ 1938 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1939 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1940 mutex_destroy(&mlxsw_pci->cmd.lock); 1941} 1942 1943static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1944{ 1945 const char *driver_name = dev_driver_string(&pdev->dev); 1946 struct mlxsw_pci *mlxsw_pci; 1947 int err; 1948 1949 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1950 if (!mlxsw_pci) 1951 return -ENOMEM; 1952 1953 err = pci_enable_device(pdev); 1954 if (err) { 1955 dev_err(&pdev->dev, "pci_enable_device failed\n"); 1956 goto err_pci_enable_device; 1957 } 1958 1959 err = pci_request_regions(pdev, driver_name); 1960 if (err) { 1961 dev_err(&pdev->dev, "pci_request_regions failed\n"); 1962 goto err_pci_request_regions; 1963 } 1964 1965 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1966 if (err) { 1967 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1968 if (err) { 1969 dev_err(&pdev->dev, "dma_set_mask failed\n"); 1970 goto err_pci_set_dma_mask; 1971 } 1972 } 1973 1974 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1975 dev_err(&pdev->dev, "invalid PCI region size\n"); 1976 err = -EINVAL; 1977 goto err_pci_resource_len_check; 1978 } 1979 1980 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1981 pci_resource_len(pdev, 0)); 1982 if (!mlxsw_pci->hw_addr) { 1983 dev_err(&pdev->dev, "ioremap failed\n"); 1984 err = -EIO; 1985 goto err_ioremap; 1986 } 1987 pci_set_master(pdev); 1988 1989 mlxsw_pci->pdev = pdev; 1990 pci_set_drvdata(pdev, mlxsw_pci); 1991 1992 err = mlxsw_pci_cmd_init(mlxsw_pci); 1993 if (err) 1994 goto err_pci_cmd_init; 1995 1996 mlxsw_pci->bus_info.device_kind = driver_name; 1997 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1998 mlxsw_pci->bus_info.dev = &pdev->dev; 1999 mlxsw_pci->bus_info.read_clock_capable = true; 2000 mlxsw_pci->id = id; 2001 2002 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 2003 &mlxsw_pci_bus, mlxsw_pci, false, 2004 NULL, NULL); 2005 if (err) { 2006 dev_err(&pdev->dev, "cannot register bus device\n"); 2007 goto err_bus_device_register; 2008 } 2009 2010 return 0; 2011 2012err_bus_device_register: 2013 mlxsw_pci_cmd_fini(mlxsw_pci); 2014err_pci_cmd_init: 2015 iounmap(mlxsw_pci->hw_addr); 2016err_ioremap: 2017err_pci_resource_len_check: 2018err_pci_set_dma_mask: 2019 pci_release_regions(pdev); 2020err_pci_request_regions: 2021 pci_disable_device(pdev); 2022err_pci_enable_device: 2023 kfree(mlxsw_pci); 2024 return err; 2025} 2026 2027static void mlxsw_pci_remove(struct pci_dev *pdev) 2028{ 2029 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 2030 2031 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 2032 mlxsw_pci_cmd_fini(mlxsw_pci); 2033 iounmap(mlxsw_pci->hw_addr); 2034 pci_release_regions(mlxsw_pci->pdev); 2035 pci_disable_device(mlxsw_pci->pdev); 2036 kfree(mlxsw_pci); 2037} 2038 2039int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 2040{ 2041 pci_driver->probe = mlxsw_pci_probe; 2042 pci_driver->remove = mlxsw_pci_remove; 2043 pci_driver->shutdown = mlxsw_pci_remove; 2044 return pci_register_driver(pci_driver); 2045} 2046EXPORT_SYMBOL(mlxsw_pci_driver_register); 2047 2048void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 2049{ 2050 pci_unregister_driver(pci_driver); 2051} 2052EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 2053 2054static int __init mlxsw_pci_module_init(void) 2055{ 2056 return 0; 2057} 2058 2059static void __exit mlxsw_pci_module_exit(void) 2060{ 2061} 2062 2063module_init(mlxsw_pci_module_init); 2064module_exit(mlxsw_pci_module_exit); 2065 2066MODULE_LICENSE("Dual BSD/GPL"); 2067MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 2068MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 2069