1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9#include <linux/of.h> 10#include <linux/of_mdio.h> 11#include <linux/of_net.h> 12#include <linux/of_address.h> 13#include <linux/mfd/syscon.h> 14#include <linux/platform_device.h> 15#include <linux/regmap.h> 16#include <linux/clk.h> 17#include <linux/pm_runtime.h> 18#include <linux/if_vlan.h> 19#include <linux/reset.h> 20#include <linux/tcp.h> 21#include <linux/interrupt.h> 22#include <linux/pinctrl/devinfo.h> 23#include <linux/phylink.h> 24#include <linux/pcs/pcs-mtk-lynxi.h> 25#include <linux/jhash.h> 26#include <linux/bitfield.h> 27#include <net/dsa.h> 28#include <net/dst_metadata.h> 29#include <net/page_pool/helpers.h> 30 31#include "mtk_eth_soc.h" 32#include "mtk_wed.h" 33 34static int mtk_msg_level = -1; 35module_param_named(msg_level, mtk_msg_level, int, 0); 36MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 37 38#define MTK_ETHTOOL_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 40 41#define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 43 sizeof(u64) } 44 45static const struct mtk_reg_map mtk_reg_map = { 46 .tx_irq_mask = 0x1a1c, 47 .tx_irq_status = 0x1a18, 48 .pdma = { 49 .rx_ptr = 0x0900, 50 .rx_cnt_cfg = 0x0904, 51 .pcrx_ptr = 0x0908, 52 .glo_cfg = 0x0a04, 53 .rst_idx = 0x0a08, 54 .delay_irq = 0x0a0c, 55 .irq_status = 0x0a20, 56 .irq_mask = 0x0a28, 57 .adma_rx_dbg0 = 0x0a38, 58 .int_grp = 0x0a50, 59 }, 60 .qdma = { 61 .qtx_cfg = 0x1800, 62 .qtx_sch = 0x1804, 63 .rx_ptr = 0x1900, 64 .rx_cnt_cfg = 0x1904, 65 .qcrx_ptr = 0x1908, 66 .glo_cfg = 0x1a04, 67 .rst_idx = 0x1a08, 68 .delay_irq = 0x1a0c, 69 .fc_th = 0x1a10, 70 .tx_sch_rate = 0x1a14, 71 .int_grp = 0x1a20, 72 .hred = 0x1a44, 73 .ctx_ptr = 0x1b00, 74 .dtx_ptr = 0x1b04, 75 .crx_ptr = 0x1b10, 76 .drx_ptr = 0x1b14, 77 .fq_head = 0x1b20, 78 .fq_tail = 0x1b24, 79 .fq_count = 0x1b28, 80 .fq_blen = 0x1b2c, 81 }, 82 .gdm1_cnt = 0x2400, 83 .gdma_to_ppe = 0x4444, 84 .ppe_base = 0x0c00, 85 .wdma_base = { 86 [0] = 0x2800, 87 [1] = 0x2c00, 88 }, 89 .pse_iq_sta = 0x0110, 90 .pse_oq_sta = 0x0118, 91}; 92 93static const struct mtk_reg_map mt7628_reg_map = { 94 .tx_irq_mask = 0x0a28, 95 .tx_irq_status = 0x0a20, 96 .pdma = { 97 .rx_ptr = 0x0900, 98 .rx_cnt_cfg = 0x0904, 99 .pcrx_ptr = 0x0908, 100 .glo_cfg = 0x0a04, 101 .rst_idx = 0x0a08, 102 .delay_irq = 0x0a0c, 103 .irq_status = 0x0a20, 104 .irq_mask = 0x0a28, 105 .int_grp = 0x0a50, 106 }, 107}; 108 109static const struct mtk_reg_map mt7986_reg_map = { 110 .tx_irq_mask = 0x461c, 111 .tx_irq_status = 0x4618, 112 .pdma = { 113 .rx_ptr = 0x6100, 114 .rx_cnt_cfg = 0x6104, 115 .pcrx_ptr = 0x6108, 116 .glo_cfg = 0x6204, 117 .rst_idx = 0x6208, 118 .delay_irq = 0x620c, 119 .irq_status = 0x6220, 120 .irq_mask = 0x6228, 121 .adma_rx_dbg0 = 0x6238, 122 .int_grp = 0x6250, 123 }, 124 .qdma = { 125 .qtx_cfg = 0x4400, 126 .qtx_sch = 0x4404, 127 .rx_ptr = 0x4500, 128 .rx_cnt_cfg = 0x4504, 129 .qcrx_ptr = 0x4508, 130 .glo_cfg = 0x4604, 131 .rst_idx = 0x4608, 132 .delay_irq = 0x460c, 133 .fc_th = 0x4610, 134 .int_grp = 0x4620, 135 .hred = 0x4644, 136 .ctx_ptr = 0x4700, 137 .dtx_ptr = 0x4704, 138 .crx_ptr = 0x4710, 139 .drx_ptr = 0x4714, 140 .fq_head = 0x4720, 141 .fq_tail = 0x4724, 142 .fq_count = 0x4728, 143 .fq_blen = 0x472c, 144 .tx_sch_rate = 0x4798, 145 }, 146 .gdm1_cnt = 0x1c00, 147 .gdma_to_ppe = 0x3333, 148 .ppe_base = 0x2000, 149 .wdma_base = { 150 [0] = 0x4800, 151 [1] = 0x4c00, 152 }, 153 .pse_iq_sta = 0x0180, 154 .pse_oq_sta = 0x01a0, 155}; 156 157static const struct mtk_reg_map mt7988_reg_map = { 158 .tx_irq_mask = 0x461c, 159 .tx_irq_status = 0x4618, 160 .pdma = { 161 .rx_ptr = 0x6900, 162 .rx_cnt_cfg = 0x6904, 163 .pcrx_ptr = 0x6908, 164 .glo_cfg = 0x6a04, 165 .rst_idx = 0x6a08, 166 .delay_irq = 0x6a0c, 167 .irq_status = 0x6a20, 168 .irq_mask = 0x6a28, 169 .adma_rx_dbg0 = 0x6a38, 170 .int_grp = 0x6a50, 171 }, 172 .qdma = { 173 .qtx_cfg = 0x4400, 174 .qtx_sch = 0x4404, 175 .rx_ptr = 0x4500, 176 .rx_cnt_cfg = 0x4504, 177 .qcrx_ptr = 0x4508, 178 .glo_cfg = 0x4604, 179 .rst_idx = 0x4608, 180 .delay_irq = 0x460c, 181 .fc_th = 0x4610, 182 .int_grp = 0x4620, 183 .hred = 0x4644, 184 .ctx_ptr = 0x4700, 185 .dtx_ptr = 0x4704, 186 .crx_ptr = 0x4710, 187 .drx_ptr = 0x4714, 188 .fq_head = 0x4720, 189 .fq_tail = 0x4724, 190 .fq_count = 0x4728, 191 .fq_blen = 0x472c, 192 .tx_sch_rate = 0x4798, 193 }, 194 .gdm1_cnt = 0x1c00, 195 .gdma_to_ppe = 0x3333, 196 .ppe_base = 0x2000, 197 .wdma_base = { 198 [0] = 0x4800, 199 [1] = 0x4c00, 200 }, 201 .pse_iq_sta = 0x0180, 202 .pse_oq_sta = 0x01a0, 203}; 204 205/* strings used by ethtool */ 206static const struct mtk_ethtool_stats { 207 char str[ETH_GSTRING_LEN]; 208 u32 offset; 209} mtk_ethtool_stats[] = { 210 MTK_ETHTOOL_STAT(tx_bytes), 211 MTK_ETHTOOL_STAT(tx_packets), 212 MTK_ETHTOOL_STAT(tx_skip), 213 MTK_ETHTOOL_STAT(tx_collisions), 214 MTK_ETHTOOL_STAT(rx_bytes), 215 MTK_ETHTOOL_STAT(rx_packets), 216 MTK_ETHTOOL_STAT(rx_overflow), 217 MTK_ETHTOOL_STAT(rx_fcs_errors), 218 MTK_ETHTOOL_STAT(rx_short_errors), 219 MTK_ETHTOOL_STAT(rx_long_errors), 220 MTK_ETHTOOL_STAT(rx_checksum_errors), 221 MTK_ETHTOOL_STAT(rx_flow_control_packets), 222 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 223 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 224 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 225 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 226 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 227 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 228 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 229}; 230 231static const char * const mtk_clks_source_name[] = { 232 "ethif", 233 "sgmiitop", 234 "esw", 235 "gp0", 236 "gp1", 237 "gp2", 238 "gp3", 239 "xgp1", 240 "xgp2", 241 "xgp3", 242 "crypto", 243 "fe", 244 "trgpll", 245 "sgmii_tx250m", 246 "sgmii_rx250m", 247 "sgmii_cdr_ref", 248 "sgmii_cdr_fb", 249 "sgmii2_tx250m", 250 "sgmii2_rx250m", 251 "sgmii2_cdr_ref", 252 "sgmii2_cdr_fb", 253 "sgmii_ck", 254 "eth2pll", 255 "wocpu0", 256 "wocpu1", 257 "netsys0", 258 "netsys1", 259 "ethwarp_wocpu2", 260 "ethwarp_wocpu1", 261 "ethwarp_wocpu0", 262 "top_usxgmii0_sel", 263 "top_usxgmii1_sel", 264 "top_sgm0_sel", 265 "top_sgm1_sel", 266 "top_xfi_phy0_xtal_sel", 267 "top_xfi_phy1_xtal_sel", 268 "top_eth_gmii_sel", 269 "top_eth_refck_50m_sel", 270 "top_eth_sys_200m_sel", 271 "top_eth_sys_sel", 272 "top_eth_xgmii_sel", 273 "top_eth_mii_sel", 274 "top_netsys_sel", 275 "top_netsys_500m_sel", 276 "top_netsys_pao_2x_sel", 277 "top_netsys_sync_250m_sel", 278 "top_netsys_ppefb_250m_sel", 279 "top_netsys_warp_sel", 280}; 281 282void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 283{ 284 __raw_writel(val, eth->base + reg); 285} 286 287u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 288{ 289 return __raw_readl(eth->base + reg); 290} 291 292u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 293{ 294 u32 val; 295 296 val = mtk_r32(eth, reg); 297 val &= ~mask; 298 val |= set; 299 mtk_w32(eth, val, reg); 300 return reg; 301} 302 303static int mtk_mdio_busy_wait(struct mtk_eth *eth) 304{ 305 unsigned long t_start = jiffies; 306 307 while (1) { 308 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 309 return 0; 310 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 311 break; 312 cond_resched(); 313 } 314 315 dev_err(eth->dev, "mdio: MDIO timeout\n"); 316 return -ETIMEDOUT; 317} 318 319static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 320 u32 write_data) 321{ 322 int ret; 323 324 ret = mtk_mdio_busy_wait(eth); 325 if (ret < 0) 326 return ret; 327 328 mtk_w32(eth, PHY_IAC_ACCESS | 329 PHY_IAC_START_C22 | 330 PHY_IAC_CMD_WRITE | 331 PHY_IAC_REG(phy_reg) | 332 PHY_IAC_ADDR(phy_addr) | 333 PHY_IAC_DATA(write_data), 334 MTK_PHY_IAC); 335 336 ret = mtk_mdio_busy_wait(eth); 337 if (ret < 0) 338 return ret; 339 340 return 0; 341} 342 343static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 344 u32 devad, u32 phy_reg, u32 write_data) 345{ 346 int ret; 347 348 ret = mtk_mdio_busy_wait(eth); 349 if (ret < 0) 350 return ret; 351 352 mtk_w32(eth, PHY_IAC_ACCESS | 353 PHY_IAC_START_C45 | 354 PHY_IAC_CMD_C45_ADDR | 355 PHY_IAC_REG(devad) | 356 PHY_IAC_ADDR(phy_addr) | 357 PHY_IAC_DATA(phy_reg), 358 MTK_PHY_IAC); 359 360 ret = mtk_mdio_busy_wait(eth); 361 if (ret < 0) 362 return ret; 363 364 mtk_w32(eth, PHY_IAC_ACCESS | 365 PHY_IAC_START_C45 | 366 PHY_IAC_CMD_WRITE | 367 PHY_IAC_REG(devad) | 368 PHY_IAC_ADDR(phy_addr) | 369 PHY_IAC_DATA(write_data), 370 MTK_PHY_IAC); 371 372 ret = mtk_mdio_busy_wait(eth); 373 if (ret < 0) 374 return ret; 375 376 return 0; 377} 378 379static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 380{ 381 int ret; 382 383 ret = mtk_mdio_busy_wait(eth); 384 if (ret < 0) 385 return ret; 386 387 mtk_w32(eth, PHY_IAC_ACCESS | 388 PHY_IAC_START_C22 | 389 PHY_IAC_CMD_C22_READ | 390 PHY_IAC_REG(phy_reg) | 391 PHY_IAC_ADDR(phy_addr), 392 MTK_PHY_IAC); 393 394 ret = mtk_mdio_busy_wait(eth); 395 if (ret < 0) 396 return ret; 397 398 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 399} 400 401static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 402 u32 devad, u32 phy_reg) 403{ 404 int ret; 405 406 ret = mtk_mdio_busy_wait(eth); 407 if (ret < 0) 408 return ret; 409 410 mtk_w32(eth, PHY_IAC_ACCESS | 411 PHY_IAC_START_C45 | 412 PHY_IAC_CMD_C45_ADDR | 413 PHY_IAC_REG(devad) | 414 PHY_IAC_ADDR(phy_addr) | 415 PHY_IAC_DATA(phy_reg), 416 MTK_PHY_IAC); 417 418 ret = mtk_mdio_busy_wait(eth); 419 if (ret < 0) 420 return ret; 421 422 mtk_w32(eth, PHY_IAC_ACCESS | 423 PHY_IAC_START_C45 | 424 PHY_IAC_CMD_C45_READ | 425 PHY_IAC_REG(devad) | 426 PHY_IAC_ADDR(phy_addr), 427 MTK_PHY_IAC); 428 429 ret = mtk_mdio_busy_wait(eth); 430 if (ret < 0) 431 return ret; 432 433 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 434} 435 436static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 437 int phy_reg, u16 val) 438{ 439 struct mtk_eth *eth = bus->priv; 440 441 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 442} 443 444static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 445 int devad, int phy_reg, u16 val) 446{ 447 struct mtk_eth *eth = bus->priv; 448 449 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 450} 451 452static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 453{ 454 struct mtk_eth *eth = bus->priv; 455 456 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 457} 458 459static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 460 int phy_reg) 461{ 462 struct mtk_eth *eth = bus->priv; 463 464 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 465} 466 467static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 468 phy_interface_t interface) 469{ 470 u32 val; 471 472 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 473 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 474 475 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 476 ETHSYS_TRGMII_MT7621_MASK, val); 477 478 return 0; 479} 480 481static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 482 phy_interface_t interface) 483{ 484 int ret; 485 486 if (interface == PHY_INTERFACE_MODE_TRGMII) { 487 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 488 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 489 if (ret) 490 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 491 return; 492 } 493 494 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 495} 496 497static void mtk_setup_bridge_switch(struct mtk_eth *eth) 498{ 499 /* Force Port1 XGMAC Link Up */ 500 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 501 MTK_XGMAC_STS(MTK_GMAC1_ID)); 502 503 /* Adjust GSW bridge IPG to 11 */ 504 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 505 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 506 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 507 MTK_GSW_CFG); 508} 509 510static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 511 phy_interface_t interface) 512{ 513 struct mtk_mac *mac = container_of(config, struct mtk_mac, 514 phylink_config); 515 struct mtk_eth *eth = mac->hw; 516 unsigned int sid; 517 518 if (interface == PHY_INTERFACE_MODE_SGMII || 519 phy_interface_mode_is_8023z(interface)) { 520 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 521 0 : mac->id; 522 523 return eth->sgmii_pcs[sid]; 524 } 525 526 return NULL; 527} 528 529static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 530 const struct phylink_link_state *state) 531{ 532 struct mtk_mac *mac = container_of(config, struct mtk_mac, 533 phylink_config); 534 struct mtk_eth *eth = mac->hw; 535 int val, ge_mode, err = 0; 536 u32 i; 537 538 /* MT76x8 has no hardware settings between for the MAC */ 539 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 540 mac->interface != state->interface) { 541 /* Setup soc pin functions */ 542 switch (state->interface) { 543 case PHY_INTERFACE_MODE_TRGMII: 544 case PHY_INTERFACE_MODE_RGMII_TXID: 545 case PHY_INTERFACE_MODE_RGMII_RXID: 546 case PHY_INTERFACE_MODE_RGMII_ID: 547 case PHY_INTERFACE_MODE_RGMII: 548 case PHY_INTERFACE_MODE_MII: 549 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 550 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 551 if (err) 552 goto init_err; 553 } 554 break; 555 case PHY_INTERFACE_MODE_1000BASEX: 556 case PHY_INTERFACE_MODE_2500BASEX: 557 case PHY_INTERFACE_MODE_SGMII: 558 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 559 if (err) 560 goto init_err; 561 break; 562 case PHY_INTERFACE_MODE_GMII: 563 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 564 err = mtk_gmac_gephy_path_setup(eth, mac->id); 565 if (err) 566 goto init_err; 567 } 568 break; 569 case PHY_INTERFACE_MODE_INTERNAL: 570 break; 571 default: 572 goto err_phy; 573 } 574 575 /* Setup clock for 1st gmac */ 576 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 577 !phy_interface_mode_is_8023z(state->interface) && 578 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 579 if (MTK_HAS_CAPS(mac->hw->soc->caps, 580 MTK_TRGMII_MT7621_CLK)) { 581 if (mt7621_gmac0_rgmii_adjust(mac->hw, 582 state->interface)) 583 goto err_phy; 584 } else { 585 mtk_gmac0_rgmii_adjust(mac->hw, 586 state->interface); 587 588 /* mt7623_pad_clk_setup */ 589 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 590 mtk_w32(mac->hw, 591 TD_DM_DRVP(8) | TD_DM_DRVN(8), 592 TRGMII_TD_ODT(i)); 593 594 /* Assert/release MT7623 RXC reset */ 595 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 596 TRGMII_RCK_CTRL); 597 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 598 } 599 } 600 601 switch (state->interface) { 602 case PHY_INTERFACE_MODE_MII: 603 case PHY_INTERFACE_MODE_GMII: 604 ge_mode = 1; 605 break; 606 default: 607 ge_mode = 0; 608 break; 609 } 610 611 /* put the gmac into the right mode */ 612 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 613 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 614 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 615 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 616 617 mac->interface = state->interface; 618 } 619 620 /* SGMII */ 621 if (state->interface == PHY_INTERFACE_MODE_SGMII || 622 phy_interface_mode_is_8023z(state->interface)) { 623 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 624 * being setup done. 625 */ 626 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 627 628 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 629 SYSCFG0_SGMII_MASK, 630 ~(u32)SYSCFG0_SGMII_MASK); 631 632 /* Save the syscfg0 value for mac_finish */ 633 mac->syscfg0 = val; 634 } else if (phylink_autoneg_inband(mode)) { 635 dev_err(eth->dev, 636 "In-band mode not supported in non SGMII mode!\n"); 637 return; 638 } 639 640 /* Setup gmac */ 641 if (mtk_is_netsys_v3_or_greater(eth) && 642 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 643 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 644 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 645 646 mtk_setup_bridge_switch(eth); 647 } 648 649 return; 650 651err_phy: 652 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 653 mac->id, phy_modes(state->interface)); 654 return; 655 656init_err: 657 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 658 mac->id, phy_modes(state->interface), err); 659} 660 661static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 662 phy_interface_t interface) 663{ 664 struct mtk_mac *mac = container_of(config, struct mtk_mac, 665 phylink_config); 666 struct mtk_eth *eth = mac->hw; 667 u32 mcr_cur, mcr_new; 668 669 /* Enable SGMII */ 670 if (interface == PHY_INTERFACE_MODE_SGMII || 671 phy_interface_mode_is_8023z(interface)) 672 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 673 SYSCFG0_SGMII_MASK, mac->syscfg0); 674 675 /* Setup gmac */ 676 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 677 mcr_new = mcr_cur; 678 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 679 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS; 680 681 /* Only update control register when needed! */ 682 if (mcr_new != mcr_cur) 683 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 684 685 return 0; 686} 687 688static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 689 phy_interface_t interface) 690{ 691 struct mtk_mac *mac = container_of(config, struct mtk_mac, 692 phylink_config); 693 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 694 695 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK); 696 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 697} 698 699static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 700 int speed) 701{ 702 const struct mtk_soc_data *soc = eth->soc; 703 u32 ofs, val; 704 705 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 706 return; 707 708 val = MTK_QTX_SCH_MIN_RATE_EN | 709 /* minimum: 10 Mbps */ 710 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 711 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 712 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 713 if (mtk_is_netsys_v1(eth)) 714 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 715 716 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 717 switch (speed) { 718 case SPEED_10: 719 val |= MTK_QTX_SCH_MAX_RATE_EN | 720 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 721 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 723 break; 724 case SPEED_100: 725 val |= MTK_QTX_SCH_MAX_RATE_EN | 726 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 729 break; 730 case SPEED_1000: 731 val |= MTK_QTX_SCH_MAX_RATE_EN | 732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 735 break; 736 default: 737 break; 738 } 739 } else { 740 switch (speed) { 741 case SPEED_10: 742 val |= MTK_QTX_SCH_MAX_RATE_EN | 743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 745 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 746 break; 747 case SPEED_100: 748 val |= MTK_QTX_SCH_MAX_RATE_EN | 749 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 752 break; 753 case SPEED_1000: 754 val |= MTK_QTX_SCH_MAX_RATE_EN | 755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 758 break; 759 default: 760 break; 761 } 762 } 763 764 ofs = MTK_QTX_OFFSET * idx; 765 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 766} 767 768static void mtk_mac_link_up(struct phylink_config *config, 769 struct phy_device *phy, 770 unsigned int mode, phy_interface_t interface, 771 int speed, int duplex, bool tx_pause, bool rx_pause) 772{ 773 struct mtk_mac *mac = container_of(config, struct mtk_mac, 774 phylink_config); 775 u32 mcr; 776 777 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 778 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 779 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 780 MAC_MCR_FORCE_RX_FC); 781 782 /* Configure speed */ 783 mac->speed = speed; 784 switch (speed) { 785 case SPEED_2500: 786 case SPEED_1000: 787 mcr |= MAC_MCR_SPEED_1000; 788 break; 789 case SPEED_100: 790 mcr |= MAC_MCR_SPEED_100; 791 break; 792 } 793 794 /* Configure duplex */ 795 if (duplex == DUPLEX_FULL) 796 mcr |= MAC_MCR_FORCE_DPX; 797 798 /* Configure pause modes - phylink will avoid these for half duplex */ 799 if (tx_pause) 800 mcr |= MAC_MCR_FORCE_TX_FC; 801 if (rx_pause) 802 mcr |= MAC_MCR_FORCE_RX_FC; 803 804 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK; 805 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 806} 807 808static const struct phylink_mac_ops mtk_phylink_ops = { 809 .mac_select_pcs = mtk_mac_select_pcs, 810 .mac_config = mtk_mac_config, 811 .mac_finish = mtk_mac_finish, 812 .mac_link_down = mtk_mac_link_down, 813 .mac_link_up = mtk_mac_link_up, 814}; 815 816static int mtk_mdio_init(struct mtk_eth *eth) 817{ 818 unsigned int max_clk = 2500000, divider; 819 struct device_node *mii_np; 820 int ret; 821 u32 val; 822 823 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 824 if (!mii_np) { 825 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 826 return -ENODEV; 827 } 828 829 if (!of_device_is_available(mii_np)) { 830 ret = -ENODEV; 831 goto err_put_node; 832 } 833 834 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 835 if (!eth->mii_bus) { 836 ret = -ENOMEM; 837 goto err_put_node; 838 } 839 840 eth->mii_bus->name = "mdio"; 841 eth->mii_bus->read = mtk_mdio_read_c22; 842 eth->mii_bus->write = mtk_mdio_write_c22; 843 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 844 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 845 eth->mii_bus->priv = eth; 846 eth->mii_bus->parent = eth->dev; 847 848 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 849 850 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 851 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 852 dev_err(eth->dev, "MDIO clock frequency out of range"); 853 ret = -EINVAL; 854 goto err_put_node; 855 } 856 max_clk = val; 857 } 858 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 859 860 /* Configure MDC Turbo Mode */ 861 if (mtk_is_netsys_v3_or_greater(eth)) 862 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 863 864 /* Configure MDC Divider */ 865 val = FIELD_PREP(PPSC_MDC_CFG, divider); 866 if (!mtk_is_netsys_v3_or_greater(eth)) 867 val |= PPSC_MDC_TURBO; 868 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 869 870 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 871 872 ret = of_mdiobus_register(eth->mii_bus, mii_np); 873 874err_put_node: 875 of_node_put(mii_np); 876 return ret; 877} 878 879static void mtk_mdio_cleanup(struct mtk_eth *eth) 880{ 881 if (!eth->mii_bus) 882 return; 883 884 mdiobus_unregister(eth->mii_bus); 885} 886 887static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 888{ 889 unsigned long flags; 890 u32 val; 891 892 spin_lock_irqsave(ð->tx_irq_lock, flags); 893 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 894 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 895 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 896} 897 898static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 899{ 900 unsigned long flags; 901 u32 val; 902 903 spin_lock_irqsave(ð->tx_irq_lock, flags); 904 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 905 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 906 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 907} 908 909static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 910{ 911 unsigned long flags; 912 u32 val; 913 914 spin_lock_irqsave(ð->rx_irq_lock, flags); 915 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 916 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 917 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 918} 919 920static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 921{ 922 unsigned long flags; 923 u32 val; 924 925 spin_lock_irqsave(ð->rx_irq_lock, flags); 926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 927 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 928 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 929} 930 931static int mtk_set_mac_address(struct net_device *dev, void *p) 932{ 933 int ret = eth_mac_addr(dev, p); 934 struct mtk_mac *mac = netdev_priv(dev); 935 struct mtk_eth *eth = mac->hw; 936 const char *macaddr = dev->dev_addr; 937 938 if (ret) 939 return ret; 940 941 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 942 return -EBUSY; 943 944 spin_lock_bh(&mac->hw->page_lock); 945 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 946 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 947 MT7628_SDM_MAC_ADRH); 948 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 949 (macaddr[4] << 8) | macaddr[5], 950 MT7628_SDM_MAC_ADRL); 951 } else { 952 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 953 MTK_GDMA_MAC_ADRH(mac->id)); 954 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 955 (macaddr[4] << 8) | macaddr[5], 956 MTK_GDMA_MAC_ADRL(mac->id)); 957 } 958 spin_unlock_bh(&mac->hw->page_lock); 959 960 return 0; 961} 962 963void mtk_stats_update_mac(struct mtk_mac *mac) 964{ 965 struct mtk_hw_stats *hw_stats = mac->hw_stats; 966 struct mtk_eth *eth = mac->hw; 967 968 u64_stats_update_begin(&hw_stats->syncp); 969 970 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 971 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 972 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 973 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 974 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 975 hw_stats->rx_checksum_errors += 976 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 977 } else { 978 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 979 unsigned int offs = hw_stats->reg_offset; 980 u64 stats; 981 982 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 983 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 984 if (stats) 985 hw_stats->rx_bytes += (stats << 32); 986 hw_stats->rx_packets += 987 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 988 hw_stats->rx_overflow += 989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 990 hw_stats->rx_fcs_errors += 991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 992 hw_stats->rx_short_errors += 993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 994 hw_stats->rx_long_errors += 995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 996 hw_stats->rx_checksum_errors += 997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 998 hw_stats->rx_flow_control_packets += 999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1000 1001 if (mtk_is_netsys_v3_or_greater(eth)) { 1002 hw_stats->tx_skip += 1003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1004 hw_stats->tx_collisions += 1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1006 hw_stats->tx_bytes += 1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1008 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1009 if (stats) 1010 hw_stats->tx_bytes += (stats << 32); 1011 hw_stats->tx_packets += 1012 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1013 } else { 1014 hw_stats->tx_skip += 1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1016 hw_stats->tx_collisions += 1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1018 hw_stats->tx_bytes += 1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1020 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1021 if (stats) 1022 hw_stats->tx_bytes += (stats << 32); 1023 hw_stats->tx_packets += 1024 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1025 } 1026 } 1027 1028 u64_stats_update_end(&hw_stats->syncp); 1029} 1030 1031static void mtk_stats_update(struct mtk_eth *eth) 1032{ 1033 int i; 1034 1035 for (i = 0; i < MTK_MAX_DEVS; i++) { 1036 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1037 continue; 1038 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1039 mtk_stats_update_mac(eth->mac[i]); 1040 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1041 } 1042 } 1043} 1044 1045static void mtk_get_stats64(struct net_device *dev, 1046 struct rtnl_link_stats64 *storage) 1047{ 1048 struct mtk_mac *mac = netdev_priv(dev); 1049 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1050 unsigned int start; 1051 1052 if (netif_running(dev) && netif_device_present(dev)) { 1053 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1054 mtk_stats_update_mac(mac); 1055 spin_unlock_bh(&hw_stats->stats_lock); 1056 } 1057 } 1058 1059 do { 1060 start = u64_stats_fetch_begin(&hw_stats->syncp); 1061 storage->rx_packets = hw_stats->rx_packets; 1062 storage->tx_packets = hw_stats->tx_packets; 1063 storage->rx_bytes = hw_stats->rx_bytes; 1064 storage->tx_bytes = hw_stats->tx_bytes; 1065 storage->collisions = hw_stats->tx_collisions; 1066 storage->rx_length_errors = hw_stats->rx_short_errors + 1067 hw_stats->rx_long_errors; 1068 storage->rx_over_errors = hw_stats->rx_overflow; 1069 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1070 storage->rx_errors = hw_stats->rx_checksum_errors; 1071 storage->tx_aborted_errors = hw_stats->tx_skip; 1072 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1073 1074 storage->tx_errors = dev->stats.tx_errors; 1075 storage->rx_dropped = dev->stats.rx_dropped; 1076 storage->tx_dropped = dev->stats.tx_dropped; 1077} 1078 1079static inline int mtk_max_frag_size(int mtu) 1080{ 1081 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1082 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1083 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1084 1085 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1086 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1087} 1088 1089static inline int mtk_max_buf_size(int frag_size) 1090{ 1091 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1092 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1093 1094 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1095 1096 return buf_size; 1097} 1098 1099static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1100 struct mtk_rx_dma_v2 *dma_rxd) 1101{ 1102 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1103 if (!(rxd->rxd2 & RX_DMA_DONE)) 1104 return false; 1105 1106 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1107 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1108 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1109 if (mtk_is_netsys_v2_or_greater(eth)) { 1110 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1111 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1112 } 1113 1114 return true; 1115} 1116 1117static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1118{ 1119 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1120 unsigned long data; 1121 1122 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1123 get_order(size)); 1124 1125 return (void *)data; 1126} 1127 1128/* the qdma core needs scratch memory to be setup */ 1129static int mtk_init_fq_dma(struct mtk_eth *eth) 1130{ 1131 const struct mtk_soc_data *soc = eth->soc; 1132 dma_addr_t phy_ring_tail; 1133 int cnt = MTK_QDMA_RING_SIZE; 1134 dma_addr_t dma_addr; 1135 int i; 1136 1137 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) 1138 eth->scratch_ring = eth->sram_base; 1139 else 1140 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1141 cnt * soc->txrx.txd_size, 1142 ð->phy_scratch_ring, 1143 GFP_KERNEL); 1144 if (unlikely(!eth->scratch_ring)) 1145 return -ENOMEM; 1146 1147 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1148 if (unlikely(!eth->scratch_head)) 1149 return -ENOMEM; 1150 1151 dma_addr = dma_map_single(eth->dma_dev, 1152 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1153 DMA_FROM_DEVICE); 1154 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1155 return -ENOMEM; 1156 1157 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1158 1159 for (i = 0; i < cnt; i++) { 1160 struct mtk_tx_dma_v2 *txd; 1161 1162 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1163 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1164 if (i < cnt - 1) 1165 txd->txd2 = eth->phy_scratch_ring + 1166 (i + 1) * soc->txrx.txd_size; 1167 1168 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1169 txd->txd4 = 0; 1170 if (mtk_is_netsys_v2_or_greater(eth)) { 1171 txd->txd5 = 0; 1172 txd->txd6 = 0; 1173 txd->txd7 = 0; 1174 txd->txd8 = 0; 1175 } 1176 } 1177 1178 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1179 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1180 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1181 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1182 1183 return 0; 1184} 1185 1186static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1187{ 1188 return ring->dma + (desc - ring->phys); 1189} 1190 1191static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1192 void *txd, u32 txd_size) 1193{ 1194 int idx = (txd - ring->dma) / txd_size; 1195 1196 return &ring->buf[idx]; 1197} 1198 1199static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1200 struct mtk_tx_dma *dma) 1201{ 1202 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1203} 1204 1205static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1206{ 1207 return (dma - ring->dma) / txd_size; 1208} 1209 1210static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1211 struct xdp_frame_bulk *bq, bool napi) 1212{ 1213 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1214 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1215 dma_unmap_single(eth->dma_dev, 1216 dma_unmap_addr(tx_buf, dma_addr0), 1217 dma_unmap_len(tx_buf, dma_len0), 1218 DMA_TO_DEVICE); 1219 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1220 dma_unmap_page(eth->dma_dev, 1221 dma_unmap_addr(tx_buf, dma_addr0), 1222 dma_unmap_len(tx_buf, dma_len0), 1223 DMA_TO_DEVICE); 1224 } 1225 } else { 1226 if (dma_unmap_len(tx_buf, dma_len0)) { 1227 dma_unmap_page(eth->dma_dev, 1228 dma_unmap_addr(tx_buf, dma_addr0), 1229 dma_unmap_len(tx_buf, dma_len0), 1230 DMA_TO_DEVICE); 1231 } 1232 1233 if (dma_unmap_len(tx_buf, dma_len1)) { 1234 dma_unmap_page(eth->dma_dev, 1235 dma_unmap_addr(tx_buf, dma_addr1), 1236 dma_unmap_len(tx_buf, dma_len1), 1237 DMA_TO_DEVICE); 1238 } 1239 } 1240 1241 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1242 if (tx_buf->type == MTK_TYPE_SKB) { 1243 struct sk_buff *skb = tx_buf->data; 1244 1245 if (napi) 1246 napi_consume_skb(skb, napi); 1247 else 1248 dev_kfree_skb_any(skb); 1249 } else { 1250 struct xdp_frame *xdpf = tx_buf->data; 1251 1252 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1253 xdp_return_frame_rx_napi(xdpf); 1254 else if (bq) 1255 xdp_return_frame_bulk(xdpf, bq); 1256 else 1257 xdp_return_frame(xdpf); 1258 } 1259 } 1260 tx_buf->flags = 0; 1261 tx_buf->data = NULL; 1262} 1263 1264static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1265 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1266 size_t size, int idx) 1267{ 1268 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1269 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1270 dma_unmap_len_set(tx_buf, dma_len0, size); 1271 } else { 1272 if (idx & 1) { 1273 txd->txd3 = mapped_addr; 1274 txd->txd2 |= TX_DMA_PLEN1(size); 1275 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1276 dma_unmap_len_set(tx_buf, dma_len1, size); 1277 } else { 1278 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1279 txd->txd1 = mapped_addr; 1280 txd->txd2 = TX_DMA_PLEN0(size); 1281 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1282 dma_unmap_len_set(tx_buf, dma_len0, size); 1283 } 1284 } 1285} 1286 1287static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1288 struct mtk_tx_dma_desc_info *info) 1289{ 1290 struct mtk_mac *mac = netdev_priv(dev); 1291 struct mtk_eth *eth = mac->hw; 1292 struct mtk_tx_dma *desc = txd; 1293 u32 data; 1294 1295 WRITE_ONCE(desc->txd1, info->addr); 1296 1297 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1298 FIELD_PREP(TX_DMA_PQID, info->qid); 1299 if (info->last) 1300 data |= TX_DMA_LS0; 1301 WRITE_ONCE(desc->txd3, data); 1302 1303 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1304 if (info->first) { 1305 if (info->gso) 1306 data |= TX_DMA_TSO; 1307 /* tx checksum offload */ 1308 if (info->csum) 1309 data |= TX_DMA_CHKSUM; 1310 /* vlan header offload */ 1311 if (info->vlan) 1312 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1313 } 1314 WRITE_ONCE(desc->txd4, data); 1315} 1316 1317static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1318 struct mtk_tx_dma_desc_info *info) 1319{ 1320 struct mtk_mac *mac = netdev_priv(dev); 1321 struct mtk_tx_dma_v2 *desc = txd; 1322 struct mtk_eth *eth = mac->hw; 1323 u32 data; 1324 1325 WRITE_ONCE(desc->txd1, info->addr); 1326 1327 data = TX_DMA_PLEN0(info->size); 1328 if (info->last) 1329 data |= TX_DMA_LS0; 1330 1331 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 1332 data |= TX_DMA_PREP_ADDR64(info->addr); 1333 1334 WRITE_ONCE(desc->txd3, data); 1335 1336 /* set forward port */ 1337 switch (mac->id) { 1338 case MTK_GMAC1_ID: 1339 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1340 break; 1341 case MTK_GMAC2_ID: 1342 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1343 break; 1344 case MTK_GMAC3_ID: 1345 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1346 break; 1347 } 1348 1349 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1350 WRITE_ONCE(desc->txd4, data); 1351 1352 data = 0; 1353 if (info->first) { 1354 if (info->gso) 1355 data |= TX_DMA_TSO_V2; 1356 /* tx checksum offload */ 1357 if (info->csum) 1358 data |= TX_DMA_CHKSUM_V2; 1359 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1360 data |= TX_DMA_SPTAG_V3; 1361 } 1362 WRITE_ONCE(desc->txd5, data); 1363 1364 data = 0; 1365 if (info->first && info->vlan) 1366 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1367 WRITE_ONCE(desc->txd6, data); 1368 1369 WRITE_ONCE(desc->txd7, 0); 1370 WRITE_ONCE(desc->txd8, 0); 1371} 1372 1373static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1374 struct mtk_tx_dma_desc_info *info) 1375{ 1376 struct mtk_mac *mac = netdev_priv(dev); 1377 struct mtk_eth *eth = mac->hw; 1378 1379 if (mtk_is_netsys_v2_or_greater(eth)) 1380 mtk_tx_set_dma_desc_v2(dev, txd, info); 1381 else 1382 mtk_tx_set_dma_desc_v1(dev, txd, info); 1383} 1384 1385static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1386 int tx_num, struct mtk_tx_ring *ring, bool gso) 1387{ 1388 struct mtk_tx_dma_desc_info txd_info = { 1389 .size = skb_headlen(skb), 1390 .gso = gso, 1391 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1392 .vlan = skb_vlan_tag_present(skb), 1393 .qid = skb_get_queue_mapping(skb), 1394 .vlan_tci = skb_vlan_tag_get(skb), 1395 .first = true, 1396 .last = !skb_is_nonlinear(skb), 1397 }; 1398 struct netdev_queue *txq; 1399 struct mtk_mac *mac = netdev_priv(dev); 1400 struct mtk_eth *eth = mac->hw; 1401 const struct mtk_soc_data *soc = eth->soc; 1402 struct mtk_tx_dma *itxd, *txd; 1403 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1404 struct mtk_tx_buf *itx_buf, *tx_buf; 1405 int i, n_desc = 1; 1406 int queue = skb_get_queue_mapping(skb); 1407 int k = 0; 1408 1409 txq = netdev_get_tx_queue(dev, queue); 1410 itxd = ring->next_free; 1411 itxd_pdma = qdma_to_pdma(ring, itxd); 1412 if (itxd == ring->last_free) 1413 return -ENOMEM; 1414 1415 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1416 memset(itx_buf, 0, sizeof(*itx_buf)); 1417 1418 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1419 DMA_TO_DEVICE); 1420 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1421 return -ENOMEM; 1422 1423 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1424 1425 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1426 itx_buf->mac_id = mac->id; 1427 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1428 k++); 1429 1430 /* TX SG offload */ 1431 txd = itxd; 1432 txd_pdma = qdma_to_pdma(ring, txd); 1433 1434 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1435 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1436 unsigned int offset = 0; 1437 int frag_size = skb_frag_size(frag); 1438 1439 while (frag_size) { 1440 bool new_desc = true; 1441 1442 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1443 (i & 0x1)) { 1444 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1445 txd_pdma = qdma_to_pdma(ring, txd); 1446 if (txd == ring->last_free) 1447 goto err_dma; 1448 1449 n_desc++; 1450 } else { 1451 new_desc = false; 1452 } 1453 1454 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1455 txd_info.size = min_t(unsigned int, frag_size, 1456 soc->txrx.dma_max_len); 1457 txd_info.qid = queue; 1458 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1459 !(frag_size - txd_info.size); 1460 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1461 offset, txd_info.size, 1462 DMA_TO_DEVICE); 1463 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1464 goto err_dma; 1465 1466 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1467 1468 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1469 soc->txrx.txd_size); 1470 if (new_desc) 1471 memset(tx_buf, 0, sizeof(*tx_buf)); 1472 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1473 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1474 tx_buf->mac_id = mac->id; 1475 1476 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1477 txd_info.size, k++); 1478 1479 frag_size -= txd_info.size; 1480 offset += txd_info.size; 1481 } 1482 } 1483 1484 /* store skb to cleanup */ 1485 itx_buf->type = MTK_TYPE_SKB; 1486 itx_buf->data = skb; 1487 1488 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1489 if (k & 0x1) 1490 txd_pdma->txd2 |= TX_DMA_LS0; 1491 else 1492 txd_pdma->txd2 |= TX_DMA_LS1; 1493 } 1494 1495 netdev_tx_sent_queue(txq, skb->len); 1496 skb_tx_timestamp(skb); 1497 1498 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1499 atomic_sub(n_desc, &ring->free_count); 1500 1501 /* make sure that all changes to the dma ring are flushed before we 1502 * continue 1503 */ 1504 wmb(); 1505 1506 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1507 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1508 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1509 } else { 1510 int next_idx; 1511 1512 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1513 ring->dma_size); 1514 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1515 } 1516 1517 return 0; 1518 1519err_dma: 1520 do { 1521 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1522 1523 /* unmap dma */ 1524 mtk_tx_unmap(eth, tx_buf, NULL, false); 1525 1526 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1527 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1528 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1529 1530 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1531 itxd_pdma = qdma_to_pdma(ring, itxd); 1532 } while (itxd != txd); 1533 1534 return -ENOMEM; 1535} 1536 1537static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1538{ 1539 int i, nfrags = 1; 1540 skb_frag_t *frag; 1541 1542 if (skb_is_gso(skb)) { 1543 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1544 frag = &skb_shinfo(skb)->frags[i]; 1545 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1546 eth->soc->txrx.dma_max_len); 1547 } 1548 } else { 1549 nfrags += skb_shinfo(skb)->nr_frags; 1550 } 1551 1552 return nfrags; 1553} 1554 1555static int mtk_queue_stopped(struct mtk_eth *eth) 1556{ 1557 int i; 1558 1559 for (i = 0; i < MTK_MAX_DEVS; i++) { 1560 if (!eth->netdev[i]) 1561 continue; 1562 if (netif_queue_stopped(eth->netdev[i])) 1563 return 1; 1564 } 1565 1566 return 0; 1567} 1568 1569static void mtk_wake_queue(struct mtk_eth *eth) 1570{ 1571 int i; 1572 1573 for (i = 0; i < MTK_MAX_DEVS; i++) { 1574 if (!eth->netdev[i]) 1575 continue; 1576 netif_tx_wake_all_queues(eth->netdev[i]); 1577 } 1578} 1579 1580static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1581{ 1582 struct mtk_mac *mac = netdev_priv(dev); 1583 struct mtk_eth *eth = mac->hw; 1584 struct mtk_tx_ring *ring = ð->tx_ring; 1585 struct net_device_stats *stats = &dev->stats; 1586 bool gso = false; 1587 int tx_num; 1588 1589 /* normally we can rely on the stack not calling this more than once, 1590 * however we have 2 queues running on the same ring so we need to lock 1591 * the ring access 1592 */ 1593 spin_lock(ð->page_lock); 1594 1595 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1596 goto drop; 1597 1598 tx_num = mtk_cal_txd_req(eth, skb); 1599 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1600 netif_tx_stop_all_queues(dev); 1601 netif_err(eth, tx_queued, dev, 1602 "Tx Ring full when queue awake!\n"); 1603 spin_unlock(ð->page_lock); 1604 return NETDEV_TX_BUSY; 1605 } 1606 1607 /* TSO: fill MSS info in tcp checksum field */ 1608 if (skb_is_gso(skb)) { 1609 if (skb_cow_head(skb, 0)) { 1610 netif_warn(eth, tx_err, dev, 1611 "GSO expand head fail.\n"); 1612 goto drop; 1613 } 1614 1615 if (skb_shinfo(skb)->gso_type & 1616 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1617 gso = true; 1618 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1619 } 1620 } 1621 1622 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1623 goto drop; 1624 1625 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1626 netif_tx_stop_all_queues(dev); 1627 1628 spin_unlock(ð->page_lock); 1629 1630 return NETDEV_TX_OK; 1631 1632drop: 1633 spin_unlock(ð->page_lock); 1634 stats->tx_dropped++; 1635 dev_kfree_skb_any(skb); 1636 return NETDEV_TX_OK; 1637} 1638 1639static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1640{ 1641 int i; 1642 struct mtk_rx_ring *ring; 1643 int idx; 1644 1645 if (!eth->hwlro) 1646 return ð->rx_ring[0]; 1647 1648 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1649 struct mtk_rx_dma *rxd; 1650 1651 ring = ð->rx_ring[i]; 1652 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1653 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1654 if (rxd->rxd2 & RX_DMA_DONE) { 1655 ring->calc_idx_update = true; 1656 return ring; 1657 } 1658 } 1659 1660 return NULL; 1661} 1662 1663static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1664{ 1665 struct mtk_rx_ring *ring; 1666 int i; 1667 1668 if (!eth->hwlro) { 1669 ring = ð->rx_ring[0]; 1670 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1671 } else { 1672 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1673 ring = ð->rx_ring[i]; 1674 if (ring->calc_idx_update) { 1675 ring->calc_idx_update = false; 1676 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1677 } 1678 } 1679 } 1680} 1681 1682static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1683{ 1684 return mtk_is_netsys_v2_or_greater(eth); 1685} 1686 1687static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1688 struct xdp_rxq_info *xdp_q, 1689 int id, int size) 1690{ 1691 struct page_pool_params pp_params = { 1692 .order = 0, 1693 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1694 .pool_size = size, 1695 .nid = NUMA_NO_NODE, 1696 .dev = eth->dma_dev, 1697 .offset = MTK_PP_HEADROOM, 1698 .max_len = MTK_PP_MAX_BUF_SIZE, 1699 }; 1700 struct page_pool *pp; 1701 int err; 1702 1703 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1704 : DMA_FROM_DEVICE; 1705 pp = page_pool_create(&pp_params); 1706 if (IS_ERR(pp)) 1707 return pp; 1708 1709 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1710 eth->rx_napi.napi_id, PAGE_SIZE); 1711 if (err < 0) 1712 goto err_free_pp; 1713 1714 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1715 if (err) 1716 goto err_unregister_rxq; 1717 1718 return pp; 1719 1720err_unregister_rxq: 1721 xdp_rxq_info_unreg(xdp_q); 1722err_free_pp: 1723 page_pool_destroy(pp); 1724 1725 return ERR_PTR(err); 1726} 1727 1728static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1729 gfp_t gfp_mask) 1730{ 1731 struct page *page; 1732 1733 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1734 if (!page) 1735 return NULL; 1736 1737 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1738 return page_address(page); 1739} 1740 1741static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1742{ 1743 if (ring->page_pool) 1744 page_pool_put_full_page(ring->page_pool, 1745 virt_to_head_page(data), napi); 1746 else 1747 skb_free_frag(data); 1748} 1749 1750static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1751 struct mtk_tx_dma_desc_info *txd_info, 1752 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1753 void *data, u16 headroom, int index, bool dma_map) 1754{ 1755 struct mtk_tx_ring *ring = ð->tx_ring; 1756 struct mtk_mac *mac = netdev_priv(dev); 1757 struct mtk_tx_dma *txd_pdma; 1758 1759 if (dma_map) { /* ndo_xdp_xmit */ 1760 txd_info->addr = dma_map_single(eth->dma_dev, data, 1761 txd_info->size, DMA_TO_DEVICE); 1762 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1763 return -ENOMEM; 1764 1765 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1766 } else { 1767 struct page *page = virt_to_head_page(data); 1768 1769 txd_info->addr = page_pool_get_dma_addr(page) + 1770 sizeof(struct xdp_frame) + headroom; 1771 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1772 txd_info->size, DMA_BIDIRECTIONAL); 1773 } 1774 mtk_tx_set_dma_desc(dev, txd, txd_info); 1775 1776 tx_buf->mac_id = mac->id; 1777 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1778 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1779 1780 txd_pdma = qdma_to_pdma(ring, txd); 1781 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1782 index); 1783 1784 return 0; 1785} 1786 1787static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1788 struct net_device *dev, bool dma_map) 1789{ 1790 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1791 const struct mtk_soc_data *soc = eth->soc; 1792 struct mtk_tx_ring *ring = ð->tx_ring; 1793 struct mtk_mac *mac = netdev_priv(dev); 1794 struct mtk_tx_dma_desc_info txd_info = { 1795 .size = xdpf->len, 1796 .first = true, 1797 .last = !xdp_frame_has_frags(xdpf), 1798 .qid = mac->id, 1799 }; 1800 int err, index = 0, n_desc = 1, nr_frags; 1801 struct mtk_tx_buf *htx_buf, *tx_buf; 1802 struct mtk_tx_dma *htxd, *txd; 1803 void *data = xdpf->data; 1804 1805 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1806 return -EBUSY; 1807 1808 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1809 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1810 return -EBUSY; 1811 1812 spin_lock(ð->page_lock); 1813 1814 txd = ring->next_free; 1815 if (txd == ring->last_free) { 1816 spin_unlock(ð->page_lock); 1817 return -ENOMEM; 1818 } 1819 htxd = txd; 1820 1821 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1822 memset(tx_buf, 0, sizeof(*tx_buf)); 1823 htx_buf = tx_buf; 1824 1825 for (;;) { 1826 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1827 data, xdpf->headroom, index, dma_map); 1828 if (err < 0) 1829 goto unmap; 1830 1831 if (txd_info.last) 1832 break; 1833 1834 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1835 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1836 if (txd == ring->last_free) 1837 goto unmap; 1838 1839 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1840 soc->txrx.txd_size); 1841 memset(tx_buf, 0, sizeof(*tx_buf)); 1842 n_desc++; 1843 } 1844 1845 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1846 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1847 txd_info.last = index + 1 == nr_frags; 1848 txd_info.qid = mac->id; 1849 data = skb_frag_address(&sinfo->frags[index]); 1850 1851 index++; 1852 } 1853 /* store xdpf for cleanup */ 1854 htx_buf->data = xdpf; 1855 1856 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1857 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1858 1859 if (index & 1) 1860 txd_pdma->txd2 |= TX_DMA_LS0; 1861 else 1862 txd_pdma->txd2 |= TX_DMA_LS1; 1863 } 1864 1865 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1866 atomic_sub(n_desc, &ring->free_count); 1867 1868 /* make sure that all changes to the dma ring are flushed before we 1869 * continue 1870 */ 1871 wmb(); 1872 1873 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1874 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1875 } else { 1876 int idx; 1877 1878 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1879 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1880 MT7628_TX_CTX_IDX0); 1881 } 1882 1883 spin_unlock(ð->page_lock); 1884 1885 return 0; 1886 1887unmap: 1888 while (htxd != txd) { 1889 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1890 mtk_tx_unmap(eth, tx_buf, NULL, false); 1891 1892 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1893 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1894 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1895 1896 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1897 } 1898 1899 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1900 } 1901 1902 spin_unlock(ð->page_lock); 1903 1904 return err; 1905} 1906 1907static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1908 struct xdp_frame **frames, u32 flags) 1909{ 1910 struct mtk_mac *mac = netdev_priv(dev); 1911 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1912 struct mtk_eth *eth = mac->hw; 1913 int i, nxmit = 0; 1914 1915 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1916 return -EINVAL; 1917 1918 for (i = 0; i < num_frame; i++) { 1919 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1920 break; 1921 nxmit++; 1922 } 1923 1924 u64_stats_update_begin(&hw_stats->syncp); 1925 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1926 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1927 u64_stats_update_end(&hw_stats->syncp); 1928 1929 return nxmit; 1930} 1931 1932static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1933 struct xdp_buff *xdp, struct net_device *dev) 1934{ 1935 struct mtk_mac *mac = netdev_priv(dev); 1936 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1937 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1938 struct bpf_prog *prog; 1939 u32 act = XDP_PASS; 1940 1941 rcu_read_lock(); 1942 1943 prog = rcu_dereference(eth->prog); 1944 if (!prog) 1945 goto out; 1946 1947 act = bpf_prog_run_xdp(prog, xdp); 1948 switch (act) { 1949 case XDP_PASS: 1950 count = &hw_stats->xdp_stats.rx_xdp_pass; 1951 goto update_stats; 1952 case XDP_REDIRECT: 1953 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1954 act = XDP_DROP; 1955 break; 1956 } 1957 1958 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1959 goto update_stats; 1960 case XDP_TX: { 1961 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1962 1963 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1964 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1965 act = XDP_DROP; 1966 break; 1967 } 1968 1969 count = &hw_stats->xdp_stats.rx_xdp_tx; 1970 goto update_stats; 1971 } 1972 default: 1973 bpf_warn_invalid_xdp_action(dev, prog, act); 1974 fallthrough; 1975 case XDP_ABORTED: 1976 trace_xdp_exception(dev, prog, act); 1977 fallthrough; 1978 case XDP_DROP: 1979 break; 1980 } 1981 1982 page_pool_put_full_page(ring->page_pool, 1983 virt_to_head_page(xdp->data), true); 1984 1985update_stats: 1986 u64_stats_update_begin(&hw_stats->syncp); 1987 *count = *count + 1; 1988 u64_stats_update_end(&hw_stats->syncp); 1989out: 1990 rcu_read_unlock(); 1991 1992 return act; 1993} 1994 1995static int mtk_poll_rx(struct napi_struct *napi, int budget, 1996 struct mtk_eth *eth) 1997{ 1998 struct dim_sample dim_sample = {}; 1999 struct mtk_rx_ring *ring; 2000 bool xdp_flush = false; 2001 int idx; 2002 struct sk_buff *skb; 2003 u64 addr64 = 0; 2004 u8 *data, *new_data; 2005 struct mtk_rx_dma_v2 *rxd, trxd; 2006 int done = 0, bytes = 0; 2007 dma_addr_t dma_addr = DMA_MAPPING_ERROR; 2008 2009 while (done < budget) { 2010 unsigned int pktlen, *rxdcsum; 2011 struct net_device *netdev; 2012 u32 hash, reason; 2013 int mac = 0; 2014 2015 ring = mtk_get_rx_ring(eth); 2016 if (unlikely(!ring)) 2017 goto rx_done; 2018 2019 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2020 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 2021 data = ring->data[idx]; 2022 2023 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2024 break; 2025 2026 /* find out which mac the packet come from. values start at 1 */ 2027 if (mtk_is_netsys_v2_or_greater(eth)) { 2028 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2029 2030 switch (val) { 2031 case PSE_GDM1_PORT: 2032 case PSE_GDM2_PORT: 2033 mac = val - 1; 2034 break; 2035 case PSE_GDM3_PORT: 2036 mac = MTK_GMAC3_ID; 2037 break; 2038 default: 2039 break; 2040 } 2041 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2042 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2043 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2044 } 2045 2046 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2047 !eth->netdev[mac])) 2048 goto release_desc; 2049 2050 netdev = eth->netdev[mac]; 2051 2052 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2053 goto release_desc; 2054 2055 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2056 2057 /* alloc new buffer */ 2058 if (ring->page_pool) { 2059 struct page *page = virt_to_head_page(data); 2060 struct xdp_buff xdp; 2061 u32 ret; 2062 2063 new_data = mtk_page_pool_get_buff(ring->page_pool, 2064 &dma_addr, 2065 GFP_ATOMIC); 2066 if (unlikely(!new_data)) { 2067 netdev->stats.rx_dropped++; 2068 goto release_desc; 2069 } 2070 2071 dma_sync_single_for_cpu(eth->dma_dev, 2072 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2073 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2074 2075 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2076 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2077 false); 2078 xdp_buff_clear_frags_flag(&xdp); 2079 2080 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2081 if (ret == XDP_REDIRECT) 2082 xdp_flush = true; 2083 2084 if (ret != XDP_PASS) 2085 goto skip_rx; 2086 2087 skb = build_skb(data, PAGE_SIZE); 2088 if (unlikely(!skb)) { 2089 page_pool_put_full_page(ring->page_pool, 2090 page, true); 2091 netdev->stats.rx_dropped++; 2092 goto skip_rx; 2093 } 2094 2095 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2096 skb_put(skb, xdp.data_end - xdp.data); 2097 skb_mark_for_recycle(skb); 2098 } else { 2099 if (ring->frag_size <= PAGE_SIZE) 2100 new_data = napi_alloc_frag(ring->frag_size); 2101 else 2102 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2103 2104 if (unlikely(!new_data)) { 2105 netdev->stats.rx_dropped++; 2106 goto release_desc; 2107 } 2108 2109 dma_addr = dma_map_single(eth->dma_dev, 2110 new_data + NET_SKB_PAD + eth->ip_align, 2111 ring->buf_size, DMA_FROM_DEVICE); 2112 if (unlikely(dma_mapping_error(eth->dma_dev, 2113 dma_addr))) { 2114 skb_free_frag(new_data); 2115 netdev->stats.rx_dropped++; 2116 goto release_desc; 2117 } 2118 2119 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2120 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2); 2121 2122 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), 2123 ring->buf_size, DMA_FROM_DEVICE); 2124 2125 skb = build_skb(data, ring->frag_size); 2126 if (unlikely(!skb)) { 2127 netdev->stats.rx_dropped++; 2128 skb_free_frag(data); 2129 goto skip_rx; 2130 } 2131 2132 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2133 skb_put(skb, pktlen); 2134 } 2135 2136 skb->dev = netdev; 2137 bytes += skb->len; 2138 2139 if (mtk_is_netsys_v2_or_greater(eth)) { 2140 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2141 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2142 if (hash != MTK_RXD5_FOE_ENTRY) 2143 skb_set_hash(skb, jhash_1word(hash, 0), 2144 PKT_HASH_TYPE_L4); 2145 rxdcsum = &trxd.rxd3; 2146 } else { 2147 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2148 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2149 if (hash != MTK_RXD4_FOE_ENTRY) 2150 skb_set_hash(skb, jhash_1word(hash, 0), 2151 PKT_HASH_TYPE_L4); 2152 rxdcsum = &trxd.rxd4; 2153 } 2154 2155 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2156 skb->ip_summed = CHECKSUM_UNNECESSARY; 2157 else 2158 skb_checksum_none_assert(skb); 2159 skb->protocol = eth_type_trans(skb, netdev); 2160 2161 /* When using VLAN untagging in combination with DSA, the 2162 * hardware treats the MTK special tag as a VLAN and untags it. 2163 */ 2164 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2165 netdev_uses_dsa(netdev)) { 2166 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2167 2168 if (port < ARRAY_SIZE(eth->dsa_meta) && 2169 eth->dsa_meta[port]) 2170 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2171 } 2172 2173 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2174 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2175 2176 skb_record_rx_queue(skb, 0); 2177 napi_gro_receive(napi, skb); 2178 2179skip_rx: 2180 ring->data[idx] = new_data; 2181 rxd->rxd1 = (unsigned int)dma_addr; 2182release_desc: 2183 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2184 rxd->rxd2 = RX_DMA_LSO; 2185 else 2186 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2187 2188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && 2189 likely(dma_addr != DMA_MAPPING_ERROR)) 2190 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2191 2192 ring->calc_idx = idx; 2193 done++; 2194 } 2195 2196rx_done: 2197 if (done) { 2198 /* make sure that all changes to the dma ring are flushed before 2199 * we continue 2200 */ 2201 wmb(); 2202 mtk_update_rx_cpu_idx(eth); 2203 } 2204 2205 eth->rx_packets += done; 2206 eth->rx_bytes += bytes; 2207 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2208 &dim_sample); 2209 net_dim(ð->rx_dim, dim_sample); 2210 2211 if (xdp_flush) 2212 xdp_do_flush_map(); 2213 2214 return done; 2215} 2216 2217struct mtk_poll_state { 2218 struct netdev_queue *txq; 2219 unsigned int total; 2220 unsigned int done; 2221 unsigned int bytes; 2222}; 2223 2224static void 2225mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2226 struct sk_buff *skb) 2227{ 2228 struct netdev_queue *txq; 2229 struct net_device *dev; 2230 unsigned int bytes = skb->len; 2231 2232 state->total++; 2233 eth->tx_packets++; 2234 eth->tx_bytes += bytes; 2235 2236 dev = eth->netdev[mac]; 2237 if (!dev) 2238 return; 2239 2240 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2241 if (state->txq == txq) { 2242 state->done++; 2243 state->bytes += bytes; 2244 return; 2245 } 2246 2247 if (state->txq) 2248 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2249 2250 state->txq = txq; 2251 state->done = 1; 2252 state->bytes = bytes; 2253} 2254 2255static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2256 struct mtk_poll_state *state) 2257{ 2258 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2259 struct mtk_tx_ring *ring = ð->tx_ring; 2260 struct mtk_tx_buf *tx_buf; 2261 struct xdp_frame_bulk bq; 2262 struct mtk_tx_dma *desc; 2263 u32 cpu, dma; 2264 2265 cpu = ring->last_free_ptr; 2266 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2267 2268 desc = mtk_qdma_phys_to_virt(ring, cpu); 2269 xdp_frame_bulk_init(&bq); 2270 2271 while ((cpu != dma) && budget) { 2272 u32 next_cpu = desc->txd2; 2273 2274 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2275 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2276 break; 2277 2278 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2279 eth->soc->txrx.txd_size); 2280 if (!tx_buf->data) 2281 break; 2282 2283 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2284 if (tx_buf->type == MTK_TYPE_SKB) 2285 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2286 tx_buf->data); 2287 2288 budget--; 2289 } 2290 mtk_tx_unmap(eth, tx_buf, &bq, true); 2291 2292 ring->last_free = desc; 2293 atomic_inc(&ring->free_count); 2294 2295 cpu = next_cpu; 2296 } 2297 xdp_flush_frame_bulk(&bq); 2298 2299 ring->last_free_ptr = cpu; 2300 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2301 2302 return budget; 2303} 2304 2305static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2306 struct mtk_poll_state *state) 2307{ 2308 struct mtk_tx_ring *ring = ð->tx_ring; 2309 struct mtk_tx_buf *tx_buf; 2310 struct xdp_frame_bulk bq; 2311 struct mtk_tx_dma *desc; 2312 u32 cpu, dma; 2313 2314 cpu = ring->cpu_idx; 2315 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2316 xdp_frame_bulk_init(&bq); 2317 2318 while ((cpu != dma) && budget) { 2319 tx_buf = &ring->buf[cpu]; 2320 if (!tx_buf->data) 2321 break; 2322 2323 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2324 if (tx_buf->type == MTK_TYPE_SKB) 2325 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2326 budget--; 2327 } 2328 mtk_tx_unmap(eth, tx_buf, &bq, true); 2329 2330 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2331 ring->last_free = desc; 2332 atomic_inc(&ring->free_count); 2333 2334 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2335 } 2336 xdp_flush_frame_bulk(&bq); 2337 2338 ring->cpu_idx = cpu; 2339 2340 return budget; 2341} 2342 2343static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2344{ 2345 struct mtk_tx_ring *ring = ð->tx_ring; 2346 struct dim_sample dim_sample = {}; 2347 struct mtk_poll_state state = {}; 2348 2349 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2350 budget = mtk_poll_tx_qdma(eth, budget, &state); 2351 else 2352 budget = mtk_poll_tx_pdma(eth, budget, &state); 2353 2354 if (state.txq) 2355 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2356 2357 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2358 &dim_sample); 2359 net_dim(ð->tx_dim, dim_sample); 2360 2361 if (mtk_queue_stopped(eth) && 2362 (atomic_read(&ring->free_count) > ring->thresh)) 2363 mtk_wake_queue(eth); 2364 2365 return state.total; 2366} 2367 2368static void mtk_handle_status_irq(struct mtk_eth *eth) 2369{ 2370 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2371 2372 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2373 mtk_stats_update(eth); 2374 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2375 MTK_INT_STATUS2); 2376 } 2377} 2378 2379static int mtk_napi_tx(struct napi_struct *napi, int budget) 2380{ 2381 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2382 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2383 int tx_done = 0; 2384 2385 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2386 mtk_handle_status_irq(eth); 2387 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2388 tx_done = mtk_poll_tx(eth, budget); 2389 2390 if (unlikely(netif_msg_intr(eth))) { 2391 dev_info(eth->dev, 2392 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2393 mtk_r32(eth, reg_map->tx_irq_status), 2394 mtk_r32(eth, reg_map->tx_irq_mask)); 2395 } 2396 2397 if (tx_done == budget) 2398 return budget; 2399 2400 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2401 return budget; 2402 2403 if (napi_complete_done(napi, tx_done)) 2404 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2405 2406 return tx_done; 2407} 2408 2409static int mtk_napi_rx(struct napi_struct *napi, int budget) 2410{ 2411 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2412 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2413 int rx_done_total = 0; 2414 2415 mtk_handle_status_irq(eth); 2416 2417 do { 2418 int rx_done; 2419 2420 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2421 reg_map->pdma.irq_status); 2422 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2423 rx_done_total += rx_done; 2424 2425 if (unlikely(netif_msg_intr(eth))) { 2426 dev_info(eth->dev, 2427 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2428 mtk_r32(eth, reg_map->pdma.irq_status), 2429 mtk_r32(eth, reg_map->pdma.irq_mask)); 2430 } 2431 2432 if (rx_done_total == budget) 2433 return budget; 2434 2435 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2436 eth->soc->txrx.rx_irq_done_mask); 2437 2438 if (napi_complete_done(napi, rx_done_total)) 2439 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2440 2441 return rx_done_total; 2442} 2443 2444static int mtk_tx_alloc(struct mtk_eth *eth) 2445{ 2446 const struct mtk_soc_data *soc = eth->soc; 2447 struct mtk_tx_ring *ring = ð->tx_ring; 2448 int i, sz = soc->txrx.txd_size; 2449 struct mtk_tx_dma_v2 *txd; 2450 int ring_size; 2451 u32 ofs, val; 2452 2453 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2454 ring_size = MTK_QDMA_RING_SIZE; 2455 else 2456 ring_size = MTK_DMA_SIZE; 2457 2458 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2459 GFP_KERNEL); 2460 if (!ring->buf) 2461 goto no_tx_mem; 2462 2463 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { 2464 ring->dma = eth->sram_base + ring_size * sz; 2465 ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; 2466 } else { 2467 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2468 &ring->phys, GFP_KERNEL); 2469 } 2470 2471 if (!ring->dma) 2472 goto no_tx_mem; 2473 2474 for (i = 0; i < ring_size; i++) { 2475 int next = (i + 1) % ring_size; 2476 u32 next_ptr = ring->phys + next * sz; 2477 2478 txd = ring->dma + i * sz; 2479 txd->txd2 = next_ptr; 2480 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2481 txd->txd4 = 0; 2482 if (mtk_is_netsys_v2_or_greater(eth)) { 2483 txd->txd5 = 0; 2484 txd->txd6 = 0; 2485 txd->txd7 = 0; 2486 txd->txd8 = 0; 2487 } 2488 } 2489 2490 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2491 * only as the framework. The real HW descriptors are the PDMA 2492 * descriptors in ring->dma_pdma. 2493 */ 2494 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2495 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2496 &ring->phys_pdma, GFP_KERNEL); 2497 if (!ring->dma_pdma) 2498 goto no_tx_mem; 2499 2500 for (i = 0; i < ring_size; i++) { 2501 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2502 ring->dma_pdma[i].txd4 = 0; 2503 } 2504 } 2505 2506 ring->dma_size = ring_size; 2507 atomic_set(&ring->free_count, ring_size - 2); 2508 ring->next_free = ring->dma; 2509 ring->last_free = (void *)txd; 2510 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2511 ring->thresh = MAX_SKB_FRAGS; 2512 2513 /* make sure that all changes to the dma ring are flushed before we 2514 * continue 2515 */ 2516 wmb(); 2517 2518 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2519 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2520 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2521 mtk_w32(eth, 2522 ring->phys + ((ring_size - 1) * sz), 2523 soc->reg_map->qdma.crx_ptr); 2524 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2525 2526 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2527 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2528 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2529 2530 val = MTK_QTX_SCH_MIN_RATE_EN | 2531 /* minimum: 10 Mbps */ 2532 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2533 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2534 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2535 if (mtk_is_netsys_v1(eth)) 2536 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2537 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2538 ofs += MTK_QTX_OFFSET; 2539 } 2540 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2541 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2542 if (mtk_is_netsys_v2_or_greater(eth)) 2543 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2544 } else { 2545 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2546 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2547 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2548 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2549 } 2550 2551 return 0; 2552 2553no_tx_mem: 2554 return -ENOMEM; 2555} 2556 2557static void mtk_tx_clean(struct mtk_eth *eth) 2558{ 2559 const struct mtk_soc_data *soc = eth->soc; 2560 struct mtk_tx_ring *ring = ð->tx_ring; 2561 int i; 2562 2563 if (ring->buf) { 2564 for (i = 0; i < ring->dma_size; i++) 2565 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2566 kfree(ring->buf); 2567 ring->buf = NULL; 2568 } 2569 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { 2570 dma_free_coherent(eth->dma_dev, 2571 ring->dma_size * soc->txrx.txd_size, 2572 ring->dma, ring->phys); 2573 ring->dma = NULL; 2574 } 2575 2576 if (ring->dma_pdma) { 2577 dma_free_coherent(eth->dma_dev, 2578 ring->dma_size * soc->txrx.txd_size, 2579 ring->dma_pdma, ring->phys_pdma); 2580 ring->dma_pdma = NULL; 2581 } 2582} 2583 2584static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2585{ 2586 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2587 struct mtk_rx_ring *ring; 2588 int rx_data_len, rx_dma_size, tx_ring_size; 2589 int i; 2590 2591 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2592 tx_ring_size = MTK_QDMA_RING_SIZE; 2593 else 2594 tx_ring_size = MTK_DMA_SIZE; 2595 2596 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2597 if (ring_no) 2598 return -EINVAL; 2599 ring = ð->rx_ring_qdma; 2600 } else { 2601 ring = ð->rx_ring[ring_no]; 2602 } 2603 2604 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2605 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2606 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2607 } else { 2608 rx_data_len = ETH_DATA_LEN; 2609 rx_dma_size = MTK_DMA_SIZE; 2610 } 2611 2612 ring->frag_size = mtk_max_frag_size(rx_data_len); 2613 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2614 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2615 GFP_KERNEL); 2616 if (!ring->data) 2617 return -ENOMEM; 2618 2619 if (mtk_page_pool_enabled(eth)) { 2620 struct page_pool *pp; 2621 2622 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2623 rx_dma_size); 2624 if (IS_ERR(pp)) 2625 return PTR_ERR(pp); 2626 2627 ring->page_pool = pp; 2628 } 2629 2630 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || 2631 rx_flag != MTK_RX_FLAGS_NORMAL) { 2632 ring->dma = dma_alloc_coherent(eth->dma_dev, 2633 rx_dma_size * eth->soc->txrx.rxd_size, 2634 &ring->phys, GFP_KERNEL); 2635 } else { 2636 struct mtk_tx_ring *tx_ring = ð->tx_ring; 2637 2638 ring->dma = tx_ring->dma + tx_ring_size * 2639 eth->soc->txrx.txd_size * (ring_no + 1); 2640 ring->phys = tx_ring->phys + tx_ring_size * 2641 eth->soc->txrx.txd_size * (ring_no + 1); 2642 } 2643 2644 if (!ring->dma) 2645 return -ENOMEM; 2646 2647 for (i = 0; i < rx_dma_size; i++) { 2648 struct mtk_rx_dma_v2 *rxd; 2649 dma_addr_t dma_addr; 2650 void *data; 2651 2652 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2653 if (ring->page_pool) { 2654 data = mtk_page_pool_get_buff(ring->page_pool, 2655 &dma_addr, GFP_KERNEL); 2656 if (!data) 2657 return -ENOMEM; 2658 } else { 2659 if (ring->frag_size <= PAGE_SIZE) 2660 data = netdev_alloc_frag(ring->frag_size); 2661 else 2662 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2663 2664 if (!data) 2665 return -ENOMEM; 2666 2667 dma_addr = dma_map_single(eth->dma_dev, 2668 data + NET_SKB_PAD + eth->ip_align, 2669 ring->buf_size, DMA_FROM_DEVICE); 2670 if (unlikely(dma_mapping_error(eth->dma_dev, 2671 dma_addr))) { 2672 skb_free_frag(data); 2673 return -ENOMEM; 2674 } 2675 } 2676 rxd->rxd1 = (unsigned int)dma_addr; 2677 ring->data[i] = data; 2678 2679 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2680 rxd->rxd2 = RX_DMA_LSO; 2681 else 2682 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2683 2684 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2685 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); 2686 2687 rxd->rxd3 = 0; 2688 rxd->rxd4 = 0; 2689 if (mtk_is_netsys_v2_or_greater(eth)) { 2690 rxd->rxd5 = 0; 2691 rxd->rxd6 = 0; 2692 rxd->rxd7 = 0; 2693 rxd->rxd8 = 0; 2694 } 2695 } 2696 2697 ring->dma_size = rx_dma_size; 2698 ring->calc_idx_update = false; 2699 ring->calc_idx = rx_dma_size - 1; 2700 if (rx_flag == MTK_RX_FLAGS_QDMA) 2701 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2702 ring_no * MTK_QRX_OFFSET; 2703 else 2704 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2705 ring_no * MTK_QRX_OFFSET; 2706 /* make sure that all changes to the dma ring are flushed before we 2707 * continue 2708 */ 2709 wmb(); 2710 2711 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2712 mtk_w32(eth, ring->phys, 2713 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2714 mtk_w32(eth, rx_dma_size, 2715 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2716 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2717 reg_map->qdma.rst_idx); 2718 } else { 2719 mtk_w32(eth, ring->phys, 2720 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2721 mtk_w32(eth, rx_dma_size, 2722 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2723 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2724 reg_map->pdma.rst_idx); 2725 } 2726 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2727 2728 return 0; 2729} 2730 2731static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram) 2732{ 2733 u64 addr64 = 0; 2734 int i; 2735 2736 if (ring->data && ring->dma) { 2737 for (i = 0; i < ring->dma_size; i++) { 2738 struct mtk_rx_dma *rxd; 2739 2740 if (!ring->data[i]) 2741 continue; 2742 2743 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2744 if (!rxd->rxd1) 2745 continue; 2746 2747 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) 2748 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); 2749 2750 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), 2751 ring->buf_size, DMA_FROM_DEVICE); 2752 mtk_rx_put_buff(ring, ring->data[i], false); 2753 } 2754 kfree(ring->data); 2755 ring->data = NULL; 2756 } 2757 2758 if (!in_sram && ring->dma) { 2759 dma_free_coherent(eth->dma_dev, 2760 ring->dma_size * eth->soc->txrx.rxd_size, 2761 ring->dma, ring->phys); 2762 ring->dma = NULL; 2763 } 2764 2765 if (ring->page_pool) { 2766 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2767 xdp_rxq_info_unreg(&ring->xdp_q); 2768 page_pool_destroy(ring->page_pool); 2769 ring->page_pool = NULL; 2770 } 2771} 2772 2773static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2774{ 2775 int i; 2776 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2777 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2778 2779 /* set LRO rings to auto-learn modes */ 2780 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2781 2782 /* validate LRO ring */ 2783 ring_ctrl_dw2 |= MTK_RING_VLD; 2784 2785 /* set AGE timer (unit: 20us) */ 2786 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2787 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2788 2789 /* set max AGG timer (unit: 20us) */ 2790 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2791 2792 /* set max LRO AGG count */ 2793 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2794 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2795 2796 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2797 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2798 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2799 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2800 } 2801 2802 /* IPv4 checksum update enable */ 2803 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2804 2805 /* switch priority comparison to packet count mode */ 2806 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2807 2808 /* bandwidth threshold setting */ 2809 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2810 2811 /* auto-learn score delta setting */ 2812 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2813 2814 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2815 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2816 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2817 2818 /* set HW LRO mode & the max aggregation count for rx packets */ 2819 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2820 2821 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2822 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2823 2824 /* enable HW LRO */ 2825 lro_ctrl_dw0 |= MTK_LRO_EN; 2826 2827 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2828 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2829 2830 return 0; 2831} 2832 2833static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2834{ 2835 int i; 2836 u32 val; 2837 2838 /* relinquish lro rings, flush aggregated packets */ 2839 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2840 2841 /* wait for relinquishments done */ 2842 for (i = 0; i < 10; i++) { 2843 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2844 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2845 msleep(20); 2846 continue; 2847 } 2848 break; 2849 } 2850 2851 /* invalidate lro rings */ 2852 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2853 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2854 2855 /* disable HW LRO */ 2856 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2857} 2858 2859static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2860{ 2861 u32 reg_val; 2862 2863 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2864 2865 /* invalidate the IP setting */ 2866 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2867 2868 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2869 2870 /* validate the IP setting */ 2871 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2872} 2873 2874static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2875{ 2876 u32 reg_val; 2877 2878 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2879 2880 /* invalidate the IP setting */ 2881 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2882 2883 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2884} 2885 2886static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2887{ 2888 int cnt = 0; 2889 int i; 2890 2891 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2892 if (mac->hwlro_ip[i]) 2893 cnt++; 2894 } 2895 2896 return cnt; 2897} 2898 2899static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2900 struct ethtool_rxnfc *cmd) 2901{ 2902 struct ethtool_rx_flow_spec *fsp = 2903 (struct ethtool_rx_flow_spec *)&cmd->fs; 2904 struct mtk_mac *mac = netdev_priv(dev); 2905 struct mtk_eth *eth = mac->hw; 2906 int hwlro_idx; 2907 2908 if ((fsp->flow_type != TCP_V4_FLOW) || 2909 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2910 (fsp->location > 1)) 2911 return -EINVAL; 2912 2913 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2914 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2915 2916 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2917 2918 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2919 2920 return 0; 2921} 2922 2923static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2924 struct ethtool_rxnfc *cmd) 2925{ 2926 struct ethtool_rx_flow_spec *fsp = 2927 (struct ethtool_rx_flow_spec *)&cmd->fs; 2928 struct mtk_mac *mac = netdev_priv(dev); 2929 struct mtk_eth *eth = mac->hw; 2930 int hwlro_idx; 2931 2932 if (fsp->location > 1) 2933 return -EINVAL; 2934 2935 mac->hwlro_ip[fsp->location] = 0; 2936 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2937 2938 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2939 2940 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2941 2942 return 0; 2943} 2944 2945static void mtk_hwlro_netdev_disable(struct net_device *dev) 2946{ 2947 struct mtk_mac *mac = netdev_priv(dev); 2948 struct mtk_eth *eth = mac->hw; 2949 int i, hwlro_idx; 2950 2951 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2952 mac->hwlro_ip[i] = 0; 2953 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2954 2955 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2956 } 2957 2958 mac->hwlro_ip_cnt = 0; 2959} 2960 2961static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2962 struct ethtool_rxnfc *cmd) 2963{ 2964 struct mtk_mac *mac = netdev_priv(dev); 2965 struct ethtool_rx_flow_spec *fsp = 2966 (struct ethtool_rx_flow_spec *)&cmd->fs; 2967 2968 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2969 return -EINVAL; 2970 2971 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2972 fsp->flow_type = TCP_V4_FLOW; 2973 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2974 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2975 2976 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2977 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2978 fsp->h_u.tcp_ip4_spec.psrc = 0; 2979 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2980 fsp->h_u.tcp_ip4_spec.pdst = 0; 2981 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2982 fsp->h_u.tcp_ip4_spec.tos = 0; 2983 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2984 2985 return 0; 2986} 2987 2988static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2989 struct ethtool_rxnfc *cmd, 2990 u32 *rule_locs) 2991{ 2992 struct mtk_mac *mac = netdev_priv(dev); 2993 int cnt = 0; 2994 int i; 2995 2996 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2997 if (cnt == cmd->rule_cnt) 2998 return -EMSGSIZE; 2999 3000 if (mac->hwlro_ip[i]) { 3001 rule_locs[cnt] = i; 3002 cnt++; 3003 } 3004 } 3005 3006 cmd->rule_cnt = cnt; 3007 3008 return 0; 3009} 3010 3011static netdev_features_t mtk_fix_features(struct net_device *dev, 3012 netdev_features_t features) 3013{ 3014 if (!(features & NETIF_F_LRO)) { 3015 struct mtk_mac *mac = netdev_priv(dev); 3016 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 3017 3018 if (ip_cnt) { 3019 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 3020 3021 features |= NETIF_F_LRO; 3022 } 3023 } 3024 3025 return features; 3026} 3027 3028static int mtk_set_features(struct net_device *dev, netdev_features_t features) 3029{ 3030 netdev_features_t diff = dev->features ^ features; 3031 3032 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 3033 mtk_hwlro_netdev_disable(dev); 3034 3035 return 0; 3036} 3037 3038/* wait for DMA to finish whatever it is doing before we start using it again */ 3039static int mtk_dma_busy_wait(struct mtk_eth *eth) 3040{ 3041 unsigned int reg; 3042 int ret; 3043 u32 val; 3044 3045 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3046 reg = eth->soc->reg_map->qdma.glo_cfg; 3047 else 3048 reg = eth->soc->reg_map->pdma.glo_cfg; 3049 3050 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3051 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3052 5, MTK_DMA_BUSY_TIMEOUT_US); 3053 if (ret) 3054 dev_err(eth->dev, "DMA init timeout\n"); 3055 3056 return ret; 3057} 3058 3059static int mtk_dma_init(struct mtk_eth *eth) 3060{ 3061 int err; 3062 u32 i; 3063 3064 if (mtk_dma_busy_wait(eth)) 3065 return -EBUSY; 3066 3067 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3068 /* QDMA needs scratch memory for internal reordering of the 3069 * descriptors 3070 */ 3071 err = mtk_init_fq_dma(eth); 3072 if (err) 3073 return err; 3074 } 3075 3076 err = mtk_tx_alloc(eth); 3077 if (err) 3078 return err; 3079 3080 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3081 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3082 if (err) 3083 return err; 3084 } 3085 3086 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3087 if (err) 3088 return err; 3089 3090 if (eth->hwlro) { 3091 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3092 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3093 if (err) 3094 return err; 3095 } 3096 err = mtk_hwlro_rx_init(eth); 3097 if (err) 3098 return err; 3099 } 3100 3101 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3102 /* Enable random early drop and set drop threshold 3103 * automatically 3104 */ 3105 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3106 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3107 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3108 } 3109 3110 return 0; 3111} 3112 3113static void mtk_dma_free(struct mtk_eth *eth) 3114{ 3115 const struct mtk_soc_data *soc = eth->soc; 3116 int i; 3117 3118 for (i = 0; i < MTK_MAX_DEVS; i++) 3119 if (eth->netdev[i]) 3120 netdev_reset_queue(eth->netdev[i]); 3121 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { 3122 dma_free_coherent(eth->dma_dev, 3123 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3124 eth->scratch_ring, eth->phy_scratch_ring); 3125 eth->scratch_ring = NULL; 3126 eth->phy_scratch_ring = 0; 3127 } 3128 mtk_tx_clean(eth); 3129 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); 3130 mtk_rx_clean(eth, ð->rx_ring_qdma, false); 3131 3132 if (eth->hwlro) { 3133 mtk_hwlro_rx_uninit(eth); 3134 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3135 mtk_rx_clean(eth, ð->rx_ring[i], false); 3136 } 3137 3138 kfree(eth->scratch_head); 3139} 3140 3141static bool mtk_hw_reset_check(struct mtk_eth *eth) 3142{ 3143 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3144 3145 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3146 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3147 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3148} 3149 3150static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3151{ 3152 struct mtk_mac *mac = netdev_priv(dev); 3153 struct mtk_eth *eth = mac->hw; 3154 3155 if (test_bit(MTK_RESETTING, ð->state)) 3156 return; 3157 3158 if (!mtk_hw_reset_check(eth)) 3159 return; 3160 3161 eth->netdev[mac->id]->stats.tx_errors++; 3162 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3163 3164 schedule_work(ð->pending_work); 3165} 3166 3167static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3168{ 3169 struct mtk_eth *eth = _eth; 3170 3171 eth->rx_events++; 3172 if (likely(napi_schedule_prep(ð->rx_napi))) { 3173 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3174 __napi_schedule(ð->rx_napi); 3175 } 3176 3177 return IRQ_HANDLED; 3178} 3179 3180static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3181{ 3182 struct mtk_eth *eth = _eth; 3183 3184 eth->tx_events++; 3185 if (likely(napi_schedule_prep(ð->tx_napi))) { 3186 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3187 __napi_schedule(ð->tx_napi); 3188 } 3189 3190 return IRQ_HANDLED; 3191} 3192 3193static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3194{ 3195 struct mtk_eth *eth = _eth; 3196 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3197 3198 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3199 eth->soc->txrx.rx_irq_done_mask) { 3200 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3201 eth->soc->txrx.rx_irq_done_mask) 3202 mtk_handle_irq_rx(irq, _eth); 3203 } 3204 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3205 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3206 mtk_handle_irq_tx(irq, _eth); 3207 } 3208 3209 return IRQ_HANDLED; 3210} 3211 3212#ifdef CONFIG_NET_POLL_CONTROLLER 3213static void mtk_poll_controller(struct net_device *dev) 3214{ 3215 struct mtk_mac *mac = netdev_priv(dev); 3216 struct mtk_eth *eth = mac->hw; 3217 3218 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3219 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3220 mtk_handle_irq_rx(eth->irq[2], dev); 3221 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3222 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3223} 3224#endif 3225 3226static int mtk_start_dma(struct mtk_eth *eth) 3227{ 3228 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3229 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3230 int err; 3231 3232 err = mtk_dma_init(eth); 3233 if (err) { 3234 mtk_dma_free(eth); 3235 return err; 3236 } 3237 3238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3239 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3240 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3241 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3242 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3243 3244 if (mtk_is_netsys_v2_or_greater(eth)) 3245 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3246 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3247 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3248 else 3249 val |= MTK_RX_BT_32DWORDS; 3250 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3251 3252 mtk_w32(eth, 3253 MTK_RX_DMA_EN | rx_2b_offset | 3254 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3255 reg_map->pdma.glo_cfg); 3256 } else { 3257 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3258 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3259 reg_map->pdma.glo_cfg); 3260 } 3261 3262 return 0; 3263} 3264 3265static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3266{ 3267 int i; 3268 3269 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3270 return; 3271 3272 for (i = 0; i < MTK_MAX_DEVS; i++) { 3273 u32 val; 3274 3275 if (!eth->netdev[i]) 3276 continue; 3277 3278 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3279 3280 /* default setup the forward port to send frame to PDMA */ 3281 val &= ~0xffff; 3282 3283 /* Enable RX checksum */ 3284 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3285 3286 val |= config; 3287 3288 if (netdev_uses_dsa(eth->netdev[i])) 3289 val |= MTK_GDMA_SPECIAL_TAG; 3290 3291 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3292 } 3293 /* Reset and enable PSE */ 3294 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3295 mtk_w32(eth, 0, MTK_RST_GL); 3296} 3297 3298 3299static bool mtk_uses_dsa(struct net_device *dev) 3300{ 3301#if IS_ENABLED(CONFIG_NET_DSA) 3302 return netdev_uses_dsa(dev) && 3303 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3304#else 3305 return false; 3306#endif 3307} 3308 3309static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3310{ 3311 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3312 struct mtk_eth *eth = mac->hw; 3313 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3314 struct ethtool_link_ksettings s; 3315 struct net_device *ldev; 3316 struct list_head *iter; 3317 struct dsa_port *dp; 3318 3319 if (event != NETDEV_CHANGE) 3320 return NOTIFY_DONE; 3321 3322 netdev_for_each_lower_dev(dev, ldev, iter) { 3323 if (netdev_priv(ldev) == mac) 3324 goto found; 3325 } 3326 3327 return NOTIFY_DONE; 3328 3329found: 3330 if (!dsa_slave_dev_check(dev)) 3331 return NOTIFY_DONE; 3332 3333 if (__ethtool_get_link_ksettings(dev, &s)) 3334 return NOTIFY_DONE; 3335 3336 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3337 return NOTIFY_DONE; 3338 3339 dp = dsa_port_from_netdev(dev); 3340 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3341 return NOTIFY_DONE; 3342 3343 if (mac->speed > 0 && mac->speed <= s.base.speed) 3344 s.base.speed = 0; 3345 3346 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3347 3348 return NOTIFY_DONE; 3349} 3350 3351static int mtk_open(struct net_device *dev) 3352{ 3353 struct mtk_mac *mac = netdev_priv(dev); 3354 struct mtk_eth *eth = mac->hw; 3355 int i, err; 3356 3357 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3358 if (err) { 3359 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3360 err); 3361 return err; 3362 } 3363 3364 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3365 if (!refcount_read(ð->dma_refcnt)) { 3366 const struct mtk_soc_data *soc = eth->soc; 3367 u32 gdm_config; 3368 int i; 3369 3370 err = mtk_start_dma(eth); 3371 if (err) { 3372 phylink_disconnect_phy(mac->phylink); 3373 return err; 3374 } 3375 3376 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3377 mtk_ppe_start(eth->ppe[i]); 3378 3379 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3380 : MTK_GDMA_TO_PDMA; 3381 mtk_gdm_config(eth, gdm_config); 3382 3383 napi_enable(ð->tx_napi); 3384 napi_enable(ð->rx_napi); 3385 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3386 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3387 refcount_set(ð->dma_refcnt, 1); 3388 } 3389 else 3390 refcount_inc(ð->dma_refcnt); 3391 3392 phylink_start(mac->phylink); 3393 netif_tx_start_all_queues(dev); 3394 3395 if (mtk_is_netsys_v2_or_greater(eth)) 3396 return 0; 3397 3398 if (mtk_uses_dsa(dev) && !eth->prog) { 3399 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3400 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3401 3402 if (md_dst) 3403 continue; 3404 3405 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3406 GFP_KERNEL); 3407 if (!md_dst) 3408 return -ENOMEM; 3409 3410 md_dst->u.port_info.port_id = i; 3411 eth->dsa_meta[i] = md_dst; 3412 } 3413 } else { 3414 /* Hardware DSA untagging and VLAN RX offloading need to be 3415 * disabled if at least one MAC does not use DSA. 3416 */ 3417 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3418 3419 val &= ~MTK_CDMP_STAG_EN; 3420 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3421 3422 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3423 } 3424 3425 return 0; 3426} 3427 3428static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3429{ 3430 u32 val; 3431 int i; 3432 3433 /* stop the dma engine */ 3434 spin_lock_bh(ð->page_lock); 3435 val = mtk_r32(eth, glo_cfg); 3436 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3437 glo_cfg); 3438 spin_unlock_bh(ð->page_lock); 3439 3440 /* wait for dma stop */ 3441 for (i = 0; i < 10; i++) { 3442 val = mtk_r32(eth, glo_cfg); 3443 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3444 msleep(20); 3445 continue; 3446 } 3447 break; 3448 } 3449} 3450 3451static int mtk_stop(struct net_device *dev) 3452{ 3453 struct mtk_mac *mac = netdev_priv(dev); 3454 struct mtk_eth *eth = mac->hw; 3455 int i; 3456 3457 phylink_stop(mac->phylink); 3458 3459 netif_tx_disable(dev); 3460 3461 phylink_disconnect_phy(mac->phylink); 3462 3463 /* only shutdown DMA if this is the last user */ 3464 if (!refcount_dec_and_test(ð->dma_refcnt)) 3465 return 0; 3466 3467 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3468 3469 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3470 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3471 napi_disable(ð->tx_napi); 3472 napi_disable(ð->rx_napi); 3473 3474 cancel_work_sync(ð->rx_dim.work); 3475 cancel_work_sync(ð->tx_dim.work); 3476 3477 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3478 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3479 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3480 3481 mtk_dma_free(eth); 3482 3483 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3484 mtk_ppe_stop(eth->ppe[i]); 3485 3486 return 0; 3487} 3488 3489static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3490 struct netlink_ext_ack *extack) 3491{ 3492 struct mtk_mac *mac = netdev_priv(dev); 3493 struct mtk_eth *eth = mac->hw; 3494 struct bpf_prog *old_prog; 3495 bool need_update; 3496 3497 if (eth->hwlro) { 3498 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3499 return -EOPNOTSUPP; 3500 } 3501 3502 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3503 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3504 return -EOPNOTSUPP; 3505 } 3506 3507 need_update = !!eth->prog != !!prog; 3508 if (netif_running(dev) && need_update) 3509 mtk_stop(dev); 3510 3511 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3512 if (old_prog) 3513 bpf_prog_put(old_prog); 3514 3515 if (netif_running(dev) && need_update) 3516 return mtk_open(dev); 3517 3518 return 0; 3519} 3520 3521static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3522{ 3523 switch (xdp->command) { 3524 case XDP_SETUP_PROG: 3525 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3526 default: 3527 return -EINVAL; 3528 } 3529} 3530 3531static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3532{ 3533 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3534 reset_bits, 3535 reset_bits); 3536 3537 usleep_range(1000, 1100); 3538 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3539 reset_bits, 3540 ~reset_bits); 3541 mdelay(10); 3542} 3543 3544static void mtk_clk_disable(struct mtk_eth *eth) 3545{ 3546 int clk; 3547 3548 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3549 clk_disable_unprepare(eth->clks[clk]); 3550} 3551 3552static int mtk_clk_enable(struct mtk_eth *eth) 3553{ 3554 int clk, ret; 3555 3556 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3557 ret = clk_prepare_enable(eth->clks[clk]); 3558 if (ret) 3559 goto err_disable_clks; 3560 } 3561 3562 return 0; 3563 3564err_disable_clks: 3565 while (--clk >= 0) 3566 clk_disable_unprepare(eth->clks[clk]); 3567 3568 return ret; 3569} 3570 3571static void mtk_dim_rx(struct work_struct *work) 3572{ 3573 struct dim *dim = container_of(work, struct dim, work); 3574 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3575 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3576 struct dim_cq_moder cur_profile; 3577 u32 val, cur; 3578 3579 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3580 dim->profile_ix); 3581 spin_lock_bh(ð->dim_lock); 3582 3583 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3584 val &= MTK_PDMA_DELAY_TX_MASK; 3585 val |= MTK_PDMA_DELAY_RX_EN; 3586 3587 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3588 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3589 3590 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3591 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3592 3593 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3594 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3595 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3596 3597 spin_unlock_bh(ð->dim_lock); 3598 3599 dim->state = DIM_START_MEASURE; 3600} 3601 3602static void mtk_dim_tx(struct work_struct *work) 3603{ 3604 struct dim *dim = container_of(work, struct dim, work); 3605 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3606 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3607 struct dim_cq_moder cur_profile; 3608 u32 val, cur; 3609 3610 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3611 dim->profile_ix); 3612 spin_lock_bh(ð->dim_lock); 3613 3614 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3615 val &= MTK_PDMA_DELAY_RX_MASK; 3616 val |= MTK_PDMA_DELAY_TX_EN; 3617 3618 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3619 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3620 3621 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3622 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3623 3624 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3625 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3626 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3627 3628 spin_unlock_bh(ð->dim_lock); 3629 3630 dim->state = DIM_START_MEASURE; 3631} 3632 3633static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3634{ 3635 struct mtk_eth *eth = mac->hw; 3636 u32 mcr_cur, mcr_new; 3637 3638 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3639 return; 3640 3641 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3642 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3643 3644 if (val <= 1518) 3645 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3646 else if (val <= 1536) 3647 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3648 else if (val <= 1552) 3649 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3650 else 3651 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3652 3653 if (mcr_new != mcr_cur) 3654 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3655} 3656 3657static void mtk_hw_reset(struct mtk_eth *eth) 3658{ 3659 u32 val; 3660 3661 if (mtk_is_netsys_v2_or_greater(eth)) 3662 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3663 3664 if (mtk_is_netsys_v3_or_greater(eth)) { 3665 val = RSTCTRL_PPE0_V3; 3666 3667 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3668 val |= RSTCTRL_PPE1_V3; 3669 3670 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3671 val |= RSTCTRL_PPE2; 3672 3673 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3674 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3675 val = RSTCTRL_PPE0_V2; 3676 3677 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3678 val |= RSTCTRL_PPE1; 3679 } else { 3680 val = RSTCTRL_PPE0; 3681 } 3682 3683 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3684 3685 if (mtk_is_netsys_v3_or_greater(eth)) 3686 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3687 0x6f8ff); 3688 else if (mtk_is_netsys_v2_or_greater(eth)) 3689 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3690 0x3ffffff); 3691} 3692 3693static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3694{ 3695 u32 val; 3696 3697 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3698 return val; 3699} 3700 3701static void mtk_hw_warm_reset(struct mtk_eth *eth) 3702{ 3703 u32 rst_mask, val; 3704 3705 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3706 RSTCTRL_FE); 3707 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3708 val & RSTCTRL_FE, 1, 1000)) { 3709 dev_err(eth->dev, "warm reset failed\n"); 3710 mtk_hw_reset(eth); 3711 return; 3712 } 3713 3714 if (mtk_is_netsys_v3_or_greater(eth)) { 3715 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3; 3716 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3717 rst_mask |= RSTCTRL_PPE1_V3; 3718 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 3719 rst_mask |= RSTCTRL_PPE2; 3720 3721 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2; 3722 } else if (mtk_is_netsys_v2_or_greater(eth)) { 3723 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3724 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3725 rst_mask |= RSTCTRL_PPE1; 3726 } else { 3727 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3728 } 3729 3730 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3731 3732 udelay(1); 3733 val = mtk_hw_reset_read(eth); 3734 if (!(val & rst_mask)) 3735 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3736 val, rst_mask); 3737 3738 rst_mask |= RSTCTRL_FE; 3739 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3740 3741 udelay(1); 3742 val = mtk_hw_reset_read(eth); 3743 if (val & rst_mask) 3744 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3745 val, rst_mask); 3746} 3747 3748static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3749{ 3750 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3751 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3752 bool oq_hang, cdm1_busy, adma_busy; 3753 bool wtx_busy, cdm_full, oq_free; 3754 u32 wdidx, val, gdm1_fc, gdm2_fc; 3755 bool qfsm_hang, qfwd_hang; 3756 bool ret = false; 3757 3758 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3759 return false; 3760 3761 /* WDMA sanity checks */ 3762 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3763 3764 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3765 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3766 3767 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3768 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3769 3770 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3771 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3772 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3773 3774 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3775 if (++eth->reset.wdma_hang_count > 2) { 3776 eth->reset.wdma_hang_count = 0; 3777 ret = true; 3778 } 3779 goto out; 3780 } 3781 3782 /* QDMA sanity checks */ 3783 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3784 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3785 3786 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3787 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3788 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3789 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3790 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3791 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3792 3793 if (qfsm_hang && qfwd_hang && 3794 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3795 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3796 if (++eth->reset.qdma_hang_count > 2) { 3797 eth->reset.qdma_hang_count = 0; 3798 ret = true; 3799 } 3800 goto out; 3801 } 3802 3803 /* ADMA sanity checks */ 3804 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3805 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3806 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3807 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3808 3809 if (oq_hang && cdm1_busy && adma_busy) { 3810 if (++eth->reset.adma_hang_count > 2) { 3811 eth->reset.adma_hang_count = 0; 3812 ret = true; 3813 } 3814 goto out; 3815 } 3816 3817 eth->reset.wdma_hang_count = 0; 3818 eth->reset.qdma_hang_count = 0; 3819 eth->reset.adma_hang_count = 0; 3820out: 3821 eth->reset.wdidx = wdidx; 3822 3823 return ret; 3824} 3825 3826static void mtk_hw_reset_monitor_work(struct work_struct *work) 3827{ 3828 struct delayed_work *del_work = to_delayed_work(work); 3829 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3830 reset.monitor_work); 3831 3832 if (test_bit(MTK_RESETTING, ð->state)) 3833 goto out; 3834 3835 /* DMA stuck checks */ 3836 if (mtk_hw_check_dma_hang(eth)) 3837 schedule_work(ð->pending_work); 3838 3839out: 3840 schedule_delayed_work(ð->reset.monitor_work, 3841 MTK_DMA_MONITOR_TIMEOUT); 3842} 3843 3844static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3845{ 3846 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3847 ETHSYS_DMA_AG_MAP_PPE; 3848 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3849 int i, val, ret; 3850 3851 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3852 return 0; 3853 3854 if (!reset) { 3855 pm_runtime_enable(eth->dev); 3856 pm_runtime_get_sync(eth->dev); 3857 3858 ret = mtk_clk_enable(eth); 3859 if (ret) 3860 goto err_disable_pm; 3861 } 3862 3863 if (eth->ethsys) 3864 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3865 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3866 3867 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3868 ret = device_reset(eth->dev); 3869 if (ret) { 3870 dev_err(eth->dev, "MAC reset failed!\n"); 3871 goto err_disable_pm; 3872 } 3873 3874 /* set interrupt delays based on current Net DIM sample */ 3875 mtk_dim_rx(ð->rx_dim.work); 3876 mtk_dim_tx(ð->tx_dim.work); 3877 3878 /* disable delay and normal interrupt */ 3879 mtk_tx_irq_disable(eth, ~0); 3880 mtk_rx_irq_disable(eth, ~0); 3881 3882 return 0; 3883 } 3884 3885 msleep(100); 3886 3887 if (reset) 3888 mtk_hw_warm_reset(eth); 3889 else 3890 mtk_hw_reset(eth); 3891 3892 if (mtk_is_netsys_v2_or_greater(eth)) { 3893 /* Set FE to PDMAv2 if necessary */ 3894 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3895 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3896 } 3897 3898 if (eth->pctl) { 3899 /* Set GE2 driving and slew rate */ 3900 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3901 3902 /* set GE2 TDSEL */ 3903 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3904 3905 /* set GE2 TUNE */ 3906 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3907 } 3908 3909 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3910 * up with the more appropriate value when mtk_mac_config call is being 3911 * invoked. 3912 */ 3913 for (i = 0; i < MTK_MAX_DEVS; i++) { 3914 struct net_device *dev = eth->netdev[i]; 3915 3916 if (!dev) 3917 continue; 3918 3919 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3920 mtk_set_mcr_max_rx(netdev_priv(dev), 3921 dev->mtu + MTK_RX_ETH_HLEN); 3922 } 3923 3924 /* Indicates CDM to parse the MTK special tag from CPU 3925 * which also is working out for untag packets. 3926 */ 3927 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3928 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3929 if (mtk_is_netsys_v1(eth)) { 3930 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3931 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3932 3933 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3934 } 3935 3936 /* set interrupt delays based on current Net DIM sample */ 3937 mtk_dim_rx(ð->rx_dim.work); 3938 mtk_dim_tx(ð->tx_dim.work); 3939 3940 /* disable delay and normal interrupt */ 3941 mtk_tx_irq_disable(eth, ~0); 3942 mtk_rx_irq_disable(eth, ~0); 3943 3944 /* FE int grouping */ 3945 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3946 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3947 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3948 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3949 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3950 3951 if (mtk_is_netsys_v3_or_greater(eth)) { 3952 /* PSE should not drop port1, port8 and port9 packets */ 3953 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 3954 3955 /* GDM and CDM Threshold */ 3956 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 3957 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 3958 3959 /* Disable GDM1 RX CRC stripping */ 3960 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 3961 3962 /* PSE GDM3 MIB counter has incorrect hw default values, 3963 * so the driver ought to read clear the values beforehand 3964 * in case ethtool retrieve wrong mib values. 3965 */ 3966 for (i = 0; i < 0x80; i += 0x4) 3967 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 3968 } else if (!mtk_is_netsys_v1(eth)) { 3969 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3970 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3971 3972 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3973 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3974 3975 /* PSE Free Queue Flow Control */ 3976 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3977 3978 /* PSE config input queue threshold */ 3979 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3980 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3981 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3982 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3983 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3984 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3985 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3986 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3987 3988 /* PSE config output queue threshold */ 3989 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3990 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3991 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3992 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3993 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3994 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3995 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3996 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3997 3998 /* GDM and CDM Threshold */ 3999 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 4000 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 4001 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 4002 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 4003 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 4004 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 4005 } 4006 4007 return 0; 4008 4009err_disable_pm: 4010 if (!reset) { 4011 pm_runtime_put_sync(eth->dev); 4012 pm_runtime_disable(eth->dev); 4013 } 4014 4015 return ret; 4016} 4017 4018static int mtk_hw_deinit(struct mtk_eth *eth) 4019{ 4020 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 4021 return 0; 4022 4023 mtk_clk_disable(eth); 4024 4025 pm_runtime_put_sync(eth->dev); 4026 pm_runtime_disable(eth->dev); 4027 4028 return 0; 4029} 4030 4031static void mtk_uninit(struct net_device *dev) 4032{ 4033 struct mtk_mac *mac = netdev_priv(dev); 4034 struct mtk_eth *eth = mac->hw; 4035 4036 phylink_disconnect_phy(mac->phylink); 4037 mtk_tx_irq_disable(eth, ~0); 4038 mtk_rx_irq_disable(eth, ~0); 4039} 4040 4041static int mtk_change_mtu(struct net_device *dev, int new_mtu) 4042{ 4043 int length = new_mtu + MTK_RX_ETH_HLEN; 4044 struct mtk_mac *mac = netdev_priv(dev); 4045 struct mtk_eth *eth = mac->hw; 4046 4047 if (rcu_access_pointer(eth->prog) && 4048 length > MTK_PP_MAX_BUF_SIZE) { 4049 netdev_err(dev, "Invalid MTU for XDP mode\n"); 4050 return -EINVAL; 4051 } 4052 4053 mtk_set_mcr_max_rx(mac, length); 4054 dev->mtu = new_mtu; 4055 4056 return 0; 4057} 4058 4059static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4060{ 4061 struct mtk_mac *mac = netdev_priv(dev); 4062 4063 switch (cmd) { 4064 case SIOCGMIIPHY: 4065 case SIOCGMIIREG: 4066 case SIOCSMIIREG: 4067 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 4068 default: 4069 break; 4070 } 4071 4072 return -EOPNOTSUPP; 4073} 4074 4075static void mtk_prepare_for_reset(struct mtk_eth *eth) 4076{ 4077 u32 val; 4078 int i; 4079 4080 /* set FE PPE ports link down */ 4081 for (i = MTK_GMAC1_ID; 4082 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4083 i += 2) { 4084 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4085 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4086 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4087 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4088 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4089 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4090 } 4091 4092 /* adjust PPE configurations to prepare for reset */ 4093 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4094 mtk_ppe_prepare_reset(eth->ppe[i]); 4095 4096 /* disable NETSYS interrupts */ 4097 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4098 4099 /* force link down GMAC */ 4100 for (i = 0; i < 2; i++) { 4101 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4102 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4103 } 4104} 4105 4106static void mtk_pending_work(struct work_struct *work) 4107{ 4108 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4109 unsigned long restart = 0; 4110 u32 val; 4111 int i; 4112 4113 rtnl_lock(); 4114 set_bit(MTK_RESETTING, ð->state); 4115 4116 mtk_prepare_for_reset(eth); 4117 mtk_wed_fe_reset(); 4118 /* Run again reset preliminary configuration in order to avoid any 4119 * possible race during FE reset since it can run releasing RTNL lock. 4120 */ 4121 mtk_prepare_for_reset(eth); 4122 4123 /* stop all devices to make sure that dma is properly shut down */ 4124 for (i = 0; i < MTK_MAX_DEVS; i++) { 4125 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4126 continue; 4127 4128 mtk_stop(eth->netdev[i]); 4129 __set_bit(i, &restart); 4130 } 4131 4132 usleep_range(15000, 16000); 4133 4134 if (eth->dev->pins) 4135 pinctrl_select_state(eth->dev->pins->p, 4136 eth->dev->pins->default_state); 4137 mtk_hw_init(eth, true); 4138 4139 /* restart DMA and enable IRQs */ 4140 for (i = 0; i < MTK_MAX_DEVS; i++) { 4141 if (!eth->netdev[i] || !test_bit(i, &restart)) 4142 continue; 4143 4144 if (mtk_open(eth->netdev[i])) { 4145 netif_alert(eth, ifup, eth->netdev[i], 4146 "Driver up/down cycle failed\n"); 4147 dev_close(eth->netdev[i]); 4148 } 4149 } 4150 4151 /* set FE PPE ports link up */ 4152 for (i = MTK_GMAC1_ID; 4153 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID); 4154 i += 2) { 4155 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT); 4156 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4157 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT); 4158 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) 4159 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT); 4160 4161 mtk_w32(eth, val, MTK_FE_GLO_CFG(i)); 4162 } 4163 4164 clear_bit(MTK_RESETTING, ð->state); 4165 4166 mtk_wed_fe_reset_complete(); 4167 4168 rtnl_unlock(); 4169} 4170 4171static int mtk_free_dev(struct mtk_eth *eth) 4172{ 4173 int i; 4174 4175 for (i = 0; i < MTK_MAX_DEVS; i++) { 4176 if (!eth->netdev[i]) 4177 continue; 4178 free_netdev(eth->netdev[i]); 4179 } 4180 4181 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4182 if (!eth->dsa_meta[i]) 4183 break; 4184 metadata_dst_free(eth->dsa_meta[i]); 4185 } 4186 4187 return 0; 4188} 4189 4190static int mtk_unreg_dev(struct mtk_eth *eth) 4191{ 4192 int i; 4193 4194 for (i = 0; i < MTK_MAX_DEVS; i++) { 4195 struct mtk_mac *mac; 4196 if (!eth->netdev[i]) 4197 continue; 4198 mac = netdev_priv(eth->netdev[i]); 4199 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4200 unregister_netdevice_notifier(&mac->device_notifier); 4201 unregister_netdev(eth->netdev[i]); 4202 } 4203 4204 return 0; 4205} 4206 4207static void mtk_sgmii_destroy(struct mtk_eth *eth) 4208{ 4209 int i; 4210 4211 for (i = 0; i < MTK_MAX_DEVS; i++) 4212 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4213} 4214 4215static int mtk_cleanup(struct mtk_eth *eth) 4216{ 4217 mtk_sgmii_destroy(eth); 4218 mtk_unreg_dev(eth); 4219 mtk_free_dev(eth); 4220 cancel_work_sync(ð->pending_work); 4221 cancel_delayed_work_sync(ð->reset.monitor_work); 4222 4223 return 0; 4224} 4225 4226static int mtk_get_link_ksettings(struct net_device *ndev, 4227 struct ethtool_link_ksettings *cmd) 4228{ 4229 struct mtk_mac *mac = netdev_priv(ndev); 4230 4231 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4232 return -EBUSY; 4233 4234 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4235} 4236 4237static int mtk_set_link_ksettings(struct net_device *ndev, 4238 const struct ethtool_link_ksettings *cmd) 4239{ 4240 struct mtk_mac *mac = netdev_priv(ndev); 4241 4242 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4243 return -EBUSY; 4244 4245 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4246} 4247 4248static void mtk_get_drvinfo(struct net_device *dev, 4249 struct ethtool_drvinfo *info) 4250{ 4251 struct mtk_mac *mac = netdev_priv(dev); 4252 4253 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4254 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4255 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4256} 4257 4258static u32 mtk_get_msglevel(struct net_device *dev) 4259{ 4260 struct mtk_mac *mac = netdev_priv(dev); 4261 4262 return mac->hw->msg_enable; 4263} 4264 4265static void mtk_set_msglevel(struct net_device *dev, u32 value) 4266{ 4267 struct mtk_mac *mac = netdev_priv(dev); 4268 4269 mac->hw->msg_enable = value; 4270} 4271 4272static int mtk_nway_reset(struct net_device *dev) 4273{ 4274 struct mtk_mac *mac = netdev_priv(dev); 4275 4276 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4277 return -EBUSY; 4278 4279 if (!mac->phylink) 4280 return -ENOTSUPP; 4281 4282 return phylink_ethtool_nway_reset(mac->phylink); 4283} 4284 4285static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4286{ 4287 int i; 4288 4289 switch (stringset) { 4290 case ETH_SS_STATS: { 4291 struct mtk_mac *mac = netdev_priv(dev); 4292 4293 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4294 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4295 data += ETH_GSTRING_LEN; 4296 } 4297 if (mtk_page_pool_enabled(mac->hw)) 4298 page_pool_ethtool_stats_get_strings(data); 4299 break; 4300 } 4301 default: 4302 break; 4303 } 4304} 4305 4306static int mtk_get_sset_count(struct net_device *dev, int sset) 4307{ 4308 switch (sset) { 4309 case ETH_SS_STATS: { 4310 int count = ARRAY_SIZE(mtk_ethtool_stats); 4311 struct mtk_mac *mac = netdev_priv(dev); 4312 4313 if (mtk_page_pool_enabled(mac->hw)) 4314 count += page_pool_ethtool_stats_get_count(); 4315 return count; 4316 } 4317 default: 4318 return -EOPNOTSUPP; 4319 } 4320} 4321 4322static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4323{ 4324 struct page_pool_stats stats = {}; 4325 int i; 4326 4327 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4328 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4329 4330 if (!ring->page_pool) 4331 continue; 4332 4333 page_pool_get_stats(ring->page_pool, &stats); 4334 } 4335 page_pool_ethtool_stats_get(data, &stats); 4336} 4337 4338static void mtk_get_ethtool_stats(struct net_device *dev, 4339 struct ethtool_stats *stats, u64 *data) 4340{ 4341 struct mtk_mac *mac = netdev_priv(dev); 4342 struct mtk_hw_stats *hwstats = mac->hw_stats; 4343 u64 *data_src, *data_dst; 4344 unsigned int start; 4345 int i; 4346 4347 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4348 return; 4349 4350 if (netif_running(dev) && netif_device_present(dev)) { 4351 if (spin_trylock_bh(&hwstats->stats_lock)) { 4352 mtk_stats_update_mac(mac); 4353 spin_unlock_bh(&hwstats->stats_lock); 4354 } 4355 } 4356 4357 data_src = (u64 *)hwstats; 4358 4359 do { 4360 data_dst = data; 4361 start = u64_stats_fetch_begin(&hwstats->syncp); 4362 4363 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4364 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4365 if (mtk_page_pool_enabled(mac->hw)) 4366 mtk_ethtool_pp_stats(mac->hw, data_dst); 4367 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4368} 4369 4370static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4371 u32 *rule_locs) 4372{ 4373 int ret = -EOPNOTSUPP; 4374 4375 switch (cmd->cmd) { 4376 case ETHTOOL_GRXRINGS: 4377 if (dev->hw_features & NETIF_F_LRO) { 4378 cmd->data = MTK_MAX_RX_RING_NUM; 4379 ret = 0; 4380 } 4381 break; 4382 case ETHTOOL_GRXCLSRLCNT: 4383 if (dev->hw_features & NETIF_F_LRO) { 4384 struct mtk_mac *mac = netdev_priv(dev); 4385 4386 cmd->rule_cnt = mac->hwlro_ip_cnt; 4387 ret = 0; 4388 } 4389 break; 4390 case ETHTOOL_GRXCLSRULE: 4391 if (dev->hw_features & NETIF_F_LRO) 4392 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4393 break; 4394 case ETHTOOL_GRXCLSRLALL: 4395 if (dev->hw_features & NETIF_F_LRO) 4396 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4397 rule_locs); 4398 break; 4399 default: 4400 break; 4401 } 4402 4403 return ret; 4404} 4405 4406static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4407{ 4408 int ret = -EOPNOTSUPP; 4409 4410 switch (cmd->cmd) { 4411 case ETHTOOL_SRXCLSRLINS: 4412 if (dev->hw_features & NETIF_F_LRO) 4413 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4414 break; 4415 case ETHTOOL_SRXCLSRLDEL: 4416 if (dev->hw_features & NETIF_F_LRO) 4417 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4418 break; 4419 default: 4420 break; 4421 } 4422 4423 return ret; 4424} 4425 4426static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4427 struct net_device *sb_dev) 4428{ 4429 struct mtk_mac *mac = netdev_priv(dev); 4430 unsigned int queue = 0; 4431 4432 if (netdev_uses_dsa(dev)) 4433 queue = skb_get_queue_mapping(skb) + 3; 4434 else 4435 queue = mac->id; 4436 4437 if (queue >= dev->num_tx_queues) 4438 queue = 0; 4439 4440 return queue; 4441} 4442 4443static const struct ethtool_ops mtk_ethtool_ops = { 4444 .get_link_ksettings = mtk_get_link_ksettings, 4445 .set_link_ksettings = mtk_set_link_ksettings, 4446 .get_drvinfo = mtk_get_drvinfo, 4447 .get_msglevel = mtk_get_msglevel, 4448 .set_msglevel = mtk_set_msglevel, 4449 .nway_reset = mtk_nway_reset, 4450 .get_link = ethtool_op_get_link, 4451 .get_strings = mtk_get_strings, 4452 .get_sset_count = mtk_get_sset_count, 4453 .get_ethtool_stats = mtk_get_ethtool_stats, 4454 .get_rxnfc = mtk_get_rxnfc, 4455 .set_rxnfc = mtk_set_rxnfc, 4456}; 4457 4458static const struct net_device_ops mtk_netdev_ops = { 4459 .ndo_uninit = mtk_uninit, 4460 .ndo_open = mtk_open, 4461 .ndo_stop = mtk_stop, 4462 .ndo_start_xmit = mtk_start_xmit, 4463 .ndo_set_mac_address = mtk_set_mac_address, 4464 .ndo_validate_addr = eth_validate_addr, 4465 .ndo_eth_ioctl = mtk_do_ioctl, 4466 .ndo_change_mtu = mtk_change_mtu, 4467 .ndo_tx_timeout = mtk_tx_timeout, 4468 .ndo_get_stats64 = mtk_get_stats64, 4469 .ndo_fix_features = mtk_fix_features, 4470 .ndo_set_features = mtk_set_features, 4471#ifdef CONFIG_NET_POLL_CONTROLLER 4472 .ndo_poll_controller = mtk_poll_controller, 4473#endif 4474 .ndo_setup_tc = mtk_eth_setup_tc, 4475 .ndo_bpf = mtk_xdp, 4476 .ndo_xdp_xmit = mtk_xdp_xmit, 4477 .ndo_select_queue = mtk_select_queue, 4478}; 4479 4480static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4481{ 4482 const __be32 *_id = of_get_property(np, "reg", NULL); 4483 phy_interface_t phy_mode; 4484 struct phylink *phylink; 4485 struct mtk_mac *mac; 4486 int id, err; 4487 int txqs = 1; 4488 u32 val; 4489 4490 if (!_id) { 4491 dev_err(eth->dev, "missing mac id\n"); 4492 return -EINVAL; 4493 } 4494 4495 id = be32_to_cpup(_id); 4496 if (id >= MTK_MAX_DEVS) { 4497 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4498 return -EINVAL; 4499 } 4500 4501 if (eth->netdev[id]) { 4502 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4503 return -EINVAL; 4504 } 4505 4506 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4507 txqs = MTK_QDMA_NUM_QUEUES; 4508 4509 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4510 if (!eth->netdev[id]) { 4511 dev_err(eth->dev, "alloc_etherdev failed\n"); 4512 return -ENOMEM; 4513 } 4514 mac = netdev_priv(eth->netdev[id]); 4515 eth->mac[id] = mac; 4516 mac->id = id; 4517 mac->hw = eth; 4518 mac->of_node = np; 4519 4520 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4521 if (err == -EPROBE_DEFER) 4522 return err; 4523 4524 if (err) { 4525 /* If the mac address is invalid, use random mac address */ 4526 eth_hw_addr_random(eth->netdev[id]); 4527 dev_err(eth->dev, "generated random MAC address %pM\n", 4528 eth->netdev[id]->dev_addr); 4529 } 4530 4531 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4532 mac->hwlro_ip_cnt = 0; 4533 4534 mac->hw_stats = devm_kzalloc(eth->dev, 4535 sizeof(*mac->hw_stats), 4536 GFP_KERNEL); 4537 if (!mac->hw_stats) { 4538 dev_err(eth->dev, "failed to allocate counter memory\n"); 4539 err = -ENOMEM; 4540 goto free_netdev; 4541 } 4542 spin_lock_init(&mac->hw_stats->stats_lock); 4543 u64_stats_init(&mac->hw_stats->syncp); 4544 4545 if (mtk_is_netsys_v3_or_greater(eth)) 4546 mac->hw_stats->reg_offset = id * 0x80; 4547 else 4548 mac->hw_stats->reg_offset = id * 0x40; 4549 4550 /* phylink create */ 4551 err = of_get_phy_mode(np, &phy_mode); 4552 if (err) { 4553 dev_err(eth->dev, "incorrect phy-mode\n"); 4554 goto free_netdev; 4555 } 4556 4557 /* mac config is not set */ 4558 mac->interface = PHY_INTERFACE_MODE_NA; 4559 mac->speed = SPEED_UNKNOWN; 4560 4561 mac->phylink_config.dev = ð->netdev[id]->dev; 4562 mac->phylink_config.type = PHYLINK_NETDEV; 4563 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4564 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4565 4566 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4567 * in its .mac_config method (since state->speed is not valid there. 4568 * Disable support for MII, GMII and RGMII. 4569 */ 4570 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4571 __set_bit(PHY_INTERFACE_MODE_MII, 4572 mac->phylink_config.supported_interfaces); 4573 __set_bit(PHY_INTERFACE_MODE_GMII, 4574 mac->phylink_config.supported_interfaces); 4575 4576 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4577 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4578 } 4579 4580 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4581 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4582 mac->phylink_config.supported_interfaces); 4583 4584 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4585 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4586 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4587 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4588 if (val & SYSCFG_DRAM_TYPE_DDR2) 4589 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4590 mac->phylink_config.supported_interfaces); 4591 } 4592 4593 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4594 __set_bit(PHY_INTERFACE_MODE_SGMII, 4595 mac->phylink_config.supported_interfaces); 4596 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4597 mac->phylink_config.supported_interfaces); 4598 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4599 mac->phylink_config.supported_interfaces); 4600 } 4601 4602 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4603 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4604 id == MTK_GMAC1_ID) { 4605 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4606 MAC_SYM_PAUSE | 4607 MAC_10000FD; 4608 phy_interface_zero(mac->phylink_config.supported_interfaces); 4609 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4610 mac->phylink_config.supported_interfaces); 4611 } 4612 4613 phylink = phylink_create(&mac->phylink_config, 4614 of_fwnode_handle(mac->of_node), 4615 phy_mode, &mtk_phylink_ops); 4616 if (IS_ERR(phylink)) { 4617 err = PTR_ERR(phylink); 4618 goto free_netdev; 4619 } 4620 4621 mac->phylink = phylink; 4622 4623 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4624 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4625 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4626 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4627 4628 eth->netdev[id]->hw_features = eth->soc->hw_features; 4629 if (eth->hwlro) 4630 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4631 4632 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4633 ~NETIF_F_HW_VLAN_CTAG_TX; 4634 eth->netdev[id]->features |= eth->soc->hw_features; 4635 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4636 4637 eth->netdev[id]->irq = eth->irq[0]; 4638 eth->netdev[id]->dev.of_node = np; 4639 4640 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4641 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4642 else 4643 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4644 4645 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4646 mac->device_notifier.notifier_call = mtk_device_event; 4647 register_netdevice_notifier(&mac->device_notifier); 4648 } 4649 4650 if (mtk_page_pool_enabled(eth)) 4651 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4652 NETDEV_XDP_ACT_REDIRECT | 4653 NETDEV_XDP_ACT_NDO_XMIT | 4654 NETDEV_XDP_ACT_NDO_XMIT_SG; 4655 4656 return 0; 4657 4658free_netdev: 4659 free_netdev(eth->netdev[id]); 4660 return err; 4661} 4662 4663void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4664{ 4665 struct net_device *dev, *tmp; 4666 LIST_HEAD(dev_list); 4667 int i; 4668 4669 rtnl_lock(); 4670 4671 for (i = 0; i < MTK_MAX_DEVS; i++) { 4672 dev = eth->netdev[i]; 4673 4674 if (!dev || !(dev->flags & IFF_UP)) 4675 continue; 4676 4677 list_add_tail(&dev->close_list, &dev_list); 4678 } 4679 4680 dev_close_many(&dev_list, false); 4681 4682 eth->dma_dev = dma_dev; 4683 4684 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4685 list_del_init(&dev->close_list); 4686 dev_open(dev, NULL); 4687 } 4688 4689 rtnl_unlock(); 4690} 4691 4692static int mtk_sgmii_init(struct mtk_eth *eth) 4693{ 4694 struct device_node *np; 4695 struct regmap *regmap; 4696 u32 flags; 4697 int i; 4698 4699 for (i = 0; i < MTK_MAX_DEVS; i++) { 4700 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4701 if (!np) 4702 break; 4703 4704 regmap = syscon_node_to_regmap(np); 4705 flags = 0; 4706 if (of_property_read_bool(np, "mediatek,pnswap")) 4707 flags |= MTK_SGMII_FLAG_PN_SWAP; 4708 4709 of_node_put(np); 4710 4711 if (IS_ERR(regmap)) 4712 return PTR_ERR(regmap); 4713 4714 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4715 eth->soc->ana_rgc3, 4716 flags); 4717 } 4718 4719 return 0; 4720} 4721 4722static int mtk_probe(struct platform_device *pdev) 4723{ 4724 struct resource *res = NULL, *res_sram; 4725 struct device_node *mac_np; 4726 struct mtk_eth *eth; 4727 int err, i; 4728 4729 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4730 if (!eth) 4731 return -ENOMEM; 4732 4733 eth->soc = of_device_get_match_data(&pdev->dev); 4734 4735 eth->dev = &pdev->dev; 4736 eth->dma_dev = &pdev->dev; 4737 eth->base = devm_platform_ioremap_resource(pdev, 0); 4738 if (IS_ERR(eth->base)) 4739 return PTR_ERR(eth->base); 4740 4741 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4742 eth->ip_align = NET_IP_ALIGN; 4743 4744 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4745 /* SRAM is actual memory and supports transparent access just like DRAM. 4746 * Hence we don't require __iomem being set and don't need to use accessor 4747 * functions to read from or write to SRAM. 4748 */ 4749 if (mtk_is_netsys_v3_or_greater(eth)) { 4750 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); 4751 if (IS_ERR(eth->sram_base)) 4752 return PTR_ERR(eth->sram_base); 4753 } else { 4754 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; 4755 } 4756 } 4757 4758 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { 4759 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); 4760 if (!err) 4761 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 4762 4763 if (err) { 4764 dev_err(&pdev->dev, "Wrong DMA config\n"); 4765 return -EINVAL; 4766 } 4767 } 4768 4769 spin_lock_init(ð->page_lock); 4770 spin_lock_init(ð->tx_irq_lock); 4771 spin_lock_init(ð->rx_irq_lock); 4772 spin_lock_init(ð->dim_lock); 4773 4774 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4775 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4776 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4777 4778 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4779 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4780 4781 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4782 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4783 "mediatek,ethsys"); 4784 if (IS_ERR(eth->ethsys)) { 4785 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4786 return PTR_ERR(eth->ethsys); 4787 } 4788 } 4789 4790 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4791 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4792 "mediatek,infracfg"); 4793 if (IS_ERR(eth->infra)) { 4794 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4795 return PTR_ERR(eth->infra); 4796 } 4797 } 4798 4799 if (of_dma_is_coherent(pdev->dev.of_node)) { 4800 struct regmap *cci; 4801 4802 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4803 "cci-control-port"); 4804 /* enable CPU/bus coherency */ 4805 if (!IS_ERR(cci)) 4806 regmap_write(cci, 0, 3); 4807 } 4808 4809 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4810 err = mtk_sgmii_init(eth); 4811 4812 if (err) 4813 return err; 4814 } 4815 4816 if (eth->soc->required_pctl) { 4817 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4818 "mediatek,pctl"); 4819 if (IS_ERR(eth->pctl)) { 4820 dev_err(&pdev->dev, "no pctl regmap found\n"); 4821 err = PTR_ERR(eth->pctl); 4822 goto err_destroy_sgmii; 4823 } 4824 } 4825 4826 if (mtk_is_netsys_v2_or_greater(eth)) { 4827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4828 if (!res) { 4829 err = -EINVAL; 4830 goto err_destroy_sgmii; 4831 } 4832 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { 4833 if (mtk_is_netsys_v3_or_greater(eth)) { 4834 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1); 4835 if (!res_sram) { 4836 err = -EINVAL; 4837 goto err_destroy_sgmii; 4838 } 4839 eth->phy_scratch_ring = res_sram->start; 4840 } else { 4841 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; 4842 } 4843 } 4844 } 4845 4846 if (eth->soc->offload_version) { 4847 for (i = 0;; i++) { 4848 struct device_node *np; 4849 phys_addr_t wdma_phy; 4850 u32 wdma_base; 4851 4852 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4853 break; 4854 4855 np = of_parse_phandle(pdev->dev.of_node, 4856 "mediatek,wed", i); 4857 if (!np) 4858 break; 4859 4860 wdma_base = eth->soc->reg_map->wdma_base[i]; 4861 wdma_phy = res ? res->start + wdma_base : 0; 4862 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4863 wdma_phy, i); 4864 } 4865 } 4866 4867 for (i = 0; i < 3; i++) { 4868 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4869 eth->irq[i] = eth->irq[0]; 4870 else 4871 eth->irq[i] = platform_get_irq(pdev, i); 4872 if (eth->irq[i] < 0) { 4873 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4874 err = -ENXIO; 4875 goto err_wed_exit; 4876 } 4877 } 4878 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4879 eth->clks[i] = devm_clk_get(eth->dev, 4880 mtk_clks_source_name[i]); 4881 if (IS_ERR(eth->clks[i])) { 4882 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4883 err = -EPROBE_DEFER; 4884 goto err_wed_exit; 4885 } 4886 if (eth->soc->required_clks & BIT(i)) { 4887 dev_err(&pdev->dev, "clock %s not found\n", 4888 mtk_clks_source_name[i]); 4889 err = -EINVAL; 4890 goto err_wed_exit; 4891 } 4892 eth->clks[i] = NULL; 4893 } 4894 } 4895 4896 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4897 INIT_WORK(ð->pending_work, mtk_pending_work); 4898 4899 err = mtk_hw_init(eth, false); 4900 if (err) 4901 goto err_wed_exit; 4902 4903 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4904 4905 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4906 if (!of_device_is_compatible(mac_np, 4907 "mediatek,eth-mac")) 4908 continue; 4909 4910 if (!of_device_is_available(mac_np)) 4911 continue; 4912 4913 err = mtk_add_mac(eth, mac_np); 4914 if (err) { 4915 of_node_put(mac_np); 4916 goto err_deinit_hw; 4917 } 4918 } 4919 4920 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4921 err = devm_request_irq(eth->dev, eth->irq[0], 4922 mtk_handle_irq, 0, 4923 dev_name(eth->dev), eth); 4924 } else { 4925 err = devm_request_irq(eth->dev, eth->irq[1], 4926 mtk_handle_irq_tx, 0, 4927 dev_name(eth->dev), eth); 4928 if (err) 4929 goto err_free_dev; 4930 4931 err = devm_request_irq(eth->dev, eth->irq[2], 4932 mtk_handle_irq_rx, 0, 4933 dev_name(eth->dev), eth); 4934 } 4935 if (err) 4936 goto err_free_dev; 4937 4938 /* No MT7628/88 support yet */ 4939 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4940 err = mtk_mdio_init(eth); 4941 if (err) 4942 goto err_free_dev; 4943 } 4944 4945 if (eth->soc->offload_version) { 4946 u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; 4947 4948 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4949 for (i = 0; i < num_ppe; i++) { 4950 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4951 4952 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4953 4954 if (!eth->ppe[i]) { 4955 err = -ENOMEM; 4956 goto err_deinit_ppe; 4957 } 4958 } 4959 4960 err = mtk_eth_offload_init(eth); 4961 if (err) 4962 goto err_deinit_ppe; 4963 } 4964 4965 for (i = 0; i < MTK_MAX_DEVS; i++) { 4966 if (!eth->netdev[i]) 4967 continue; 4968 4969 err = register_netdev(eth->netdev[i]); 4970 if (err) { 4971 dev_err(eth->dev, "error bringing up device\n"); 4972 goto err_deinit_ppe; 4973 } else 4974 netif_info(eth, probe, eth->netdev[i], 4975 "mediatek frame engine at 0x%08lx, irq %d\n", 4976 eth->netdev[i]->base_addr, eth->irq[0]); 4977 } 4978 4979 /* we run 2 devices on the same DMA ring so we need a dummy device 4980 * for NAPI to work 4981 */ 4982 init_dummy_netdev(ð->dummy_dev); 4983 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4984 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4985 4986 platform_set_drvdata(pdev, eth); 4987 schedule_delayed_work(ð->reset.monitor_work, 4988 MTK_DMA_MONITOR_TIMEOUT); 4989 4990 return 0; 4991 4992err_deinit_ppe: 4993 mtk_ppe_deinit(eth); 4994 mtk_mdio_cleanup(eth); 4995err_free_dev: 4996 mtk_free_dev(eth); 4997err_deinit_hw: 4998 mtk_hw_deinit(eth); 4999err_wed_exit: 5000 mtk_wed_exit(); 5001err_destroy_sgmii: 5002 mtk_sgmii_destroy(eth); 5003 5004 return err; 5005} 5006 5007static int mtk_remove(struct platform_device *pdev) 5008{ 5009 struct mtk_eth *eth = platform_get_drvdata(pdev); 5010 struct mtk_mac *mac; 5011 int i; 5012 5013 /* stop all devices to make sure that dma is properly shut down */ 5014 for (i = 0; i < MTK_MAX_DEVS; i++) { 5015 if (!eth->netdev[i]) 5016 continue; 5017 mtk_stop(eth->netdev[i]); 5018 mac = netdev_priv(eth->netdev[i]); 5019 phylink_disconnect_phy(mac->phylink); 5020 } 5021 5022 mtk_wed_exit(); 5023 mtk_hw_deinit(eth); 5024 5025 netif_napi_del(ð->tx_napi); 5026 netif_napi_del(ð->rx_napi); 5027 mtk_cleanup(eth); 5028 mtk_mdio_cleanup(eth); 5029 5030 return 0; 5031} 5032 5033static const struct mtk_soc_data mt2701_data = { 5034 .reg_map = &mtk_reg_map, 5035 .caps = MT7623_CAPS | MTK_HWLRO, 5036 .hw_features = MTK_HW_FEATURES, 5037 .required_clks = MT7623_CLKS_BITMAP, 5038 .required_pctl = true, 5039 .version = 1, 5040 .txrx = { 5041 .txd_size = sizeof(struct mtk_tx_dma), 5042 .rxd_size = sizeof(struct mtk_rx_dma), 5043 .rx_irq_done_mask = MTK_RX_DONE_INT, 5044 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5045 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5046 .dma_len_offset = 16, 5047 }, 5048}; 5049 5050static const struct mtk_soc_data mt7621_data = { 5051 .reg_map = &mtk_reg_map, 5052 .caps = MT7621_CAPS, 5053 .hw_features = MTK_HW_FEATURES, 5054 .required_clks = MT7621_CLKS_BITMAP, 5055 .required_pctl = false, 5056 .version = 1, 5057 .offload_version = 1, 5058 .hash_offset = 2, 5059 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5060 .txrx = { 5061 .txd_size = sizeof(struct mtk_tx_dma), 5062 .rxd_size = sizeof(struct mtk_rx_dma), 5063 .rx_irq_done_mask = MTK_RX_DONE_INT, 5064 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5065 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5066 .dma_len_offset = 16, 5067 }, 5068}; 5069 5070static const struct mtk_soc_data mt7622_data = { 5071 .reg_map = &mtk_reg_map, 5072 .ana_rgc3 = 0x2028, 5073 .caps = MT7622_CAPS | MTK_HWLRO, 5074 .hw_features = MTK_HW_FEATURES, 5075 .required_clks = MT7622_CLKS_BITMAP, 5076 .required_pctl = false, 5077 .version = 1, 5078 .offload_version = 2, 5079 .hash_offset = 2, 5080 .has_accounting = true, 5081 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5082 .txrx = { 5083 .txd_size = sizeof(struct mtk_tx_dma), 5084 .rxd_size = sizeof(struct mtk_rx_dma), 5085 .rx_irq_done_mask = MTK_RX_DONE_INT, 5086 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5087 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5088 .dma_len_offset = 16, 5089 }, 5090}; 5091 5092static const struct mtk_soc_data mt7623_data = { 5093 .reg_map = &mtk_reg_map, 5094 .caps = MT7623_CAPS | MTK_HWLRO, 5095 .hw_features = MTK_HW_FEATURES, 5096 .required_clks = MT7623_CLKS_BITMAP, 5097 .required_pctl = true, 5098 .version = 1, 5099 .offload_version = 1, 5100 .hash_offset = 2, 5101 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 5102 .disable_pll_modes = true, 5103 .txrx = { 5104 .txd_size = sizeof(struct mtk_tx_dma), 5105 .rxd_size = sizeof(struct mtk_rx_dma), 5106 .rx_irq_done_mask = MTK_RX_DONE_INT, 5107 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5108 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5109 .dma_len_offset = 16, 5110 }, 5111}; 5112 5113static const struct mtk_soc_data mt7629_data = { 5114 .reg_map = &mtk_reg_map, 5115 .ana_rgc3 = 0x128, 5116 .caps = MT7629_CAPS | MTK_HWLRO, 5117 .hw_features = MTK_HW_FEATURES, 5118 .required_clks = MT7629_CLKS_BITMAP, 5119 .required_pctl = false, 5120 .has_accounting = true, 5121 .version = 1, 5122 .txrx = { 5123 .txd_size = sizeof(struct mtk_tx_dma), 5124 .rxd_size = sizeof(struct mtk_rx_dma), 5125 .rx_irq_done_mask = MTK_RX_DONE_INT, 5126 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5127 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5128 .dma_len_offset = 16, 5129 }, 5130}; 5131 5132static const struct mtk_soc_data mt7981_data = { 5133 .reg_map = &mt7986_reg_map, 5134 .ana_rgc3 = 0x128, 5135 .caps = MT7981_CAPS, 5136 .hw_features = MTK_HW_FEATURES, 5137 .required_clks = MT7981_CLKS_BITMAP, 5138 .required_pctl = false, 5139 .version = 2, 5140 .offload_version = 2, 5141 .hash_offset = 4, 5142 .has_accounting = true, 5143 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5144 .txrx = { 5145 .txd_size = sizeof(struct mtk_tx_dma_v2), 5146 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5147 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5148 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5149 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5150 .dma_len_offset = 8, 5151 }, 5152}; 5153 5154static const struct mtk_soc_data mt7986_data = { 5155 .reg_map = &mt7986_reg_map, 5156 .ana_rgc3 = 0x128, 5157 .caps = MT7986_CAPS, 5158 .hw_features = MTK_HW_FEATURES, 5159 .required_clks = MT7986_CLKS_BITMAP, 5160 .required_pctl = false, 5161 .version = 2, 5162 .offload_version = 2, 5163 .hash_offset = 4, 5164 .has_accounting = true, 5165 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5166 .txrx = { 5167 .txd_size = sizeof(struct mtk_tx_dma_v2), 5168 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5169 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5170 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5171 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5172 .dma_len_offset = 8, 5173 }, 5174}; 5175 5176static const struct mtk_soc_data mt7988_data = { 5177 .reg_map = &mt7988_reg_map, 5178 .ana_rgc3 = 0x128, 5179 .caps = MT7988_CAPS, 5180 .hw_features = MTK_HW_FEATURES, 5181 .required_clks = MT7988_CLKS_BITMAP, 5182 .required_pctl = false, 5183 .version = 3, 5184 .offload_version = 2, 5185 .hash_offset = 4, 5186 .has_accounting = true, 5187 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5188 .txrx = { 5189 .txd_size = sizeof(struct mtk_tx_dma_v2), 5190 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5191 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5192 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5193 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5194 .dma_len_offset = 8, 5195 }, 5196}; 5197 5198static const struct mtk_soc_data rt5350_data = { 5199 .reg_map = &mt7628_reg_map, 5200 .caps = MT7628_CAPS, 5201 .hw_features = MTK_HW_FEATURES_MT7628, 5202 .required_clks = MT7628_CLKS_BITMAP, 5203 .required_pctl = false, 5204 .version = 1, 5205 .txrx = { 5206 .txd_size = sizeof(struct mtk_tx_dma), 5207 .rxd_size = sizeof(struct mtk_rx_dma), 5208 .rx_irq_done_mask = MTK_RX_DONE_INT, 5209 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5210 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5211 .dma_len_offset = 16, 5212 }, 5213}; 5214 5215const struct of_device_id of_mtk_match[] = { 5216 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5217 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5218 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5219 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5220 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5221 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5222 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5223 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5224 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5225 {}, 5226}; 5227MODULE_DEVICE_TABLE(of, of_mtk_match); 5228 5229static struct platform_driver mtk_driver = { 5230 .probe = mtk_probe, 5231 .remove = mtk_remove, 5232 .driver = { 5233 .name = "mtk_soc_eth", 5234 .of_match_table = of_mtk_match, 5235 }, 5236}; 5237 5238module_platform_driver(mtk_driver); 5239 5240MODULE_LICENSE("GPL"); 5241MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5242MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5243