1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef RVU_H 9#define RVU_H 10 11#include <linux/pci.h> 12#include <net/devlink.h> 13 14#include "rvu_struct.h" 15#include "rvu_devlink.h" 16#include "common.h" 17#include "mbox.h" 18#include "npc.h" 19#include "rvu_reg.h" 20#include "ptp.h" 21 22/* PCI device IDs */ 23#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 24#define PCI_DEVID_OCTEONTX2_LBK 0xA061 25 26/* Subsystem Device ID */ 27#define PCI_SUBSYS_DEVID_98XX 0xB100 28#define PCI_SUBSYS_DEVID_96XX 0xB200 29#define PCI_SUBSYS_DEVID_CN10K_A 0xB900 30#define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 31#define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 32#define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 33 34/* PCI BAR nos */ 35#define PCI_AF_REG_BAR_NUM 0 36#define PCI_PF_REG_BAR_NUM 2 37#define PCI_MBOX_BAR_NUM 4 38 39#define NAME_SIZE 32 40#define MAX_NIX_BLKS 2 41#define MAX_CPT_BLKS 2 42 43/* PF_FUNC */ 44#define RVU_PFVF_PF_SHIFT 10 45#define RVU_PFVF_PF_MASK 0x3F 46#define RVU_PFVF_FUNC_SHIFT 0 47#define RVU_PFVF_FUNC_MASK 0x3FF 48 49#ifdef CONFIG_DEBUG_FS 50struct dump_ctx { 51 int lf; 52 int id; 53 bool all; 54}; 55 56struct cpt_ctx { 57 int blkaddr; 58 struct rvu *rvu; 59}; 60 61struct rvu_debugfs { 62 struct dentry *root; 63 struct dentry *cgx_root; 64 struct dentry *cgx; 65 struct dentry *lmac; 66 struct dentry *npa; 67 struct dentry *nix; 68 struct dentry *npc; 69 struct dentry *cpt; 70 struct dentry *mcs_root; 71 struct dentry *mcs; 72 struct dentry *mcs_rx; 73 struct dentry *mcs_tx; 74 struct dump_ctx npa_aura_ctx; 75 struct dump_ctx npa_pool_ctx; 76 struct dump_ctx nix_cq_ctx; 77 struct dump_ctx nix_rq_ctx; 78 struct dump_ctx nix_sq_ctx; 79 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 80 int npa_qsize_id; 81 int nix_qsize_id; 82}; 83#endif 84 85struct rvu_work { 86 struct work_struct work; 87 struct rvu *rvu; 88 int num_msgs; 89 int up_num_msgs; 90}; 91 92struct rsrc_bmap { 93 unsigned long *bmap; /* Pointer to resource bitmap */ 94 u16 max; /* Max resource id or count */ 95}; 96 97struct rvu_block { 98 struct rsrc_bmap lf; 99 struct admin_queue *aq; /* NIX/NPA AQ */ 100 u16 *fn_map; /* LF to pcifunc mapping */ 101 bool multislot; 102 bool implemented; 103 u8 addr; /* RVU_BLOCK_ADDR_E */ 104 u8 type; /* RVU_BLOCK_TYPE_E */ 105 u8 lfshift; 106 u64 lookup_reg; 107 u64 pf_lfcnt_reg; 108 u64 vf_lfcnt_reg; 109 u64 lfcfg_reg; 110 u64 msixcfg_reg; 111 u64 lfreset_reg; 112 unsigned char name[NAME_SIZE]; 113 struct rvu *rvu; 114 u64 cpt_flt_eng_map[3]; 115 u64 cpt_rcvrd_eng_map[3]; 116}; 117 118struct nix_mcast { 119 struct qmem *mce_ctx; 120 struct qmem *mcast_buf; 121 int replay_pkind; 122 int next_free_mce; 123 struct mutex mce_lock; /* Serialize MCE updates */ 124}; 125 126struct nix_mce_list { 127 struct hlist_head head; 128 int count; 129 int max; 130}; 131 132/* layer metadata to uniquely identify a packet header field */ 133struct npc_layer_mdata { 134 u8 lid; 135 u8 ltype; 136 u8 hdr; 137 u8 key; 138 u8 len; 139}; 140 141/* Structure to represent a field present in the 142 * generated key. A key field may present anywhere and can 143 * be of any size in the generated key. Once this structure 144 * is populated for fields of interest then field's presence 145 * and location (if present) can be known. 146 */ 147struct npc_key_field { 148 /* Masks where all set bits indicate position 149 * of a field in the key 150 */ 151 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 152 /* Number of words in the key a field spans. If a field is 153 * of 16 bytes and key offset is 4 then the field will use 154 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 155 * nr_kws will be 3(KW0, KW1 and KW2). 156 */ 157 int nr_kws; 158 /* used by packet header fields */ 159 struct npc_layer_mdata layer_mdata; 160}; 161 162struct npc_mcam { 163 struct rsrc_bmap counters; 164 struct mutex lock; /* MCAM entries and counters update lock */ 165 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 166 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 167 u16 bmap_entries; /* Number of unreserved MCAM entries */ 168 u16 bmap_fcnt; /* MCAM entries free count */ 169 u16 *entry2pfvf_map; 170 u16 *entry2cntr_map; 171 u16 *cntr2pfvf_map; 172 u16 *cntr_refcnt; 173 u16 *entry2target_pffunc; 174 u8 keysize; /* MCAM keysize 112/224/448 bits */ 175 u8 banks; /* Number of MCAM banks */ 176 u8 banks_per_entry;/* Number of keywords in key */ 177 u16 banksize; /* Number of MCAM entries in each bank */ 178 u16 total_entries; /* Total number of MCAM entries */ 179 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 180 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 181 u16 lprio_count; 182 u16 lprio_start; 183 u16 hprio_count; 184 u16 hprio_end; 185 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 186 /* fields present in the generated key */ 187 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 188 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 189 u64 tx_features; 190 u64 rx_features; 191 struct list_head mcam_rules; 192}; 193 194/* Structure for per RVU func info ie PF/VF */ 195struct rvu_pfvf { 196 bool npalf; /* Only one NPALF per RVU_FUNC */ 197 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 198 u16 sso; 199 u16 ssow; 200 u16 cptlfs; 201 u16 timlfs; 202 u16 cpt1_lfs; 203 u8 cgx_lmac; 204 205 /* Block LF's MSIX vector info */ 206 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 207#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 208 u16 *msix_lfmap; /* Vector to block LF mapping */ 209 210 /* NPA contexts */ 211 struct qmem *aura_ctx; 212 struct qmem *pool_ctx; 213 struct qmem *npa_qints_ctx; 214 unsigned long *aura_bmap; 215 unsigned long *pool_bmap; 216 217 /* NIX contexts */ 218 struct qmem *rq_ctx; 219 struct qmem *sq_ctx; 220 struct qmem *cq_ctx; 221 struct qmem *rss_ctx; 222 struct qmem *cq_ints_ctx; 223 struct qmem *nix_qints_ctx; 224 unsigned long *sq_bmap; 225 unsigned long *rq_bmap; 226 unsigned long *cq_bmap; 227 228 u16 rx_chan_base; 229 u16 tx_chan_base; 230 u8 rx_chan_cnt; /* total number of RX channels */ 231 u8 tx_chan_cnt; /* total number of TX channels */ 232 u16 maxlen; 233 u16 minlen; 234 235 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 236 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 237 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 238 239 /* Broadcast/Multicast/Promisc pkt replication info */ 240 u16 bcast_mce_idx; 241 u16 mcast_mce_idx; 242 u16 promisc_mce_idx; 243 struct nix_mce_list bcast_mce_list; 244 struct nix_mce_list mcast_mce_list; 245 struct nix_mce_list promisc_mce_list; 246 bool use_mce_list; 247 248 struct rvu_npc_mcam_rule *def_ucast_rule; 249 250 bool cgx_in_use; /* this PF/VF using CGX? */ 251 int cgx_users; /* number of cgx users - used only by PFs */ 252 253 int intf_mode; 254 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 255 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 256 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 257 u8 lbkid; /* NIX0/1 lbk link ID */ 258 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 259 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 260 unsigned long flags; 261 struct sdp_node_info *sdp_info; 262}; 263 264enum rvu_pfvf_flags { 265 NIXLF_INITIALIZED = 0, 266 PF_SET_VF_MAC, 267 PF_SET_VF_CFG, 268 PF_SET_VF_TRUSTED, 269}; 270 271#define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 272 273struct nix_txsch { 274 struct rsrc_bmap schq; 275 u8 lvl; 276#define NIX_TXSCHQ_FREE BIT_ULL(1) 277#define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 278#define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 279#define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 280#define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 281#define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 282 u32 *pfvf_map; 283}; 284 285struct nix_mark_format { 286 u8 total; 287 u8 in_use; 288 u32 *cfg; 289}; 290 291/* smq(flush) to tl1 cir/pir info */ 292struct nix_smq_tree_ctx { 293 u64 cir_off; 294 u64 cir_val; 295 u64 pir_off; 296 u64 pir_val; 297}; 298 299/* smq flush context */ 300struct nix_smq_flush_ctx { 301 int smq; 302 u16 tl1_schq; 303 u16 tl2_schq; 304 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 305}; 306 307struct npc_pkind { 308 struct rsrc_bmap rsrc; 309 u32 *pfchan_map; 310}; 311 312struct nix_flowkey { 313#define NIX_FLOW_KEY_ALG_MAX 32 314 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 315 int in_use; 316}; 317 318struct nix_lso { 319 u8 total; 320 u8 in_use; 321}; 322 323struct nix_txvlan { 324#define NIX_TX_VTAG_DEF_MAX 0x400 325 struct rsrc_bmap rsrc; 326 u16 *entry2pfvf_map; 327 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 328}; 329 330struct nix_ipolicer { 331 struct rsrc_bmap band_prof; 332 u16 *pfvf_map; 333 u16 *match_id; 334 u16 *ref_count; 335}; 336 337struct nix_hw { 338 int blkaddr; 339 struct rvu *rvu; 340 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 341 struct nix_mcast mcast; 342 struct nix_flowkey flowkey; 343 struct nix_mark_format mark_format; 344 struct nix_lso lso; 345 struct nix_txvlan txvlan; 346 struct nix_ipolicer *ipolicer; 347 u64 *tx_credits; 348 u8 cc_mcs_cnt; 349}; 350 351/* RVU block's capabilities or functionality, 352 * which vary by silicon version/skew. 353 */ 354struct hw_cap { 355 /* Transmit side supported functionality */ 356 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 357 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 358 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 359 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 360 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 361 bool nix_shaping; /* Is shaping and coloring supported */ 362 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 363 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 364 bool nix_rx_multicast; /* Rx packet replication support */ 365 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 366 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 367 bool programmable_chans; /* Channels programmable ? */ 368 bool ipolicer; 369 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 370 bool npc_hash_extract; /* Hash extract enabled ? */ 371 bool npc_exact_match_enabled; /* Exact match supported ? */ 372}; 373 374struct rvu_hwinfo { 375 u8 total_pfs; /* MAX RVU PFs HW supports */ 376 u16 total_vfs; /* Max RVU VFs HW supports */ 377 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 378 u8 cgx; 379 u8 lmac_per_cgx; 380 u16 cgx_chan_base; /* CGX base channel number */ 381 u16 lbk_chan_base; /* LBK base channel number */ 382 u16 sdp_chan_base; /* SDP base channel number */ 383 u16 cpt_chan_base; /* CPT base channel number */ 384 u8 cgx_links; 385 u8 lbk_links; 386 u8 sdp_links; 387 u8 cpt_links; /* Number of CPT links */ 388 u8 npc_kpus; /* No of parser units */ 389 u8 npc_pkinds; /* No of port kinds */ 390 u8 npc_intfs; /* No of interfaces */ 391 u8 npc_kpu_entries; /* No of KPU entries */ 392 u16 npc_counters; /* No of match stats counters */ 393 u32 lbk_bufsize; /* FIFO size supported by LBK */ 394 bool npc_ext_set; /* Extended register set */ 395 u64 npc_stat_ena; /* Match stats enable bit */ 396 397 struct hw_cap cap; 398 struct rvu_block block[BLK_COUNT]; /* Block info */ 399 struct nix_hw *nix; 400 struct rvu *rvu; 401 struct npc_pkind pkind; 402 struct npc_mcam mcam; 403 struct npc_exact_table *table; 404}; 405 406struct mbox_wq_info { 407 struct otx2_mbox mbox; 408 struct rvu_work *mbox_wrk; 409 410 struct otx2_mbox mbox_up; 411 struct rvu_work *mbox_wrk_up; 412 413 struct workqueue_struct *mbox_wq; 414}; 415 416struct rvu_fwdata { 417#define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 418#define RVU_FWDATA_VERSION 0x0001 419 u32 header_magic; 420 u32 version; /* version id */ 421 422 /* MAC address */ 423#define PF_MACNUM_MAX 32 424#define VF_MACNUM_MAX 256 425 u64 pf_macs[PF_MACNUM_MAX]; 426 u64 vf_macs[VF_MACNUM_MAX]; 427 u64 sclk; 428 u64 rclk; 429 u64 mcam_addr; 430 u64 mcam_sz; 431 u64 msixtr_base; 432 u32 ptp_ext_clk_rate; 433 u32 ptp_ext_tstamp; 434#define FWDATA_RESERVED_MEM 1022 435 u64 reserved[FWDATA_RESERVED_MEM]; 436#define CGX_MAX 9 437#define CGX_LMACS_MAX 4 438#define CGX_LMACS_USX 8 439 union { 440 struct cgx_lmac_fwdata_s 441 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 442 struct cgx_lmac_fwdata_s 443 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 444 }; 445 /* Do not add new fields below this line */ 446}; 447 448struct ptp; 449 450/* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 451 * source where it came from. 452 */ 453struct npc_kpu_profile_adapter { 454 const char *name; 455 u64 version; 456 const struct npc_lt_def_cfg *lt_def; 457 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 458 const struct npc_kpu_profile *kpu; /* array[kpus] */ 459 struct npc_mcam_kex *mkex; 460 struct npc_mcam_kex_hash *mkex_hash; 461 bool custom; 462 size_t pkinds; 463 size_t kpus; 464}; 465 466#define RVU_SWITCH_LBK_CHAN 63 467 468struct rvu_switch { 469 struct mutex switch_lock; /* Serialize flow installation */ 470 u32 used_entries; 471 u16 *entry2pcifunc; 472 u16 mode; 473 u16 start_entry; 474}; 475 476struct rvu { 477 void __iomem *afreg_base; 478 void __iomem *pfreg_base; 479 struct pci_dev *pdev; 480 struct device *dev; 481 struct rvu_hwinfo *hw; 482 struct rvu_pfvf *pf; 483 struct rvu_pfvf *hwvf; 484 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 485 struct mutex alias_lock; /* Serialize bar2 alias access */ 486 int vfs; /* Number of VFs attached to RVU */ 487 int nix_blkaddr[MAX_NIX_BLKS]; 488 489 /* Mbox */ 490 struct mbox_wq_info afpf_wq_info; 491 struct mbox_wq_info afvf_wq_info; 492 493 /* PF FLR */ 494 struct rvu_work *flr_wrk; 495 struct workqueue_struct *flr_wq; 496 struct mutex flr_lock; /* Serialize FLRs */ 497 498 /* MSI-X */ 499 u16 num_vec; 500 char *irq_name; 501 bool *irq_allocated; 502 dma_addr_t msix_base_iova; 503 u64 msixtr_base_phy; /* Register reset value */ 504 505 /* CGX */ 506#define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 507 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 508 u8 cgx_mapped_pfs; 509 u8 cgx_cnt_max; /* CGX port count max */ 510 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 511 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 512 * every cgx lmac port 513 */ 514 unsigned long pf_notify_bmap; /* Flags for PF notification */ 515 void **cgx_idmap; /* cgx id to cgx data map table */ 516 struct work_struct cgx_evh_work; 517 struct workqueue_struct *cgx_evh_wq; 518 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 519 struct list_head cgx_evq_head; /* cgx event queue head */ 520 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 521 522 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 523 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 524 525 /* Firmware data */ 526 struct rvu_fwdata *fwdata; 527 void *kpu_fwdata; 528 size_t kpu_fwdata_sz; 529 void __iomem *kpu_prfl_addr; 530 531 /* NPC KPU data */ 532 struct npc_kpu_profile_adapter kpu; 533 534 struct ptp *ptp; 535 536 int mcs_blk_cnt; 537 int cpt_pf_num; 538 539#ifdef CONFIG_DEBUG_FS 540 struct rvu_debugfs rvu_dbg; 541#endif 542 struct rvu_devlink *rvu_dl; 543 544 /* RVU switch implementation over NPC with DMAC rules */ 545 struct rvu_switch rswitch; 546 547 struct work_struct mcs_intr_work; 548 struct workqueue_struct *mcs_intr_wq; 549 struct list_head mcs_intrq_head; 550 /* mcs interrupt queue lock */ 551 spinlock_t mcs_intrq_lock; 552 /* CPT interrupt lock */ 553 spinlock_t cpt_intr_lock; 554 555 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 556}; 557 558static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 559{ 560 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 561} 562 563static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 564{ 565 return readq(rvu->afreg_base + ((block << 28) | offset)); 566} 567 568static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 569{ 570 writeq(val, rvu->pfreg_base + offset); 571} 572 573static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 574{ 575 return readq(rvu->pfreg_base + offset); 576} 577 578static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 579{ 580 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 581 * write operation. 582 */ 583 rvu_write64(rvu, block, offset, val); 584 rvu_read64(rvu, block, offset); 585 /* Barrier to ensure read completes before accessing LF registers */ 586 mb(); 587} 588 589/* Silicon revisions */ 590static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 591{ 592 struct pci_dev *pdev = rvu->pdev; 593 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 594 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 595 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 596 (pdev->revision == 0x14)); 597} 598 599static inline bool is_rvu_96xx_A0(struct rvu *rvu) 600{ 601 struct pci_dev *pdev = rvu->pdev; 602 603 return (pdev->revision == 0x00); 604} 605 606static inline bool is_rvu_96xx_B0(struct rvu *rvu) 607{ 608 struct pci_dev *pdev = rvu->pdev; 609 610 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 611} 612 613static inline bool is_rvu_95xx_A0(struct rvu *rvu) 614{ 615 struct pci_dev *pdev = rvu->pdev; 616 617 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 618} 619 620/* REVID for PCIe devices. 621 * Bits 0..1: minor pass, bit 3..2: major pass 622 * bits 7..4: midr id 623 */ 624#define PCI_REVISION_ID_96XX 0x00 625#define PCI_REVISION_ID_95XX 0x10 626#define PCI_REVISION_ID_95XXN 0x20 627#define PCI_REVISION_ID_98XX 0x30 628#define PCI_REVISION_ID_95XXMM 0x40 629#define PCI_REVISION_ID_95XXO 0xE0 630 631static inline bool is_rvu_otx2(struct rvu *rvu) 632{ 633 struct pci_dev *pdev = rvu->pdev; 634 635 u8 midr = pdev->revision & 0xF0; 636 637 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 638 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 639 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 640} 641 642static inline bool is_cnf10ka_a0(struct rvu *rvu) 643{ 644 struct pci_dev *pdev = rvu->pdev; 645 646 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 647 (pdev->revision & 0x0F) == 0x0) 648 return true; 649 return false; 650} 651 652static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 653{ 654 u64 npc_const3; 655 656 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 657 if (!(npc_const3 & BIT_ULL(62))) 658 return false; 659 660 return true; 661} 662 663static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 664 u8 lmacid, u8 chan) 665{ 666 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 667 u16 cgx_chans = nix_const & 0xFFULL; 668 struct rvu_hwinfo *hw = rvu->hw; 669 670 if (!hw->cap.programmable_chans) 671 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 672 673 return rvu->hw->cgx_chan_base + 674 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 675} 676 677static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 678 u8 chan) 679{ 680 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 681 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 682 struct rvu_hwinfo *hw = rvu->hw; 683 684 if (!hw->cap.programmable_chans) 685 return NIX_CHAN_LBK_CHX(lbkid, chan); 686 687 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 688} 689 690static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 691{ 692 struct rvu_hwinfo *hw = rvu->hw; 693 694 if (!hw->cap.programmable_chans) 695 return NIX_CHAN_SDP_CHX(chan); 696 697 return hw->sdp_chan_base + chan; 698} 699 700static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 701{ 702 return rvu->hw->cpt_chan_base + chan; 703} 704 705static inline bool is_rvu_supports_nix1(struct rvu *rvu) 706{ 707 struct pci_dev *pdev = rvu->pdev; 708 709 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 710 return true; 711 712 return false; 713} 714 715/* Function Prototypes 716 * RVU 717 */ 718static inline bool is_afvf(u16 pcifunc) 719{ 720 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 721} 722 723static inline bool is_vf(u16 pcifunc) 724{ 725 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 726} 727 728/* check if PF_FUNC is AF */ 729static inline bool is_pffunc_af(u16 pcifunc) 730{ 731 return !pcifunc; 732} 733 734static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 735{ 736 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 737 (rvu->fwdata->version == RVU_FWDATA_VERSION); 738} 739 740int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 741void rvu_free_bitmap(struct rsrc_bmap *rsrc); 742int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 743void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 744bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 745int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 746int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 747bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 748u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 749int rvu_get_pf(u16 pcifunc); 750struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 751void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 752bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 753bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 754int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 755int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 756int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 757int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 758int rvu_get_num_lbk_chans(void); 759int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 760 u16 global_slot, u16 *slot_in_block); 761 762/* RVU HW reg validation */ 763enum regmap_block { 764 TXSCHQ_HWREGMAP = 0, 765 MAX_HWREGMAP, 766}; 767 768bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 769 770/* NPA/NIX AQ APIs */ 771int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 772 int qsize, int inst_size, int res_size); 773void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 774 775/* SDP APIs */ 776int rvu_sdp_init(struct rvu *rvu); 777bool is_sdp_pfvf(u16 pcifunc); 778bool is_sdp_pf(u16 pcifunc); 779bool is_sdp_vf(u16 pcifunc); 780 781/* CGX APIs */ 782static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 783{ 784 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 785 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 786} 787 788static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 789{ 790 *cgx_id = (map >> 4) & 0xF; 791 *lmac_id = (map & 0xF); 792} 793 794static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 795{ 796 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 797 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 798} 799 800#define M(_name, _id, fn_name, req, rsp) \ 801int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 802MBOX_MESSAGES 803#undef M 804 805int rvu_cgx_init(struct rvu *rvu); 806int rvu_cgx_exit(struct rvu *rvu); 807void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 808int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 809void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 810int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 811int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 812 int rxtxflag, u64 *stat); 813void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 814 815/* NPA APIs */ 816int rvu_npa_init(struct rvu *rvu); 817void rvu_npa_freemem(struct rvu *rvu); 818void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 819int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 820 struct npa_aq_enq_rsp *rsp); 821 822/* NIX APIs */ 823bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 824int rvu_nix_init(struct rvu *rvu); 825int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 826 int blkaddr, u32 cfg); 827void rvu_nix_freemem(struct rvu *rvu); 828int rvu_get_nixlf_count(struct rvu *rvu); 829void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 830int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 831int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 832 struct nix_mce_list *mce_list, 833 int mce_idx, int mcam_index, bool add); 834void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 835 struct nix_mce_list **mce_list, int *mce_idx); 836struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 837int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 838void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 839int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 840 struct nix_hw **nix_hw, int *blkaddr); 841int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 842 u16 rq_idx, u16 match_id); 843int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 844 struct nix_cn10k_aq_enq_req *aq_req, 845 struct nix_cn10k_aq_enq_rsp *aq_rsp, 846 u16 pcifunc, u8 ctype, u32 qidx); 847int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 848int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 849u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 850u32 convert_bytes_to_dwrr_mtu(u32 bytes); 851void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 852 struct nix_txsch *txsch, bool enable); 853 854/* NPC APIs */ 855void rvu_npc_freemem(struct rvu *rvu); 856int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 857void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 858int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 859void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 860 int nixlf, u64 chan, u8 *mac_addr); 861void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 862 int nixlf, u64 chan, u8 chan_cnt); 863void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 864 bool enable); 865void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 866 int nixlf, u64 chan); 867void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 868 bool enable); 869void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 870 u64 chan); 871void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 872 bool enable); 873 874void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 875 int nixlf, int type, bool enable); 876void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 877bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 878void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 879void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 880void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 881void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 882 int group, int alg_idx, int mcam_index); 883 884void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 885 int blkaddr, int *alloc_cnt, 886 int *enable_cnt); 887void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 888 int blkaddr, int *alloc_cnt, 889 int *enable_cnt); 890bool is_npc_intf_tx(u8 intf); 891bool is_npc_intf_rx(u8 intf); 892bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 893int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 894int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 895const char *npc_get_field_name(u8 hdr); 896int npc_get_bank(struct npc_mcam *mcam, int index); 897void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 898void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 899void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 900 int blkaddr, int index, bool enable); 901void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 902 int blkaddr, u16 src, struct mcam_entry *entry, 903 u8 *intf, u8 *ena); 904bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 905bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 906u32 rvu_cgx_get_fifolen(struct rvu *rvu); 907void *rvu_first_cgx_pdata(struct rvu *rvu); 908int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 909int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 910int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 911int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 912 u16 pfc_en); 913int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 914void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 915u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 916int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 917 int type); 918bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 919 int index); 920int rvu_npc_init(struct rvu *rvu); 921int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 922 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 923 u64 bcast_mcast_val, u64 bcast_mcast_mask); 924void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 925bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 926 927/* CPT APIs */ 928int rvu_cpt_register_interrupts(struct rvu *rvu); 929void rvu_cpt_unregister_interrupts(struct rvu *rvu); 930int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 931 int slot); 932int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 933int rvu_cpt_init(struct rvu *rvu); 934 935#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 936#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 937 938/* CN10K RVU */ 939int rvu_set_channels_base(struct rvu *rvu); 940void rvu_program_channels(struct rvu *rvu); 941 942/* CN10K NIX */ 943void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 944 945/* CN10K RVU - LMT*/ 946void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 947 948#ifdef CONFIG_DEBUG_FS 949void rvu_dbg_init(struct rvu *rvu); 950void rvu_dbg_exit(struct rvu *rvu); 951#else 952static inline void rvu_dbg_init(struct rvu *rvu) {} 953static inline void rvu_dbg_exit(struct rvu *rvu) {} 954#endif 955 956int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 957 958/* RVU Switch */ 959void rvu_switch_enable(struct rvu *rvu); 960void rvu_switch_disable(struct rvu *rvu); 961void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 962 963int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 964 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 965 u8 shift_dir); 966int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 967 968/* CN10K MCS */ 969int rvu_mcs_init(struct rvu *rvu); 970int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 971void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 972void rvu_mcs_exit(struct rvu *rvu); 973 974#endif /* RVU_H */ 975