1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell CN10K RPM driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef RPM_H 9#define RPM_H 10 11#include <linux/bits.h> 12 13/* PCI device IDs */ 14#define PCI_DEVID_CN10K_RPM 0xA060 15#define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00 16#define PCI_DEVID_CN10KB_RPM 0xA09F 17 18/* Registers */ 19#define RPMX_CMRX_CFG 0x00 20#define RPMX_RX_TS_PREPEND BIT_ULL(22) 21#define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17) 22#define RPMX_CMRX_RX_ID_MAP 0x80 23#define RPMX_CMRX_SW_INT 0x180 24#define RPMX_CMRX_SW_INT_W1S 0x188 25#define RPMX_CMRX_SW_INT_ENA_W1S 0x198 26#define RPMX_CMRX_LINK_CFG 0x1070 27#define RPMX_MTI_PCS100X_CONTROL1 0x20000 28#define RPMX_MTI_PCS_LBK BIT_ULL(14) 29#define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100)) 30 31#define RPMX_CMRX_LINK_RANGE_MASK GENMASK_ULL(19, 16) 32#define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0) 33#define RPMX_MTI_MAC100X_COMMAND_CONFIG 0x8010 34#define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29) 35#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28) 36#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8) 37#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19) 38#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8 39#define RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA 0x80B0 40#define RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA 0x80B8 41#define RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA 0x80C0 42#define RPMX_MTI_MAC100X_CL01_QUANTA_THRESH 0x80C8 43#define RPMX_MTI_MAC100X_CL23_QUANTA_THRESH 0x80D0 44#define RPMX_MTI_MAC100X_CL45_QUANTA_THRESH 0x80D8 45#define RPMX_MTI_MAC100X_CL67_QUANTA_THRESH 0x80E0 46#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108 47#define RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA 0x8110 48#define RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA 0x8118 49#define RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA 0x8120 50#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128 51#define RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH 0x8130 52#define RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH 0x8138 53#define RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH 0x8140 54#define RPMX_CMR_RX_OVR_BP 0x4120 55#define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8) 56#define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4) 57#define RPMX_CMR_CHAN_MSK_OR 0x4118 58#define RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX 0x12000 59#define RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX 0x13000 60#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038 61 62#define RPM_LMAC_FWI 0xa 63#define RPM_TX_EN BIT_ULL(0) 64#define RPM_RX_EN BIT_ULL(1) 65#define RPMX_CMRX_PRT_CBFC_CTL 0x5B08 66#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_RX_SHIFT 33 67#define RPMX_CMRX_PRT_CBFC_CTL_PHYS_BP_SHIFT 16 68#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_TX_SHIFT 0 69#define RPM_PFC_CLASS_MASK GENMASK_ULL(48, 33) 70#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128 71#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_PAD_EN BIT_ULL(11) 72#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8) 73#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD BIT_ULL(7) 74#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8 75#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108 76#define RPM_DEFAULT_PAUSE_TIME 0x7FF 77#define RPMX_CMRX_RX_LOGL_XON 0x4100 78 79#define RPMX_MTI_MAC100X_XIF_MODE 0x8100 80#define RPMX_ONESTEP_ENABLE BIT_ULL(5) 81#define RPMX_TS_BINARY_MODE BIT_ULL(11) 82#define RPMX_CONST1 0x2008 83 84/* FEC stats */ 85#define RPMX_MTI_STAT_STATN_CONTROL 0x10018 86#define RPMX_MTI_STAT_DATA_HI_CDC 0x10038 87#define RPMX_RSFEC_RX_CAPTURE BIT_ULL(27) 88#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x40050 89#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x40058 90#define RPMX_MTI_FCFECX_VL0_CCW_LO 0x38618 91#define RPMX_MTI_FCFECX_VL0_NCCW_LO 0x38620 92#define RPMX_MTI_FCFECX_VL1_CCW_LO 0x38628 93#define RPMX_MTI_FCFECX_VL1_NCCW_LO 0x38630 94#define RPMX_MTI_FCFECX_CW_HI 0x38638 95 96/* CN10KB CSR Declaration */ 97#define RPM2_CMRX_SW_INT 0x1b0 98#define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8 99#define RPM2_LMAC_FWI 0x12 100#define RPM2_CMR_CHAN_MSK_OR 0x3120 101#define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2) 102#define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1) 103#define RPM2_CMR_RX_OVR_BP 0x3130 104#define RPM2_CSR_OFFSET 0x3e00 105#define RPM2_CMRX_PRT_CBFC_CTL 0x6510 106#define RPM2_CMRX_RX_LMACS 0x100 107#define RPM2_CMRX_RX_LOGL_XON 0x3100 108#define RPM2_CMRX_RX_STAT2 0x3010 109#define RPM2_USX_PCSX_CONTROL1 0x80000 110#define RPM2_USX_PCS_LBK BIT_ULL(14) 111 112/* Function Declarations */ 113int rpm_get_nr_lmacs(void *rpmd); 114u8 rpm_get_lmac_type(void *rpmd, int lmac_id); 115u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id); 116u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id); 117int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable); 118void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable); 119int rpm_lmac_get_pause_frm_status(void *cgxd, int lmac_id, u8 *tx_pause, 120 u8 *rx_pause); 121void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable); 122int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 123 u8 rx_pause); 124int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat); 125int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat); 126void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable); 127int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable); 128int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable); 129int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, 130 u16 pfc_en); 131int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, 132 u8 *rx_pause); 133int rpm2_get_nr_lmacs(void *rpmd); 134bool is_dev_rpm2(void *rpmd); 135int rpm_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); 136int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr); 137#endif /* RPM_H */ 138