1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef NPC_H 9#define NPC_H 10 11#define NPC_KEX_CHAN_MASK 0xFFFULL 12 13#define SET_KEX_LD(intf, lid, ltype, ld, cfg) \ 14 rvu_write64(rvu, blkaddr, \ 15 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg) 16 17#define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \ 18 rvu_write64(rvu, blkaddr, \ 19 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg) 20 21enum NPC_LID_E { 22 NPC_LID_LA = 0, 23 NPC_LID_LB, 24 NPC_LID_LC, 25 NPC_LID_LD, 26 NPC_LID_LE, 27 NPC_LID_LF, 28 NPC_LID_LG, 29 NPC_LID_LH, 30}; 31 32#define NPC_LT_NA 0 33 34enum npc_kpu_la_ltype { 35 NPC_LT_LA_8023 = 1, 36 NPC_LT_LA_ETHER, 37 NPC_LT_LA_IH_NIX_ETHER, 38 NPC_LT_LA_HIGIG2_ETHER = 7, 39 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 40 NPC_LT_LA_CUSTOM_L2_90B_ETHER, 41 NPC_LT_LA_CPT_HDR, 42 NPC_LT_LA_CUSTOM_L2_24B_ETHER, 43 NPC_LT_LA_CUSTOM_PRE_L2_ETHER, 44 NPC_LT_LA_CUSTOM0 = 0xE, 45 NPC_LT_LA_CUSTOM1 = 0xF, 46}; 47 48enum npc_kpu_lb_ltype { 49 NPC_LT_LB_ETAG = 1, 50 NPC_LT_LB_CTAG, 51 NPC_LT_LB_STAG_QINQ, 52 NPC_LT_LB_BTAG, 53 NPC_LT_LB_PPPOE, 54 NPC_LT_LB_DSA, 55 NPC_LT_LB_DSA_VLAN, 56 NPC_LT_LB_EDSA, 57 NPC_LT_LB_EDSA_VLAN, 58 NPC_LT_LB_EXDSA, 59 NPC_LT_LB_EXDSA_VLAN, 60 NPC_LT_LB_FDSA, 61 NPC_LT_LB_VLAN_EXDSA, 62 NPC_LT_LB_CUSTOM0 = 0xE, 63 NPC_LT_LB_CUSTOM1 = 0xF, 64}; 65 66enum npc_kpu_lc_ltype { 67 NPC_LT_LC_IP = 1, 68 NPC_LT_LC_IP_OPT, 69 NPC_LT_LC_IP6, 70 NPC_LT_LC_IP6_EXT, 71 NPC_LT_LC_ARP, 72 NPC_LT_LC_RARP, 73 NPC_LT_LC_MPLS, 74 NPC_LT_LC_NSH, 75 NPC_LT_LC_PTP, 76 NPC_LT_LC_FCOE, 77 NPC_LT_LC_NGIO, 78 NPC_LT_LC_CUSTOM0 = 0xE, 79 NPC_LT_LC_CUSTOM1 = 0xF, 80}; 81 82/* Don't modify Ltypes upto SCTP, otherwise it will 83 * effect flow tag calculation and thus RSS. 84 */ 85enum npc_kpu_ld_ltype { 86 NPC_LT_LD_TCP = 1, 87 NPC_LT_LD_UDP, 88 NPC_LT_LD_ICMP, 89 NPC_LT_LD_SCTP, 90 NPC_LT_LD_ICMP6, 91 NPC_LT_LD_CUSTOM0, 92 NPC_LT_LD_CUSTOM1, 93 NPC_LT_LD_IGMP = 8, 94 NPC_LT_LD_AH, 95 NPC_LT_LD_GRE, 96 NPC_LT_LD_NVGRE, 97 NPC_LT_LD_NSH, 98 NPC_LT_LD_TU_MPLS_IN_NSH, 99 NPC_LT_LD_TU_MPLS_IN_IP, 100}; 101 102enum npc_kpu_le_ltype { 103 NPC_LT_LE_VXLAN = 1, 104 NPC_LT_LE_GENEVE, 105 NPC_LT_LE_ESP, 106 NPC_LT_LE_GTPU = 4, 107 NPC_LT_LE_VXLANGPE, 108 NPC_LT_LE_GTPC, 109 NPC_LT_LE_NSH, 110 NPC_LT_LE_TU_MPLS_IN_GRE, 111 NPC_LT_LE_TU_NSH_IN_GRE, 112 NPC_LT_LE_TU_MPLS_IN_UDP, 113 NPC_LT_LE_CUSTOM0 = 0xE, 114 NPC_LT_LE_CUSTOM1 = 0xF, 115}; 116 117enum npc_kpu_lf_ltype { 118 NPC_LT_LF_TU_ETHER = 1, 119 NPC_LT_LF_TU_PPP, 120 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 121 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 122 NPC_LT_LF_TU_MPLS_IN_NSH, 123 NPC_LT_LF_TU_3RD_NSH, 124 NPC_LT_LF_CUSTOM0 = 0xE, 125 NPC_LT_LF_CUSTOM1 = 0xF, 126}; 127 128enum npc_kpu_lg_ltype { 129 NPC_LT_LG_TU_IP = 1, 130 NPC_LT_LG_TU_IP6, 131 NPC_LT_LG_TU_ARP, 132 NPC_LT_LG_TU_ETHER_IN_NSH, 133 NPC_LT_LG_CUSTOM0 = 0xE, 134 NPC_LT_LG_CUSTOM1 = 0xF, 135}; 136 137/* Don't modify Ltypes upto SCTP, otherwise it will 138 * effect flow tag calculation and thus RSS. 139 */ 140enum npc_kpu_lh_ltype { 141 NPC_LT_LH_TU_TCP = 1, 142 NPC_LT_LH_TU_UDP, 143 NPC_LT_LH_TU_ICMP, 144 NPC_LT_LH_TU_SCTP, 145 NPC_LT_LH_TU_ICMP6, 146 NPC_LT_LH_TU_IGMP = 8, 147 NPC_LT_LH_TU_ESP, 148 NPC_LT_LH_TU_AH, 149 NPC_LT_LH_CUSTOM0 = 0xE, 150 NPC_LT_LH_CUSTOM1 = 0xF, 151}; 152 153/* NPC port kind defines how the incoming or outgoing packets 154 * are processed. NPC accepts packets from up to 64 pkinds. 155 * Software assigns pkind for each incoming port such as CGX 156 * Ethernet interfaces, LBK interfaces, etc. 157 */ 158#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CUSTOM_PRE_L2_PKIND 159 160enum npc_pkind_type { 161 NPC_RX_LBK_PKIND = 0ULL, 162 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL, 163 NPC_RX_VLAN_EXDSA_PKIND = 56ULL, 164 NPC_RX_CHLEN24B_PKIND = 57ULL, 165 NPC_RX_CPT_HDR_PKIND, 166 NPC_RX_CHLEN90B_PKIND, 167 NPC_TX_HIGIG_PKIND, 168 NPC_RX_HIGIG_PKIND, 169 NPC_RX_EDSA_PKIND, 170 NPC_TX_DEF_PKIND, /* NIX-TX PKIND */ 171}; 172 173enum npc_interface_type { 174 NPC_INTF_MODE_DEF, 175}; 176 177/* list of known and supported fields in packet header and 178 * fields present in key structure. 179 */ 180enum key_fields { 181 NPC_DMAC, 182 NPC_SMAC, 183 NPC_ETYPE, 184 NPC_VLAN_ETYPE_CTAG, /* 0x8100 */ 185 NPC_VLAN_ETYPE_STAG, /* 0x88A8 */ 186 NPC_OUTER_VID, 187 NPC_INNER_VID, 188 NPC_TOS, 189 NPC_IPFRAG_IPV4, 190 NPC_SIP_IPV4, 191 NPC_DIP_IPV4, 192 NPC_IPFRAG_IPV6, 193 NPC_SIP_IPV6, 194 NPC_DIP_IPV6, 195 NPC_IPPROTO_TCP, 196 NPC_IPPROTO_UDP, 197 NPC_IPPROTO_SCTP, 198 NPC_IPPROTO_AH, 199 NPC_IPPROTO_ESP, 200 NPC_IPPROTO_ICMP, 201 NPC_IPPROTO_ICMP6, 202 NPC_SPORT_TCP, 203 NPC_DPORT_TCP, 204 NPC_SPORT_UDP, 205 NPC_DPORT_UDP, 206 NPC_SPORT_SCTP, 207 NPC_DPORT_SCTP, 208 NPC_IPSEC_SPI, 209 NPC_HEADER_FIELDS_MAX, 210 NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */ 211 NPC_PF_FUNC, /* Valid when Tx */ 212 NPC_ERRLEV, 213 NPC_ERRCODE, 214 NPC_LXMB, 215 NPC_EXACT_RESULT, 216 NPC_LA, 217 NPC_LB, 218 NPC_LC, 219 NPC_LD, 220 NPC_LE, 221 NPC_LF, 222 NPC_LG, 223 NPC_LH, 224 /* Ethertype for untagged frame */ 225 NPC_ETYPE_ETHER, 226 /* Ethertype for single tagged frame */ 227 NPC_ETYPE_TAG1, 228 /* Ethertype for double tagged frame */ 229 NPC_ETYPE_TAG2, 230 /* outer vlan tci for single tagged frame */ 231 NPC_VLAN_TAG1, 232 /* outer vlan tci for double tagged frame */ 233 NPC_VLAN_TAG2, 234 /* inner vlan tci for double tagged frame */ 235 NPC_VLAN_TAG3, 236 /* other header fields programmed to extract but not of our interest */ 237 NPC_UNKNOWN, 238 NPC_KEY_FIELDS_MAX, 239}; 240 241struct npc_kpu_profile_cam { 242 u8 state; 243 u8 state_mask; 244 u16 dp0; 245 u16 dp0_mask; 246 u16 dp1; 247 u16 dp1_mask; 248 u16 dp2; 249 u16 dp2_mask; 250} __packed; 251 252struct npc_kpu_profile_action { 253 u8 errlev; 254 u8 errcode; 255 u8 dp0_offset; 256 u8 dp1_offset; 257 u8 dp2_offset; 258 u8 bypass_count; 259 u8 parse_done; 260 u8 next_state; 261 u8 ptr_advance; 262 u8 cap_ena; 263 u8 lid; 264 u8 ltype; 265 u8 flags; 266 u8 offset; 267 u8 mask; 268 u8 right; 269 u8 shift; 270} __packed; 271 272struct npc_kpu_profile { 273 int cam_entries; 274 int action_entries; 275 struct npc_kpu_profile_cam *cam; 276 struct npc_kpu_profile_action *action; 277}; 278 279/* NPC KPU register formats */ 280struct npc_kpu_cam { 281#if defined(__BIG_ENDIAN_BITFIELD) 282 u64 rsvd_63_56 : 8; 283 u64 state : 8; 284 u64 dp2_data : 16; 285 u64 dp1_data : 16; 286 u64 dp0_data : 16; 287#else 288 u64 dp0_data : 16; 289 u64 dp1_data : 16; 290 u64 dp2_data : 16; 291 u64 state : 8; 292 u64 rsvd_63_56 : 8; 293#endif 294}; 295 296struct npc_kpu_action0 { 297#if defined(__BIG_ENDIAN_BITFIELD) 298 u64 rsvd_63_57 : 7; 299 u64 byp_count : 3; 300 u64 capture_ena : 1; 301 u64 parse_done : 1; 302 u64 next_state : 8; 303 u64 rsvd_43 : 1; 304 u64 capture_lid : 3; 305 u64 capture_ltype : 4; 306 u64 capture_flags : 8; 307 u64 ptr_advance : 8; 308 u64 var_len_offset : 8; 309 u64 var_len_mask : 8; 310 u64 var_len_right : 1; 311 u64 var_len_shift : 3; 312#else 313 u64 var_len_shift : 3; 314 u64 var_len_right : 1; 315 u64 var_len_mask : 8; 316 u64 var_len_offset : 8; 317 u64 ptr_advance : 8; 318 u64 capture_flags : 8; 319 u64 capture_ltype : 4; 320 u64 capture_lid : 3; 321 u64 rsvd_43 : 1; 322 u64 next_state : 8; 323 u64 parse_done : 1; 324 u64 capture_ena : 1; 325 u64 byp_count : 3; 326 u64 rsvd_63_57 : 7; 327#endif 328}; 329 330struct npc_kpu_action1 { 331#if defined(__BIG_ENDIAN_BITFIELD) 332 u64 rsvd_63_36 : 28; 333 u64 errlev : 4; 334 u64 errcode : 8; 335 u64 dp2_offset : 8; 336 u64 dp1_offset : 8; 337 u64 dp0_offset : 8; 338#else 339 u64 dp0_offset : 8; 340 u64 dp1_offset : 8; 341 u64 dp2_offset : 8; 342 u64 errcode : 8; 343 u64 errlev : 4; 344 u64 rsvd_63_36 : 28; 345#endif 346}; 347 348struct npc_kpu_pkind_cpi_def { 349#if defined(__BIG_ENDIAN_BITFIELD) 350 u64 ena : 1; 351 u64 rsvd_62_59 : 4; 352 u64 lid : 3; 353 u64 ltype_match : 4; 354 u64 ltype_mask : 4; 355 u64 flags_match : 8; 356 u64 flags_mask : 8; 357 u64 add_offset : 8; 358 u64 add_mask : 8; 359 u64 rsvd_15 : 1; 360 u64 add_shift : 3; 361 u64 rsvd_11_10 : 2; 362 u64 cpi_base : 10; 363#else 364 u64 cpi_base : 10; 365 u64 rsvd_11_10 : 2; 366 u64 add_shift : 3; 367 u64 rsvd_15 : 1; 368 u64 add_mask : 8; 369 u64 add_offset : 8; 370 u64 flags_mask : 8; 371 u64 flags_match : 8; 372 u64 ltype_mask : 4; 373 u64 ltype_match : 4; 374 u64 lid : 3; 375 u64 rsvd_62_59 : 4; 376 u64 ena : 1; 377#endif 378}; 379 380struct nix_rx_action { 381#if defined(__BIG_ENDIAN_BITFIELD) 382 u64 rsvd_63_61 :3; 383 u64 flow_key_alg :5; 384 u64 match_id :16; 385 u64 index :20; 386 u64 pf_func :16; 387 u64 op :4; 388#else 389 u64 op :4; 390 u64 pf_func :16; 391 u64 index :20; 392 u64 match_id :16; 393 u64 flow_key_alg :5; 394 u64 rsvd_63_61 :3; 395#endif 396}; 397 398/* NPC_AF_INTFX_KEX_CFG field masks */ 399#define NPC_EXACT_NIBBLE_START 40 400#define NPC_EXACT_NIBBLE_END 43 401#define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40) 402 403/* NPC_EXACT_KEX_S nibble definitions for each field */ 404#define NPC_EXACT_NIBBLE_HIT BIT_ULL(40) 405#define NPC_EXACT_NIBBLE_OPC BIT_ULL(40) 406#define NPC_EXACT_NIBBLE_WAY BIT_ULL(40) 407#define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41) 408 409#define NPC_EXACT_RESULT_HIT BIT_ULL(0) 410#define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1) 411#define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3) 412#define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5) 413 414/* NPC_AF_INTFX_KEX_CFG field masks */ 415#define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 416 417/* NPC_PARSE_KEX_S nibble definitions for each field */ 418#define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 419#define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 420#define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 421#define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 422#define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 423#define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 424#define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 425#define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 426#define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 427#define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 428#define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 429#define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 430#define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 431#define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 432#define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 433#define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 434#define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 435#define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 436#define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 437#define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 438 439struct nix_tx_action { 440#if defined(__BIG_ENDIAN_BITFIELD) 441 u64 rsvd_63_48 :16; 442 u64 match_id :16; 443 u64 index :20; 444 u64 rsvd_11_8 :8; 445 u64 op :4; 446#else 447 u64 op :4; 448 u64 rsvd_11_8 :8; 449 u64 index :20; 450 u64 match_id :16; 451 u64 rsvd_63_48 :16; 452#endif 453}; 454 455/* NIX Receive Vtag Action Structure */ 456#define RX_VTAG0_VALID_BIT BIT_ULL(15) 457#define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 458#define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 459#define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 460#define RX_VTAG1_VALID_BIT BIT_ULL(47) 461#define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44) 462#define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 463#define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 464 465/* NIX Transmit Vtag Action Structure */ 466#define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16) 467#define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12) 468#define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 469#define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 470#define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48) 471#define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44) 472#define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 473#define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 474 475/* NPC MCAM reserved entry index per nixlf */ 476#define NIXLF_UCAST_ENTRY 0 477#define NIXLF_BCAST_ENTRY 1 478#define NIXLF_ALLMULTI_ENTRY 2 479#define NIXLF_PROMISC_ENTRY 3 480 481struct npc_coalesced_kpu_prfl { 482#define NPC_SIGN 0x00666f727063706e 483#define NPC_PRFL_NAME "npc_prfls_array" 484#define NPC_NAME_LEN 32 485 __le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */ 486 u8 name[NPC_NAME_LEN]; /* KPU Profile name */ 487 u64 version; /* KPU firmware/profile version */ 488 u8 num_prfl; /* No of NPC profiles. */ 489 u16 prfl_sz[]; 490}; 491 492struct npc_mcam_kex { 493 /* MKEX Profle Header */ 494 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 495 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 496 u64 cpu_model; /* Format as profiled by CPU hardware */ 497 u64 kpu_version; /* KPU firmware/profile version */ 498 u64 reserved; /* Reserved for extension */ 499 500 /* MKEX Profle Data */ 501 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 502 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 503 u64 kex_ld_flags[NPC_MAX_LD]; 504 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 505 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 506 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 507 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 508} __packed; 509 510struct npc_kpu_fwdata { 511 int entries; 512 /* What follows is: 513 * struct npc_kpu_profile_cam[entries]; 514 * struct npc_kpu_profile_action[entries]; 515 */ 516 u8 data[]; 517} __packed; 518 519struct npc_lt_def { 520 u8 ltype_mask; 521 u8 ltype_match; 522 u8 lid; 523} __packed; 524 525struct npc_lt_def_ipsec { 526 u8 ltype_mask; 527 u8 ltype_match; 528 u8 lid; 529 u8 spi_offset; 530 u8 spi_nz; 531} __packed; 532 533struct npc_lt_def_apad { 534 u8 ltype_mask; 535 u8 ltype_match; 536 u8 lid; 537 u8 valid; 538} __packed; 539 540struct npc_lt_def_color { 541 u8 ltype_mask; 542 u8 ltype_match; 543 u8 lid; 544 u8 noffset; 545 u8 offset; 546} __packed; 547 548struct npc_lt_def_et { 549 u8 ltype_mask; 550 u8 ltype_match; 551 u8 lid; 552 u8 valid; 553 u8 offset; 554} __packed; 555 556struct npc_lt_def_cfg { 557 struct npc_lt_def rx_ol2; 558 struct npc_lt_def rx_oip4; 559 struct npc_lt_def rx_iip4; 560 struct npc_lt_def rx_oip6; 561 struct npc_lt_def rx_iip6; 562 struct npc_lt_def rx_otcp; 563 struct npc_lt_def rx_itcp; 564 struct npc_lt_def rx_oudp; 565 struct npc_lt_def rx_iudp; 566 struct npc_lt_def rx_osctp; 567 struct npc_lt_def rx_isctp; 568 struct npc_lt_def_ipsec rx_ipsec[2]; 569 struct npc_lt_def pck_ol2; 570 struct npc_lt_def pck_oip4; 571 struct npc_lt_def pck_oip6; 572 struct npc_lt_def pck_iip4; 573 struct npc_lt_def_apad rx_apad0; 574 struct npc_lt_def_apad rx_apad1; 575 struct npc_lt_def_color ovlan; 576 struct npc_lt_def_color ivlan; 577 struct npc_lt_def_color rx_gen0_color; 578 struct npc_lt_def_color rx_gen1_color; 579 struct npc_lt_def_et rx_et[2]; 580} __packed; 581 582/* Loadable KPU profile firmware data */ 583struct npc_kpu_profile_fwdata { 584#define KPU_SIGN 0x00666f727075706b 585#define KPU_NAME_LEN 32 586/** Maximum number of custom KPU entries supported by the built-in profile. */ 587#define KPU_MAX_CST_ENT 6 588 /* KPU Profle Header */ 589 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 590 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 591 __le64 version; /* KPU profile version */ 592 u8 kpus; 593 u8 reserved[7]; 594 595 /* Default MKEX profile to be used with this KPU profile. May be 596 * overridden with mkex_profile module parameter. Format is same as for 597 * the MKEX profile to streamline processing. 598 */ 599 struct npc_mcam_kex mkex; 600 /* LTYPE values for specific HW offloaded protocols. */ 601 struct npc_lt_def_cfg lt_def; 602 /* Dynamically sized data: 603 * Custom KPU CAM and ACTION configuration entries. 604 * struct npc_kpu_fwdata kpu[kpus]; 605 */ 606 u8 data[]; 607} __packed; 608 609struct rvu_npc_mcam_rule { 610 struct flow_msg packet; 611 struct flow_msg mask; 612 u8 intf; 613 union { 614 struct nix_tx_action tx_action; 615 struct nix_rx_action rx_action; 616 }; 617 u64 vtag_action; 618 struct list_head list; 619 u64 features; 620 u16 owner; 621 u16 entry; 622 u16 cntr; 623 bool has_cntr; 624 u8 default_rule; 625 bool enable; 626 bool vfvlan_cfg; 627 u16 chan; 628 u16 chan_mask; 629 u8 lxmb; 630}; 631 632#endif /* NPC_H */ 633