1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef MBOX_H 9#define MBOX_H 10 11#include <linux/etherdevice.h> 12#include <linux/sizes.h> 13 14#include "rvu_struct.h" 15#include "common.h" 16 17#define MBOX_SIZE SZ_64K 18 19#define MBOX_DOWN_MSG 1 20#define MBOX_UP_MSG 2 21 22/* AF/PF: PF initiated, PF/VF VF initiated */ 23#define MBOX_DOWN_RX_START 0 24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27/* AF/PF: AF initiated, PF/VF PF initiated */ 28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29#define MBOX_UP_RX_SIZE SZ_1K 30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31#define MBOX_UP_TX_SIZE SZ_1K 32 33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34# error "incorrect mailbox area sizes" 35#endif 36 37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39#define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 40 41#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43/* Mailbox directions */ 44#define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46#define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61}; 62 63struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75}; 76 77/* Header which precedes all mbox messages */ 78struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81}; 82 83/* Header which precedes every msg and is also part of it */ 84struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87#define OTX2_MBOX_REQ_SIG (0xdead) 88#define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90#define OTX2_MBOX_VERSION (0x000a) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94}; 95 96void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98void otx2_mbox_destroy(struct otx2_mbox *mbox); 99int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 103int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 104 struct pci_dev *pdev, void __force *reg_base, 105 int direction, int ndevs, unsigned long *bmap); 106void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 107void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 108int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 109int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 110struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 111 int size, int size_rsp); 112struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 113 struct mbox_msghdr *msg); 114int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 115int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 116 u16 pcifunc, u16 id); 117bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 118const char *otx2_mbox_id2name(u16 id); 119static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 120 int devid, int size) 121{ 122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 123} 124 125bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 126 127/* Mailbox message types */ 128#define MBOX_MSG_MASK 0xFFFF 129#define MBOX_MSG_INVALID 0xFFFE 130#define MBOX_MSG_MAX 0xFFFF 131 132#define MBOX_MESSAGES \ 133/* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 134M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 135M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 136M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 137M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 138M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 139M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 143 msg_rsp) \ 144M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 145M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 146/* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 147M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 148M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 149M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 150M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 151 cgx_mac_addr_set_or_get) \ 152M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 153 cgx_mac_addr_set_or_get) \ 154M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 155M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 156M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 157M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 158M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 159M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 160M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 161M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 162M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 163M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 164 cgx_pause_frm_cfg) \ 165M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 166M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 167M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 168 cgx_mac_addr_add_rsp) \ 169M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 170 msg_rsp) \ 171M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 172 cgx_max_dmac_entries_get_rsp) \ 173M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 174M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 175 cgx_set_link_mode_rsp) \ 176M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 177M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 178 cgx_features_info_msg) \ 179M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 180M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 181 msg_rsp) \ 182M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 183 cgx_mac_addr_update_rsp) \ 184M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 185 cgx_pfc_rsp) \ 186/* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 187M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 188 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 189M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 190M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 191M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 192/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 193/* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 194/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 195M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 196 msg_rsp) \ 197M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 198M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 199 cpt_rd_wr_reg_msg) \ 200M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 201 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 202M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 203M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 204 msg_rsp) \ 205M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 206M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 207M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 208 cpt_flt_eng_info_rsp) \ 209/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 210M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 211M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 212/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 213M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 214 npc_mcam_alloc_entry_rsp) \ 215M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 216 npc_mcam_free_entry_req, msg_rsp) \ 217M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 218 npc_mcam_write_entry_req, msg_rsp) \ 219M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 220 npc_mcam_ena_dis_entry_req, msg_rsp) \ 221M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 222 npc_mcam_ena_dis_entry_req, msg_rsp) \ 223M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 224 npc_mcam_shift_entry_rsp) \ 225M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 226 npc_mcam_alloc_counter_req, \ 227 npc_mcam_alloc_counter_rsp) \ 228M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 229 npc_mcam_oper_counter_req, msg_rsp) \ 230M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 231 npc_mcam_unmap_counter_req, msg_rsp) \ 232M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 233 npc_mcam_oper_counter_req, msg_rsp) \ 234M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 235 npc_mcam_oper_counter_req, \ 236 npc_mcam_oper_counter_rsp) \ 237M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 238 npc_mcam_alloc_and_write_entry_req, \ 239 npc_mcam_alloc_and_write_entry_rsp) \ 240M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 241 msg_req, npc_get_kex_cfg_rsp) \ 242M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 243 npc_install_flow_req, npc_install_flow_rsp) \ 244M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 245 npc_delete_flow_req, npc_delete_flow_rsp) \ 246M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 247 npc_mcam_read_entry_req, \ 248 npc_mcam_read_entry_rsp) \ 249M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 250 npc_set_pkind, msg_rsp) \ 251M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 252 msg_req, npc_mcam_read_base_rule_rsp) \ 253M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 254 npc_mcam_get_stats_req, \ 255 npc_mcam_get_stats_rsp) \ 256M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 257 npc_get_field_hash_info_req, \ 258 npc_get_field_hash_info_rsp) \ 259M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 260 npc_get_field_status_req, \ 261 npc_get_field_status_rsp) \ 262/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 263M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 264 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 265M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 266M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 267M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 268 hwctx_disable_req, msg_rsp) \ 269M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 270 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 271M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 272M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 273 nix_txschq_config) \ 274M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 275M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 276 nix_vtag_config_rsp) \ 277M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 278 nix_rss_flowkey_cfg, \ 279 nix_rss_flowkey_cfg_rsp) \ 280M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 281M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 282M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 283M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 284M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 285M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 286 nix_mark_format_cfg, \ 287 nix_mark_format_cfg_rsp) \ 288M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 289M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 290 nix_lso_format_cfg, \ 291 nix_lso_format_cfg_rsp) \ 292M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 293M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 294M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 295 nix_bp_cfg_rsp) \ 296M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 297M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 298M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 299 nix_inline_ipsec_cfg, msg_rsp) \ 300M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 301 nix_inline_ipsec_lf_cfg, msg_rsp) \ 302M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 303 nix_cn10k_aq_enq_rsp) \ 304M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 305M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 306 nix_bandprof_alloc_rsp) \ 307M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 308 msg_rsp) \ 309M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 310 nix_bandprof_get_hwinfo_rsp) \ 311M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 312 msg_req, nix_inline_ipsec_cfg) \ 313/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 314M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 315 mcs_alloc_rsrc_rsp) \ 316M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 317M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 318 msg_rsp) \ 319M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 320 msg_rsp) \ 321M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 322 msg_rsp) \ 323M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 324 msg_rsp) \ 325M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 326 msg_rsp) \ 327M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 328 msg_rsp) \ 329M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 330 msg_rsp) \ 331M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 332 msg_rsp) \ 333M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 334 msg_rsp) \ 335M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 336M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 337 mcs_flowid_stats) \ 338M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 339 mcs_secy_stats) \ 340M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 341M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 342M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 343 mcs_port_stats) \ 344M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 345M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 346M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 347M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 348 msg_rsp) \ 349M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 350 mcs_alloc_ctrl_pkt_rule_req, \ 351 mcs_alloc_ctrl_pkt_rule_rsp) \ 352M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 353 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 354M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 355 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 356M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 357M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 358M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 359 mcs_port_cfg_get_rsp) \ 360M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 361 mcs_custom_tag_cfg_get_req, \ 362 mcs_custom_tag_cfg_get_rsp) 363 364/* Messages initiated by AF (range 0xC00 - 0xEFF) */ 365#define MBOX_UP_CGX_MESSAGES \ 366M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 367 368#define MBOX_UP_CPT_MESSAGES \ 369M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 370 371#define MBOX_UP_MCS_MESSAGES \ 372M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 373 374enum { 375#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 376MBOX_MESSAGES 377MBOX_UP_CGX_MESSAGES 378MBOX_UP_CPT_MESSAGES 379MBOX_UP_MCS_MESSAGES 380#undef M 381}; 382 383/* Mailbox message formats */ 384 385#define RVU_DEFAULT_PF_FUNC 0xFFFF 386 387/* Generic request msg used for those mbox messages which 388 * don't send any data in the request. 389 */ 390struct msg_req { 391 struct mbox_msghdr hdr; 392}; 393 394/* Generic response msg used an ack or response for those mbox 395 * messages which don't have a specific rsp msg format. 396 */ 397struct msg_rsp { 398 struct mbox_msghdr hdr; 399}; 400 401/* RVU mailbox error codes 402 * Range 256 - 300. 403 */ 404enum rvu_af_status { 405 RVU_INVALID_VF_ID = -256, 406}; 407 408struct ready_msg_rsp { 409 struct mbox_msghdr hdr; 410 u16 sclk_freq; /* SCLK frequency (in MHz) */ 411 u16 rclk_freq; /* RCLK frequency (in MHz) */ 412}; 413 414/* Structure for requesting resource provisioning. 415 * 'modify' flag to be used when either requesting more 416 * or to detach partial of a certain resource type. 417 * Rest of the fields specify how many of what type to 418 * be attached. 419 * To request LFs from two blocks of same type this mailbox 420 * can be sent twice as below: 421 * struct rsrc_attach *attach; 422 * .. Allocate memory for message .. 423 * attach->cptlfs = 3; <3 LFs from CPT0> 424 * .. Send message .. 425 * .. Allocate memory for message .. 426 * attach->modify = 1; 427 * attach->cpt_blkaddr = BLKADDR_CPT1; 428 * attach->cptlfs = 2; <2 LFs from CPT1> 429 * .. Send message .. 430 */ 431struct rsrc_attach { 432 struct mbox_msghdr hdr; 433 u8 modify:1; 434 u8 npalf:1; 435 u8 nixlf:1; 436 u16 sso; 437 u16 ssow; 438 u16 timlfs; 439 u16 cptlfs; 440 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 441}; 442 443/* Structure for relinquishing resources. 444 * 'partial' flag to be used when relinquishing all resources 445 * but only of a certain type. If not set, all resources of all 446 * types provisioned to the RVU function will be detached. 447 */ 448struct rsrc_detach { 449 struct mbox_msghdr hdr; 450 u8 partial:1; 451 u8 npalf:1; 452 u8 nixlf:1; 453 u8 sso:1; 454 u8 ssow:1; 455 u8 timlfs:1; 456 u8 cptlfs:1; 457}; 458 459/* Number of resources available to the caller. 460 * In reply to MBOX_MSG_FREE_RSRC_CNT. 461 */ 462struct free_rsrcs_rsp { 463 struct mbox_msghdr hdr; 464 u16 schq[NIX_TXSCH_LVL_CNT]; 465 u16 sso; 466 u16 tim; 467 u16 ssow; 468 u16 cpt; 469 u8 npa; 470 u8 nix; 471 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 472 u8 nix1; 473 u8 cpt1; 474 u8 ree0; 475 u8 ree1; 476}; 477 478#define MSIX_VECTOR_INVALID 0xFFFF 479#define MAX_RVU_BLKLF_CNT 256 480 481struct msix_offset_rsp { 482 struct mbox_msghdr hdr; 483 u16 npa_msixoff; 484 u16 nix_msixoff; 485 u16 sso; 486 u16 ssow; 487 u16 timlfs; 488 u16 cptlfs; 489 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 490 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 491 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 492 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 493 u16 cpt1_lfs; 494 u16 ree0_lfs; 495 u16 ree1_lfs; 496 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 497 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 498 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 499}; 500 501struct get_hw_cap_rsp { 502 struct mbox_msghdr hdr; 503 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 504 u8 nix_shaping; /* Is shaping and coloring supported */ 505 u8 npc_hash_extract; /* Is hash extract supported */ 506}; 507 508/* CGX mbox message formats */ 509 510struct cgx_stats_rsp { 511 struct mbox_msghdr hdr; 512#define CGX_RX_STATS_COUNT 9 513#define CGX_TX_STATS_COUNT 18 514 u64 rx_stats[CGX_RX_STATS_COUNT]; 515 u64 tx_stats[CGX_TX_STATS_COUNT]; 516}; 517 518struct cgx_fec_stats_rsp { 519 struct mbox_msghdr hdr; 520 u64 fec_corr_blks; 521 u64 fec_uncorr_blks; 522}; 523/* Structure for requesting the operation for 524 * setting/getting mac address in the CGX interface 525 */ 526struct cgx_mac_addr_set_or_get { 527 struct mbox_msghdr hdr; 528 u8 mac_addr[ETH_ALEN]; 529 u32 index; 530}; 531 532/* Structure for requesting the operation to 533 * add DMAC filter entry into CGX interface 534 */ 535struct cgx_mac_addr_add_req { 536 struct mbox_msghdr hdr; 537 u8 mac_addr[ETH_ALEN]; 538}; 539 540/* Structure for response against the operation to 541 * add DMAC filter entry into CGX interface 542 */ 543struct cgx_mac_addr_add_rsp { 544 struct mbox_msghdr hdr; 545 u32 index; 546}; 547 548/* Structure for requesting the operation to 549 * delete DMAC filter entry from CGX interface 550 */ 551struct cgx_mac_addr_del_req { 552 struct mbox_msghdr hdr; 553 u32 index; 554}; 555 556/* Structure for response against the operation to 557 * get maximum supported DMAC filter entries 558 */ 559struct cgx_max_dmac_entries_get_rsp { 560 struct mbox_msghdr hdr; 561 u32 max_dmac_filters; 562}; 563 564struct cgx_link_user_info { 565 uint64_t link_up:1; 566 uint64_t full_duplex:1; 567 uint64_t lmac_type_id:4; 568 uint64_t speed:20; /* speed in Mbps */ 569 uint64_t an:1; /* AN supported or not */ 570 uint64_t fec:2; /* FEC type if enabled else 0 */ 571#define LMACTYPE_STR_LEN 16 572 char lmac_type[LMACTYPE_STR_LEN]; 573}; 574 575struct cgx_link_info_msg { 576 struct mbox_msghdr hdr; 577 struct cgx_link_user_info link_info; 578}; 579 580struct cgx_pause_frm_cfg { 581 struct mbox_msghdr hdr; 582 u8 set; 583 /* set = 1 if the request is to config pause frames */ 584 /* set = 0 if the request is to fetch pause frames config */ 585 u8 rx_pause; 586 u8 tx_pause; 587}; 588 589enum fec_type { 590 OTX2_FEC_NONE, 591 OTX2_FEC_BASER, 592 OTX2_FEC_RS, 593 OTX2_FEC_STATS_CNT = 2, 594 OTX2_FEC_OFF, 595}; 596 597struct fec_mode { 598 struct mbox_msghdr hdr; 599 int fec; 600}; 601 602struct sfp_eeprom_s { 603#define SFP_EEPROM_SIZE 256 604 u16 sff_id; 605 u8 buf[SFP_EEPROM_SIZE]; 606 u64 reserved; 607}; 608 609struct phy_s { 610 struct { 611 u64 can_change_mod_type:1; 612 u64 mod_type:1; 613 u64 has_fec_stats:1; 614 } misc; 615 struct fec_stats_s { 616 u32 rsfec_corr_cws; 617 u32 rsfec_uncorr_cws; 618 u32 brfec_corr_blks; 619 u32 brfec_uncorr_blks; 620 } fec_stats; 621}; 622 623struct cgx_lmac_fwdata_s { 624 u16 rw_valid; 625 u64 supported_fec; 626 u64 supported_an; 627 u64 supported_link_modes; 628 /* only applicable if AN is supported */ 629 u64 advertised_fec; 630 u64 advertised_link_modes; 631 /* Only applicable if SFP/QSFP slot is present */ 632 struct sfp_eeprom_s sfp_eeprom; 633 struct phy_s phy; 634#define LMAC_FWDATA_RESERVED_MEM 1021 635 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 636}; 637 638struct cgx_fw_data { 639 struct mbox_msghdr hdr; 640 struct cgx_lmac_fwdata_s fwdata; 641}; 642 643struct cgx_set_link_mode_args { 644 u32 speed; 645 u8 duplex; 646 u8 an; 647 u8 ports; 648 u64 mode; 649}; 650 651struct cgx_set_link_mode_req { 652#define AUTONEG_UNKNOWN 0xff 653 struct mbox_msghdr hdr; 654 struct cgx_set_link_mode_args args; 655}; 656 657struct cgx_set_link_mode_rsp { 658 struct mbox_msghdr hdr; 659 int status; 660}; 661 662struct cgx_mac_addr_reset_req { 663 struct mbox_msghdr hdr; 664 u32 index; 665}; 666 667struct cgx_mac_addr_update_req { 668 struct mbox_msghdr hdr; 669 u8 mac_addr[ETH_ALEN]; 670 u32 index; 671}; 672 673struct cgx_mac_addr_update_rsp { 674 struct mbox_msghdr hdr; 675 u32 index; 676}; 677 678#define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 679#define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 680 /* flow control from physical link higig2 messages */ 681#define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 682#define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 683#define RVU_MAC_VERSION BIT_ULL(4) 684#define RVU_MAC_CGX BIT_ULL(5) 685#define RVU_MAC_RPM BIT_ULL(6) 686 687struct cgx_features_info_msg { 688 struct mbox_msghdr hdr; 689 u64 lmac_features; 690}; 691 692struct rpm_stats_rsp { 693 struct mbox_msghdr hdr; 694#define RPM_RX_STATS_COUNT 43 695#define RPM_TX_STATS_COUNT 34 696 u64 rx_stats[RPM_RX_STATS_COUNT]; 697 u64 tx_stats[RPM_TX_STATS_COUNT]; 698}; 699 700struct cgx_pfc_cfg { 701 struct mbox_msghdr hdr; 702 u8 rx_pause; 703 u8 tx_pause; 704 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 705}; 706 707struct cgx_pfc_rsp { 708 struct mbox_msghdr hdr; 709 u8 rx_pause; 710 u8 tx_pause; 711}; 712 713 /* NPA mbox message formats */ 714 715struct npc_set_pkind { 716 struct mbox_msghdr hdr; 717#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 718#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 719 u64 mode; 720#define PKIND_TX BIT_ULL(0) 721#define PKIND_RX BIT_ULL(1) 722 u8 dir; 723 u8 pkind; /* valid only in case custom flag */ 724 u8 var_len_off; /* Offset of custom header length field. 725 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 726 */ 727 u8 var_len_off_mask; /* Mask for length with in offset */ 728 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 729}; 730 731/* NPA mbox message formats */ 732 733/* NPA mailbox error codes 734 * Range 301 - 400. 735 */ 736enum npa_af_status { 737 NPA_AF_ERR_PARAM = -301, 738 NPA_AF_ERR_AQ_FULL = -302, 739 NPA_AF_ERR_AQ_ENQUEUE = -303, 740 NPA_AF_ERR_AF_LF_INVALID = -304, 741 NPA_AF_ERR_AF_LF_ALLOC = -305, 742 NPA_AF_ERR_LF_RESET = -306, 743}; 744 745/* For NPA LF context alloc and init */ 746struct npa_lf_alloc_req { 747 struct mbox_msghdr hdr; 748 int node; 749 int aura_sz; /* No of auras */ 750 u32 nr_pools; /* No of pools */ 751 u64 way_mask; 752}; 753 754struct npa_lf_alloc_rsp { 755 struct mbox_msghdr hdr; 756 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 757 u32 stack_pg_bytes; /* Size of stack page */ 758 u16 qints; /* NPA_AF_CONST::QINTS */ 759 u8 cache_lines; /*BATCH ALLOC DMA */ 760}; 761 762/* NPA AQ enqueue msg */ 763struct npa_aq_enq_req { 764 struct mbox_msghdr hdr; 765 u32 aura_id; 766 u8 ctype; 767 u8 op; 768 union { 769 /* Valid when op == WRITE/INIT and ctype == AURA. 770 * LF fills the pool_id in aura.pool_addr. AF will translate 771 * the pool_id to pool context pointer. 772 */ 773 struct npa_aura_s aura; 774 /* Valid when op == WRITE/INIT and ctype == POOL */ 775 struct npa_pool_s pool; 776 }; 777 /* Mask data when op == WRITE (1=write, 0=don't write) */ 778 union { 779 /* Valid when op == WRITE and ctype == AURA */ 780 struct npa_aura_s aura_mask; 781 /* Valid when op == WRITE and ctype == POOL */ 782 struct npa_pool_s pool_mask; 783 }; 784}; 785 786struct npa_aq_enq_rsp { 787 struct mbox_msghdr hdr; 788 union { 789 /* Valid when op == READ and ctype == AURA */ 790 struct npa_aura_s aura; 791 /* Valid when op == READ and ctype == POOL */ 792 struct npa_pool_s pool; 793 }; 794}; 795 796/* Disable all contexts of type 'ctype' */ 797struct hwctx_disable_req { 798 struct mbox_msghdr hdr; 799 u8 ctype; 800}; 801 802/* NIX mbox message formats */ 803 804/* NIX mailbox error codes 805 * Range 401 - 500. 806 */ 807enum nix_af_status { 808 NIX_AF_ERR_PARAM = -401, 809 NIX_AF_ERR_AQ_FULL = -402, 810 NIX_AF_ERR_AQ_ENQUEUE = -403, 811 NIX_AF_ERR_AF_LF_INVALID = -404, 812 NIX_AF_ERR_AF_LF_ALLOC = -405, 813 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 814 NIX_AF_ERR_TLX_INVALID = -407, 815 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 816 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 817 NIX_AF_ERR_FRS_INVALID = -410, 818 NIX_AF_ERR_RX_LINK_INVALID = -411, 819 NIX_AF_INVAL_TXSCHQ_CFG = -412, 820 NIX_AF_SMQ_FLUSH_FAILED = -413, 821 NIX_AF_ERR_LF_RESET = -414, 822 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 823 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 824 NIX_AF_ERR_MARK_CFG_FAIL = -417, 825 NIX_AF_ERR_LSO_CFG_FAIL = -418, 826 NIX_AF_INVAL_NPA_PF_FUNC = -419, 827 NIX_AF_INVAL_SSO_PF_FUNC = -420, 828 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 829 NIX_AF_ERR_RX_VTAG_INUSE = -422, 830 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 831 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 832 NIX_AF_ERR_INVALID_NIXBLK = -425, 833 NIX_AF_ERR_INVALID_BANDPROF = -426, 834 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 835 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 836 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 837 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 838 NIX_AF_ERR_LINK_CREDITS = -431, 839}; 840 841/* For NIX RX vtag action */ 842enum nix_rx_vtag0_type { 843 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 844 NIX_AF_LFX_RX_VTAG_TYPE1, 845 NIX_AF_LFX_RX_VTAG_TYPE2, 846 NIX_AF_LFX_RX_VTAG_TYPE3, 847 NIX_AF_LFX_RX_VTAG_TYPE4, 848 NIX_AF_LFX_RX_VTAG_TYPE5, 849 NIX_AF_LFX_RX_VTAG_TYPE6, 850 NIX_AF_LFX_RX_VTAG_TYPE7, 851}; 852 853/* For NIX LF context alloc and init */ 854struct nix_lf_alloc_req { 855 struct mbox_msghdr hdr; 856 int node; 857 u32 rq_cnt; /* No of receive queues */ 858 u32 sq_cnt; /* No of send queues */ 859 u32 cq_cnt; /* No of completion queues */ 860 u8 xqe_sz; 861 u16 rss_sz; 862 u8 rss_grps; 863 u16 npa_func; 864 u16 sso_func; 865 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 866 u64 way_mask; 867#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 868#define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 869 u64 flags; 870}; 871 872struct nix_lf_alloc_rsp { 873 struct mbox_msghdr hdr; 874 u16 sqb_size; 875 u16 rx_chan_base; 876 u16 tx_chan_base; 877 u8 rx_chan_cnt; /* total number of RX channels */ 878 u8 tx_chan_cnt; /* total number of TX channels */ 879 u8 lso_tsov4_idx; 880 u8 lso_tsov6_idx; 881 u8 mac_addr[ETH_ALEN]; 882 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 883 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 884 u16 cints; /* NIX_AF_CONST2::CINTS */ 885 u16 qints; /* NIX_AF_CONST2::QINTS */ 886 u8 cgx_links; /* No. of CGX links present in HW */ 887 u8 lbk_links; /* No. of LBK links present in HW */ 888 u8 sdp_links; /* No. of SDP links present in HW */ 889 u8 tx_link; /* Transmit channel link number */ 890}; 891 892struct nix_lf_free_req { 893 struct mbox_msghdr hdr; 894#define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 895#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 896 u64 flags; 897}; 898 899/* CN10K NIX AQ enqueue msg */ 900struct nix_cn10k_aq_enq_req { 901 struct mbox_msghdr hdr; 902 u32 qidx; 903 u8 ctype; 904 u8 op; 905 union { 906 struct nix_cn10k_rq_ctx_s rq; 907 struct nix_cn10k_sq_ctx_s sq; 908 struct nix_cq_ctx_s cq; 909 struct nix_rsse_s rss; 910 struct nix_rx_mce_s mce; 911 struct nix_bandprof_s prof; 912 }; 913 union { 914 struct nix_cn10k_rq_ctx_s rq_mask; 915 struct nix_cn10k_sq_ctx_s sq_mask; 916 struct nix_cq_ctx_s cq_mask; 917 struct nix_rsse_s rss_mask; 918 struct nix_rx_mce_s mce_mask; 919 struct nix_bandprof_s prof_mask; 920 }; 921}; 922 923struct nix_cn10k_aq_enq_rsp { 924 struct mbox_msghdr hdr; 925 union { 926 struct nix_cn10k_rq_ctx_s rq; 927 struct nix_cn10k_sq_ctx_s sq; 928 struct nix_cq_ctx_s cq; 929 struct nix_rsse_s rss; 930 struct nix_rx_mce_s mce; 931 struct nix_bandprof_s prof; 932 }; 933}; 934 935/* NIX AQ enqueue msg */ 936struct nix_aq_enq_req { 937 struct mbox_msghdr hdr; 938 u32 qidx; 939 u8 ctype; 940 u8 op; 941 union { 942 struct nix_rq_ctx_s rq; 943 struct nix_sq_ctx_s sq; 944 struct nix_cq_ctx_s cq; 945 struct nix_rsse_s rss; 946 struct nix_rx_mce_s mce; 947 struct nix_bandprof_s prof; 948 }; 949 union { 950 struct nix_rq_ctx_s rq_mask; 951 struct nix_sq_ctx_s sq_mask; 952 struct nix_cq_ctx_s cq_mask; 953 struct nix_rsse_s rss_mask; 954 struct nix_rx_mce_s mce_mask; 955 struct nix_bandprof_s prof_mask; 956 }; 957}; 958 959struct nix_aq_enq_rsp { 960 struct mbox_msghdr hdr; 961 union { 962 struct nix_rq_ctx_s rq; 963 struct nix_sq_ctx_s sq; 964 struct nix_cq_ctx_s cq; 965 struct nix_rsse_s rss; 966 struct nix_rx_mce_s mce; 967 struct nix_bandprof_s prof; 968 }; 969}; 970 971/* Tx scheduler/shaper mailbox messages */ 972 973#define MAX_TXSCHQ_PER_FUNC 128 974 975struct nix_txsch_alloc_req { 976 struct mbox_msghdr hdr; 977 /* Scheduler queue count request at each level */ 978 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 979 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 980}; 981 982struct nix_txsch_alloc_rsp { 983 struct mbox_msghdr hdr; 984 /* Scheduler queue count allocated at each level */ 985 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 986 u16 schq[NIX_TXSCH_LVL_CNT]; 987 /* Scheduler queue list allocated at each level */ 988 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 989 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 990 u8 aggr_level; /* Traffic aggregation scheduler level */ 991 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 992 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 993}; 994 995struct nix_txsch_free_req { 996 struct mbox_msghdr hdr; 997#define TXSCHQ_FREE_ALL BIT_ULL(0) 998 u16 flags; 999 /* Scheduler queue level to be freed */ 1000 u16 schq_lvl; 1001 /* List of scheduler queues to be freed */ 1002 u16 schq; 1003}; 1004 1005struct nix_txschq_config { 1006 struct mbox_msghdr hdr; 1007 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1008 u8 read; 1009#define TXSCHQ_IDX_SHIFT 16 1010#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1011#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1012 u8 num_regs; 1013#define MAX_REGS_PER_MBOX_MSG 20 1014 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1015 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1016 /* All 0's => overwrite with new value */ 1017 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1018}; 1019 1020struct nix_vtag_config { 1021 struct mbox_msghdr hdr; 1022 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1023 u8 vtag_size; 1024 /* cfg_type is '0' for tx vlan cfg 1025 * cfg_type is '1' for rx vlan cfg 1026 */ 1027 u8 cfg_type; 1028 union { 1029 /* valid when cfg_type is '0' */ 1030 struct { 1031 u64 vtag0; 1032 u64 vtag1; 1033 1034 /* cfg_vtag0 & cfg_vtag1 fields are valid 1035 * when free_vtag0 & free_vtag1 are '0's. 1036 */ 1037 /* cfg_vtag0 = 1 to configure vtag0 */ 1038 u8 cfg_vtag0 :1; 1039 /* cfg_vtag1 = 1 to configure vtag1 */ 1040 u8 cfg_vtag1 :1; 1041 1042 /* vtag0_idx & vtag1_idx are only valid when 1043 * both cfg_vtag0 & cfg_vtag1 are '0's, 1044 * these fields are used along with free_vtag0 1045 * & free_vtag1 to free the nix lf's tx_vlan 1046 * configuration. 1047 * 1048 * Denotes the indices of tx_vtag def registers 1049 * that needs to be cleared and freed. 1050 */ 1051 int vtag0_idx; 1052 int vtag1_idx; 1053 1054 /* free_vtag0 & free_vtag1 fields are valid 1055 * when cfg_vtag0 & cfg_vtag1 are '0's. 1056 */ 1057 /* free_vtag0 = 1 clears vtag0 configuration 1058 * vtag0_idx denotes the index to be cleared. 1059 */ 1060 u8 free_vtag0 :1; 1061 /* free_vtag1 = 1 clears vtag1 configuration 1062 * vtag1_idx denotes the index to be cleared. 1063 */ 1064 u8 free_vtag1 :1; 1065 } tx; 1066 1067 /* valid when cfg_type is '1' */ 1068 struct { 1069 /* rx vtag type index, valid values are in 0..7 range */ 1070 u8 vtag_type; 1071 /* rx vtag strip */ 1072 u8 strip_vtag :1; 1073 /* rx vtag capture */ 1074 u8 capture_vtag :1; 1075 } rx; 1076 }; 1077}; 1078 1079struct nix_vtag_config_rsp { 1080 struct mbox_msghdr hdr; 1081 int vtag0_idx; 1082 int vtag1_idx; 1083 /* Indices of tx_vtag def registers used to configure 1084 * tx vtag0 & vtag1 headers, these indices are valid 1085 * when nix_vtag_config mbox requested for vtag0 and/ 1086 * or vtag1 configuration. 1087 */ 1088}; 1089 1090#define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1091 1092struct nix_rss_flowkey_cfg { 1093 struct mbox_msghdr hdr; 1094 int mcam_index; /* MCAM entry index to modify */ 1095#define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1096#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1097#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1098#define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1099#define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1100#define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1101#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1102#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1103#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1104#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1105#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1106#define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1107#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1108#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1109#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1110#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1111#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1112#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1113#define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1114#define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1115#define NIX_FLOW_KEY_TYPE_AH BIT(22) 1116#define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1117#define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1118#define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1119#define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1120#define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1121 u32 flowkey_cfg; /* Flowkey types selected */ 1122 u8 group; /* RSS context or group */ 1123}; 1124 1125struct nix_rss_flowkey_cfg_rsp { 1126 struct mbox_msghdr hdr; 1127 u8 alg_idx; /* Selected algo index */ 1128}; 1129 1130struct nix_set_mac_addr { 1131 struct mbox_msghdr hdr; 1132 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1133}; 1134 1135struct nix_get_mac_addr_rsp { 1136 struct mbox_msghdr hdr; 1137 u8 mac_addr[ETH_ALEN]; 1138}; 1139 1140struct nix_mark_format_cfg { 1141 struct mbox_msghdr hdr; 1142 u8 offset; 1143 u8 y_mask; 1144 u8 y_val; 1145 u8 r_mask; 1146 u8 r_val; 1147}; 1148 1149struct nix_mark_format_cfg_rsp { 1150 struct mbox_msghdr hdr; 1151 u8 mark_format_idx; 1152}; 1153 1154struct nix_rx_mode { 1155 struct mbox_msghdr hdr; 1156#define NIX_RX_MODE_UCAST BIT(0) 1157#define NIX_RX_MODE_PROMISC BIT(1) 1158#define NIX_RX_MODE_ALLMULTI BIT(2) 1159#define NIX_RX_MODE_USE_MCE BIT(3) 1160 u16 mode; 1161}; 1162 1163struct nix_rx_cfg { 1164 struct mbox_msghdr hdr; 1165#define NIX_RX_OL3_VERIFY BIT(0) 1166#define NIX_RX_OL4_VERIFY BIT(1) 1167#define NIX_RX_DROP_RE BIT(2) 1168 u8 len_verify; /* Outer L3/L4 len check */ 1169#define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1170 u8 csum_verify; /* Outer L4 checksum verification */ 1171}; 1172 1173struct nix_frs_cfg { 1174 struct mbox_msghdr hdr; 1175 u8 update_smq; /* Update SMQ's min/max lens */ 1176 u8 update_minlen; /* Set minlen also */ 1177 u8 sdp_link; /* Set SDP RX link */ 1178 u16 maxlen; 1179 u16 minlen; 1180}; 1181 1182struct nix_lso_format_cfg { 1183 struct mbox_msghdr hdr; 1184 u64 field_mask; 1185#define NIX_LSO_FIELD_MAX 8 1186 u64 fields[NIX_LSO_FIELD_MAX]; 1187}; 1188 1189struct nix_lso_format_cfg_rsp { 1190 struct mbox_msghdr hdr; 1191 u8 lso_format_idx; 1192}; 1193 1194struct nix_bp_cfg_req { 1195 struct mbox_msghdr hdr; 1196 u16 chan_base; /* Starting channel number */ 1197 u8 chan_cnt; /* Number of channels */ 1198 u8 bpid_per_chan; 1199 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1200 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1201}; 1202 1203/* PF can be mapped to either CGX or LBK interface, 1204 * so maximum 64 channels are possible. 1205 */ 1206#define NIX_MAX_BPID_CHAN 64 1207struct nix_bp_cfg_rsp { 1208 struct mbox_msghdr hdr; 1209 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1210 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1211}; 1212 1213/* Global NIX inline IPSec configuration */ 1214struct nix_inline_ipsec_cfg { 1215 struct mbox_msghdr hdr; 1216 u32 cpt_credit; 1217 struct { 1218 u8 egrp; 1219 u16 opcode; 1220 u16 param1; 1221 u16 param2; 1222 } gen_cfg; 1223 struct { 1224 u16 cpt_pf_func; 1225 u8 cpt_slot; 1226 } inst_qsel; 1227 u8 enable; 1228 u16 bpid; 1229 u32 credit_th; 1230}; 1231 1232/* Per NIX LF inline IPSec configuration */ 1233struct nix_inline_ipsec_lf_cfg { 1234 struct mbox_msghdr hdr; 1235 u64 sa_base_addr; 1236 struct { 1237 u32 tag_const; 1238 u16 lenm1_max; 1239 u8 sa_pow2_size; 1240 u8 tt; 1241 } ipsec_cfg0; 1242 struct { 1243 u32 sa_idx_max; 1244 u8 sa_idx_w; 1245 } ipsec_cfg1; 1246 u8 enable; 1247}; 1248 1249struct nix_hw_info { 1250 struct mbox_msghdr hdr; 1251 u16 rsvs16; 1252 u16 max_mtu; 1253 u16 min_mtu; 1254 u32 rpm_dwrr_mtu; 1255 u32 sdp_dwrr_mtu; 1256 u32 lbk_dwrr_mtu; 1257 u32 rsvd32[1]; 1258 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1259}; 1260 1261struct nix_bandprof_alloc_req { 1262 struct mbox_msghdr hdr; 1263 /* Count of profiles needed per layer */ 1264 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1265}; 1266 1267struct nix_bandprof_alloc_rsp { 1268 struct mbox_msghdr hdr; 1269 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1270 1271 /* There is no need to allocate morethan 1 bandwidth profile 1272 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1273 * profiles to 64 per PF_FUNC. 1274 */ 1275#define MAX_BANDPROF_PER_PFFUNC 64 1276 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1277}; 1278 1279struct nix_bandprof_free_req { 1280 struct mbox_msghdr hdr; 1281 u8 free_all; 1282 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1283 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1284}; 1285 1286struct nix_bandprof_get_hwinfo_rsp { 1287 struct mbox_msghdr hdr; 1288 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1289 u32 policer_timeunit; 1290}; 1291 1292/* NPC mbox message structs */ 1293 1294#define NPC_MCAM_ENTRY_INVALID 0xFFFF 1295#define NPC_MCAM_INVALID_MAP 0xFFFF 1296 1297/* NPC mailbox error codes 1298 * Range 701 - 800. 1299 */ 1300enum npc_af_status { 1301 NPC_MCAM_INVALID_REQ = -701, 1302 NPC_MCAM_ALLOC_DENIED = -702, 1303 NPC_MCAM_ALLOC_FAILED = -703, 1304 NPC_MCAM_PERM_DENIED = -704, 1305 NPC_FLOW_INTF_INVALID = -707, 1306 NPC_FLOW_CHAN_INVALID = -708, 1307 NPC_FLOW_NO_NIXLF = -709, 1308 NPC_FLOW_NOT_SUPPORTED = -710, 1309 NPC_FLOW_VF_PERM_DENIED = -711, 1310 NPC_FLOW_VF_NOT_INIT = -712, 1311 NPC_FLOW_VF_OVERLAP = -713, 1312}; 1313 1314struct npc_mcam_alloc_entry_req { 1315 struct mbox_msghdr hdr; 1316#define NPC_MAX_NONCONTIG_ENTRIES 256 1317 u8 contig; /* Contiguous entries ? */ 1318#define NPC_MCAM_ANY_PRIO 0 1319#define NPC_MCAM_LOWER_PRIO 1 1320#define NPC_MCAM_HIGHER_PRIO 2 1321 u8 priority; /* Lower or higher w.r.t ref_entry */ 1322 u16 ref_entry; 1323 u16 count; /* Number of entries requested */ 1324}; 1325 1326struct npc_mcam_alloc_entry_rsp { 1327 struct mbox_msghdr hdr; 1328 u16 entry; /* Entry allocated or start index if contiguous. 1329 * Invalid incase of non-contiguous. 1330 */ 1331 u16 count; /* Number of entries allocated */ 1332 u16 free_count; /* Number of entries available */ 1333 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1334}; 1335 1336struct npc_mcam_free_entry_req { 1337 struct mbox_msghdr hdr; 1338 u16 entry; /* Entry index to be freed */ 1339 u8 all; /* If all entries allocated to this PFVF to be freed */ 1340}; 1341 1342struct mcam_entry { 1343#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1344 u64 kw[NPC_MAX_KWS_IN_KEY]; 1345 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1346 u64 action; 1347 u64 vtag_action; 1348}; 1349 1350struct npc_mcam_write_entry_req { 1351 struct mbox_msghdr hdr; 1352 struct mcam_entry entry_data; 1353 u16 entry; /* MCAM entry to write this match key */ 1354 u16 cntr; /* Counter for this MCAM entry */ 1355 u8 intf; /* Rx or Tx interface */ 1356 u8 enable_entry;/* Enable this MCAM entry ? */ 1357 u8 set_cntr; /* Set counter for this entry ? */ 1358}; 1359 1360/* Enable/Disable a given entry */ 1361struct npc_mcam_ena_dis_entry_req { 1362 struct mbox_msghdr hdr; 1363 u16 entry; 1364}; 1365 1366struct npc_mcam_shift_entry_req { 1367 struct mbox_msghdr hdr; 1368#define NPC_MCAM_MAX_SHIFTS 64 1369 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1370 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1371 u16 shift_count; /* Number of entries to shift */ 1372}; 1373 1374struct npc_mcam_shift_entry_rsp { 1375 struct mbox_msghdr hdr; 1376 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1377}; 1378 1379struct npc_mcam_alloc_counter_req { 1380 struct mbox_msghdr hdr; 1381 u8 contig; /* Contiguous counters ? */ 1382#define NPC_MAX_NONCONTIG_COUNTERS 64 1383 u16 count; /* Number of counters requested */ 1384}; 1385 1386struct npc_mcam_alloc_counter_rsp { 1387 struct mbox_msghdr hdr; 1388 u16 cntr; /* Counter allocated or start index if contiguous. 1389 * Invalid incase of non-contiguous. 1390 */ 1391 u16 count; /* Number of counters allocated */ 1392 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1393}; 1394 1395struct npc_mcam_oper_counter_req { 1396 struct mbox_msghdr hdr; 1397 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1398}; 1399 1400struct npc_mcam_oper_counter_rsp { 1401 struct mbox_msghdr hdr; 1402 u64 stat; /* valid only while fetching counter's stats */ 1403}; 1404 1405struct npc_mcam_unmap_counter_req { 1406 struct mbox_msghdr hdr; 1407 u16 cntr; 1408 u16 entry; /* Entry and counter to be unmapped */ 1409 u8 all; /* Unmap all entries using this counter ? */ 1410}; 1411 1412struct npc_mcam_alloc_and_write_entry_req { 1413 struct mbox_msghdr hdr; 1414 struct mcam_entry entry_data; 1415 u16 ref_entry; 1416 u8 priority; /* Lower or higher w.r.t ref_entry */ 1417 u8 intf; /* Rx or Tx interface */ 1418 u8 enable_entry;/* Enable this MCAM entry ? */ 1419 u8 alloc_cntr; /* Allocate counter and map ? */ 1420}; 1421 1422struct npc_mcam_alloc_and_write_entry_rsp { 1423 struct mbox_msghdr hdr; 1424 u16 entry; 1425 u16 cntr; 1426}; 1427 1428struct npc_get_kex_cfg_rsp { 1429 struct mbox_msghdr hdr; 1430 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1431 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1432#define NPC_MAX_INTF 2 1433#define NPC_MAX_LID 8 1434#define NPC_MAX_LT 16 1435#define NPC_MAX_LD 2 1436#define NPC_MAX_LFL 16 1437 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1438 u64 kex_ld_flags[NPC_MAX_LD]; 1439 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1440 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1441 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1442 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1443#define MKEX_NAME_LEN 128 1444 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1445}; 1446 1447struct ptp_get_cap_rsp { 1448 struct mbox_msghdr hdr; 1449#define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1450 u64 cap; 1451}; 1452 1453struct flow_msg { 1454 unsigned char dmac[6]; 1455 unsigned char smac[6]; 1456 __be16 etype; 1457 __be16 vlan_etype; 1458 __be16 vlan_tci; 1459 union { 1460 __be32 ip4src; 1461 __be32 ip6src[4]; 1462 }; 1463 union { 1464 __be32 ip4dst; 1465 __be32 ip6dst[4]; 1466 }; 1467 union { 1468 __be32 spi; 1469 }; 1470 1471 u8 tos; 1472 u8 ip_ver; 1473 u8 ip_proto; 1474 u8 tc; 1475 __be16 sport; 1476 __be16 dport; 1477 union { 1478 u8 ip_flag; 1479 u8 next_header; 1480 }; 1481 __be16 vlan_itci; 1482}; 1483 1484struct npc_install_flow_req { 1485 struct mbox_msghdr hdr; 1486 struct flow_msg packet; 1487 struct flow_msg mask; 1488 u64 features; 1489 u16 entry; 1490 u16 channel; 1491 u16 chan_mask; 1492 u8 intf; 1493 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1494 u8 default_rule; 1495 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1496 u16 vf; 1497 /* action */ 1498 u32 index; 1499 u16 match_id; 1500 u8 flow_key_alg; 1501 u8 op; 1502 /* vtag rx action */ 1503 u8 vtag0_type; 1504 u8 vtag0_valid; 1505 u8 vtag1_type; 1506 u8 vtag1_valid; 1507 /* vtag tx action */ 1508 u16 vtag0_def; 1509 u8 vtag0_op; 1510 u16 vtag1_def; 1511 u8 vtag1_op; 1512 /* old counter value */ 1513 u16 cntr_val; 1514}; 1515 1516struct npc_install_flow_rsp { 1517 struct mbox_msghdr hdr; 1518 int counter; /* negative if no counter else counter number */ 1519}; 1520 1521struct npc_delete_flow_req { 1522 struct mbox_msghdr hdr; 1523 u16 entry; 1524 u16 start;/*Disable range of entries */ 1525 u16 end; 1526 u8 all; /* PF + VFs */ 1527}; 1528 1529struct npc_delete_flow_rsp { 1530 struct mbox_msghdr hdr; 1531 u16 cntr_val; 1532}; 1533 1534struct npc_mcam_read_entry_req { 1535 struct mbox_msghdr hdr; 1536 u16 entry; /* MCAM entry to read */ 1537}; 1538 1539struct npc_mcam_read_entry_rsp { 1540 struct mbox_msghdr hdr; 1541 struct mcam_entry entry_data; 1542 u8 intf; 1543 u8 enable; 1544}; 1545 1546struct npc_mcam_read_base_rule_rsp { 1547 struct mbox_msghdr hdr; 1548 struct mcam_entry entry; 1549}; 1550 1551struct npc_mcam_get_stats_req { 1552 struct mbox_msghdr hdr; 1553 u16 entry; /* mcam entry */ 1554}; 1555 1556struct npc_mcam_get_stats_rsp { 1557 struct mbox_msghdr hdr; 1558 u64 stat; /* counter stats */ 1559 u8 stat_ena; /* enabled */ 1560}; 1561 1562struct npc_get_field_hash_info_req { 1563 struct mbox_msghdr hdr; 1564 u8 intf; 1565}; 1566 1567struct npc_get_field_hash_info_rsp { 1568 struct mbox_msghdr hdr; 1569 u64 secret_key[3]; 1570#define NPC_MAX_HASH 2 1571#define NPC_MAX_HASH_MASK 2 1572 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1573 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1574 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1575 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1576}; 1577 1578enum ptp_op { 1579 PTP_OP_ADJFINE = 0, 1580 PTP_OP_GET_CLOCK = 1, 1581 PTP_OP_GET_TSTMP = 2, 1582 PTP_OP_SET_THRESH = 3, 1583 PTP_OP_EXTTS_ON = 4, 1584 PTP_OP_ADJTIME = 5, 1585 PTP_OP_SET_CLOCK = 6, 1586}; 1587 1588struct ptp_req { 1589 struct mbox_msghdr hdr; 1590 u8 op; 1591 s64 scaled_ppm; 1592 u64 thresh; 1593 int extts_on; 1594 s64 delta; 1595 u64 clk; 1596}; 1597 1598struct ptp_rsp { 1599 struct mbox_msghdr hdr; 1600 u64 clk; 1601 u64 tsc; 1602}; 1603 1604struct npc_get_field_status_req { 1605 struct mbox_msghdr hdr; 1606 u8 intf; 1607 u8 field; 1608}; 1609 1610struct npc_get_field_status_rsp { 1611 struct mbox_msghdr hdr; 1612 u8 enable; 1613}; 1614 1615struct set_vf_perm { 1616 struct mbox_msghdr hdr; 1617 u16 vf; 1618#define RESET_VF_PERM BIT_ULL(0) 1619#define VF_TRUSTED BIT_ULL(1) 1620 u64 flags; 1621}; 1622 1623struct lmtst_tbl_setup_req { 1624 struct mbox_msghdr hdr; 1625 u64 dis_sched_early_comp :1; 1626 u64 sch_ena :1; 1627 u64 dis_line_pref :1; 1628 u64 ssow_pf_func :13; 1629 u16 base_pcifunc; 1630 u8 use_local_lmt_region; 1631 u64 lmt_iova; 1632 u64 rsvd[4]; 1633}; 1634 1635/* CPT mailbox error codes 1636 * Range 901 - 1000. 1637 */ 1638enum cpt_af_status { 1639 CPT_AF_ERR_PARAM = -901, 1640 CPT_AF_ERR_GRP_INVALID = -902, 1641 CPT_AF_ERR_LF_INVALID = -903, 1642 CPT_AF_ERR_ACCESS_DENIED = -904, 1643 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1644 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1645 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1646 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1647}; 1648 1649/* CPT mbox message formats */ 1650struct cpt_rd_wr_reg_msg { 1651 struct mbox_msghdr hdr; 1652 u64 reg_offset; 1653 u64 *ret_val; 1654 u64 val; 1655 u8 is_write; 1656 int blkaddr; 1657}; 1658 1659struct cpt_lf_alloc_req_msg { 1660 struct mbox_msghdr hdr; 1661 u16 nix_pf_func; 1662 u16 sso_pf_func; 1663 u16 eng_grpmsk; 1664 int blkaddr; 1665 u8 ctx_ilen_valid : 1; 1666 u8 ctx_ilen : 7; 1667}; 1668 1669#define CPT_INLINE_INBOUND 0 1670#define CPT_INLINE_OUTBOUND 1 1671 1672/* Mailbox message request format for CPT IPsec 1673 * inline inbound and outbound configuration. 1674 */ 1675struct cpt_inline_ipsec_cfg_msg { 1676 struct mbox_msghdr hdr; 1677 u8 enable; 1678 u8 slot; 1679 u8 dir; 1680 u8 sso_pf_func_ovrd; 1681 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1682 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1683}; 1684 1685/* Mailbox message request and response format for CPT stats. */ 1686struct cpt_sts_req { 1687 struct mbox_msghdr hdr; 1688 u8 blkaddr; 1689}; 1690 1691struct cpt_sts_rsp { 1692 struct mbox_msghdr hdr; 1693 u64 inst_req_pc; 1694 u64 inst_lat_pc; 1695 u64 rd_req_pc; 1696 u64 rd_lat_pc; 1697 u64 rd_uc_pc; 1698 u64 active_cycles_pc; 1699 u64 ctx_mis_pc; 1700 u64 ctx_hit_pc; 1701 u64 ctx_aop_pc; 1702 u64 ctx_aop_lat_pc; 1703 u64 ctx_ifetch_pc; 1704 u64 ctx_ifetch_lat_pc; 1705 u64 ctx_ffetch_pc; 1706 u64 ctx_ffetch_lat_pc; 1707 u64 ctx_wback_pc; 1708 u64 ctx_wback_lat_pc; 1709 u64 ctx_psh_pc; 1710 u64 ctx_psh_lat_pc; 1711 u64 ctx_err; 1712 u64 ctx_enc_id; 1713 u64 ctx_flush_timer; 1714 u64 rxc_time; 1715 u64 rxc_time_cfg; 1716 u64 rxc_active_sts; 1717 u64 rxc_zombie_sts; 1718 u64 busy_sts_ae; 1719 u64 free_sts_ae; 1720 u64 busy_sts_se; 1721 u64 free_sts_se; 1722 u64 busy_sts_ie; 1723 u64 free_sts_ie; 1724 u64 exe_err_info; 1725 u64 cptclk_cnt; 1726 u64 diag; 1727 u64 rxc_dfrg; 1728 u64 x2p_link_cfg0; 1729 u64 x2p_link_cfg1; 1730}; 1731 1732/* Mailbox message request format to configure reassembly timeout. */ 1733struct cpt_rxc_time_cfg_req { 1734 struct mbox_msghdr hdr; 1735 int blkaddr; 1736 u32 step; 1737 u16 zombie_thres; 1738 u16 zombie_limit; 1739 u16 active_thres; 1740 u16 active_limit; 1741}; 1742 1743/* Mailbox message request format to request for CPT_INST_S lmtst. */ 1744struct cpt_inst_lmtst_req { 1745 struct mbox_msghdr hdr; 1746 u64 inst[8]; 1747 u64 rsvd; 1748}; 1749 1750/* Mailbox message format to request for CPT LF reset */ 1751struct cpt_lf_rst_req { 1752 struct mbox_msghdr hdr; 1753 u32 slot; 1754 u32 rsvd; 1755}; 1756 1757/* Mailbox message format to request for CPT faulted engines */ 1758struct cpt_flt_eng_info_req { 1759 struct mbox_msghdr hdr; 1760 int blkaddr; 1761 bool reset; 1762 u32 rsvd; 1763}; 1764 1765struct cpt_flt_eng_info_rsp { 1766 struct mbox_msghdr hdr; 1767 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1768 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1769 u64 rsvd; 1770}; 1771 1772struct sdp_node_info { 1773 /* Node to which this PF belons to */ 1774 u8 node_id; 1775 u8 max_vfs; 1776 u8 num_pf_rings; 1777 u8 pf_srn; 1778#define SDP_MAX_VFS 128 1779 u8 vf_rings[SDP_MAX_VFS]; 1780}; 1781 1782struct sdp_chan_info_msg { 1783 struct mbox_msghdr hdr; 1784 struct sdp_node_info info; 1785}; 1786 1787struct sdp_get_chan_info_msg { 1788 struct mbox_msghdr hdr; 1789 u16 chan_base; 1790 u16 num_chan; 1791}; 1792 1793/* CGX mailbox error codes 1794 * Range 1101 - 1200. 1795 */ 1796enum cgx_af_status { 1797 LMAC_AF_ERR_INVALID_PARAM = -1101, 1798 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1799 LMAC_AF_ERR_PERM_DENIED = -1103, 1800 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1801 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1802 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1803 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1804 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1805 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1806 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1807}; 1808 1809enum mcs_direction { 1810 MCS_RX, 1811 MCS_TX, 1812}; 1813 1814enum mcs_rsrc_type { 1815 MCS_RSRC_TYPE_FLOWID, 1816 MCS_RSRC_TYPE_SECY, 1817 MCS_RSRC_TYPE_SC, 1818 MCS_RSRC_TYPE_SA, 1819}; 1820 1821struct mcs_alloc_rsrc_req { 1822 struct mbox_msghdr hdr; 1823 u8 rsrc_type; 1824 u8 rsrc_cnt; /* Resources count */ 1825 u8 mcs_id; /* MCS block ID */ 1826 u8 dir; /* Macsec ingress or egress side */ 1827 u8 all; /* Allocate all resource type one each */ 1828 u64 rsvd; 1829}; 1830 1831struct mcs_alloc_rsrc_rsp { 1832 struct mbox_msghdr hdr; 1833 u8 flow_ids[128]; /* Index of reserved entries */ 1834 u8 secy_ids[128]; 1835 u8 sc_ids[128]; 1836 u8 sa_ids[256]; 1837 u8 rsrc_type; 1838 u8 rsrc_cnt; /* No of entries reserved */ 1839 u8 mcs_id; 1840 u8 dir; 1841 u8 all; 1842 u8 rsvd[256]; /* reserved fields for future expansion */ 1843}; 1844 1845struct mcs_free_rsrc_req { 1846 struct mbox_msghdr hdr; 1847 u8 rsrc_id; /* Index of the entry to be freed */ 1848 u8 rsrc_type; 1849 u8 mcs_id; 1850 u8 dir; 1851 u8 all; /* Free all the cam resources */ 1852 u64 rsvd; 1853}; 1854 1855struct mcs_flowid_entry_write_req { 1856 struct mbox_msghdr hdr; 1857 u64 data[4]; 1858 u64 mask[4]; 1859 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1860 u8 flow_id; 1861 u8 secy_id; /* secyid for which flowid is mapped */ 1862 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1863 u8 ena; /* Enable tcam entry */ 1864 u8 ctrl_pkt; 1865 u8 mcs_id; 1866 u8 dir; 1867 u64 rsvd; 1868}; 1869 1870struct mcs_secy_plcy_write_req { 1871 struct mbox_msghdr hdr; 1872 u64 plcy; 1873 u8 secy_id; 1874 u8 mcs_id; 1875 u8 dir; 1876 u64 rsvd; 1877}; 1878 1879/* RX SC_CAM mapping */ 1880struct mcs_rx_sc_cam_write_req { 1881 struct mbox_msghdr hdr; 1882 u64 sci; /* SCI */ 1883 u64 secy_id; /* secy index mapped to SC */ 1884 u8 sc_id; /* SC CAM entry index */ 1885 u8 mcs_id; 1886 u64 rsvd; 1887}; 1888 1889struct mcs_sa_plcy_write_req { 1890 struct mbox_msghdr hdr; 1891 u64 plcy[2][9]; /* Support 2 SA policy */ 1892 u8 sa_index[2]; 1893 u8 sa_cnt; 1894 u8 mcs_id; 1895 u8 dir; 1896 u64 rsvd; 1897}; 1898 1899struct mcs_tx_sc_sa_map { 1900 struct mbox_msghdr hdr; 1901 u8 sa_index0; 1902 u8 sa_index1; 1903 u8 rekey_ena; 1904 u8 sa_index0_vld; 1905 u8 sa_index1_vld; 1906 u8 tx_sa_active; 1907 u64 sectag_sci; 1908 u8 sc_id; /* used as index for SA_MEM_MAP */ 1909 u8 mcs_id; 1910 u64 rsvd; 1911}; 1912 1913struct mcs_rx_sc_sa_map { 1914 struct mbox_msghdr hdr; 1915 u8 sa_index; 1916 u8 sa_in_use; 1917 u8 sc_id; 1918 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1919 u8 mcs_id; 1920 u64 rsvd; 1921}; 1922 1923struct mcs_flowid_ena_dis_entry { 1924 struct mbox_msghdr hdr; 1925 u8 flow_id; 1926 u8 ena; 1927 u8 mcs_id; 1928 u8 dir; 1929 u64 rsvd; 1930}; 1931 1932struct mcs_pn_table_write_req { 1933 struct mbox_msghdr hdr; 1934 u64 next_pn; 1935 u8 pn_id; 1936 u8 mcs_id; 1937 u8 dir; 1938 u64 rsvd; 1939}; 1940 1941struct mcs_hw_info { 1942 struct mbox_msghdr hdr; 1943 u8 num_mcs_blks; /* Number of MCS blocks */ 1944 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1945 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1946 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1947 u16 sa_entries; /* PN table entries = SA entries */ 1948 u64 rsvd[16]; 1949}; 1950 1951struct mcs_set_active_lmac { 1952 struct mbox_msghdr hdr; 1953 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1954 u8 mcs_id; 1955 u16 chan_base; /* MCS channel base */ 1956 u64 rsvd; 1957}; 1958 1959struct mcs_set_lmac_mode { 1960 struct mbox_msghdr hdr; 1961 u8 mode; /* 1:Bypass 0:Operational */ 1962 u8 lmac_id; 1963 u8 mcs_id; 1964 u64 rsvd; 1965}; 1966 1967struct mcs_port_reset_req { 1968 struct mbox_msghdr hdr; 1969 u8 reset; 1970 u8 mcs_id; 1971 u8 port_id; 1972 u64 rsvd; 1973}; 1974 1975struct mcs_port_cfg_set_req { 1976 struct mbox_msghdr hdr; 1977 u8 cstm_tag_rel_mode_sel; 1978 u8 custom_hdr_enb; 1979 u8 fifo_skid; 1980 u8 port_mode; 1981 u8 port_id; 1982 u8 mcs_id; 1983 u64 rsvd; 1984}; 1985 1986struct mcs_port_cfg_get_req { 1987 struct mbox_msghdr hdr; 1988 u8 port_id; 1989 u8 mcs_id; 1990 u64 rsvd; 1991}; 1992 1993struct mcs_port_cfg_get_rsp { 1994 struct mbox_msghdr hdr; 1995 u8 cstm_tag_rel_mode_sel; 1996 u8 custom_hdr_enb; 1997 u8 fifo_skid; 1998 u8 port_mode; 1999 u8 port_id; 2000 u8 mcs_id; 2001 u64 rsvd; 2002}; 2003 2004struct mcs_custom_tag_cfg_get_req { 2005 struct mbox_msghdr hdr; 2006 u8 mcs_id; 2007 u8 dir; 2008 u64 rsvd; 2009}; 2010 2011struct mcs_custom_tag_cfg_get_rsp { 2012 struct mbox_msghdr hdr; 2013 u16 cstm_etype[8]; 2014 u8 cstm_indx[8]; 2015 u8 cstm_etype_en; 2016 u8 mcs_id; 2017 u8 dir; 2018 u64 rsvd; 2019}; 2020 2021/* MCS mailbox error codes 2022 * Range 1201 - 1300. 2023 */ 2024enum mcs_af_status { 2025 MCS_AF_ERR_INVALID_MCSID = -1201, 2026 MCS_AF_ERR_NOT_MAPPED = -1202, 2027}; 2028 2029struct mcs_set_pn_threshold { 2030 struct mbox_msghdr hdr; 2031 u64 threshold; 2032 u8 xpn; /* '1' for setting xpn threshold */ 2033 u8 mcs_id; 2034 u8 dir; 2035 u64 rsvd; 2036}; 2037 2038enum mcs_ctrl_pkt_rulew_type { 2039 MCS_CTRL_PKT_RULE_TYPE_ETH, 2040 MCS_CTRL_PKT_RULE_TYPE_DA, 2041 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2042 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2043 MCS_CTRL_PKT_RULE_TYPE_MAC, 2044}; 2045 2046struct mcs_alloc_ctrl_pkt_rule_req { 2047 struct mbox_msghdr hdr; 2048 u8 rule_type; 2049 u8 mcs_id; /* MCS block ID */ 2050 u8 dir; /* Macsec ingress or egress side */ 2051 u64 rsvd; 2052}; 2053 2054struct mcs_alloc_ctrl_pkt_rule_rsp { 2055 struct mbox_msghdr hdr; 2056 u8 rule_idx; 2057 u8 rule_type; 2058 u8 mcs_id; 2059 u8 dir; 2060 u64 rsvd; 2061}; 2062 2063struct mcs_free_ctrl_pkt_rule_req { 2064 struct mbox_msghdr hdr; 2065 u8 rule_idx; 2066 u8 rule_type; 2067 u8 mcs_id; 2068 u8 dir; 2069 u8 all; 2070 u64 rsvd; 2071}; 2072 2073struct mcs_ctrl_pkt_rule_write_req { 2074 struct mbox_msghdr hdr; 2075 u64 data0; 2076 u64 data1; 2077 u64 data2; 2078 u8 rule_idx; 2079 u8 rule_type; 2080 u8 mcs_id; 2081 u8 dir; 2082 u64 rsvd; 2083}; 2084 2085struct mcs_stats_req { 2086 struct mbox_msghdr hdr; 2087 u8 id; 2088 u8 mcs_id; 2089 u8 dir; 2090 u64 rsvd; 2091}; 2092 2093struct mcs_flowid_stats { 2094 struct mbox_msghdr hdr; 2095 u64 tcam_hit_cnt; 2096 u64 rsvd; 2097}; 2098 2099struct mcs_secy_stats { 2100 struct mbox_msghdr hdr; 2101 u64 ctl_pkt_bcast_cnt; 2102 u64 ctl_pkt_mcast_cnt; 2103 u64 ctl_pkt_ucast_cnt; 2104 u64 ctl_octet_cnt; 2105 u64 unctl_pkt_bcast_cnt; 2106 u64 unctl_pkt_mcast_cnt; 2107 u64 unctl_pkt_ucast_cnt; 2108 u64 unctl_octet_cnt; 2109 /* Valid only for RX */ 2110 u64 octet_decrypted_cnt; 2111 u64 octet_validated_cnt; 2112 u64 pkt_port_disabled_cnt; 2113 u64 pkt_badtag_cnt; 2114 u64 pkt_nosa_cnt; 2115 u64 pkt_nosaerror_cnt; 2116 u64 pkt_tagged_ctl_cnt; 2117 u64 pkt_untaged_cnt; 2118 u64 pkt_ctl_cnt; /* CN10K-B */ 2119 u64 pkt_notag_cnt; /* CNF10K-B */ 2120 /* Valid only for TX */ 2121 u64 octet_encrypted_cnt; 2122 u64 octet_protected_cnt; 2123 u64 pkt_noactivesa_cnt; 2124 u64 pkt_toolong_cnt; 2125 u64 pkt_untagged_cnt; 2126 u64 rsvd[4]; 2127}; 2128 2129struct mcs_port_stats { 2130 struct mbox_msghdr hdr; 2131 u64 tcam_miss_cnt; 2132 u64 parser_err_cnt; 2133 u64 preempt_err_cnt; /* CNF10K-B */ 2134 u64 sectag_insert_err_cnt; 2135 u64 rsvd[4]; 2136}; 2137 2138/* Only for CN10K-B */ 2139struct mcs_sa_stats { 2140 struct mbox_msghdr hdr; 2141 /* RX */ 2142 u64 pkt_invalid_cnt; 2143 u64 pkt_nosaerror_cnt; 2144 u64 pkt_notvalid_cnt; 2145 u64 pkt_ok_cnt; 2146 u64 pkt_nosa_cnt; 2147 /* TX */ 2148 u64 pkt_encrypt_cnt; 2149 u64 pkt_protected_cnt; 2150 u64 rsvd[4]; 2151}; 2152 2153struct mcs_sc_stats { 2154 struct mbox_msghdr hdr; 2155 /* RX */ 2156 u64 hit_cnt; 2157 u64 pkt_invalid_cnt; 2158 u64 pkt_late_cnt; 2159 u64 pkt_notvalid_cnt; 2160 u64 pkt_unchecked_cnt; 2161 u64 pkt_delay_cnt; /* CNF10K-B */ 2162 u64 pkt_ok_cnt; /* CNF10K-B */ 2163 u64 octet_decrypt_cnt; /* CN10K-B */ 2164 u64 octet_validate_cnt; /* CN10K-B */ 2165 /* TX */ 2166 u64 pkt_encrypt_cnt; 2167 u64 pkt_protected_cnt; 2168 u64 octet_encrypt_cnt; /* CN10K-B */ 2169 u64 octet_protected_cnt; /* CN10K-B */ 2170 u64 rsvd[4]; 2171}; 2172 2173struct mcs_clear_stats { 2174 struct mbox_msghdr hdr; 2175#define MCS_FLOWID_STATS 0 2176#define MCS_SECY_STATS 1 2177#define MCS_SC_STATS 2 2178#define MCS_SA_STATS 3 2179#define MCS_PORT_STATS 4 2180 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2181 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2182 u8 mcs_id; 2183 u8 dir; 2184 u8 all; /* All resources stats mapped to PF are cleared */ 2185}; 2186 2187struct mcs_intr_cfg { 2188 struct mbox_msghdr hdr; 2189#define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2190#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2191#define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2192#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2193#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2194#define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2195#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2196#define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2197#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2198#define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2199#define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2200#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2201#define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2202#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2203#define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2204#define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2205 u64 intr_mask; /* Interrupt enable mask */ 2206 u8 mcs_id; 2207 u8 lmac_id; 2208 u64 rsvd; 2209}; 2210 2211struct mcs_intr_info { 2212 struct mbox_msghdr hdr; 2213 u64 intr_mask; 2214 int sa_id; 2215 u8 mcs_id; 2216 u8 lmac_id; 2217 u64 rsvd; 2218}; 2219 2220#endif /* MBOX_H */ 2221