1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#include <linux/pci.h> 5#include <linux/delay.h> 6#include <linux/sched.h> 7#include <linux/netdevice.h> 8 9#include "ixgbe.h" 10#include "ixgbe_common.h" 11#include "ixgbe_phy.h" 12 13static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 14static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 15static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 16static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 17static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 18static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 19 u16 count); 20static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 21static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 22static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 23static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 24 25static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 26static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 27static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 28 u16 words, u16 *data); 29static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 30 u16 words, u16 *data); 31static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 32 u16 offset); 33static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw); 34 35/* Base table for registers values that change by MAC */ 36const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 37 IXGBE_MVALS_INIT(8259X) 38}; 39 40/** 41 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 42 * control 43 * @hw: pointer to hardware structure 44 * 45 * There are several phys that do not support autoneg flow control. This 46 * function check the device id to see if the associated phy supports 47 * autoneg flow control. 48 **/ 49bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 50{ 51 bool supported = false; 52 ixgbe_link_speed speed; 53 bool link_up; 54 55 switch (hw->phy.media_type) { 56 case ixgbe_media_type_fiber: 57 /* flow control autoneg black list */ 58 switch (hw->device_id) { 59 case IXGBE_DEV_ID_X550EM_A_SFP: 60 case IXGBE_DEV_ID_X550EM_A_SFP_N: 61 supported = false; 62 break; 63 default: 64 hw->mac.ops.check_link(hw, &speed, &link_up, false); 65 /* if link is down, assume supported */ 66 if (link_up) 67 supported = speed == IXGBE_LINK_SPEED_1GB_FULL; 68 else 69 supported = true; 70 } 71 72 break; 73 case ixgbe_media_type_backplane: 74 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 75 supported = false; 76 else 77 supported = true; 78 break; 79 case ixgbe_media_type_copper: 80 /* only some copper devices support flow control autoneg */ 81 switch (hw->device_id) { 82 case IXGBE_DEV_ID_82599_T3_LOM: 83 case IXGBE_DEV_ID_X540T: 84 case IXGBE_DEV_ID_X540T1: 85 case IXGBE_DEV_ID_X550T: 86 case IXGBE_DEV_ID_X550T1: 87 case IXGBE_DEV_ID_X550EM_X_10G_T: 88 case IXGBE_DEV_ID_X550EM_A_10G_T: 89 case IXGBE_DEV_ID_X550EM_A_1G_T: 90 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 91 supported = true; 92 break; 93 default: 94 break; 95 } 96 break; 97 default: 98 break; 99 } 100 101 if (!supported) 102 hw_dbg(hw, "Device %x does not support flow control autoneg\n", 103 hw->device_id); 104 105 return supported; 106} 107 108/** 109 * ixgbe_setup_fc_generic - Set up flow control 110 * @hw: pointer to hardware structure 111 * 112 * Called at init time to set up flow control. 113 **/ 114s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 115{ 116 s32 ret_val = 0; 117 u32 reg = 0, reg_bp = 0; 118 u16 reg_cu = 0; 119 bool locked = false; 120 121 /* 122 * Validate the requested mode. Strict IEEE mode does not allow 123 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 124 */ 125 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 126 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 127 return -EINVAL; 128 } 129 130 /* 131 * 10gig parts do not have a word in the EEPROM to determine the 132 * default flow control setting, so we explicitly set it to full. 133 */ 134 if (hw->fc.requested_mode == ixgbe_fc_default) 135 hw->fc.requested_mode = ixgbe_fc_full; 136 137 /* 138 * Set up the 1G and 10G flow control advertisement registers so the 139 * HW will be able to do fc autoneg once the cable is plugged in. If 140 * we link at 10G, the 1G advertisement is harmless and vice versa. 141 */ 142 switch (hw->phy.media_type) { 143 case ixgbe_media_type_backplane: 144 /* some MAC's need RMW protection on AUTOC */ 145 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 146 if (ret_val) 147 return ret_val; 148 149 fallthrough; /* only backplane uses autoc */ 150 case ixgbe_media_type_fiber: 151 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 152 153 break; 154 case ixgbe_media_type_copper: 155 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 156 MDIO_MMD_AN, ®_cu); 157 break; 158 default: 159 break; 160 } 161 162 /* 163 * The possible values of fc.requested_mode are: 164 * 0: Flow control is completely disabled 165 * 1: Rx flow control is enabled (we can receive pause frames, 166 * but not send pause frames). 167 * 2: Tx flow control is enabled (we can send pause frames but 168 * we do not support receiving pause frames). 169 * 3: Both Rx and Tx flow control (symmetric) are enabled. 170 * other: Invalid. 171 */ 172 switch (hw->fc.requested_mode) { 173 case ixgbe_fc_none: 174 /* Flow control completely disabled by software override. */ 175 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 176 if (hw->phy.media_type == ixgbe_media_type_backplane) 177 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 178 IXGBE_AUTOC_ASM_PAUSE); 179 else if (hw->phy.media_type == ixgbe_media_type_copper) 180 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 181 break; 182 case ixgbe_fc_tx_pause: 183 /* 184 * Tx Flow control is enabled, and Rx Flow control is 185 * disabled by software override. 186 */ 187 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 188 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 189 if (hw->phy.media_type == ixgbe_media_type_backplane) { 190 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 191 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 192 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 193 reg_cu |= IXGBE_TAF_ASM_PAUSE; 194 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 195 } 196 break; 197 case ixgbe_fc_rx_pause: 198 /* 199 * Rx Flow control is enabled and Tx Flow control is 200 * disabled by software override. Since there really 201 * isn't a way to advertise that we are capable of RX 202 * Pause ONLY, we will advertise that we support both 203 * symmetric and asymmetric Rx PAUSE, as such we fall 204 * through to the fc_full statement. Later, we will 205 * disable the adapter's ability to send PAUSE frames. 206 */ 207 case ixgbe_fc_full: 208 /* Flow control (both Rx and Tx) is enabled by SW override. */ 209 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 210 if (hw->phy.media_type == ixgbe_media_type_backplane) 211 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 212 IXGBE_AUTOC_ASM_PAUSE; 213 else if (hw->phy.media_type == ixgbe_media_type_copper) 214 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 215 break; 216 default: 217 hw_dbg(hw, "Flow control param set incorrectly\n"); 218 return -EIO; 219 } 220 221 if (hw->mac.type != ixgbe_mac_X540) { 222 /* 223 * Enable auto-negotiation between the MAC & PHY; 224 * the MAC will advertise clause 37 flow control. 225 */ 226 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 227 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 228 229 /* Disable AN timeout */ 230 if (hw->fc.strict_ieee) 231 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 232 233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 234 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 235 } 236 237 /* 238 * AUTOC restart handles negotiation of 1G and 10G on backplane 239 * and copper. There is no need to set the PCS1GCTL register. 240 * 241 */ 242 if (hw->phy.media_type == ixgbe_media_type_backplane) { 243 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 244 * LESM is on, likewise reset_pipeline requries the lock as 245 * it also writes AUTOC. 246 */ 247 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 248 if (ret_val) 249 return ret_val; 250 251 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 252 ixgbe_device_supports_autoneg_fc(hw)) { 253 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 254 MDIO_MMD_AN, reg_cu); 255 } 256 257 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 258 return ret_val; 259} 260 261/** 262 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 263 * @hw: pointer to hardware structure 264 * 265 * Starts the hardware by filling the bus info structure and media type, clears 266 * all on chip counters, initializes receive address registers, multicast 267 * table, VLAN filter table, calls routine to set up link and flow control 268 * settings, and leaves transmit and receive units disabled and uninitialized 269 **/ 270s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 271{ 272 s32 ret_val; 273 u32 ctrl_ext; 274 u16 device_caps; 275 276 /* Set the media type */ 277 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 278 279 /* Identify the PHY */ 280 hw->phy.ops.identify(hw); 281 282 /* Clear the VLAN filter table */ 283 hw->mac.ops.clear_vfta(hw); 284 285 /* Clear statistics registers */ 286 hw->mac.ops.clear_hw_cntrs(hw); 287 288 /* Set No Snoop Disable */ 289 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 290 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 291 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 292 IXGBE_WRITE_FLUSH(hw); 293 294 /* Setup flow control if method for doing so */ 295 if (hw->mac.ops.setup_fc) { 296 ret_val = hw->mac.ops.setup_fc(hw); 297 if (ret_val) 298 return ret_val; 299 } 300 301 /* Cashe bit indicating need for crosstalk fix */ 302 switch (hw->mac.type) { 303 case ixgbe_mac_82599EB: 304 case ixgbe_mac_X550EM_x: 305 case ixgbe_mac_x550em_a: 306 hw->mac.ops.get_device_caps(hw, &device_caps); 307 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 308 hw->need_crosstalk_fix = false; 309 else 310 hw->need_crosstalk_fix = true; 311 break; 312 default: 313 hw->need_crosstalk_fix = false; 314 break; 315 } 316 317 /* Clear adapter stopped flag */ 318 hw->adapter_stopped = false; 319 320 return 0; 321} 322 323/** 324 * ixgbe_start_hw_gen2 - Init sequence for common device family 325 * @hw: pointer to hw structure 326 * 327 * Performs the init sequence common to the second generation 328 * of 10 GbE devices. 329 * Devices in the second generation: 330 * 82599 331 * X540 332 **/ 333s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 334{ 335 u32 i; 336 337 /* Clear the rate limiters */ 338 for (i = 0; i < hw->mac.max_tx_queues; i++) { 339 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 340 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 341 } 342 IXGBE_WRITE_FLUSH(hw); 343 344 return 0; 345} 346 347/** 348 * ixgbe_init_hw_generic - Generic hardware initialization 349 * @hw: pointer to hardware structure 350 * 351 * Initialize the hardware by resetting the hardware, filling the bus info 352 * structure and media type, clears all on chip counters, initializes receive 353 * address registers, multicast table, VLAN filter table, calls routine to set 354 * up link and flow control settings, and leaves transmit and receive units 355 * disabled and uninitialized 356 **/ 357s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 358{ 359 s32 status; 360 361 /* Reset the hardware */ 362 status = hw->mac.ops.reset_hw(hw); 363 364 if (status == 0) { 365 /* Start the HW */ 366 status = hw->mac.ops.start_hw(hw); 367 } 368 369 /* Initialize the LED link active for LED blink support */ 370 if (hw->mac.ops.init_led_link_act) 371 hw->mac.ops.init_led_link_act(hw); 372 373 return status; 374} 375 376/** 377 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 378 * @hw: pointer to hardware structure 379 * 380 * Clears all hardware statistics counters by reading them from the hardware 381 * Statistics counters are clear on read. 382 **/ 383s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 384{ 385 u16 i = 0; 386 387 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 388 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 389 IXGBE_READ_REG(hw, IXGBE_ERRBC); 390 IXGBE_READ_REG(hw, IXGBE_MSPDC); 391 for (i = 0; i < 8; i++) 392 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 393 394 IXGBE_READ_REG(hw, IXGBE_MLFC); 395 IXGBE_READ_REG(hw, IXGBE_MRFC); 396 IXGBE_READ_REG(hw, IXGBE_RLEC); 397 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 398 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 399 if (hw->mac.type >= ixgbe_mac_82599EB) { 400 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 401 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 402 } else { 403 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 404 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 405 } 406 407 for (i = 0; i < 8; i++) { 408 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 409 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 410 if (hw->mac.type >= ixgbe_mac_82599EB) { 411 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 412 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 413 } else { 414 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 415 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 416 } 417 } 418 if (hw->mac.type >= ixgbe_mac_82599EB) 419 for (i = 0; i < 8; i++) 420 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 421 IXGBE_READ_REG(hw, IXGBE_PRC64); 422 IXGBE_READ_REG(hw, IXGBE_PRC127); 423 IXGBE_READ_REG(hw, IXGBE_PRC255); 424 IXGBE_READ_REG(hw, IXGBE_PRC511); 425 IXGBE_READ_REG(hw, IXGBE_PRC1023); 426 IXGBE_READ_REG(hw, IXGBE_PRC1522); 427 IXGBE_READ_REG(hw, IXGBE_GPRC); 428 IXGBE_READ_REG(hw, IXGBE_BPRC); 429 IXGBE_READ_REG(hw, IXGBE_MPRC); 430 IXGBE_READ_REG(hw, IXGBE_GPTC); 431 IXGBE_READ_REG(hw, IXGBE_GORCL); 432 IXGBE_READ_REG(hw, IXGBE_GORCH); 433 IXGBE_READ_REG(hw, IXGBE_GOTCL); 434 IXGBE_READ_REG(hw, IXGBE_GOTCH); 435 if (hw->mac.type == ixgbe_mac_82598EB) 436 for (i = 0; i < 8; i++) 437 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 438 IXGBE_READ_REG(hw, IXGBE_RUC); 439 IXGBE_READ_REG(hw, IXGBE_RFC); 440 IXGBE_READ_REG(hw, IXGBE_ROC); 441 IXGBE_READ_REG(hw, IXGBE_RJC); 442 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 443 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 444 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 445 IXGBE_READ_REG(hw, IXGBE_TORL); 446 IXGBE_READ_REG(hw, IXGBE_TORH); 447 IXGBE_READ_REG(hw, IXGBE_TPR); 448 IXGBE_READ_REG(hw, IXGBE_TPT); 449 IXGBE_READ_REG(hw, IXGBE_PTC64); 450 IXGBE_READ_REG(hw, IXGBE_PTC127); 451 IXGBE_READ_REG(hw, IXGBE_PTC255); 452 IXGBE_READ_REG(hw, IXGBE_PTC511); 453 IXGBE_READ_REG(hw, IXGBE_PTC1023); 454 IXGBE_READ_REG(hw, IXGBE_PTC1522); 455 IXGBE_READ_REG(hw, IXGBE_MPTC); 456 IXGBE_READ_REG(hw, IXGBE_BPTC); 457 for (i = 0; i < 16; i++) { 458 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 459 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 460 if (hw->mac.type >= ixgbe_mac_82599EB) { 461 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 462 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 463 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 464 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 465 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 466 } else { 467 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 468 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 469 } 470 } 471 472 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 473 if (hw->phy.id == 0) 474 hw->phy.ops.identify(hw); 475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 479 } 480 481 return 0; 482} 483 484/** 485 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 486 * @hw: pointer to hardware structure 487 * @pba_num: stores the part number string from the EEPROM 488 * @pba_num_size: part number string buffer length 489 * 490 * Reads the part number string from the EEPROM. 491 **/ 492s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 493 u32 pba_num_size) 494{ 495 s32 ret_val; 496 u16 data; 497 u16 pba_ptr; 498 u16 offset; 499 u16 length; 500 501 if (pba_num == NULL) { 502 hw_dbg(hw, "PBA string buffer was null\n"); 503 return -EINVAL; 504 } 505 506 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 507 if (ret_val) { 508 hw_dbg(hw, "NVM Read Error\n"); 509 return ret_val; 510 } 511 512 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 513 if (ret_val) { 514 hw_dbg(hw, "NVM Read Error\n"); 515 return ret_val; 516 } 517 518 /* 519 * if data is not ptr guard the PBA must be in legacy format which 520 * means pba_ptr is actually our second data word for the PBA number 521 * and we can decode it into an ascii string 522 */ 523 if (data != IXGBE_PBANUM_PTR_GUARD) { 524 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 525 526 /* we will need 11 characters to store the PBA */ 527 if (pba_num_size < 11) { 528 hw_dbg(hw, "PBA string buffer too small\n"); 529 return -ENOSPC; 530 } 531 532 /* extract hex string from data and pba_ptr */ 533 pba_num[0] = (data >> 12) & 0xF; 534 pba_num[1] = (data >> 8) & 0xF; 535 pba_num[2] = (data >> 4) & 0xF; 536 pba_num[3] = data & 0xF; 537 pba_num[4] = (pba_ptr >> 12) & 0xF; 538 pba_num[5] = (pba_ptr >> 8) & 0xF; 539 pba_num[6] = '-'; 540 pba_num[7] = 0; 541 pba_num[8] = (pba_ptr >> 4) & 0xF; 542 pba_num[9] = pba_ptr & 0xF; 543 544 /* put a null character on the end of our string */ 545 pba_num[10] = '\0'; 546 547 /* switch all the data but the '-' to hex char */ 548 for (offset = 0; offset < 10; offset++) { 549 if (pba_num[offset] < 0xA) 550 pba_num[offset] += '0'; 551 else if (pba_num[offset] < 0x10) 552 pba_num[offset] += 'A' - 0xA; 553 } 554 555 return 0; 556 } 557 558 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 559 if (ret_val) { 560 hw_dbg(hw, "NVM Read Error\n"); 561 return ret_val; 562 } 563 564 if (length == 0xFFFF || length == 0) { 565 hw_dbg(hw, "NVM PBA number section invalid length\n"); 566 return -EIO; 567 } 568 569 /* check if pba_num buffer is big enough */ 570 if (pba_num_size < (((u32)length * 2) - 1)) { 571 hw_dbg(hw, "PBA string buffer too small\n"); 572 return -ENOSPC; 573 } 574 575 /* trim pba length from start of string */ 576 pba_ptr++; 577 length--; 578 579 for (offset = 0; offset < length; offset++) { 580 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 581 if (ret_val) { 582 hw_dbg(hw, "NVM Read Error\n"); 583 return ret_val; 584 } 585 pba_num[offset * 2] = (u8)(data >> 8); 586 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 587 } 588 pba_num[offset * 2] = '\0'; 589 590 return 0; 591} 592 593/** 594 * ixgbe_get_mac_addr_generic - Generic get MAC address 595 * @hw: pointer to hardware structure 596 * @mac_addr: Adapter MAC address 597 * 598 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 599 * A reset of the adapter must be performed prior to calling this function 600 * in order for the MAC address to have been loaded from the EEPROM into RAR0 601 **/ 602s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 603{ 604 u32 rar_high; 605 u32 rar_low; 606 u16 i; 607 608 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 609 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 610 611 for (i = 0; i < 4; i++) 612 mac_addr[i] = (u8)(rar_low >> (i*8)); 613 614 for (i = 0; i < 2; i++) 615 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 616 617 return 0; 618} 619 620enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 621{ 622 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 623 case IXGBE_PCI_LINK_WIDTH_1: 624 return ixgbe_bus_width_pcie_x1; 625 case IXGBE_PCI_LINK_WIDTH_2: 626 return ixgbe_bus_width_pcie_x2; 627 case IXGBE_PCI_LINK_WIDTH_4: 628 return ixgbe_bus_width_pcie_x4; 629 case IXGBE_PCI_LINK_WIDTH_8: 630 return ixgbe_bus_width_pcie_x8; 631 default: 632 return ixgbe_bus_width_unknown; 633 } 634} 635 636enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 637{ 638 switch (link_status & IXGBE_PCI_LINK_SPEED) { 639 case IXGBE_PCI_LINK_SPEED_2500: 640 return ixgbe_bus_speed_2500; 641 case IXGBE_PCI_LINK_SPEED_5000: 642 return ixgbe_bus_speed_5000; 643 case IXGBE_PCI_LINK_SPEED_8000: 644 return ixgbe_bus_speed_8000; 645 default: 646 return ixgbe_bus_speed_unknown; 647 } 648} 649 650/** 651 * ixgbe_get_bus_info_generic - Generic set PCI bus info 652 * @hw: pointer to hardware structure 653 * 654 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 655 **/ 656s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 657{ 658 u16 link_status; 659 660 hw->bus.type = ixgbe_bus_type_pci_express; 661 662 /* Get the negotiated link width and speed from PCI config space */ 663 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 664 665 hw->bus.width = ixgbe_convert_bus_width(link_status); 666 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 667 668 hw->mac.ops.set_lan_id(hw); 669 670 return 0; 671} 672 673/** 674 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 675 * @hw: pointer to the HW structure 676 * 677 * Determines the LAN function id by reading memory-mapped registers 678 * and swaps the port value if requested. 679 **/ 680void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 681{ 682 struct ixgbe_bus_info *bus = &hw->bus; 683 u16 ee_ctrl_4; 684 u32 reg; 685 686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 687 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 688 bus->lan_id = bus->func; 689 690 /* check for a port swap */ 691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 692 if (reg & IXGBE_FACTPS_LFS) 693 bus->func ^= 0x1; 694 695 /* Get MAC instance from EEPROM for configuring CS4227 */ 696 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 697 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 698 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 699 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 700 } 701} 702 703/** 704 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 705 * @hw: pointer to hardware structure 706 * 707 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 708 * disables transmit and receive units. The adapter_stopped flag is used by 709 * the shared code and drivers to determine if the adapter is in a stopped 710 * state and should not touch the hardware. 711 **/ 712s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 713{ 714 u32 reg_val; 715 u16 i; 716 717 /* 718 * Set the adapter_stopped flag so other driver functions stop touching 719 * the hardware 720 */ 721 hw->adapter_stopped = true; 722 723 /* Disable the receive unit */ 724 hw->mac.ops.disable_rx(hw); 725 726 /* Clear interrupt mask to stop interrupts from being generated */ 727 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 728 729 /* Clear any pending interrupts, flush previous writes */ 730 IXGBE_READ_REG(hw, IXGBE_EICR); 731 732 /* Disable the transmit unit. Each queue must be disabled. */ 733 for (i = 0; i < hw->mac.max_tx_queues; i++) 734 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 735 736 /* Disable the receive unit by stopping each queue */ 737 for (i = 0; i < hw->mac.max_rx_queues; i++) { 738 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 739 reg_val &= ~IXGBE_RXDCTL_ENABLE; 740 reg_val |= IXGBE_RXDCTL_SWFLSH; 741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 742 } 743 744 /* flush all queues disables */ 745 IXGBE_WRITE_FLUSH(hw); 746 usleep_range(1000, 2000); 747 748 /* 749 * Prevent the PCI-E bus from hanging by disabling PCI-E primary 750 * access and verify no pending requests 751 */ 752 return ixgbe_disable_pcie_primary(hw); 753} 754 755/** 756 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 757 * @hw: pointer to hardware structure 758 * 759 * Store the index for the link active LED. This will be used to support 760 * blinking the LED. 761 **/ 762s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 763{ 764 struct ixgbe_mac_info *mac = &hw->mac; 765 u32 led_reg, led_mode; 766 u16 i; 767 768 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 769 770 /* Get LED link active from the LEDCTL register */ 771 for (i = 0; i < 4; i++) { 772 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 773 774 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 775 IXGBE_LED_LINK_ACTIVE) { 776 mac->led_link_act = i; 777 return 0; 778 } 779 } 780 781 /* If LEDCTL register does not have the LED link active set, then use 782 * known MAC defaults. 783 */ 784 switch (hw->mac.type) { 785 case ixgbe_mac_x550em_a: 786 mac->led_link_act = 0; 787 break; 788 case ixgbe_mac_X550EM_x: 789 mac->led_link_act = 1; 790 break; 791 default: 792 mac->led_link_act = 2; 793 } 794 795 return 0; 796} 797 798/** 799 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 800 * @hw: pointer to hardware structure 801 * @index: led number to turn on 802 **/ 803s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 804{ 805 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 806 807 if (index > 3) 808 return -EINVAL; 809 810 /* To turn on the LED, set mode to ON. */ 811 led_reg &= ~IXGBE_LED_MODE_MASK(index); 812 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 814 IXGBE_WRITE_FLUSH(hw); 815 816 return 0; 817} 818 819/** 820 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 821 * @hw: pointer to hardware structure 822 * @index: led number to turn off 823 **/ 824s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 825{ 826 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 827 828 if (index > 3) 829 return -EINVAL; 830 831 /* To turn off the LED, set mode to OFF. */ 832 led_reg &= ~IXGBE_LED_MODE_MASK(index); 833 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 834 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 835 IXGBE_WRITE_FLUSH(hw); 836 837 return 0; 838} 839 840/** 841 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 842 * @hw: pointer to hardware structure 843 * 844 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 845 * ixgbe_hw struct in order to set up EEPROM access. 846 **/ 847s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 848{ 849 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 850 u32 eec; 851 u16 eeprom_size; 852 853 if (eeprom->type == ixgbe_eeprom_uninitialized) { 854 eeprom->type = ixgbe_eeprom_none; 855 /* Set default semaphore delay to 10ms which is a well 856 * tested value */ 857 eeprom->semaphore_delay = 10; 858 /* Clear EEPROM page size, it will be initialized as needed */ 859 eeprom->word_page_size = 0; 860 861 /* 862 * Check for EEPROM present first. 863 * If not present leave as none 864 */ 865 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 866 if (eec & IXGBE_EEC_PRES) { 867 eeprom->type = ixgbe_eeprom_spi; 868 869 /* 870 * SPI EEPROM is assumed here. This code would need to 871 * change if a future EEPROM is not SPI. 872 */ 873 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 874 IXGBE_EEC_SIZE_SHIFT); 875 eeprom->word_size = BIT(eeprom_size + 876 IXGBE_EEPROM_WORD_SIZE_SHIFT); 877 } 878 879 if (eec & IXGBE_EEC_ADDR_SIZE) 880 eeprom->address_bits = 16; 881 else 882 eeprom->address_bits = 8; 883 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 884 eeprom->type, eeprom->word_size, eeprom->address_bits); 885 } 886 887 return 0; 888} 889 890/** 891 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 892 * @hw: pointer to hardware structure 893 * @offset: offset within the EEPROM to write 894 * @words: number of words 895 * @data: 16 bit word(s) to write to EEPROM 896 * 897 * Reads 16 bit word(s) from EEPROM through bit-bang method 898 **/ 899s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 900 u16 words, u16 *data) 901{ 902 s32 status; 903 u16 i, count; 904 905 hw->eeprom.ops.init_params(hw); 906 907 if (words == 0 || (offset + words > hw->eeprom.word_size)) 908 return -EINVAL; 909 910 /* 911 * The EEPROM page size cannot be queried from the chip. We do lazy 912 * initialization. It is worth to do that when we write large buffer. 913 */ 914 if ((hw->eeprom.word_page_size == 0) && 915 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 916 ixgbe_detect_eeprom_page_size_generic(hw, offset); 917 918 /* 919 * We cannot hold synchronization semaphores for too long 920 * to avoid other entity starvation. However it is more efficient 921 * to read in bursts than synchronizing access for each word. 922 */ 923 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 924 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 925 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 926 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 927 count, &data[i]); 928 929 if (status != 0) 930 break; 931 } 932 933 return status; 934} 935 936/** 937 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 938 * @hw: pointer to hardware structure 939 * @offset: offset within the EEPROM to be written to 940 * @words: number of word(s) 941 * @data: 16 bit word(s) to be written to the EEPROM 942 * 943 * If ixgbe_eeprom_update_checksum is not called after this function, the 944 * EEPROM will most likely contain an invalid checksum. 945 **/ 946static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 947 u16 words, u16 *data) 948{ 949 s32 status; 950 u16 word; 951 u16 page_size; 952 u16 i; 953 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 954 955 /* Prepare the EEPROM for writing */ 956 status = ixgbe_acquire_eeprom(hw); 957 if (status) 958 return status; 959 960 if (ixgbe_ready_eeprom(hw) != 0) { 961 ixgbe_release_eeprom(hw); 962 return -EIO; 963 } 964 965 for (i = 0; i < words; i++) { 966 ixgbe_standby_eeprom(hw); 967 968 /* Send the WRITE ENABLE command (8 bit opcode) */ 969 ixgbe_shift_out_eeprom_bits(hw, 970 IXGBE_EEPROM_WREN_OPCODE_SPI, 971 IXGBE_EEPROM_OPCODE_BITS); 972 973 ixgbe_standby_eeprom(hw); 974 975 /* Some SPI eeproms use the 8th address bit embedded 976 * in the opcode 977 */ 978 if ((hw->eeprom.address_bits == 8) && 979 ((offset + i) >= 128)) 980 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 981 982 /* Send the Write command (8-bit opcode + addr) */ 983 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 984 IXGBE_EEPROM_OPCODE_BITS); 985 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 986 hw->eeprom.address_bits); 987 988 page_size = hw->eeprom.word_page_size; 989 990 /* Send the data in burst via SPI */ 991 do { 992 word = data[i]; 993 word = (word >> 8) | (word << 8); 994 ixgbe_shift_out_eeprom_bits(hw, word, 16); 995 996 if (page_size == 0) 997 break; 998 999 /* do not wrap around page */ 1000 if (((offset + i) & (page_size - 1)) == 1001 (page_size - 1)) 1002 break; 1003 } while (++i < words); 1004 1005 ixgbe_standby_eeprom(hw); 1006 usleep_range(10000, 20000); 1007 } 1008 /* Done with writing - release the EEPROM */ 1009 ixgbe_release_eeprom(hw); 1010 1011 return 0; 1012} 1013 1014/** 1015 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1016 * @hw: pointer to hardware structure 1017 * @offset: offset within the EEPROM to be written to 1018 * @data: 16 bit word to be written to the EEPROM 1019 * 1020 * If ixgbe_eeprom_update_checksum is not called after this function, the 1021 * EEPROM will most likely contain an invalid checksum. 1022 **/ 1023s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1024{ 1025 hw->eeprom.ops.init_params(hw); 1026 1027 if (offset >= hw->eeprom.word_size) 1028 return -EINVAL; 1029 1030 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1031} 1032 1033/** 1034 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1035 * @hw: pointer to hardware structure 1036 * @offset: offset within the EEPROM to be read 1037 * @words: number of word(s) 1038 * @data: read 16 bit words(s) from EEPROM 1039 * 1040 * Reads 16 bit word(s) from EEPROM through bit-bang method 1041 **/ 1042s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1043 u16 words, u16 *data) 1044{ 1045 s32 status; 1046 u16 i, count; 1047 1048 hw->eeprom.ops.init_params(hw); 1049 1050 if (words == 0 || (offset + words > hw->eeprom.word_size)) 1051 return -EINVAL; 1052 1053 /* 1054 * We cannot hold synchronization semaphores for too long 1055 * to avoid other entity starvation. However it is more efficient 1056 * to read in bursts than synchronizing access for each word. 1057 */ 1058 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1059 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1060 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1061 1062 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1063 count, &data[i]); 1064 1065 if (status) 1066 return status; 1067 } 1068 1069 return 0; 1070} 1071 1072/** 1073 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1074 * @hw: pointer to hardware structure 1075 * @offset: offset within the EEPROM to be read 1076 * @words: number of word(s) 1077 * @data: read 16 bit word(s) from EEPROM 1078 * 1079 * Reads 16 bit word(s) from EEPROM through bit-bang method 1080 **/ 1081static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1082 u16 words, u16 *data) 1083{ 1084 s32 status; 1085 u16 word_in; 1086 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1087 u16 i; 1088 1089 /* Prepare the EEPROM for reading */ 1090 status = ixgbe_acquire_eeprom(hw); 1091 if (status) 1092 return status; 1093 1094 if (ixgbe_ready_eeprom(hw) != 0) { 1095 ixgbe_release_eeprom(hw); 1096 return -EIO; 1097 } 1098 1099 for (i = 0; i < words; i++) { 1100 ixgbe_standby_eeprom(hw); 1101 /* Some SPI eeproms use the 8th address bit embedded 1102 * in the opcode 1103 */ 1104 if ((hw->eeprom.address_bits == 8) && 1105 ((offset + i) >= 128)) 1106 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1107 1108 /* Send the READ command (opcode + addr) */ 1109 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1110 IXGBE_EEPROM_OPCODE_BITS); 1111 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1112 hw->eeprom.address_bits); 1113 1114 /* Read the data. */ 1115 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1116 data[i] = (word_in >> 8) | (word_in << 8); 1117 } 1118 1119 /* End this read operation */ 1120 ixgbe_release_eeprom(hw); 1121 1122 return 0; 1123} 1124 1125/** 1126 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1127 * @hw: pointer to hardware structure 1128 * @offset: offset within the EEPROM to be read 1129 * @data: read 16 bit value from EEPROM 1130 * 1131 * Reads 16 bit value from EEPROM through bit-bang method 1132 **/ 1133s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1134 u16 *data) 1135{ 1136 hw->eeprom.ops.init_params(hw); 1137 1138 if (offset >= hw->eeprom.word_size) 1139 return -EINVAL; 1140 1141 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1142} 1143 1144/** 1145 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1146 * @hw: pointer to hardware structure 1147 * @offset: offset of word in the EEPROM to read 1148 * @words: number of word(s) 1149 * @data: 16 bit word(s) from the EEPROM 1150 * 1151 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1152 **/ 1153s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1154 u16 words, u16 *data) 1155{ 1156 u32 eerd; 1157 s32 status; 1158 u32 i; 1159 1160 hw->eeprom.ops.init_params(hw); 1161 1162 if (words == 0 || offset >= hw->eeprom.word_size) 1163 return -EINVAL; 1164 1165 for (i = 0; i < words; i++) { 1166 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1167 IXGBE_EEPROM_RW_REG_START; 1168 1169 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1170 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1171 1172 if (status == 0) { 1173 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1174 IXGBE_EEPROM_RW_REG_DATA); 1175 } else { 1176 hw_dbg(hw, "Eeprom read timed out\n"); 1177 return status; 1178 } 1179 } 1180 1181 return 0; 1182} 1183 1184/** 1185 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1186 * @hw: pointer to hardware structure 1187 * @offset: offset within the EEPROM to be used as a scratch pad 1188 * 1189 * Discover EEPROM page size by writing marching data at given offset. 1190 * This function is called only when we are writing a new large buffer 1191 * at given offset so the data would be overwritten anyway. 1192 **/ 1193static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1194 u16 offset) 1195{ 1196 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1197 s32 status; 1198 u16 i; 1199 1200 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1201 data[i] = i; 1202 1203 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1204 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1205 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1206 hw->eeprom.word_page_size = 0; 1207 if (status) 1208 return status; 1209 1210 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1211 if (status) 1212 return status; 1213 1214 /* 1215 * When writing in burst more than the actual page size 1216 * EEPROM address wraps around current page. 1217 */ 1218 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1219 1220 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1221 hw->eeprom.word_page_size); 1222 return 0; 1223} 1224 1225/** 1226 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1227 * @hw: pointer to hardware structure 1228 * @offset: offset of word in the EEPROM to read 1229 * @data: word read from the EEPROM 1230 * 1231 * Reads a 16 bit word from the EEPROM using the EERD register. 1232 **/ 1233s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1234{ 1235 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1236} 1237 1238/** 1239 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1240 * @hw: pointer to hardware structure 1241 * @offset: offset of word in the EEPROM to write 1242 * @words: number of words 1243 * @data: word(s) write to the EEPROM 1244 * 1245 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1246 **/ 1247s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1248 u16 words, u16 *data) 1249{ 1250 u32 eewr; 1251 s32 status; 1252 u16 i; 1253 1254 hw->eeprom.ops.init_params(hw); 1255 1256 if (words == 0 || offset >= hw->eeprom.word_size) 1257 return -EINVAL; 1258 1259 for (i = 0; i < words; i++) { 1260 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1261 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1262 IXGBE_EEPROM_RW_REG_START; 1263 1264 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1265 if (status) { 1266 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1267 return status; 1268 } 1269 1270 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1271 1272 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1273 if (status) { 1274 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1275 return status; 1276 } 1277 } 1278 1279 return 0; 1280} 1281 1282/** 1283 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1284 * @hw: pointer to hardware structure 1285 * @offset: offset of word in the EEPROM to write 1286 * @data: word write to the EEPROM 1287 * 1288 * Write a 16 bit word to the EEPROM using the EEWR register. 1289 **/ 1290s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1291{ 1292 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1293} 1294 1295/** 1296 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1297 * @hw: pointer to hardware structure 1298 * @ee_reg: EEPROM flag for polling 1299 * 1300 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1301 * read or write is done respectively. 1302 **/ 1303static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1304{ 1305 u32 i; 1306 u32 reg; 1307 1308 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1309 if (ee_reg == IXGBE_NVM_POLL_READ) 1310 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1311 else 1312 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1313 1314 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1315 return 0; 1316 } 1317 udelay(5); 1318 } 1319 return -EIO; 1320} 1321 1322/** 1323 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1324 * @hw: pointer to hardware structure 1325 * 1326 * Prepares EEPROM for access using bit-bang method. This function should 1327 * be called before issuing a command to the EEPROM. 1328 **/ 1329static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1330{ 1331 u32 eec; 1332 u32 i; 1333 1334 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1335 return -EBUSY; 1336 1337 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1338 1339 /* Request EEPROM Access */ 1340 eec |= IXGBE_EEC_REQ; 1341 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1342 1343 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1344 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1345 if (eec & IXGBE_EEC_GNT) 1346 break; 1347 udelay(5); 1348 } 1349 1350 /* Release if grant not acquired */ 1351 if (!(eec & IXGBE_EEC_GNT)) { 1352 eec &= ~IXGBE_EEC_REQ; 1353 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1354 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1355 1356 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1357 return -EIO; 1358 } 1359 1360 /* Setup EEPROM for Read/Write */ 1361 /* Clear CS and SK */ 1362 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1363 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1364 IXGBE_WRITE_FLUSH(hw); 1365 udelay(1); 1366 return 0; 1367} 1368 1369/** 1370 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1371 * @hw: pointer to hardware structure 1372 * 1373 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1374 **/ 1375static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1376{ 1377 u32 timeout = 2000; 1378 u32 i; 1379 u32 swsm; 1380 1381 /* Get SMBI software semaphore between device drivers first */ 1382 for (i = 0; i < timeout; i++) { 1383 /* 1384 * If the SMBI bit is 0 when we read it, then the bit will be 1385 * set and we have the semaphore 1386 */ 1387 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1388 if (!(swsm & IXGBE_SWSM_SMBI)) 1389 break; 1390 usleep_range(50, 100); 1391 } 1392 1393 if (i == timeout) { 1394 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1395 /* this release is particularly important because our attempts 1396 * above to get the semaphore may have succeeded, and if there 1397 * was a timeout, we should unconditionally clear the semaphore 1398 * bits to free the driver to make progress 1399 */ 1400 ixgbe_release_eeprom_semaphore(hw); 1401 1402 usleep_range(50, 100); 1403 /* one last try 1404 * If the SMBI bit is 0 when we read it, then the bit will be 1405 * set and we have the semaphore 1406 */ 1407 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1408 if (swsm & IXGBE_SWSM_SMBI) { 1409 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1410 return -EIO; 1411 } 1412 } 1413 1414 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1415 for (i = 0; i < timeout; i++) { 1416 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1417 1418 /* Set the SW EEPROM semaphore bit to request access */ 1419 swsm |= IXGBE_SWSM_SWESMBI; 1420 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1421 1422 /* If we set the bit successfully then we got the 1423 * semaphore. 1424 */ 1425 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1426 if (swsm & IXGBE_SWSM_SWESMBI) 1427 break; 1428 1429 usleep_range(50, 100); 1430 } 1431 1432 /* Release semaphores and return error if SW EEPROM semaphore 1433 * was not granted because we don't have access to the EEPROM 1434 */ 1435 if (i >= timeout) { 1436 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1437 ixgbe_release_eeprom_semaphore(hw); 1438 return -EIO; 1439 } 1440 1441 return 0; 1442} 1443 1444/** 1445 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1446 * @hw: pointer to hardware structure 1447 * 1448 * This function clears hardware semaphore bits. 1449 **/ 1450static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1451{ 1452 u32 swsm; 1453 1454 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1455 1456 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1457 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1458 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1459 IXGBE_WRITE_FLUSH(hw); 1460} 1461 1462/** 1463 * ixgbe_ready_eeprom - Polls for EEPROM ready 1464 * @hw: pointer to hardware structure 1465 **/ 1466static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1467{ 1468 u16 i; 1469 u8 spi_stat_reg; 1470 1471 /* 1472 * Read "Status Register" repeatedly until the LSB is cleared. The 1473 * EEPROM will signal that the command has been completed by clearing 1474 * bit 0 of the internal status register. If it's not cleared within 1475 * 5 milliseconds, then error out. 1476 */ 1477 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1478 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1479 IXGBE_EEPROM_OPCODE_BITS); 1480 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1481 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1482 break; 1483 1484 udelay(5); 1485 ixgbe_standby_eeprom(hw); 1486 } 1487 1488 /* 1489 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1490 * devices (and only 0-5mSec on 5V devices) 1491 */ 1492 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1493 hw_dbg(hw, "SPI EEPROM Status error\n"); 1494 return -EIO; 1495 } 1496 1497 return 0; 1498} 1499 1500/** 1501 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1502 * @hw: pointer to hardware structure 1503 **/ 1504static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1505{ 1506 u32 eec; 1507 1508 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1509 1510 /* Toggle CS to flush commands */ 1511 eec |= IXGBE_EEC_CS; 1512 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1513 IXGBE_WRITE_FLUSH(hw); 1514 udelay(1); 1515 eec &= ~IXGBE_EEC_CS; 1516 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1517 IXGBE_WRITE_FLUSH(hw); 1518 udelay(1); 1519} 1520 1521/** 1522 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1523 * @hw: pointer to hardware structure 1524 * @data: data to send to the EEPROM 1525 * @count: number of bits to shift out 1526 **/ 1527static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1528 u16 count) 1529{ 1530 u32 eec; 1531 u32 mask; 1532 u32 i; 1533 1534 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1535 1536 /* 1537 * Mask is used to shift "count" bits of "data" out to the EEPROM 1538 * one bit at a time. Determine the starting bit based on count 1539 */ 1540 mask = BIT(count - 1); 1541 1542 for (i = 0; i < count; i++) { 1543 /* 1544 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1545 * "1", and then raising and then lowering the clock (the SK 1546 * bit controls the clock input to the EEPROM). A "0" is 1547 * shifted out to the EEPROM by setting "DI" to "0" and then 1548 * raising and then lowering the clock. 1549 */ 1550 if (data & mask) 1551 eec |= IXGBE_EEC_DI; 1552 else 1553 eec &= ~IXGBE_EEC_DI; 1554 1555 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1556 IXGBE_WRITE_FLUSH(hw); 1557 1558 udelay(1); 1559 1560 ixgbe_raise_eeprom_clk(hw, &eec); 1561 ixgbe_lower_eeprom_clk(hw, &eec); 1562 1563 /* 1564 * Shift mask to signify next bit of data to shift in to the 1565 * EEPROM 1566 */ 1567 mask = mask >> 1; 1568 } 1569 1570 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1571 eec &= ~IXGBE_EEC_DI; 1572 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1573 IXGBE_WRITE_FLUSH(hw); 1574} 1575 1576/** 1577 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1578 * @hw: pointer to hardware structure 1579 * @count: number of bits to shift 1580 **/ 1581static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1582{ 1583 u32 eec; 1584 u32 i; 1585 u16 data = 0; 1586 1587 /* 1588 * In order to read a register from the EEPROM, we need to shift 1589 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1590 * the clock input to the EEPROM (setting the SK bit), and then reading 1591 * the value of the "DO" bit. During this "shifting in" process the 1592 * "DI" bit should always be clear. 1593 */ 1594 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1595 1596 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1597 1598 for (i = 0; i < count; i++) { 1599 data = data << 1; 1600 ixgbe_raise_eeprom_clk(hw, &eec); 1601 1602 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1603 1604 eec &= ~(IXGBE_EEC_DI); 1605 if (eec & IXGBE_EEC_DO) 1606 data |= 1; 1607 1608 ixgbe_lower_eeprom_clk(hw, &eec); 1609 } 1610 1611 return data; 1612} 1613 1614/** 1615 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1616 * @hw: pointer to hardware structure 1617 * @eec: EEC register's current value 1618 **/ 1619static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1620{ 1621 /* 1622 * Raise the clock input to the EEPROM 1623 * (setting the SK bit), then delay 1624 */ 1625 *eec = *eec | IXGBE_EEC_SK; 1626 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1627 IXGBE_WRITE_FLUSH(hw); 1628 udelay(1); 1629} 1630 1631/** 1632 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1633 * @hw: pointer to hardware structure 1634 * @eec: EEC's current value 1635 **/ 1636static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1637{ 1638 /* 1639 * Lower the clock input to the EEPROM (clearing the SK bit), then 1640 * delay 1641 */ 1642 *eec = *eec & ~IXGBE_EEC_SK; 1643 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1644 IXGBE_WRITE_FLUSH(hw); 1645 udelay(1); 1646} 1647 1648/** 1649 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1650 * @hw: pointer to hardware structure 1651 **/ 1652static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1653{ 1654 u32 eec; 1655 1656 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1657 1658 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1659 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1660 1661 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1662 IXGBE_WRITE_FLUSH(hw); 1663 1664 udelay(1); 1665 1666 /* Stop requesting EEPROM access */ 1667 eec &= ~IXGBE_EEC_REQ; 1668 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1669 1670 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1671 1672 /* 1673 * Delay before attempt to obtain semaphore again to allow FW 1674 * access. semaphore_delay is in ms we need us for usleep_range 1675 */ 1676 usleep_range(hw->eeprom.semaphore_delay * 1000, 1677 hw->eeprom.semaphore_delay * 2000); 1678} 1679 1680/** 1681 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1682 * @hw: pointer to hardware structure 1683 **/ 1684s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1685{ 1686 u16 i; 1687 u16 j; 1688 u16 checksum = 0; 1689 u16 length = 0; 1690 u16 pointer = 0; 1691 u16 word = 0; 1692 1693 /* Include 0x0-0x3F in the checksum */ 1694 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1695 if (hw->eeprom.ops.read(hw, i, &word)) { 1696 hw_dbg(hw, "EEPROM read failed\n"); 1697 break; 1698 } 1699 checksum += word; 1700 } 1701 1702 /* Include all data from pointers except for the fw pointer */ 1703 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1704 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1705 hw_dbg(hw, "EEPROM read failed\n"); 1706 return -EIO; 1707 } 1708 1709 /* If the pointer seems invalid */ 1710 if (pointer == 0xFFFF || pointer == 0) 1711 continue; 1712 1713 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1714 hw_dbg(hw, "EEPROM read failed\n"); 1715 return -EIO; 1716 } 1717 1718 if (length == 0xFFFF || length == 0) 1719 continue; 1720 1721 for (j = pointer + 1; j <= pointer + length; j++) { 1722 if (hw->eeprom.ops.read(hw, j, &word)) { 1723 hw_dbg(hw, "EEPROM read failed\n"); 1724 return -EIO; 1725 } 1726 checksum += word; 1727 } 1728 } 1729 1730 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1731 1732 return (s32)checksum; 1733} 1734 1735/** 1736 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1737 * @hw: pointer to hardware structure 1738 * @checksum_val: calculated checksum 1739 * 1740 * Performs checksum calculation and validates the EEPROM checksum. If the 1741 * caller does not need checksum_val, the value can be NULL. 1742 **/ 1743s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1744 u16 *checksum_val) 1745{ 1746 s32 status; 1747 u16 checksum; 1748 u16 read_checksum = 0; 1749 1750 /* 1751 * Read the first word from the EEPROM. If this times out or fails, do 1752 * not continue or we could be in for a very long wait while every 1753 * EEPROM read fails 1754 */ 1755 status = hw->eeprom.ops.read(hw, 0, &checksum); 1756 if (status) { 1757 hw_dbg(hw, "EEPROM read failed\n"); 1758 return status; 1759 } 1760 1761 status = hw->eeprom.ops.calc_checksum(hw); 1762 if (status < 0) 1763 return status; 1764 1765 checksum = (u16)(status & 0xffff); 1766 1767 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1768 if (status) { 1769 hw_dbg(hw, "EEPROM read failed\n"); 1770 return status; 1771 } 1772 1773 /* Verify read checksum from EEPROM is the same as 1774 * calculated checksum 1775 */ 1776 if (read_checksum != checksum) 1777 status = -EIO; 1778 1779 /* If the user cares, return the calculated checksum */ 1780 if (checksum_val) 1781 *checksum_val = checksum; 1782 1783 return status; 1784} 1785 1786/** 1787 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1788 * @hw: pointer to hardware structure 1789 **/ 1790s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1791{ 1792 s32 status; 1793 u16 checksum; 1794 1795 /* 1796 * Read the first word from the EEPROM. If this times out or fails, do 1797 * not continue or we could be in for a very long wait while every 1798 * EEPROM read fails 1799 */ 1800 status = hw->eeprom.ops.read(hw, 0, &checksum); 1801 if (status) { 1802 hw_dbg(hw, "EEPROM read failed\n"); 1803 return status; 1804 } 1805 1806 status = hw->eeprom.ops.calc_checksum(hw); 1807 if (status < 0) 1808 return status; 1809 1810 checksum = (u16)(status & 0xffff); 1811 1812 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1813 1814 return status; 1815} 1816 1817/** 1818 * ixgbe_set_rar_generic - Set Rx address register 1819 * @hw: pointer to hardware structure 1820 * @index: Receive address register to write 1821 * @addr: Address to put into receive address register 1822 * @vmdq: VMDq "set" or "pool" index 1823 * @enable_addr: set flag that address is active 1824 * 1825 * Puts an ethernet address into a receive address register. 1826 **/ 1827s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1828 u32 enable_addr) 1829{ 1830 u32 rar_low, rar_high; 1831 u32 rar_entries = hw->mac.num_rar_entries; 1832 1833 /* Make sure we are using a valid rar index range */ 1834 if (index >= rar_entries) { 1835 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1836 return -EINVAL; 1837 } 1838 1839 /* setup VMDq pool selection before this RAR gets enabled */ 1840 hw->mac.ops.set_vmdq(hw, index, vmdq); 1841 1842 /* 1843 * HW expects these in little endian so we reverse the byte 1844 * order from network order (big endian) to little endian 1845 */ 1846 rar_low = ((u32)addr[0] | 1847 ((u32)addr[1] << 8) | 1848 ((u32)addr[2] << 16) | 1849 ((u32)addr[3] << 24)); 1850 /* 1851 * Some parts put the VMDq setting in the extra RAH bits, 1852 * so save everything except the lower 16 bits that hold part 1853 * of the address and the address valid bit. 1854 */ 1855 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1856 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1857 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1858 1859 if (enable_addr != 0) 1860 rar_high |= IXGBE_RAH_AV; 1861 1862 /* Record lower 32 bits of MAC address and then make 1863 * sure that write is flushed to hardware before writing 1864 * the upper 16 bits and setting the valid bit. 1865 */ 1866 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1867 IXGBE_WRITE_FLUSH(hw); 1868 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1869 1870 return 0; 1871} 1872 1873/** 1874 * ixgbe_clear_rar_generic - Remove Rx address register 1875 * @hw: pointer to hardware structure 1876 * @index: Receive address register to write 1877 * 1878 * Clears an ethernet address from a receive address register. 1879 **/ 1880s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1881{ 1882 u32 rar_high; 1883 u32 rar_entries = hw->mac.num_rar_entries; 1884 1885 /* Make sure we are using a valid rar index range */ 1886 if (index >= rar_entries) { 1887 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1888 return -EINVAL; 1889 } 1890 1891 /* 1892 * Some parts put the VMDq setting in the extra RAH bits, 1893 * so save everything except the lower 16 bits that hold part 1894 * of the address and the address valid bit. 1895 */ 1896 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1897 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1898 1899 /* Clear the address valid bit and upper 16 bits of the address 1900 * before clearing the lower bits. This way we aren't updating 1901 * a live filter. 1902 */ 1903 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1904 IXGBE_WRITE_FLUSH(hw); 1905 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1906 1907 /* clear VMDq pool/queue selection for this RAR */ 1908 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1909 1910 return 0; 1911} 1912 1913/** 1914 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1915 * @hw: pointer to hardware structure 1916 * 1917 * Places the MAC address in receive address register 0 and clears the rest 1918 * of the receive address registers. Clears the multicast table. Assumes 1919 * the receiver is in reset when the routine is called. 1920 **/ 1921s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1922{ 1923 u32 i; 1924 u32 rar_entries = hw->mac.num_rar_entries; 1925 1926 /* 1927 * If the current mac address is valid, assume it is a software override 1928 * to the permanent address. 1929 * Otherwise, use the permanent address from the eeprom. 1930 */ 1931 if (!is_valid_ether_addr(hw->mac.addr)) { 1932 /* Get the MAC address from the RAR0 for later reference */ 1933 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1934 1935 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1936 } else { 1937 /* Setup the receive address. */ 1938 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1939 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1940 1941 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1942 } 1943 1944 /* clear VMDq pool/queue selection for RAR 0 */ 1945 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1946 1947 hw->addr_ctrl.overflow_promisc = 0; 1948 1949 hw->addr_ctrl.rar_used_count = 1; 1950 1951 /* Zero out the other receive addresses. */ 1952 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1953 for (i = 1; i < rar_entries; i++) { 1954 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1955 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1956 } 1957 1958 /* Clear the MTA */ 1959 hw->addr_ctrl.mta_in_use = 0; 1960 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1961 1962 hw_dbg(hw, " Clearing MTA\n"); 1963 for (i = 0; i < hw->mac.mcft_size; i++) 1964 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1965 1966 if (hw->mac.ops.init_uta_tables) 1967 hw->mac.ops.init_uta_tables(hw); 1968 1969 return 0; 1970} 1971 1972/** 1973 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1974 * @hw: pointer to hardware structure 1975 * @mc_addr: the multicast address 1976 * 1977 * Extracts the 12 bits, from a multicast address, to determine which 1978 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1979 * incoming rx multicast addresses, to determine the bit-vector to check in 1980 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1981 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1982 * to mc_filter_type. 1983 **/ 1984static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1985{ 1986 u32 vector = 0; 1987 1988 switch (hw->mac.mc_filter_type) { 1989 case 0: /* use bits [47:36] of the address */ 1990 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1991 break; 1992 case 1: /* use bits [46:35] of the address */ 1993 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1994 break; 1995 case 2: /* use bits [45:34] of the address */ 1996 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1997 break; 1998 case 3: /* use bits [43:32] of the address */ 1999 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2000 break; 2001 default: /* Invalid mc_filter_type */ 2002 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2003 break; 2004 } 2005 2006 /* vector can only be 12-bits or boundary will be exceeded */ 2007 vector &= 0xFFF; 2008 return vector; 2009} 2010 2011/** 2012 * ixgbe_set_mta - Set bit-vector in multicast table 2013 * @hw: pointer to hardware structure 2014 * @mc_addr: Multicast address 2015 * 2016 * Sets the bit-vector in the multicast table. 2017 **/ 2018static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2019{ 2020 u32 vector; 2021 u32 vector_bit; 2022 u32 vector_reg; 2023 2024 hw->addr_ctrl.mta_in_use++; 2025 2026 vector = ixgbe_mta_vector(hw, mc_addr); 2027 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2028 2029 /* 2030 * The MTA is a register array of 128 32-bit registers. It is treated 2031 * like an array of 4096 bits. We want to set bit 2032 * BitArray[vector_value]. So we figure out what register the bit is 2033 * in, read it, OR in the new bit, then write back the new value. The 2034 * register is determined by the upper 7 bits of the vector value and 2035 * the bit within that register are determined by the lower 5 bits of 2036 * the value. 2037 */ 2038 vector_reg = (vector >> 5) & 0x7F; 2039 vector_bit = vector & 0x1F; 2040 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2041} 2042 2043/** 2044 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2045 * @hw: pointer to hardware structure 2046 * @netdev: pointer to net device structure 2047 * 2048 * The given list replaces any existing list. Clears the MC addrs from receive 2049 * address registers and the multicast table. Uses unused receive address 2050 * registers for the first multicast addresses, and hashes the rest into the 2051 * multicast table. 2052 **/ 2053s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2054 struct net_device *netdev) 2055{ 2056 struct netdev_hw_addr *ha; 2057 u32 i; 2058 2059 /* 2060 * Set the new number of MC addresses that we are being requested to 2061 * use. 2062 */ 2063 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2064 hw->addr_ctrl.mta_in_use = 0; 2065 2066 /* Clear mta_shadow */ 2067 hw_dbg(hw, " Clearing MTA\n"); 2068 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2069 2070 /* Update mta shadow */ 2071 netdev_for_each_mc_addr(ha, netdev) { 2072 hw_dbg(hw, " Adding the multicast addresses:\n"); 2073 ixgbe_set_mta(hw, ha->addr); 2074 } 2075 2076 /* Enable mta */ 2077 for (i = 0; i < hw->mac.mcft_size; i++) 2078 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2079 hw->mac.mta_shadow[i]); 2080 2081 if (hw->addr_ctrl.mta_in_use > 0) 2082 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2083 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2084 2085 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2086 return 0; 2087} 2088 2089/** 2090 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2091 * @hw: pointer to hardware structure 2092 * 2093 * Enables multicast address in RAR and the use of the multicast hash table. 2094 **/ 2095s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2096{ 2097 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2098 2099 if (a->mta_in_use > 0) 2100 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2101 hw->mac.mc_filter_type); 2102 2103 return 0; 2104} 2105 2106/** 2107 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2108 * @hw: pointer to hardware structure 2109 * 2110 * Disables multicast address in RAR and the use of the multicast hash table. 2111 **/ 2112s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2113{ 2114 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2115 2116 if (a->mta_in_use > 0) 2117 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2118 2119 return 0; 2120} 2121 2122/** 2123 * ixgbe_fc_enable_generic - Enable flow control 2124 * @hw: pointer to hardware structure 2125 * 2126 * Enable flow control according to the current settings. 2127 **/ 2128s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2129{ 2130 u32 mflcn_reg, fccfg_reg; 2131 u32 reg; 2132 u32 fcrtl, fcrth; 2133 int i; 2134 2135 /* Validate the water mark configuration. */ 2136 if (!hw->fc.pause_time) 2137 return -EINVAL; 2138 2139 /* Low water mark of zero causes XOFF floods */ 2140 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2141 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2142 hw->fc.high_water[i]) { 2143 if (!hw->fc.low_water[i] || 2144 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2145 hw_dbg(hw, "Invalid water mark configuration\n"); 2146 return -EINVAL; 2147 } 2148 } 2149 } 2150 2151 /* Negotiate the fc mode to use */ 2152 hw->mac.ops.fc_autoneg(hw); 2153 2154 /* Disable any previous flow control settings */ 2155 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2156 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2157 2158 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2159 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2160 2161 /* 2162 * The possible values of fc.current_mode are: 2163 * 0: Flow control is completely disabled 2164 * 1: Rx flow control is enabled (we can receive pause frames, 2165 * but not send pause frames). 2166 * 2: Tx flow control is enabled (we can send pause frames but 2167 * we do not support receiving pause frames). 2168 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2169 * other: Invalid. 2170 */ 2171 switch (hw->fc.current_mode) { 2172 case ixgbe_fc_none: 2173 /* 2174 * Flow control is disabled by software override or autoneg. 2175 * The code below will actually disable it in the HW. 2176 */ 2177 break; 2178 case ixgbe_fc_rx_pause: 2179 /* 2180 * Rx Flow control is enabled and Tx Flow control is 2181 * disabled by software override. Since there really 2182 * isn't a way to advertise that we are capable of RX 2183 * Pause ONLY, we will advertise that we support both 2184 * symmetric and asymmetric Rx PAUSE. Later, we will 2185 * disable the adapter's ability to send PAUSE frames. 2186 */ 2187 mflcn_reg |= IXGBE_MFLCN_RFCE; 2188 break; 2189 case ixgbe_fc_tx_pause: 2190 /* 2191 * Tx Flow control is enabled, and Rx Flow control is 2192 * disabled by software override. 2193 */ 2194 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2195 break; 2196 case ixgbe_fc_full: 2197 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2198 mflcn_reg |= IXGBE_MFLCN_RFCE; 2199 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2200 break; 2201 default: 2202 hw_dbg(hw, "Flow control param set incorrectly\n"); 2203 return -EIO; 2204 } 2205 2206 /* Set 802.3x based flow control settings. */ 2207 mflcn_reg |= IXGBE_MFLCN_DPF; 2208 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2209 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2210 2211 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2212 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2213 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2214 hw->fc.high_water[i]) { 2215 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2216 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2217 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2218 } else { 2219 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2220 /* 2221 * In order to prevent Tx hangs when the internal Tx 2222 * switch is enabled we must set the high water mark 2223 * to the Rx packet buffer size - 24KB. This allows 2224 * the Tx switch to function even under heavy Rx 2225 * workloads. 2226 */ 2227 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2228 } 2229 2230 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2231 } 2232 2233 /* Configure pause time (2 TCs per register) */ 2234 reg = hw->fc.pause_time * 0x00010001U; 2235 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2236 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2237 2238 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2239 2240 return 0; 2241} 2242 2243/** 2244 * ixgbe_negotiate_fc - Negotiate flow control 2245 * @hw: pointer to hardware structure 2246 * @adv_reg: flow control advertised settings 2247 * @lp_reg: link partner's flow control settings 2248 * @adv_sym: symmetric pause bit in advertisement 2249 * @adv_asm: asymmetric pause bit in advertisement 2250 * @lp_sym: symmetric pause bit in link partner advertisement 2251 * @lp_asm: asymmetric pause bit in link partner advertisement 2252 * 2253 * Find the intersection between advertised settings and link partner's 2254 * advertised settings 2255 **/ 2256s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2257 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2258{ 2259 if ((!(adv_reg)) || (!(lp_reg))) 2260 return -EINVAL; 2261 2262 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2263 /* 2264 * Now we need to check if the user selected Rx ONLY 2265 * of pause frames. In this case, we had to advertise 2266 * FULL flow control because we could not advertise RX 2267 * ONLY. Hence, we must now check to see if we need to 2268 * turn OFF the TRANSMISSION of PAUSE frames. 2269 */ 2270 if (hw->fc.requested_mode == ixgbe_fc_full) { 2271 hw->fc.current_mode = ixgbe_fc_full; 2272 hw_dbg(hw, "Flow Control = FULL.\n"); 2273 } else { 2274 hw->fc.current_mode = ixgbe_fc_rx_pause; 2275 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2276 } 2277 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2278 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2279 hw->fc.current_mode = ixgbe_fc_tx_pause; 2280 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2281 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2282 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2283 hw->fc.current_mode = ixgbe_fc_rx_pause; 2284 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2285 } else { 2286 hw->fc.current_mode = ixgbe_fc_none; 2287 hw_dbg(hw, "Flow Control = NONE.\n"); 2288 } 2289 return 0; 2290} 2291 2292/** 2293 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2294 * @hw: pointer to hardware structure 2295 * 2296 * Enable flow control according on 1 gig fiber. 2297 **/ 2298static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2299{ 2300 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2301 s32 ret_val; 2302 2303 /* 2304 * On multispeed fiber at 1g, bail out if 2305 * - link is up but AN did not complete, or if 2306 * - link is up and AN completed but timed out 2307 */ 2308 2309 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2310 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2311 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2312 return -EIO; 2313 2314 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2315 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2316 2317 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2318 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2319 IXGBE_PCS1GANA_ASM_PAUSE, 2320 IXGBE_PCS1GANA_SYM_PAUSE, 2321 IXGBE_PCS1GANA_ASM_PAUSE); 2322 2323 return ret_val; 2324} 2325 2326/** 2327 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2328 * @hw: pointer to hardware structure 2329 * 2330 * Enable flow control according to IEEE clause 37. 2331 **/ 2332static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2333{ 2334 u32 links2, anlp1_reg, autoc_reg, links; 2335 s32 ret_val; 2336 2337 /* 2338 * On backplane, bail out if 2339 * - backplane autoneg was not completed, or if 2340 * - we are 82599 and link partner is not AN enabled 2341 */ 2342 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2343 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2344 return -EIO; 2345 2346 if (hw->mac.type == ixgbe_mac_82599EB) { 2347 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2348 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2349 return -EIO; 2350 } 2351 /* 2352 * Read the 10g AN autoc and LP ability registers and resolve 2353 * local flow control settings accordingly 2354 */ 2355 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2356 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2357 2358 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2359 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2360 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2361 2362 return ret_val; 2363} 2364 2365/** 2366 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2367 * @hw: pointer to hardware structure 2368 * 2369 * Enable flow control according to IEEE clause 37. 2370 **/ 2371static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2372{ 2373 u16 technology_ability_reg = 0; 2374 u16 lp_technology_ability_reg = 0; 2375 2376 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2377 MDIO_MMD_AN, 2378 &technology_ability_reg); 2379 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2380 MDIO_MMD_AN, 2381 &lp_technology_ability_reg); 2382 2383 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2384 (u32)lp_technology_ability_reg, 2385 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2386 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2387} 2388 2389/** 2390 * ixgbe_fc_autoneg - Configure flow control 2391 * @hw: pointer to hardware structure 2392 * 2393 * Compares our advertised flow control capabilities to those advertised by 2394 * our link partner, and determines the proper flow control mode to use. 2395 **/ 2396void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2397{ 2398 ixgbe_link_speed speed; 2399 s32 ret_val = -EIO; 2400 bool link_up; 2401 2402 /* 2403 * AN should have completed when the cable was plugged in. 2404 * Look for reasons to bail out. Bail out if: 2405 * - FC autoneg is disabled, or if 2406 * - link is not up. 2407 * 2408 * Since we're being called from an LSC, link is already known to be up. 2409 * So use link_up_wait_to_complete=false. 2410 */ 2411 if (hw->fc.disable_fc_autoneg) 2412 goto out; 2413 2414 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2415 if (!link_up) 2416 goto out; 2417 2418 switch (hw->phy.media_type) { 2419 /* Autoneg flow control on fiber adapters */ 2420 case ixgbe_media_type_fiber: 2421 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2422 ret_val = ixgbe_fc_autoneg_fiber(hw); 2423 break; 2424 2425 /* Autoneg flow control on backplane adapters */ 2426 case ixgbe_media_type_backplane: 2427 ret_val = ixgbe_fc_autoneg_backplane(hw); 2428 break; 2429 2430 /* Autoneg flow control on copper adapters */ 2431 case ixgbe_media_type_copper: 2432 if (ixgbe_device_supports_autoneg_fc(hw)) 2433 ret_val = ixgbe_fc_autoneg_copper(hw); 2434 break; 2435 2436 default: 2437 break; 2438 } 2439 2440out: 2441 if (ret_val == 0) { 2442 hw->fc.fc_was_autonegged = true; 2443 } else { 2444 hw->fc.fc_was_autonegged = false; 2445 hw->fc.current_mode = hw->fc.requested_mode; 2446 } 2447} 2448 2449/** 2450 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2451 * @hw: pointer to hardware structure 2452 * 2453 * System-wide timeout range is encoded in PCIe Device Control2 register. 2454 * 2455 * Add 10% to specified maximum and return the number of times to poll for 2456 * completion timeout, in units of 100 microsec. Never return less than 2457 * 800 = 80 millisec. 2458 **/ 2459static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2460{ 2461 s16 devctl2; 2462 u32 pollcnt; 2463 2464 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2465 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2466 2467 switch (devctl2) { 2468 case IXGBE_PCIDEVCTRL2_65_130ms: 2469 pollcnt = 1300; /* 130 millisec */ 2470 break; 2471 case IXGBE_PCIDEVCTRL2_260_520ms: 2472 pollcnt = 5200; /* 520 millisec */ 2473 break; 2474 case IXGBE_PCIDEVCTRL2_1_2s: 2475 pollcnt = 20000; /* 2 sec */ 2476 break; 2477 case IXGBE_PCIDEVCTRL2_4_8s: 2478 pollcnt = 80000; /* 8 sec */ 2479 break; 2480 case IXGBE_PCIDEVCTRL2_17_34s: 2481 pollcnt = 34000; /* 34 sec */ 2482 break; 2483 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2484 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2485 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2486 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2487 default: 2488 pollcnt = 800; /* 80 millisec minimum */ 2489 break; 2490 } 2491 2492 /* add 10% to spec maximum */ 2493 return (pollcnt * 11) / 10; 2494} 2495 2496/** 2497 * ixgbe_disable_pcie_primary - Disable PCI-express primary access 2498 * @hw: pointer to hardware structure 2499 * 2500 * Disables PCI-Express primary access and verifies there are no pending 2501 * requests. -EALREADY is returned if primary disable 2502 * bit hasn't caused the primary requests to be disabled, else 0 2503 * is returned signifying primary requests disabled. 2504 **/ 2505static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) 2506{ 2507 u32 i, poll; 2508 u16 value; 2509 2510 /* Always set this bit to ensure any future transactions are blocked */ 2511 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2512 2513 /* Poll for bit to read as set */ 2514 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 2515 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2516 break; 2517 usleep_range(100, 120); 2518 } 2519 if (i >= IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT) { 2520 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2521 goto gio_disable_fail; 2522 } 2523 2524 /* Exit if primary requests are blocked */ 2525 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2526 ixgbe_removed(hw->hw_addr)) 2527 return 0; 2528 2529 /* Poll for primary request bit to clear */ 2530 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 2531 udelay(100); 2532 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2533 return 0; 2534 } 2535 2536 /* 2537 * Two consecutive resets are required via CTRL.RST per datasheet 2538 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine 2539 * of this need. The first reset prevents new primary requests from 2540 * being issued by our device. We then must wait 1usec or more for any 2541 * remaining completions from the PCIe bus to trickle in, and then reset 2542 * again to clear out any effects they may have had on our device. 2543 */ 2544 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n"); 2545gio_disable_fail: 2546 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2547 2548 if (hw->mac.type >= ixgbe_mac_X550) 2549 return 0; 2550 2551 /* 2552 * Before proceeding, make sure that the PCIe block does not have 2553 * transactions pending. 2554 */ 2555 poll = ixgbe_pcie_timeout_poll(hw); 2556 for (i = 0; i < poll; i++) { 2557 udelay(100); 2558 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2559 if (ixgbe_removed(hw->hw_addr)) 2560 return 0; 2561 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2562 return 0; 2563 } 2564 2565 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2566 return -EALREADY; 2567} 2568 2569/** 2570 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2571 * @hw: pointer to hardware structure 2572 * @mask: Mask to specify which semaphore to acquire 2573 * 2574 * Acquires the SWFW semaphore through the GSSR register for the specified 2575 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2576 **/ 2577s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2578{ 2579 u32 gssr = 0; 2580 u32 swmask = mask; 2581 u32 fwmask = mask << 5; 2582 u32 timeout = 200; 2583 u32 i; 2584 2585 for (i = 0; i < timeout; i++) { 2586 /* 2587 * SW NVM semaphore bit is used for access to all 2588 * SW_FW_SYNC bits (not just NVM) 2589 */ 2590 if (ixgbe_get_eeprom_semaphore(hw)) 2591 return -EBUSY; 2592 2593 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2594 if (!(gssr & (fwmask | swmask))) { 2595 gssr |= swmask; 2596 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2597 ixgbe_release_eeprom_semaphore(hw); 2598 return 0; 2599 } else { 2600 /* Resource is currently in use by FW or SW */ 2601 ixgbe_release_eeprom_semaphore(hw); 2602 usleep_range(5000, 10000); 2603 } 2604 } 2605 2606 /* If time expired clear the bits holding the lock and retry */ 2607 if (gssr & (fwmask | swmask)) 2608 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2609 2610 usleep_range(5000, 10000); 2611 return -EBUSY; 2612} 2613 2614/** 2615 * ixgbe_release_swfw_sync - Release SWFW semaphore 2616 * @hw: pointer to hardware structure 2617 * @mask: Mask to specify which semaphore to release 2618 * 2619 * Releases the SWFW semaphore through the GSSR register for the specified 2620 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2621 **/ 2622void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2623{ 2624 u32 gssr; 2625 u32 swmask = mask; 2626 2627 ixgbe_get_eeprom_semaphore(hw); 2628 2629 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2630 gssr &= ~swmask; 2631 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2632 2633 ixgbe_release_eeprom_semaphore(hw); 2634} 2635 2636/** 2637 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2638 * @hw: pointer to hardware structure 2639 * @reg_val: Value we read from AUTOC 2640 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2641 * true in this the generic case. 2642 * 2643 * The default case requires no protection so just to the register read. 2644 **/ 2645s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2646{ 2647 *locked = false; 2648 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2649 return 0; 2650} 2651 2652/** 2653 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2654 * @hw: pointer to hardware structure 2655 * @reg_val: value to write to AUTOC 2656 * @locked: bool to indicate whether the SW/FW lock was already taken by 2657 * previous read. 2658 **/ 2659s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2660{ 2661 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2662 return 0; 2663} 2664 2665/** 2666 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2667 * @hw: pointer to hardware structure 2668 * 2669 * Stops the receive data path and waits for the HW to internally 2670 * empty the Rx security block. 2671 **/ 2672s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2673{ 2674#define IXGBE_MAX_SECRX_POLL 40 2675 int i; 2676 int secrxreg; 2677 2678 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2679 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2680 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2681 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2682 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2683 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2684 break; 2685 else 2686 /* Use interrupt-safe sleep just in case */ 2687 udelay(1000); 2688 } 2689 2690 /* For informational purposes only */ 2691 if (i >= IXGBE_MAX_SECRX_POLL) 2692 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2693 2694 return 0; 2695 2696} 2697 2698/** 2699 * ixgbe_enable_rx_buff_generic - Enables the receive data path 2700 * @hw: pointer to hardware structure 2701 * 2702 * Enables the receive data path 2703 **/ 2704s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2705{ 2706 u32 secrxreg; 2707 2708 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2709 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2710 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2711 IXGBE_WRITE_FLUSH(hw); 2712 2713 return 0; 2714} 2715 2716/** 2717 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2718 * @hw: pointer to hardware structure 2719 * @regval: register value to write to RXCTRL 2720 * 2721 * Enables the Rx DMA unit 2722 **/ 2723s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2724{ 2725 if (regval & IXGBE_RXCTRL_RXEN) 2726 hw->mac.ops.enable_rx(hw); 2727 else 2728 hw->mac.ops.disable_rx(hw); 2729 2730 return 0; 2731} 2732 2733/** 2734 * ixgbe_blink_led_start_generic - Blink LED based on index. 2735 * @hw: pointer to hardware structure 2736 * @index: led number to blink 2737 **/ 2738s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2739{ 2740 ixgbe_link_speed speed = 0; 2741 bool link_up = false; 2742 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2743 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2744 bool locked = false; 2745 s32 ret_val; 2746 2747 if (index > 3) 2748 return -EINVAL; 2749 2750 /* 2751 * Link must be up to auto-blink the LEDs; 2752 * Force it if link is down. 2753 */ 2754 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2755 2756 if (!link_up) { 2757 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2758 if (ret_val) 2759 return ret_val; 2760 2761 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2762 autoc_reg |= IXGBE_AUTOC_FLU; 2763 2764 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2765 if (ret_val) 2766 return ret_val; 2767 2768 IXGBE_WRITE_FLUSH(hw); 2769 2770 usleep_range(10000, 20000); 2771 } 2772 2773 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2774 led_reg |= IXGBE_LED_BLINK(index); 2775 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2776 IXGBE_WRITE_FLUSH(hw); 2777 2778 return 0; 2779} 2780 2781/** 2782 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2783 * @hw: pointer to hardware structure 2784 * @index: led number to stop blinking 2785 **/ 2786s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2787{ 2788 u32 autoc_reg = 0; 2789 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2790 bool locked = false; 2791 s32 ret_val; 2792 2793 if (index > 3) 2794 return -EINVAL; 2795 2796 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2797 if (ret_val) 2798 return ret_val; 2799 2800 autoc_reg &= ~IXGBE_AUTOC_FLU; 2801 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2802 2803 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2804 if (ret_val) 2805 return ret_val; 2806 2807 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2808 led_reg &= ~IXGBE_LED_BLINK(index); 2809 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2810 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2811 IXGBE_WRITE_FLUSH(hw); 2812 2813 return 0; 2814} 2815 2816/** 2817 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2818 * @hw: pointer to hardware structure 2819 * @san_mac_offset: SAN MAC address offset 2820 * 2821 * This function will read the EEPROM location for the SAN MAC address 2822 * pointer, and returns the value at that location. This is used in both 2823 * get and set mac_addr routines. 2824 **/ 2825static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2826 u16 *san_mac_offset) 2827{ 2828 s32 ret_val; 2829 2830 /* 2831 * First read the EEPROM pointer to see if the MAC addresses are 2832 * available. 2833 */ 2834 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2835 san_mac_offset); 2836 if (ret_val) 2837 hw_err(hw, "eeprom read at offset %d failed\n", 2838 IXGBE_SAN_MAC_ADDR_PTR); 2839 2840 return ret_val; 2841} 2842 2843/** 2844 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2845 * @hw: pointer to hardware structure 2846 * @san_mac_addr: SAN MAC address 2847 * 2848 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2849 * per-port, so set_lan_id() must be called before reading the addresses. 2850 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2851 * upon for non-SFP connections, so we must call it here. 2852 **/ 2853s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2854{ 2855 u16 san_mac_data, san_mac_offset; 2856 u8 i; 2857 s32 ret_val; 2858 2859 /* 2860 * First read the EEPROM pointer to see if the MAC addresses are 2861 * available. If they're not, no point in calling set_lan_id() here. 2862 */ 2863 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2864 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2865 2866 goto san_mac_addr_clr; 2867 2868 /* make sure we know which port we need to program */ 2869 hw->mac.ops.set_lan_id(hw); 2870 /* apply the port offset to the address offset */ 2871 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2872 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2873 for (i = 0; i < 3; i++) { 2874 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2875 &san_mac_data); 2876 if (ret_val) { 2877 hw_err(hw, "eeprom read at offset %d failed\n", 2878 san_mac_offset); 2879 goto san_mac_addr_clr; 2880 } 2881 san_mac_addr[i * 2] = (u8)(san_mac_data); 2882 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2883 san_mac_offset++; 2884 } 2885 return 0; 2886 2887san_mac_addr_clr: 2888 /* No addresses available in this EEPROM. It's not necessarily an 2889 * error though, so just wipe the local address and return. 2890 */ 2891 for (i = 0; i < 6; i++) 2892 san_mac_addr[i] = 0xFF; 2893 return ret_val; 2894} 2895 2896/** 2897 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2898 * @hw: pointer to hardware structure 2899 * 2900 * Read PCIe configuration space, and get the MSI-X vector count from 2901 * the capabilities table. 2902 **/ 2903u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2904{ 2905 u16 msix_count; 2906 u16 max_msix_count; 2907 u16 pcie_offset; 2908 2909 switch (hw->mac.type) { 2910 case ixgbe_mac_82598EB: 2911 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2912 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2913 break; 2914 case ixgbe_mac_82599EB: 2915 case ixgbe_mac_X540: 2916 case ixgbe_mac_X550: 2917 case ixgbe_mac_X550EM_x: 2918 case ixgbe_mac_x550em_a: 2919 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2920 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2921 break; 2922 default: 2923 return 1; 2924 } 2925 2926 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2927 if (ixgbe_removed(hw->hw_addr)) 2928 msix_count = 0; 2929 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2930 2931 /* MSI-X count is zero-based in HW */ 2932 msix_count++; 2933 2934 if (msix_count > max_msix_count) 2935 msix_count = max_msix_count; 2936 2937 return msix_count; 2938} 2939 2940/** 2941 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2942 * @hw: pointer to hardware struct 2943 * @rar: receive address register index to disassociate 2944 * @vmdq: VMDq pool index to remove from the rar 2945 **/ 2946s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2947{ 2948 u32 mpsar_lo, mpsar_hi; 2949 u32 rar_entries = hw->mac.num_rar_entries; 2950 2951 /* Make sure we are using a valid rar index range */ 2952 if (rar >= rar_entries) { 2953 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2954 return -EINVAL; 2955 } 2956 2957 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2958 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2959 2960 if (ixgbe_removed(hw->hw_addr)) 2961 return 0; 2962 2963 if (!mpsar_lo && !mpsar_hi) 2964 return 0; 2965 2966 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2967 if (mpsar_lo) { 2968 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2969 mpsar_lo = 0; 2970 } 2971 if (mpsar_hi) { 2972 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2973 mpsar_hi = 0; 2974 } 2975 } else if (vmdq < 32) { 2976 mpsar_lo &= ~BIT(vmdq); 2977 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2978 } else { 2979 mpsar_hi &= ~BIT(vmdq - 32); 2980 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2981 } 2982 2983 /* was that the last pool using this rar? */ 2984 if (mpsar_lo == 0 && mpsar_hi == 0 && 2985 rar != 0 && rar != hw->mac.san_mac_rar_index) 2986 hw->mac.ops.clear_rar(hw, rar); 2987 2988 return 0; 2989} 2990 2991/** 2992 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2993 * @hw: pointer to hardware struct 2994 * @rar: receive address register index to associate with a VMDq index 2995 * @vmdq: VMDq pool index 2996 **/ 2997s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2998{ 2999 u32 mpsar; 3000 u32 rar_entries = hw->mac.num_rar_entries; 3001 3002 /* Make sure we are using a valid rar index range */ 3003 if (rar >= rar_entries) { 3004 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3005 return -EINVAL; 3006 } 3007 3008 if (vmdq < 32) { 3009 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3010 mpsar |= BIT(vmdq); 3011 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3012 } else { 3013 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3014 mpsar |= BIT(vmdq - 32); 3015 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3016 } 3017 return 0; 3018} 3019 3020/** 3021 * ixgbe_set_vmdq_san_mac_generic - Associate VMDq pool index with a rx address 3022 * @hw: pointer to hardware struct 3023 * @vmdq: VMDq pool index 3024 * 3025 * This function should only be involved in the IOV mode. 3026 * In IOV mode, Default pool is next pool after the number of 3027 * VFs advertized and not 0. 3028 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3029 **/ 3030s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3031{ 3032 u32 rar = hw->mac.san_mac_rar_index; 3033 3034 if (vmdq < 32) { 3035 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3036 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3037 } else { 3038 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3039 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3040 } 3041 3042 return 0; 3043} 3044 3045/** 3046 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3047 * @hw: pointer to hardware structure 3048 **/ 3049s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3050{ 3051 int i; 3052 3053 for (i = 0; i < 128; i++) 3054 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3055 3056 return 0; 3057} 3058 3059/** 3060 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3061 * @hw: pointer to hardware structure 3062 * @vlan: VLAN id to write to VLAN filter 3063 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3064 * vlanid not found 3065 * 3066 * return the VLVF index where this VLAN id should be placed 3067 * 3068 **/ 3069static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3070{ 3071 s32 regindex, first_empty_slot; 3072 u32 bits; 3073 3074 /* short cut the special case */ 3075 if (vlan == 0) 3076 return 0; 3077 3078 /* if vlvf_bypass is set we don't want to use an empty slot, we 3079 * will simply bypass the VLVF if there are no entries present in the 3080 * VLVF that contain our VLAN 3081 */ 3082 first_empty_slot = vlvf_bypass ? -ENOSPC : 0; 3083 3084 /* add VLAN enable bit for comparison */ 3085 vlan |= IXGBE_VLVF_VIEN; 3086 3087 /* Search for the vlan id in the VLVF entries. Save off the first empty 3088 * slot found along the way. 3089 * 3090 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3091 */ 3092 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3093 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3094 if (bits == vlan) 3095 return regindex; 3096 if (!first_empty_slot && !bits) 3097 first_empty_slot = regindex; 3098 } 3099 3100 /* If we are here then we didn't find the VLAN. Return first empty 3101 * slot we found during our search, else error. 3102 */ 3103 if (!first_empty_slot) 3104 hw_dbg(hw, "No space in VLVF.\n"); 3105 3106 return first_empty_slot ? : -ENOSPC; 3107} 3108 3109/** 3110 * ixgbe_set_vfta_generic - Set VLAN filter table 3111 * @hw: pointer to hardware structure 3112 * @vlan: VLAN id to write to VLAN filter 3113 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3114 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3115 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3116 * 3117 * Turn on/off specified VLAN in the VLAN filter table. 3118 **/ 3119s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3120 bool vlan_on, bool vlvf_bypass) 3121{ 3122 u32 regidx, vfta_delta, vfta, bits; 3123 s32 vlvf_index; 3124 3125 if ((vlan > 4095) || (vind > 63)) 3126 return -EINVAL; 3127 3128 /* 3129 * this is a 2 part operation - first the VFTA, then the 3130 * VLVF and VLVFB if VT Mode is set 3131 * We don't write the VFTA until we know the VLVF part succeeded. 3132 */ 3133 3134 /* Part 1 3135 * The VFTA is a bitstring made up of 128 32-bit registers 3136 * that enable the particular VLAN id, much like the MTA: 3137 * bits[11-5]: which register 3138 * bits[4-0]: which bit in the register 3139 */ 3140 regidx = vlan / 32; 3141 vfta_delta = BIT(vlan % 32); 3142 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3143 3144 /* vfta_delta represents the difference between the current value 3145 * of vfta and the value we want in the register. Since the diff 3146 * is an XOR mask we can just update vfta using an XOR. 3147 */ 3148 vfta_delta &= vlan_on ? ~vfta : vfta; 3149 vfta ^= vfta_delta; 3150 3151 /* Part 2 3152 * If VT Mode is set 3153 * Either vlan_on 3154 * make sure the vlan is in VLVF 3155 * set the vind bit in the matching VLVFB 3156 * Or !vlan_on 3157 * clear the pool bit and possibly the vind 3158 */ 3159 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3160 goto vfta_update; 3161 3162 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3163 if (vlvf_index < 0) { 3164 if (vlvf_bypass) 3165 goto vfta_update; 3166 return vlvf_index; 3167 } 3168 3169 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3170 3171 /* set the pool bit */ 3172 bits |= BIT(vind % 32); 3173 if (vlan_on) 3174 goto vlvf_update; 3175 3176 /* clear the pool bit */ 3177 bits ^= BIT(vind % 32); 3178 3179 if (!bits && 3180 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3181 /* Clear VFTA first, then disable VLVF. Otherwise 3182 * we run the risk of stray packets leaking into 3183 * the PF via the default pool 3184 */ 3185 if (vfta_delta) 3186 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3187 3188 /* disable VLVF and clear remaining bit from pool */ 3189 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3190 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3191 3192 return 0; 3193 } 3194 3195 /* If there are still bits set in the VLVFB registers 3196 * for the VLAN ID indicated we need to see if the 3197 * caller is requesting that we clear the VFTA entry bit. 3198 * If the caller has requested that we clear the VFTA 3199 * entry bit but there are still pools/VFs using this VLAN 3200 * ID entry then ignore the request. We're not worried 3201 * about the case where we're turning the VFTA VLAN ID 3202 * entry bit on, only when requested to turn it off as 3203 * there may be multiple pools and/or VFs using the 3204 * VLAN ID entry. In that case we cannot clear the 3205 * VFTA bit until all pools/VFs using that VLAN ID have also 3206 * been cleared. This will be indicated by "bits" being 3207 * zero. 3208 */ 3209 vfta_delta = 0; 3210 3211vlvf_update: 3212 /* record pool change and enable VLAN ID if not already enabled */ 3213 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3214 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3215 3216vfta_update: 3217 /* Update VFTA now that we are ready for traffic */ 3218 if (vfta_delta) 3219 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3220 3221 return 0; 3222} 3223 3224/** 3225 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3226 * @hw: pointer to hardware structure 3227 * 3228 * Clears the VLAN filter table, and the VMDq index associated with the filter 3229 **/ 3230s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3231{ 3232 u32 offset; 3233 3234 for (offset = 0; offset < hw->mac.vft_size; offset++) 3235 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3236 3237 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3238 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3239 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3240 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3241 } 3242 3243 return 0; 3244} 3245 3246/** 3247 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3248 * @hw: pointer to hardware structure 3249 * 3250 * Contains the logic to identify if we need to verify link for the 3251 * crosstalk fix 3252 **/ 3253static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3254{ 3255 /* Does FW say we need the fix */ 3256 if (!hw->need_crosstalk_fix) 3257 return false; 3258 3259 /* Only consider SFP+ PHYs i.e. media type fiber */ 3260 switch (hw->mac.ops.get_media_type(hw)) { 3261 case ixgbe_media_type_fiber: 3262 case ixgbe_media_type_fiber_qsfp: 3263 break; 3264 default: 3265 return false; 3266 } 3267 3268 return true; 3269} 3270 3271/** 3272 * ixgbe_check_mac_link_generic - Determine link and speed status 3273 * @hw: pointer to hardware structure 3274 * @speed: pointer to link speed 3275 * @link_up: true when link is up 3276 * @link_up_wait_to_complete: bool used to wait for link up or not 3277 * 3278 * Reads the links register to determine if link is up and the current speed 3279 **/ 3280s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3281 bool *link_up, bool link_up_wait_to_complete) 3282{ 3283 bool crosstalk_fix_active = ixgbe_need_crosstalk_fix(hw); 3284 u32 links_reg, links_orig; 3285 u32 i; 3286 3287 /* If Crosstalk fix enabled do the sanity check of making sure 3288 * the SFP+ cage is full. 3289 */ 3290 if (crosstalk_fix_active) { 3291 u32 sfp_cage_full; 3292 3293 switch (hw->mac.type) { 3294 case ixgbe_mac_82599EB: 3295 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3296 IXGBE_ESDP_SDP2; 3297 break; 3298 case ixgbe_mac_X550EM_x: 3299 case ixgbe_mac_x550em_a: 3300 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3301 IXGBE_ESDP_SDP0; 3302 break; 3303 default: 3304 /* sanity check - No SFP+ devices here */ 3305 sfp_cage_full = false; 3306 break; 3307 } 3308 3309 if (!sfp_cage_full) { 3310 *link_up = false; 3311 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3312 return 0; 3313 } 3314 } 3315 3316 /* clear the old state */ 3317 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3318 3319 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3320 3321 if (links_orig != links_reg) { 3322 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3323 links_orig, links_reg); 3324 } 3325 3326 if (link_up_wait_to_complete) { 3327 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3328 if (links_reg & IXGBE_LINKS_UP) { 3329 *link_up = true; 3330 break; 3331 } else { 3332 *link_up = false; 3333 } 3334 msleep(100); 3335 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3336 } 3337 } else { 3338 if (links_reg & IXGBE_LINKS_UP) { 3339 if (crosstalk_fix_active) { 3340 /* Check the link state again after a delay 3341 * to filter out spurious link up 3342 * notifications. 3343 */ 3344 mdelay(5); 3345 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3346 if (!(links_reg & IXGBE_LINKS_UP)) { 3347 *link_up = false; 3348 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3349 return 0; 3350 } 3351 } 3352 *link_up = true; 3353 } else { 3354 *link_up = false; 3355 } 3356 } 3357 3358 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3359 case IXGBE_LINKS_SPEED_10G_82599: 3360 if ((hw->mac.type >= ixgbe_mac_X550) && 3361 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3362 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3363 else 3364 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3365 break; 3366 case IXGBE_LINKS_SPEED_1G_82599: 3367 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3368 break; 3369 case IXGBE_LINKS_SPEED_100_82599: 3370 if ((hw->mac.type >= ixgbe_mac_X550) && 3371 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3372 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3373 else 3374 *speed = IXGBE_LINK_SPEED_100_FULL; 3375 break; 3376 case IXGBE_LINKS_SPEED_10_X550EM_A: 3377 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3378 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3379 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3380 *speed = IXGBE_LINK_SPEED_10_FULL; 3381 } 3382 break; 3383 default: 3384 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3385 } 3386 3387 return 0; 3388} 3389 3390/** 3391 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3392 * the EEPROM 3393 * @hw: pointer to hardware structure 3394 * @wwnn_prefix: the alternative WWNN prefix 3395 * @wwpn_prefix: the alternative WWPN prefix 3396 * 3397 * This function will read the EEPROM from the alternative SAN MAC address 3398 * block to check the support for the alternative WWNN/WWPN prefix support. 3399 **/ 3400s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3401 u16 *wwpn_prefix) 3402{ 3403 u16 offset, caps; 3404 u16 alt_san_mac_blk_offset; 3405 3406 /* clear output first */ 3407 *wwnn_prefix = 0xFFFF; 3408 *wwpn_prefix = 0xFFFF; 3409 3410 /* check if alternative SAN MAC is supported */ 3411 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3412 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3413 goto wwn_prefix_err; 3414 3415 if ((alt_san_mac_blk_offset == 0) || 3416 (alt_san_mac_blk_offset == 0xFFFF)) 3417 return 0; 3418 3419 /* check capability in alternative san mac address block */ 3420 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3421 if (hw->eeprom.ops.read(hw, offset, &caps)) 3422 goto wwn_prefix_err; 3423 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3424 return 0; 3425 3426 /* get the corresponding prefix for WWNN/WWPN */ 3427 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3428 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3429 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3430 3431 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3432 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3433 goto wwn_prefix_err; 3434 3435 return 0; 3436 3437wwn_prefix_err: 3438 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3439 return 0; 3440} 3441 3442/** 3443 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3444 * @hw: pointer to hardware structure 3445 * @enable: enable or disable switch for MAC anti-spoofing 3446 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3447 * 3448 **/ 3449void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3450{ 3451 int vf_target_reg = vf >> 3; 3452 int vf_target_shift = vf % 8; 3453 u32 pfvfspoof; 3454 3455 if (hw->mac.type == ixgbe_mac_82598EB) 3456 return; 3457 3458 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3459 if (enable) 3460 pfvfspoof |= BIT(vf_target_shift); 3461 else 3462 pfvfspoof &= ~BIT(vf_target_shift); 3463 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3464} 3465 3466/** 3467 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3468 * @hw: pointer to hardware structure 3469 * @enable: enable or disable switch for VLAN anti-spoofing 3470 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3471 * 3472 **/ 3473void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3474{ 3475 int vf_target_reg = vf >> 3; 3476 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3477 u32 pfvfspoof; 3478 3479 if (hw->mac.type == ixgbe_mac_82598EB) 3480 return; 3481 3482 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3483 if (enable) 3484 pfvfspoof |= BIT(vf_target_shift); 3485 else 3486 pfvfspoof &= ~BIT(vf_target_shift); 3487 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3488} 3489 3490/** 3491 * ixgbe_get_device_caps_generic - Get additional device capabilities 3492 * @hw: pointer to hardware structure 3493 * @device_caps: the EEPROM word with the extra device capabilities 3494 * 3495 * This function will read the EEPROM location for the device capabilities, 3496 * and return the word through device_caps. 3497 **/ 3498s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3499{ 3500 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3501 3502 return 0; 3503} 3504 3505/** 3506 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3507 * @hw: pointer to hardware structure 3508 * @num_pb: number of packet buffers to allocate 3509 * @headroom: reserve n KB of headroom 3510 * @strategy: packet buffer allocation strategy 3511 **/ 3512void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3513 int num_pb, 3514 u32 headroom, 3515 int strategy) 3516{ 3517 u32 pbsize = hw->mac.rx_pb_size; 3518 int i = 0; 3519 u32 rxpktsize, txpktsize, txpbthresh; 3520 3521 /* Reserve headroom */ 3522 pbsize -= headroom; 3523 3524 if (!num_pb) 3525 num_pb = 1; 3526 3527 /* Divide remaining packet buffer space amongst the number 3528 * of packet buffers requested using supplied strategy. 3529 */ 3530 switch (strategy) { 3531 case (PBA_STRATEGY_WEIGHTED): 3532 /* pba_80_48 strategy weight first half of packet buffer with 3533 * 5/8 of the packet buffer space. 3534 */ 3535 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3536 pbsize -= rxpktsize * (num_pb / 2); 3537 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3538 for (; i < (num_pb / 2); i++) 3539 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3540 fallthrough; /* configure remaining packet buffers */ 3541 case (PBA_STRATEGY_EQUAL): 3542 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3543 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3544 for (; i < num_pb; i++) 3545 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3546 break; 3547 default: 3548 break; 3549 } 3550 3551 /* 3552 * Setup Tx packet buffer and threshold equally for all TCs 3553 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3554 * 10 since the largest packet we support is just over 9K. 3555 */ 3556 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3557 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3558 for (i = 0; i < num_pb; i++) { 3559 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3560 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3561 } 3562 3563 /* Clear unused TCs, if any, to zero buffer size*/ 3564 for (; i < IXGBE_MAX_PB; i++) { 3565 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3566 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3567 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3568 } 3569} 3570 3571/** 3572 * ixgbe_calculate_checksum - Calculate checksum for buffer 3573 * @buffer: pointer to EEPROM 3574 * @length: size of EEPROM to calculate a checksum for 3575 * 3576 * Calculates the checksum for some buffer on a specified length. The 3577 * checksum calculated is returned. 3578 **/ 3579u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3580{ 3581 u32 i; 3582 u8 sum = 0; 3583 3584 if (!buffer) 3585 return 0; 3586 3587 for (i = 0; i < length; i++) 3588 sum += buffer[i]; 3589 3590 return (u8) (0 - sum); 3591} 3592 3593/** 3594 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3595 * @hw: pointer to the HW structure 3596 * @buffer: command to write and where the return status will be placed 3597 * @length: length of buffer, must be multiple of 4 bytes 3598 * @timeout: time in ms to wait for command completion 3599 * 3600 * Communicates with the manageability block. On success return 0 3601 * else returns semaphore error when encountering an error acquiring 3602 * semaphore, -EINVAL when incorrect parameters passed or -EIO when 3603 * command fails. 3604 * 3605 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3606 * by the caller. 3607 **/ 3608s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3609 u32 timeout) 3610{ 3611 u32 hicr, i, fwsts; 3612 u16 dword_len; 3613 3614 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3615 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3616 return -EINVAL; 3617 } 3618 3619 /* Set bit 9 of FWSTS clearing FW reset indication */ 3620 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3621 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3622 3623 /* Check that the host interface is enabled. */ 3624 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3625 if (!(hicr & IXGBE_HICR_EN)) { 3626 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3627 return -EIO; 3628 } 3629 3630 /* Calculate length in DWORDs. We must be DWORD aligned */ 3631 if (length % sizeof(u32)) { 3632 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3633 return -EINVAL; 3634 } 3635 3636 dword_len = length >> 2; 3637 3638 /* The device driver writes the relevant command block 3639 * into the ram area. 3640 */ 3641 for (i = 0; i < dword_len; i++) 3642 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3643 i, (__force u32)cpu_to_le32(buffer[i])); 3644 3645 /* Setting this bit tells the ARC that a new command is pending. */ 3646 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3647 3648 for (i = 0; i < timeout; i++) { 3649 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3650 if (!(hicr & IXGBE_HICR_C)) 3651 break; 3652 usleep_range(1000, 2000); 3653 } 3654 3655 /* Check command successful completion. */ 3656 if ((timeout && i == timeout) || 3657 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3658 return -EIO; 3659 3660 return 0; 3661} 3662 3663/** 3664 * ixgbe_host_interface_command - Issue command to manageability block 3665 * @hw: pointer to the HW structure 3666 * @buffer: contains the command to write and where the return status will 3667 * be placed 3668 * @length: length of buffer, must be multiple of 4 bytes 3669 * @timeout: time in ms to wait for command completion 3670 * @return_data: read and return data from the buffer (true) or not (false) 3671 * Needed because FW structures are big endian and decoding of 3672 * these fields can be 8 bit or 16 bit based on command. Decoding 3673 * is not easily understood without making a table of commands. 3674 * So we will leave this up to the caller to read back the data 3675 * in these cases. 3676 * 3677 * Communicates with the manageability block. On success return 0 3678 * else return -EIO or -EINVAL. 3679 **/ 3680s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3681 u32 length, u32 timeout, 3682 bool return_data) 3683{ 3684 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3685 struct ixgbe_hic_hdr *hdr = buffer; 3686 u32 *u32arr = buffer; 3687 u16 buf_len, dword_len; 3688 s32 status; 3689 u32 bi; 3690 3691 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3692 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3693 return -EINVAL; 3694 } 3695 /* Take management host interface semaphore */ 3696 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3697 if (status) 3698 return status; 3699 3700 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3701 if (status) 3702 goto rel_out; 3703 3704 if (!return_data) 3705 goto rel_out; 3706 3707 /* Calculate length in DWORDs */ 3708 dword_len = hdr_size >> 2; 3709 3710 /* first pull in the header so we know the buffer length */ 3711 for (bi = 0; bi < dword_len; bi++) { 3712 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3713 le32_to_cpus(&u32arr[bi]); 3714 } 3715 3716 /* If there is any thing in data position pull it in */ 3717 buf_len = hdr->buf_len; 3718 if (!buf_len) 3719 goto rel_out; 3720 3721 if (length < round_up(buf_len, 4) + hdr_size) { 3722 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3723 status = -EIO; 3724 goto rel_out; 3725 } 3726 3727 /* Calculate length in DWORDs, add 3 for odd lengths */ 3728 dword_len = (buf_len + 3) >> 2; 3729 3730 /* Pull in the rest of the buffer (bi is where we left off) */ 3731 for (; bi <= dword_len; bi++) { 3732 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3733 le32_to_cpus(&u32arr[bi]); 3734 } 3735 3736rel_out: 3737 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3738 3739 return status; 3740} 3741 3742/** 3743 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3744 * @hw: pointer to the HW structure 3745 * @maj: driver version major number 3746 * @min: driver version minor number 3747 * @build: driver version build number 3748 * @sub: driver version sub build number 3749 * @len: length of driver_ver string 3750 * @driver_ver: driver string 3751 * 3752 * Sends driver version number to firmware through the manageability 3753 * block. On success return 0 3754 * else returns -EBUSY when encountering an error acquiring 3755 * semaphore or -EIO when command fails. 3756 **/ 3757s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3758 u8 build, u8 sub, __always_unused u16 len, 3759 __always_unused const char *driver_ver) 3760{ 3761 struct ixgbe_hic_drv_info fw_cmd; 3762 int i; 3763 s32 ret_val; 3764 3765 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3766 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3767 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3768 fw_cmd.port_num = hw->bus.func; 3769 fw_cmd.ver_maj = maj; 3770 fw_cmd.ver_min = min; 3771 fw_cmd.ver_build = build; 3772 fw_cmd.ver_sub = sub; 3773 fw_cmd.hdr.checksum = 0; 3774 fw_cmd.pad = 0; 3775 fw_cmd.pad2 = 0; 3776 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3777 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3778 3779 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3780 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3781 sizeof(fw_cmd), 3782 IXGBE_HI_COMMAND_TIMEOUT, 3783 true); 3784 if (ret_val != 0) 3785 continue; 3786 3787 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3788 FW_CEM_RESP_STATUS_SUCCESS) 3789 ret_val = 0; 3790 else 3791 ret_val = -EIO; 3792 3793 break; 3794 } 3795 3796 return ret_val; 3797} 3798 3799/** 3800 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3801 * @hw: pointer to the hardware structure 3802 * 3803 * The 82599 and x540 MACs can experience issues if TX work is still pending 3804 * when a reset occurs. This function prevents this by flushing the PCIe 3805 * buffers on the system. 3806 **/ 3807void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3808{ 3809 u32 gcr_ext, hlreg0, i, poll; 3810 u16 value; 3811 3812 /* 3813 * If double reset is not requested then all transactions should 3814 * already be clear and as such there is no work to do 3815 */ 3816 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3817 return; 3818 3819 /* 3820 * Set loopback enable to prevent any transmits from being sent 3821 * should the link come up. This assumes that the RXCTRL.RXEN bit 3822 * has already been cleared. 3823 */ 3824 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3825 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3826 3827 /* wait for a last completion before clearing buffers */ 3828 IXGBE_WRITE_FLUSH(hw); 3829 usleep_range(3000, 6000); 3830 3831 /* Before proceeding, make sure that the PCIe block does not have 3832 * transactions pending. 3833 */ 3834 poll = ixgbe_pcie_timeout_poll(hw); 3835 for (i = 0; i < poll; i++) { 3836 usleep_range(100, 200); 3837 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3838 if (ixgbe_removed(hw->hw_addr)) 3839 break; 3840 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3841 break; 3842 } 3843 3844 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3845 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3846 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3847 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3848 3849 /* Flush all writes and allow 20usec for all transactions to clear */ 3850 IXGBE_WRITE_FLUSH(hw); 3851 udelay(20); 3852 3853 /* restore previous register values */ 3854 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3855 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3856} 3857 3858static const u8 ixgbe_emc_temp_data[4] = { 3859 IXGBE_EMC_INTERNAL_DATA, 3860 IXGBE_EMC_DIODE1_DATA, 3861 IXGBE_EMC_DIODE2_DATA, 3862 IXGBE_EMC_DIODE3_DATA 3863}; 3864static const u8 ixgbe_emc_therm_limit[4] = { 3865 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3866 IXGBE_EMC_DIODE1_THERM_LIMIT, 3867 IXGBE_EMC_DIODE2_THERM_LIMIT, 3868 IXGBE_EMC_DIODE3_THERM_LIMIT 3869}; 3870 3871/** 3872 * ixgbe_get_ets_data - Extracts the ETS bit data 3873 * @hw: pointer to hardware structure 3874 * @ets_cfg: extected ETS data 3875 * @ets_offset: offset of ETS data 3876 * 3877 * Returns error code. 3878 **/ 3879static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3880 u16 *ets_offset) 3881{ 3882 s32 status; 3883 3884 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3885 if (status) 3886 return status; 3887 3888 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3889 return -EOPNOTSUPP; 3890 3891 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3892 if (status) 3893 return status; 3894 3895 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3896 return -EOPNOTSUPP; 3897 3898 return 0; 3899} 3900 3901/** 3902 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data 3903 * @hw: pointer to hardware structure 3904 * 3905 * Returns the thermal sensor data structure 3906 **/ 3907s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3908{ 3909 s32 status; 3910 u16 ets_offset; 3911 u16 ets_cfg; 3912 u16 ets_sensor; 3913 u8 num_sensors; 3914 u8 i; 3915 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3916 3917 /* Only support thermal sensors attached to physical port 0 */ 3918 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3919 return -EOPNOTSUPP; 3920 3921 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3922 if (status) 3923 return status; 3924 3925 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3926 if (num_sensors > IXGBE_MAX_SENSORS) 3927 num_sensors = IXGBE_MAX_SENSORS; 3928 3929 for (i = 0; i < num_sensors; i++) { 3930 u8 sensor_index; 3931 u8 sensor_location; 3932 3933 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3934 &ets_sensor); 3935 if (status) 3936 return status; 3937 3938 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3939 IXGBE_ETS_DATA_INDEX_SHIFT); 3940 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3941 IXGBE_ETS_DATA_LOC_SHIFT); 3942 3943 if (sensor_location != 0) { 3944 status = hw->phy.ops.read_i2c_byte(hw, 3945 ixgbe_emc_temp_data[sensor_index], 3946 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3947 &data->sensor[i].temp); 3948 if (status) 3949 return status; 3950 } 3951 } 3952 3953 return 0; 3954} 3955 3956/** 3957 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3958 * @hw: pointer to hardware structure 3959 * 3960 * Inits the thermal sensor thresholds according to the NVM map 3961 * and save off the threshold and location values into mac.thermal_sensor_data 3962 **/ 3963s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3964{ 3965 s32 status; 3966 u16 ets_offset; 3967 u16 ets_cfg; 3968 u16 ets_sensor; 3969 u8 low_thresh_delta; 3970 u8 num_sensors; 3971 u8 therm_limit; 3972 u8 i; 3973 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3974 3975 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3976 3977 /* Only support thermal sensors attached to physical port 0 */ 3978 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3979 return -EOPNOTSUPP; 3980 3981 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3982 if (status) 3983 return status; 3984 3985 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3986 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3987 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3988 if (num_sensors > IXGBE_MAX_SENSORS) 3989 num_sensors = IXGBE_MAX_SENSORS; 3990 3991 for (i = 0; i < num_sensors; i++) { 3992 u8 sensor_index; 3993 u8 sensor_location; 3994 3995 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 3996 hw_err(hw, "eeprom read at offset %d failed\n", 3997 ets_offset + 1 + i); 3998 continue; 3999 } 4000 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4001 IXGBE_ETS_DATA_INDEX_SHIFT); 4002 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4003 IXGBE_ETS_DATA_LOC_SHIFT); 4004 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4005 4006 hw->phy.ops.write_i2c_byte(hw, 4007 ixgbe_emc_therm_limit[sensor_index], 4008 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4009 4010 if (sensor_location == 0) 4011 continue; 4012 4013 data->sensor[i].location = sensor_location; 4014 data->sensor[i].caution_thresh = therm_limit; 4015 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4016 } 4017 4018 return 0; 4019} 4020 4021/** 4022 * ixgbe_get_orom_version - Return option ROM from EEPROM 4023 * 4024 * @hw: pointer to hardware structure 4025 * @nvm_ver: pointer to output structure 4026 * 4027 * if valid option ROM version, nvm_ver->or_valid set to true 4028 * else nvm_ver->or_valid is false. 4029 **/ 4030void ixgbe_get_orom_version(struct ixgbe_hw *hw, 4031 struct ixgbe_nvm_version *nvm_ver) 4032{ 4033 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 4034 4035 nvm_ver->or_valid = false; 4036 /* Option Rom may or may not be present. Start with pointer */ 4037 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 4038 4039 /* make sure offset is valid */ 4040 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4041 return; 4042 4043 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 4044 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 4045 4046 /* option rom exists and is valid */ 4047 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 4048 eeprom_cfg_blkl == NVM_VER_INVALID || 4049 eeprom_cfg_blkh == NVM_VER_INVALID) 4050 return; 4051 4052 nvm_ver->or_valid = true; 4053 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 4054 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 4055 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 4056 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 4057} 4058 4059/** 4060 * ixgbe_get_oem_prod_version - Etrack ID from EEPROM 4061 * @hw: pointer to hardware structure 4062 * @nvm_ver: pointer to output structure 4063 * 4064 * if valid OEM product version, nvm_ver->oem_valid set to true 4065 * else nvm_ver->oem_valid is false. 4066 **/ 4067void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 4068 struct ixgbe_nvm_version *nvm_ver) 4069{ 4070 u16 rel_num, prod_ver, mod_len, cap, offset; 4071 4072 nvm_ver->oem_valid = false; 4073 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 4074 4075 /* Return is offset to OEM Product Version block is invalid */ 4076 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4077 return; 4078 4079 /* Read product version block */ 4080 hw->eeprom.ops.read(hw, offset, &mod_len); 4081 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 4082 4083 /* Return if OEM product version block is invalid */ 4084 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 4085 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 4086 return; 4087 4088 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 4089 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 4090 4091 /* Return if version is invalid */ 4092 if ((rel_num | prod_ver) == 0x0 || 4093 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 4094 return; 4095 4096 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 4097 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 4098 nvm_ver->oem_release = rel_num; 4099 nvm_ver->oem_valid = true; 4100} 4101 4102/** 4103 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 4104 * 4105 * @hw: pointer to hardware structure 4106 * @nvm_ver: pointer to output structure 4107 * 4108 * word read errors will return 0xFFFF 4109 **/ 4110void ixgbe_get_etk_id(struct ixgbe_hw *hw, 4111 struct ixgbe_nvm_version *nvm_ver) 4112{ 4113 u16 etk_id_l, etk_id_h; 4114 4115 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 4116 etk_id_l = NVM_VER_INVALID; 4117 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 4118 etk_id_h = NVM_VER_INVALID; 4119 4120 /* The word order for the version format is determined by high order 4121 * word bit 15. 4122 */ 4123 if ((etk_id_h & NVM_ETK_VALID) == 0) { 4124 nvm_ver->etk_id = etk_id_h; 4125 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 4126 } else { 4127 nvm_ver->etk_id = etk_id_l; 4128 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 4129 } 4130} 4131 4132void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4133{ 4134 u32 rxctrl; 4135 4136 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4137 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4138 if (hw->mac.type != ixgbe_mac_82598EB) { 4139 u32 pfdtxgswc; 4140 4141 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4142 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4143 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4144 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4145 hw->mac.set_lben = true; 4146 } else { 4147 hw->mac.set_lben = false; 4148 } 4149 } 4150 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4151 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4152 } 4153} 4154 4155void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4156{ 4157 u32 rxctrl; 4158 4159 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4160 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4161 4162 if (hw->mac.type != ixgbe_mac_82598EB) { 4163 if (hw->mac.set_lben) { 4164 u32 pfdtxgswc; 4165 4166 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4167 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4168 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4169 hw->mac.set_lben = false; 4170 } 4171 } 4172} 4173 4174/** ixgbe_mng_present - returns true when management capability is present 4175 * @hw: pointer to hardware structure 4176 **/ 4177bool ixgbe_mng_present(struct ixgbe_hw *hw) 4178{ 4179 u32 fwsm; 4180 4181 if (hw->mac.type < ixgbe_mac_82599EB) 4182 return false; 4183 4184 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4185 4186 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 4187} 4188 4189/** 4190 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4191 * @hw: pointer to hardware structure 4192 * @speed: new link speed 4193 * @autoneg_wait_to_complete: true when waiting for completion is needed 4194 * 4195 * Set the link speed in the MAC and/or PHY register and restarts link. 4196 */ 4197s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4198 ixgbe_link_speed speed, 4199 bool autoneg_wait_to_complete) 4200{ 4201 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4202 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4203 s32 status = 0; 4204 u32 speedcnt = 0; 4205 u32 i = 0; 4206 bool autoneg, link_up = false; 4207 4208 /* Mask off requested but non-supported speeds */ 4209 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4210 if (status) 4211 return status; 4212 4213 speed &= link_speed; 4214 4215 /* Try each speed one by one, highest priority first. We do this in 4216 * software because 10Gb fiber doesn't support speed autonegotiation. 4217 */ 4218 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4219 speedcnt++; 4220 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4221 4222 /* Set the module link speed */ 4223 switch (hw->phy.media_type) { 4224 case ixgbe_media_type_fiber: 4225 hw->mac.ops.set_rate_select_speed(hw, 4226 IXGBE_LINK_SPEED_10GB_FULL); 4227 break; 4228 case ixgbe_media_type_fiber_qsfp: 4229 /* QSFP module automatically detects MAC link speed */ 4230 break; 4231 default: 4232 hw_dbg(hw, "Unexpected media type\n"); 4233 break; 4234 } 4235 4236 /* Allow module to change analog characteristics (1G->10G) */ 4237 msleep(40); 4238 4239 status = hw->mac.ops.setup_mac_link(hw, 4240 IXGBE_LINK_SPEED_10GB_FULL, 4241 autoneg_wait_to_complete); 4242 if (status) 4243 return status; 4244 4245 /* Flap the Tx laser if it has not already been done */ 4246 if (hw->mac.ops.flap_tx_laser) 4247 hw->mac.ops.flap_tx_laser(hw); 4248 4249 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4250 * Section 73.10.2, we may have to wait up to 500ms if KR is 4251 * attempted. 82599 uses the same timing for 10g SFI. 4252 */ 4253 for (i = 0; i < 5; i++) { 4254 /* Wait for the link partner to also set speed */ 4255 msleep(100); 4256 4257 /* If we have link, just jump out */ 4258 status = hw->mac.ops.check_link(hw, &link_speed, 4259 &link_up, false); 4260 if (status) 4261 return status; 4262 4263 if (link_up) 4264 goto out; 4265 } 4266 } 4267 4268 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4269 speedcnt++; 4270 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4271 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4272 4273 /* Set the module link speed */ 4274 switch (hw->phy.media_type) { 4275 case ixgbe_media_type_fiber: 4276 hw->mac.ops.set_rate_select_speed(hw, 4277 IXGBE_LINK_SPEED_1GB_FULL); 4278 break; 4279 case ixgbe_media_type_fiber_qsfp: 4280 /* QSFP module automatically detects link speed */ 4281 break; 4282 default: 4283 hw_dbg(hw, "Unexpected media type\n"); 4284 break; 4285 } 4286 4287 /* Allow module to change analog characteristics (10G->1G) */ 4288 msleep(40); 4289 4290 status = hw->mac.ops.setup_mac_link(hw, 4291 IXGBE_LINK_SPEED_1GB_FULL, 4292 autoneg_wait_to_complete); 4293 if (status) 4294 return status; 4295 4296 /* Flap the Tx laser if it has not already been done */ 4297 if (hw->mac.ops.flap_tx_laser) 4298 hw->mac.ops.flap_tx_laser(hw); 4299 4300 /* Wait for the link partner to also set speed */ 4301 msleep(100); 4302 4303 /* If we have link, just jump out */ 4304 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4305 false); 4306 if (status) 4307 return status; 4308 4309 if (link_up) 4310 goto out; 4311 } 4312 4313 /* We didn't get link. Configure back to the highest speed we tried, 4314 * (if there was more than one). We call ourselves back with just the 4315 * single highest speed that the user requested. 4316 */ 4317 if (speedcnt > 1) 4318 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4319 highest_link_speed, 4320 autoneg_wait_to_complete); 4321 4322out: 4323 /* Set autoneg_advertised value based on input link speed */ 4324 hw->phy.autoneg_advertised = 0; 4325 4326 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4327 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4328 4329 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4330 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4331 4332 return status; 4333} 4334 4335/** 4336 * ixgbe_set_soft_rate_select_speed - Set module link speed 4337 * @hw: pointer to hardware structure 4338 * @speed: link speed to set 4339 * 4340 * Set module link speed via the soft rate select. 4341 */ 4342void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4343 ixgbe_link_speed speed) 4344{ 4345 s32 status; 4346 u8 rs, eeprom_data; 4347 4348 switch (speed) { 4349 case IXGBE_LINK_SPEED_10GB_FULL: 4350 /* one bit mask same as setting on */ 4351 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4352 break; 4353 case IXGBE_LINK_SPEED_1GB_FULL: 4354 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4355 break; 4356 default: 4357 hw_dbg(hw, "Invalid fixed module speed\n"); 4358 return; 4359 } 4360 4361 /* Set RS0 */ 4362 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4363 IXGBE_I2C_EEPROM_DEV_ADDR2, 4364 &eeprom_data); 4365 if (status) { 4366 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4367 return; 4368 } 4369 4370 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4371 4372 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4373 IXGBE_I2C_EEPROM_DEV_ADDR2, 4374 eeprom_data); 4375 if (status) { 4376 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4377 return; 4378 } 4379 4380 /* Set RS1 */ 4381 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4382 IXGBE_I2C_EEPROM_DEV_ADDR2, 4383 &eeprom_data); 4384 if (status) { 4385 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); 4386 return; 4387 } 4388 4389 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4390 4391 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4392 IXGBE_I2C_EEPROM_DEV_ADDR2, 4393 eeprom_data); 4394 if (status) { 4395 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); 4396 return; 4397 } 4398} 4399