162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* Copyright (c) 2020 Intel Corporation */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_cibool igc_reg_test(struct igc_adapter *adapter, u64 *data); 562306a36Sopenharmony_cibool igc_eeprom_test(struct igc_adapter *adapter, u64 *data); 662306a36Sopenharmony_cibool igc_link_test(struct igc_adapter *adapter, u64 *data); 762306a36Sopenharmony_ci 862306a36Sopenharmony_cistruct igc_reg_test { 962306a36Sopenharmony_ci u16 reg; 1062306a36Sopenharmony_ci u8 array_len; 1162306a36Sopenharmony_ci u8 test_type; 1262306a36Sopenharmony_ci u32 mask; 1362306a36Sopenharmony_ci u32 write; 1462306a36Sopenharmony_ci}; 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* In the hardware, registers are laid out either singly, in arrays 1762306a36Sopenharmony_ci * spaced 0x40 bytes apart, or in contiguous tables. We assume 1862306a36Sopenharmony_ci * most tests take place on arrays or single registers (handled 1962306a36Sopenharmony_ci * as a single-element array) and special-case the tables. 2062306a36Sopenharmony_ci * Table tests are always pattern tests. 2162306a36Sopenharmony_ci * 2262306a36Sopenharmony_ci * We also make provision for some required setup steps by specifying 2362306a36Sopenharmony_ci * registers to be written without any read-back testing. 2462306a36Sopenharmony_ci */ 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci#define PATTERN_TEST 1 2762306a36Sopenharmony_ci#define SET_READ_TEST 2 2862306a36Sopenharmony_ci#define TABLE32_TEST 3 2962306a36Sopenharmony_ci#define TABLE64_TEST_LO 4 3062306a36Sopenharmony_ci#define TABLE64_TEST_HI 5 31