1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018 Intel Corporation */ 3 4#ifndef _IGC_H_ 5#define _IGC_H_ 6 7#include <linux/kobject.h> 8#include <linux/pci.h> 9#include <linux/netdevice.h> 10#include <linux/vmalloc.h> 11#include <linux/ethtool.h> 12#include <linux/sctp.h> 13#include <linux/ptp_clock_kernel.h> 14#include <linux/timecounter.h> 15#include <linux/net_tstamp.h> 16#include <linux/bitfield.h> 17#include <linux/hrtimer.h> 18#include <net/xdp.h> 19 20#include "igc_hw.h" 21 22void igc_ethtool_set_ops(struct net_device *); 23 24/* Transmit and receive queues */ 25#define IGC_MAX_RX_QUEUES 4 26#define IGC_MAX_TX_QUEUES 4 27 28#define MAX_Q_VECTORS 8 29#define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31#define MAX_ETYPE_FILTER 8 32#define IGC_RETA_SIZE 128 33 34/* SDP support */ 35#define IGC_N_EXTTS 2 36#define IGC_N_PEROUT 2 37#define IGC_N_SDP 4 38 39#define MAX_FLEX_FILTER 32 40 41#define IGC_MAX_TX_TSTAMP_REGS 4 42 43enum igc_mac_filter_type { 44 IGC_MAC_FILTER_TYPE_DST = 0, 45 IGC_MAC_FILTER_TYPE_SRC 46}; 47 48struct igc_tx_queue_stats { 49 u64 packets; 50 u64 bytes; 51 u64 restart_queue; 52 u64 restart_queue2; 53}; 54 55struct igc_rx_queue_stats { 56 u64 packets; 57 u64 bytes; 58 u64 drops; 59 u64 csum_err; 60 u64 alloc_failed; 61}; 62 63struct igc_rx_packet_stats { 64 u64 ipv4_packets; /* IPv4 headers processed */ 65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 66 u64 ipv6_packets; /* IPv6 headers processed */ 67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 68 u64 tcp_packets; /* TCP headers processed */ 69 u64 udp_packets; /* UDP headers processed */ 70 u64 sctp_packets; /* SCTP headers processed */ 71 u64 nfs_packets; /* NFS headers processe */ 72 u64 other_packets; 73}; 74 75struct igc_tx_timestamp_request { 76 struct sk_buff *skb; /* reference to the packet being timestamped */ 77 unsigned long start; /* when the tstamp request started (jiffies) */ 78 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */ 79 u32 regl; /* which TXSTMPL_{X} register should be used */ 80 u32 regh; /* which TXSTMPH_{X} register should be used */ 81 u32 flags; /* flags that should be added to the tx_buffer */ 82}; 83 84struct igc_ring_container { 85 struct igc_ring *ring; /* pointer to linked list of rings */ 86 unsigned int total_bytes; /* total bytes processed this int */ 87 unsigned int total_packets; /* total packets processed this int */ 88 u16 work_limit; /* total work allowed per interrupt */ 89 u8 count; /* total number of rings in vector */ 90 u8 itr; /* current ITR setting for ring */ 91}; 92 93struct igc_ring { 94 struct igc_q_vector *q_vector; /* backlink to q_vector */ 95 struct net_device *netdev; /* back pointer to net_device */ 96 struct device *dev; /* device for dma mapping */ 97 union { /* array of buffer info structs */ 98 struct igc_tx_buffer *tx_buffer_info; 99 struct igc_rx_buffer *rx_buffer_info; 100 }; 101 void *desc; /* descriptor ring memory */ 102 unsigned long flags; /* ring specific flags */ 103 void __iomem *tail; /* pointer to ring tail register */ 104 dma_addr_t dma; /* phys address of the ring */ 105 unsigned int size; /* length of desc. ring in bytes */ 106 107 u16 count; /* number of desc. in the ring */ 108 u8 queue_index; /* logical index of the ring*/ 109 u8 reg_idx; /* physical index of the ring */ 110 bool launchtime_enable; /* true if LaunchTime is enabled */ 111 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 112 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 113 114 u32 start_time; 115 u32 end_time; 116 u32 max_sdu; 117 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 118 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 119 120 /* CBS parameters */ 121 bool cbs_enable; /* indicates if CBS is enabled */ 122 s32 idleslope; /* idleSlope in kbps */ 123 s32 sendslope; /* sendSlope in kbps */ 124 s32 hicredit; /* hiCredit in bytes */ 125 s32 locredit; /* loCredit in bytes */ 126 127 /* everything past this point are written often */ 128 u16 next_to_clean; 129 u16 next_to_use; 130 u16 next_to_alloc; 131 132 union { 133 /* TX */ 134 struct { 135 struct igc_tx_queue_stats tx_stats; 136 struct u64_stats_sync tx_syncp; 137 struct u64_stats_sync tx_syncp2; 138 }; 139 /* RX */ 140 struct { 141 struct igc_rx_queue_stats rx_stats; 142 struct igc_rx_packet_stats pkt_stats; 143 struct u64_stats_sync rx_syncp; 144 struct sk_buff *skb; 145 }; 146 }; 147 148 struct xdp_rxq_info xdp_rxq; 149 struct xsk_buff_pool *xsk_pool; 150} ____cacheline_internodealigned_in_smp; 151 152/* Board specific private data structure */ 153struct igc_adapter { 154 struct net_device *netdev; 155 156 struct ethtool_eee eee; 157 u16 eee_advert; 158 159 unsigned long state; 160 unsigned int flags; 161 unsigned int num_q_vectors; 162 163 struct msix_entry *msix_entries; 164 165 /* TX */ 166 u16 tx_work_limit; 167 u32 tx_timeout_count; 168 int num_tx_queues; 169 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 170 171 /* RX */ 172 int num_rx_queues; 173 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 174 175 struct timer_list watchdog_timer; 176 struct timer_list dma_err_timer; 177 struct timer_list phy_info_timer; 178 struct hrtimer hrtimer; 179 180 u32 wol; 181 u32 en_mng_pt; 182 u16 link_speed; 183 u16 link_duplex; 184 185 u8 port_num; 186 187 u8 __iomem *io_addr; 188 /* Interrupt Throttle Rate */ 189 u32 rx_itr_setting; 190 u32 tx_itr_setting; 191 192 struct work_struct reset_task; 193 struct work_struct watchdog_task; 194 struct work_struct dma_err_task; 195 bool fc_autoneg; 196 197 u8 tx_timeout_factor; 198 199 int msg_enable; 200 u32 max_frame_size; 201 u32 min_frame_size; 202 203 int tc_setup_type; 204 ktime_t base_time; 205 ktime_t cycle_time; 206 bool taprio_offload_enable; 207 u32 qbv_config_change_errors; 208 bool qbv_transition; 209 unsigned int qbv_count; 210 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 211 * are protected by the qbv_tx_lock. 212 */ 213 spinlock_t qbv_tx_lock; 214 215 /* OS defined structs */ 216 struct pci_dev *pdev; 217 /* lock for statistics */ 218 spinlock_t stats64_lock; 219 struct rtnl_link_stats64 stats64; 220 221 /* structs defined in igc_hw.h */ 222 struct igc_hw hw; 223 struct igc_hw_stats stats; 224 225 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 226 u32 eims_enable_mask; 227 u32 eims_other; 228 229 u16 tx_ring_count; 230 u16 rx_ring_count; 231 232 u32 tx_hwtstamp_timeouts; 233 u32 tx_hwtstamp_skipped; 234 u32 rx_hwtstamp_cleared; 235 236 u32 rss_queues; 237 u32 rss_indir_tbl_init; 238 239 /* Any access to elements in nfc_rule_list is protected by the 240 * nfc_rule_lock. 241 */ 242 struct mutex nfc_rule_lock; 243 struct list_head nfc_rule_list; 244 unsigned int nfc_rule_count; 245 246 u8 rss_indir_tbl[IGC_RETA_SIZE]; 247 248 unsigned long link_check_timeout; 249 struct igc_info ei; 250 251 u32 test_icr; 252 253 struct ptp_clock *ptp_clock; 254 struct ptp_clock_info ptp_caps; 255 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 256 * ptp_tx_lock. 257 */ 258 spinlock_t ptp_tx_lock; 259 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS]; 260 struct hwtstamp_config tstamp_config; 261 unsigned int ptp_flags; 262 /* System time value lock */ 263 spinlock_t tmreg_lock; 264 struct cyclecounter cc; 265 struct timecounter tc; 266 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 267 ktime_t ptp_reset_start; /* Reset time in clock mono */ 268 struct system_time_snapshot snapshot; 269 270 char fw_version[32]; 271 272 struct bpf_prog *xdp_prog; 273 274 bool pps_sys_wrap_on; 275 276 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 277 struct { 278 struct timespec64 start; 279 struct timespec64 period; 280 } perout[IGC_N_PEROUT]; 281}; 282 283void igc_up(struct igc_adapter *adapter); 284void igc_down(struct igc_adapter *adapter); 285int igc_open(struct net_device *netdev); 286int igc_close(struct net_device *netdev); 287int igc_setup_tx_resources(struct igc_ring *ring); 288int igc_setup_rx_resources(struct igc_ring *ring); 289void igc_free_tx_resources(struct igc_ring *ring); 290void igc_free_rx_resources(struct igc_ring *ring); 291unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 292void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 293 const u32 max_rss_queues); 294int igc_reinit_queues(struct igc_adapter *adapter); 295void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 296bool igc_has_link(struct igc_adapter *adapter); 297void igc_reset(struct igc_adapter *adapter); 298void igc_update_stats(struct igc_adapter *adapter); 299void igc_disable_rx_ring(struct igc_ring *ring); 300void igc_enable_rx_ring(struct igc_ring *ring); 301void igc_disable_tx_ring(struct igc_ring *ring); 302void igc_enable_tx_ring(struct igc_ring *ring); 303int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 304 305/* igc_dump declarations */ 306void igc_rings_dump(struct igc_adapter *adapter); 307void igc_regs_dump(struct igc_adapter *adapter); 308 309extern char igc_driver_name[]; 310 311#define IGC_REGS_LEN 740 312 313/* flags controlling PTP/1588 function */ 314#define IGC_PTP_ENABLED BIT(0) 315 316/* Flags definitions */ 317#define IGC_FLAG_HAS_MSI BIT(0) 318#define IGC_FLAG_QUEUE_PAIRS BIT(3) 319#define IGC_FLAG_DMAC BIT(4) 320#define IGC_FLAG_PTP BIT(8) 321#define IGC_FLAG_WOL_SUPPORTED BIT(8) 322#define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 323#define IGC_FLAG_HAS_MSIX BIT(13) 324#define IGC_FLAG_EEE BIT(14) 325#define IGC_FLAG_VLAN_PROMISC BIT(15) 326#define IGC_FLAG_RX_LEGACY BIT(16) 327#define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 328#define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 329 330#define IGC_FLAG_TSN_ANY_ENABLED \ 331 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED) 332 333#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 334#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 335 336#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 337#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 338#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 339 340/* RX-desc Write-Back format RSS Type's */ 341enum igc_rss_type_num { 342 IGC_RSS_TYPE_NO_HASH = 0, 343 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 344 IGC_RSS_TYPE_HASH_IPV4 = 2, 345 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 346 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 347 IGC_RSS_TYPE_HASH_IPV6 = 5, 348 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 349 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 350 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 351 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 352 IGC_RSS_TYPE_MAX = 10, 353}; 354#define IGC_RSS_TYPE_MAX_TABLE 16 355#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 356 357/* igc_rss_type - Rx descriptor RSS type field */ 358static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 359{ 360 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 361 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 362 * is slightly slower than via u32 (wb.lower.lo_dword.data) 363 */ 364 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 365} 366 367/* Interrupt defines */ 368#define IGC_START_ITR 648 /* ~6000 ints/sec */ 369#define IGC_4K_ITR 980 370#define IGC_20K_ITR 196 371#define IGC_70K_ITR 56 372 373#define IGC_DEFAULT_ITR 3 /* dynamic */ 374#define IGC_MAX_ITR_USECS 10000 375#define IGC_MIN_ITR_USECS 10 376#define NON_Q_VECTORS 1 377#define MAX_MSIX_ENTRIES 10 378 379/* TX/RX descriptor defines */ 380#define IGC_DEFAULT_TXD 256 381#define IGC_DEFAULT_TX_WORK 128 382#define IGC_MIN_TXD 64 383#define IGC_MAX_TXD 4096 384 385#define IGC_DEFAULT_RXD 256 386#define IGC_MIN_RXD 64 387#define IGC_MAX_RXD 4096 388 389/* Supported Rx Buffer Sizes */ 390#define IGC_RXBUFFER_256 256 391#define IGC_RXBUFFER_2048 2048 392#define IGC_RXBUFFER_3072 3072 393 394#define AUTO_ALL_MODES 0 395#define IGC_RX_HDR_LEN IGC_RXBUFFER_256 396 397/* Transmit and receive latency (for PTP timestamps) */ 398#define IGC_I225_TX_LATENCY_10 240 399#define IGC_I225_TX_LATENCY_100 58 400#define IGC_I225_TX_LATENCY_1000 80 401#define IGC_I225_TX_LATENCY_2500 1325 402#define IGC_I225_RX_LATENCY_10 6450 403#define IGC_I225_RX_LATENCY_100 185 404#define IGC_I225_RX_LATENCY_1000 300 405#define IGC_I225_RX_LATENCY_2500 1485 406 407/* RX and TX descriptor control thresholds. 408 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 409 * descriptors available in its onboard memory. 410 * Setting this to 0 disables RX descriptor prefetch. 411 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 412 * available in host memory. 413 * If PTHRESH is 0, this should also be 0. 414 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 415 * descriptors until either it has this many to write back, or the 416 * ITR timer expires. 417 */ 418#define IGC_RX_PTHRESH 8 419#define IGC_RX_HTHRESH 8 420#define IGC_TX_PTHRESH 8 421#define IGC_TX_HTHRESH 1 422#define IGC_RX_WTHRESH 4 423#define IGC_TX_WTHRESH 16 424 425#define IGC_RX_DMA_ATTR \ 426 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 427 428#define IGC_TS_HDR_LEN 16 429 430#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 431 432#if (PAGE_SIZE < 8192) 433#define IGC_MAX_FRAME_BUILD_SKB \ 434 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 435#else 436#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 437#endif 438 439/* How many Rx Buffers do we bundle into one write to the hardware ? */ 440#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 441 442/* VLAN info */ 443#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 444#define IGC_TX_FLAGS_VLAN_SHIFT 16 445 446/* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 447static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 448 const u32 stat_err_bits) 449{ 450 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 451} 452 453enum igc_state_t { 454 __IGC_TESTING, 455 __IGC_RESETTING, 456 __IGC_DOWN, 457}; 458 459enum igc_tx_flags { 460 /* cmd_type flags */ 461 IGC_TX_FLAGS_VLAN = 0x01, 462 IGC_TX_FLAGS_TSO = 0x02, 463 IGC_TX_FLAGS_TSTAMP = 0x04, 464 465 /* olinfo flags */ 466 IGC_TX_FLAGS_IPV4 = 0x10, 467 IGC_TX_FLAGS_CSUM = 0x20, 468 469 IGC_TX_FLAGS_TSTAMP_1 = 0x100, 470 IGC_TX_FLAGS_TSTAMP_2 = 0x200, 471 IGC_TX_FLAGS_TSTAMP_3 = 0x400, 472}; 473 474enum igc_boards { 475 board_base, 476}; 477 478/* The largest size we can write to the descriptor is 65535. In order to 479 * maintain a power of two alignment we have to limit ourselves to 32K. 480 */ 481#define IGC_MAX_TXD_PWR 15 482#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 483 484/* Tx Descriptors needed, worst case */ 485#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 486#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 487 488enum igc_tx_buffer_type { 489 IGC_TX_BUFFER_TYPE_SKB, 490 IGC_TX_BUFFER_TYPE_XDP, 491 IGC_TX_BUFFER_TYPE_XSK, 492}; 493 494/* wrapper around a pointer to a socket buffer, 495 * so a DMA handle can be stored along with the buffer 496 */ 497struct igc_tx_buffer { 498 union igc_adv_tx_desc *next_to_watch; 499 unsigned long time_stamp; 500 enum igc_tx_buffer_type type; 501 union { 502 struct sk_buff *skb; 503 struct xdp_frame *xdpf; 504 }; 505 unsigned int bytecount; 506 u16 gso_segs; 507 __be16 protocol; 508 509 DEFINE_DMA_UNMAP_ADDR(dma); 510 DEFINE_DMA_UNMAP_LEN(len); 511 u32 tx_flags; 512}; 513 514struct igc_rx_buffer { 515 union { 516 struct { 517 dma_addr_t dma; 518 struct page *page; 519#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 520 __u32 page_offset; 521#else 522 __u16 page_offset; 523#endif 524 __u16 pagecnt_bias; 525 }; 526 struct xdp_buff *xdp; 527 }; 528}; 529 530/* context wrapper around xdp_buff to provide access to descriptor metadata */ 531struct igc_xdp_buff { 532 struct xdp_buff xdp; 533 union igc_adv_rx_desc *rx_desc; 534 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 535}; 536 537struct igc_q_vector { 538 struct igc_adapter *adapter; /* backlink */ 539 void __iomem *itr_register; 540 u32 eims_value; /* EIMS mask value */ 541 542 u16 itr_val; 543 u8 set_itr; 544 545 struct igc_ring_container rx, tx; 546 547 struct napi_struct napi; 548 549 struct rcu_head rcu; /* to avoid race with update stats on free */ 550 char name[IFNAMSIZ + 9]; 551 struct net_device poll_dev; 552 553 /* for dynamic allocation of rings associated with this q_vector */ 554 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 555}; 556 557enum igc_filter_match_flags { 558 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 559 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 560 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 561 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 562 IGC_FILTER_FLAG_USER_DATA = BIT(4), 563 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 564}; 565 566struct igc_nfc_filter { 567 u8 match_flags; 568 u16 etype; 569 __be16 vlan_etype; 570 u16 vlan_tci; 571 u16 vlan_tci_mask; 572 u8 src_addr[ETH_ALEN]; 573 u8 dst_addr[ETH_ALEN]; 574 u8 user_data[8]; 575 u8 user_mask[8]; 576 u8 flex_index; 577 u8 rx_queue; 578 u8 prio; 579 u8 immediate_irq; 580 u8 drop; 581}; 582 583struct igc_nfc_rule { 584 struct list_head list; 585 struct igc_nfc_filter filter; 586 u32 location; 587 u16 action; 588 bool flex; 589}; 590 591/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 592 * based, 8 ethertype based and 32 Flex filter based rules. 593 */ 594#define IGC_MAX_RXNFC_RULES 64 595 596struct igc_flex_filter { 597 u8 index; 598 u8 data[128]; 599 u8 mask[16]; 600 u8 length; 601 u8 rx_queue; 602 u8 prio; 603 u8 immediate_irq; 604 u8 drop; 605}; 606 607/* igc_desc_unused - calculate if we have unused descriptors */ 608static inline u16 igc_desc_unused(const struct igc_ring *ring) 609{ 610 u16 ntc = ring->next_to_clean; 611 u16 ntu = ring->next_to_use; 612 613 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 614} 615 616static inline s32 igc_get_phy_info(struct igc_hw *hw) 617{ 618 if (hw->phy.ops.get_phy_info) 619 return hw->phy.ops.get_phy_info(hw); 620 621 return 0; 622} 623 624static inline s32 igc_reset_phy(struct igc_hw *hw) 625{ 626 if (hw->phy.ops.reset) 627 return hw->phy.ops.reset(hw); 628 629 return 0; 630} 631 632static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 633{ 634 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 635} 636 637enum igc_ring_flags_t { 638 IGC_RING_FLAG_RX_3K_BUFFER, 639 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 640 IGC_RING_FLAG_RX_SCTP_CSUM, 641 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 642 IGC_RING_FLAG_TX_CTX_IDX, 643 IGC_RING_FLAG_TX_DETECT_HANG, 644 IGC_RING_FLAG_AF_XDP_ZC, 645 IGC_RING_FLAG_TX_HWTSTAMP, 646}; 647 648#define ring_uses_large_buffer(ring) \ 649 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 650#define set_ring_uses_large_buffer(ring) \ 651 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 652#define clear_ring_uses_large_buffer(ring) \ 653 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 654 655#define ring_uses_build_skb(ring) \ 656 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 657 658static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 659{ 660#if (PAGE_SIZE < 8192) 661 if (ring_uses_large_buffer(ring)) 662 return IGC_RXBUFFER_3072; 663 664 if (ring_uses_build_skb(ring)) 665 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 666#endif 667 return IGC_RXBUFFER_2048; 668} 669 670static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 671{ 672#if (PAGE_SIZE < 8192) 673 if (ring_uses_large_buffer(ring)) 674 return 1; 675#endif 676 return 0; 677} 678 679static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 680{ 681 if (hw->phy.ops.read_reg) 682 return hw->phy.ops.read_reg(hw, offset, data); 683 684 return -EOPNOTSUPP; 685} 686 687void igc_reinit_locked(struct igc_adapter *); 688struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 689 u32 location); 690int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 691void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 692 693void igc_ptp_init(struct igc_adapter *adapter); 694void igc_ptp_reset(struct igc_adapter *adapter); 695void igc_ptp_suspend(struct igc_adapter *adapter); 696void igc_ptp_stop(struct igc_adapter *adapter); 697ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 698int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 699int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 700void igc_ptp_tx_hang(struct igc_adapter *adapter); 701void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 702void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 703 704#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 705 706#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 707 708#define IGC_RX_DESC(R, i) \ 709 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 710#define IGC_TX_DESC(R, i) \ 711 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 712#define IGC_TX_CTXTDESC(R, i) \ 713 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 714 715#endif /* _IGC_H_ */ 716