162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* Copyright(c) 2009 - 2018 Intel Corporation. */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci#ifndef _E1000_REGS_H_ 562306a36Sopenharmony_ci#define _E1000_REGS_H_ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#define E1000_CTRL 0x00000 /* Device Control - RW */ 862306a36Sopenharmony_ci#define E1000_STATUS 0x00008 /* Device Status - RO */ 962306a36Sopenharmony_ci#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 1062306a36Sopenharmony_ci#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 1162306a36Sopenharmony_ci#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 1262306a36Sopenharmony_ci#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 1362306a36Sopenharmony_ci#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 1462306a36Sopenharmony_ci#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 1562306a36Sopenharmony_ci#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 1662306a36Sopenharmony_ci#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 1762306a36Sopenharmony_ci#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 1862306a36Sopenharmony_ci#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci/* Convenience macros 2162306a36Sopenharmony_ci * 2262306a36Sopenharmony_ci * Note: "_n" is the queue number of the register to be written to. 2362306a36Sopenharmony_ci * 2462306a36Sopenharmony_ci * Example usage: 2562306a36Sopenharmony_ci * E1000_RDBAL_REG(current_rx_queue) 2662306a36Sopenharmony_ci */ 2762306a36Sopenharmony_ci#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 2862306a36Sopenharmony_ci (0x0C000 + ((_n) * 0x40))) 2962306a36Sopenharmony_ci#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 3062306a36Sopenharmony_ci (0x0C004 + ((_n) * 0x40))) 3162306a36Sopenharmony_ci#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 3262306a36Sopenharmony_ci (0x0C008 + ((_n) * 0x40))) 3362306a36Sopenharmony_ci#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 3462306a36Sopenharmony_ci (0x0C00C + ((_n) * 0x40))) 3562306a36Sopenharmony_ci#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 3662306a36Sopenharmony_ci (0x0C010 + ((_n) * 0x40))) 3762306a36Sopenharmony_ci#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 3862306a36Sopenharmony_ci (0x0C018 + ((_n) * 0x40))) 3962306a36Sopenharmony_ci#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 4062306a36Sopenharmony_ci (0x0C028 + ((_n) * 0x40))) 4162306a36Sopenharmony_ci#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 4262306a36Sopenharmony_ci (0x0E000 + ((_n) * 0x40))) 4362306a36Sopenharmony_ci#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 4462306a36Sopenharmony_ci (0x0E004 + ((_n) * 0x40))) 4562306a36Sopenharmony_ci#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 4662306a36Sopenharmony_ci (0x0E008 + ((_n) * 0x40))) 4762306a36Sopenharmony_ci#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 4862306a36Sopenharmony_ci (0x0E010 + ((_n) * 0x40))) 4962306a36Sopenharmony_ci#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 5062306a36Sopenharmony_ci (0x0E018 + ((_n) * 0x40))) 5162306a36Sopenharmony_ci#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 5262306a36Sopenharmony_ci (0x0E028 + ((_n) * 0x40))) 5362306a36Sopenharmony_ci#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) 5462306a36Sopenharmony_ci#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) 5562306a36Sopenharmony_ci#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 5662306a36Sopenharmony_ci (0x054E0 + ((_i - 16) * 8))) 5762306a36Sopenharmony_ci#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 5862306a36Sopenharmony_ci (0x054E4 + ((_i - 16) * 8))) 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci/* Statistics registers */ 6162306a36Sopenharmony_ci#define E1000_VFGPRC 0x00F10 6262306a36Sopenharmony_ci#define E1000_VFGORC 0x00F18 6362306a36Sopenharmony_ci#define E1000_VFMPRC 0x00F3C 6462306a36Sopenharmony_ci#define E1000_VFGPTC 0x00F14 6562306a36Sopenharmony_ci#define E1000_VFGOTC 0x00F34 6662306a36Sopenharmony_ci#define E1000_VFGOTLBC 0x00F50 6762306a36Sopenharmony_ci#define E1000_VFGPTLBC 0x00F44 6862306a36Sopenharmony_ci#define E1000_VFGORLBC 0x00F48 6962306a36Sopenharmony_ci#define E1000_VFGPRLBC 0x00F40 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci/* These act per VF so an array friendly macro is used */ 7262306a36Sopenharmony_ci#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 7362306a36Sopenharmony_ci#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci/* Define macros for handling registers */ 7662306a36Sopenharmony_ci#define er32(reg) readl(hw->hw_addr + E1000_##reg) 7762306a36Sopenharmony_ci#define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) 7862306a36Sopenharmony_ci#define array_er32(reg, offset) \ 7962306a36Sopenharmony_ci readl(hw->hw_addr + E1000_##reg + (offset << 2)) 8062306a36Sopenharmony_ci#define array_ew32(reg, offset, val) \ 8162306a36Sopenharmony_ci writel((val), hw->hw_addr + E1000_##reg + (offset << 2)) 8262306a36Sopenharmony_ci#define e1e_flush() er32(STATUS) 8362306a36Sopenharmony_ci 8462306a36Sopenharmony_ci#endif 85