1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2018, Intel Corporation. */ 3 4#include <linux/vmalloc.h> 5 6#include "ice_common.h" 7 8/** 9 * ice_aq_read_nvm 10 * @hw: pointer to the HW struct 11 * @module_typeid: module pointer location in words from the NVM beginning 12 * @offset: byte offset from the module beginning 13 * @length: length of the section to be read (in bytes from the offset) 14 * @data: command buffer (size [bytes] = length) 15 * @last_command: tells if this is the last command in a series 16 * @read_shadow_ram: tell if this is a shadow RAM read 17 * @cd: pointer to command details structure or NULL 18 * 19 * Read the NVM using the admin queue commands (0x0701) 20 */ 21static int 22ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length, 23 void *data, bool last_command, bool read_shadow_ram, 24 struct ice_sq_cd *cd) 25{ 26 struct ice_aq_desc desc; 27 struct ice_aqc_nvm *cmd; 28 29 cmd = &desc.params.nvm; 30 31 if (offset > ICE_AQC_NVM_MAX_OFFSET) 32 return -EINVAL; 33 34 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read); 35 36 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT) 37 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY; 38 39 /* If this is the last command in a series, set the proper flag. */ 40 if (last_command) 41 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; 42 cmd->module_typeid = cpu_to_le16(module_typeid); 43 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 44 cmd->offset_high = (offset >> 16) & 0xFF; 45 cmd->length = cpu_to_le16(length); 46 47 return ice_aq_send_cmd(hw, &desc, data, length, cd); 48} 49 50/** 51 * ice_read_flat_nvm - Read portion of NVM by flat offset 52 * @hw: pointer to the HW struct 53 * @offset: offset from beginning of NVM 54 * @length: (in) number of bytes to read; (out) number of bytes actually read 55 * @data: buffer to return data in (sized to fit the specified length) 56 * @read_shadow_ram: if true, read from shadow RAM instead of NVM 57 * 58 * Reads a portion of the NVM, as a flat memory space. This function correctly 59 * breaks read requests across Shadow RAM sectors and ensures that no single 60 * read request exceeds the maximum 4KB read for a single AdminQ command. 61 * 62 * Returns a status code on failure. Note that the data pointer may be 63 * partially updated if some reads succeed before a failure. 64 */ 65int 66ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data, 67 bool read_shadow_ram) 68{ 69 u32 inlen = *length; 70 u32 bytes_read = 0; 71 bool last_cmd; 72 int status; 73 74 *length = 0; 75 76 /* Verify the length of the read if this is for the Shadow RAM */ 77 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) { 78 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n"); 79 return -EINVAL; 80 } 81 82 do { 83 u32 read_size, sector_offset; 84 85 /* ice_aq_read_nvm cannot read more than 4KB at a time. 86 * Additionally, a read from the Shadow RAM may not cross over 87 * a sector boundary. Conveniently, the sector size is also 88 * 4KB. 89 */ 90 sector_offset = offset % ICE_AQ_MAX_BUF_LEN; 91 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset, 92 inlen - bytes_read); 93 94 last_cmd = !(bytes_read + read_size < inlen); 95 96 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, 97 offset, read_size, 98 data + bytes_read, last_cmd, 99 read_shadow_ram, NULL); 100 if (status) 101 break; 102 103 bytes_read += read_size; 104 offset += read_size; 105 } while (!last_cmd); 106 107 *length = bytes_read; 108 return status; 109} 110 111/** 112 * ice_aq_update_nvm 113 * @hw: pointer to the HW struct 114 * @module_typeid: module pointer location in words from the NVM beginning 115 * @offset: byte offset from the module beginning 116 * @length: length of the section to be written (in bytes from the offset) 117 * @data: command buffer (size [bytes] = length) 118 * @last_command: tells if this is the last command in a series 119 * @command_flags: command parameters 120 * @cd: pointer to command details structure or NULL 121 * 122 * Update the NVM using the admin queue commands (0x0703) 123 */ 124int 125ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, 126 u16 length, void *data, bool last_command, u8 command_flags, 127 struct ice_sq_cd *cd) 128{ 129 struct ice_aq_desc desc; 130 struct ice_aqc_nvm *cmd; 131 132 cmd = &desc.params.nvm; 133 134 /* In offset the highest byte must be zeroed. */ 135 if (offset & 0xFF000000) 136 return -EINVAL; 137 138 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write); 139 140 cmd->cmd_flags |= command_flags; 141 142 /* If this is the last command in a series, set the proper flag. */ 143 if (last_command) 144 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; 145 cmd->module_typeid = cpu_to_le16(module_typeid); 146 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 147 cmd->offset_high = (offset >> 16) & 0xFF; 148 cmd->length = cpu_to_le16(length); 149 150 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 151 152 return ice_aq_send_cmd(hw, &desc, data, length, cd); 153} 154 155/** 156 * ice_aq_erase_nvm 157 * @hw: pointer to the HW struct 158 * @module_typeid: module pointer location in words from the NVM beginning 159 * @cd: pointer to command details structure or NULL 160 * 161 * Erase the NVM sector using the admin queue commands (0x0702) 162 */ 163int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd) 164{ 165 struct ice_aq_desc desc; 166 struct ice_aqc_nvm *cmd; 167 168 cmd = &desc.params.nvm; 169 170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase); 171 172 cmd->module_typeid = cpu_to_le16(module_typeid); 173 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN); 174 cmd->offset_low = 0; 175 cmd->offset_high = 0; 176 177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 178} 179 180/** 181 * ice_read_sr_word_aq - Reads Shadow RAM via AQ 182 * @hw: pointer to the HW structure 183 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 184 * @data: word read from the Shadow RAM 185 * 186 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm. 187 */ 188static int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data) 189{ 190 u32 bytes = sizeof(u16); 191 __le16 data_local; 192 int status; 193 194 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and 195 * Shadow RAM sector restrictions necessary when reading from the NVM. 196 */ 197 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes, 198 (__force u8 *)&data_local, true); 199 if (status) 200 return status; 201 202 *data = le16_to_cpu(data_local); 203 return 0; 204} 205 206/** 207 * ice_acquire_nvm - Generic request for acquiring the NVM ownership 208 * @hw: pointer to the HW structure 209 * @access: NVM access type (read or write) 210 * 211 * This function will request NVM ownership. 212 */ 213int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access) 214{ 215 if (hw->flash.blank_nvm_mode) 216 return 0; 217 218 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT); 219} 220 221/** 222 * ice_release_nvm - Generic request for releasing the NVM ownership 223 * @hw: pointer to the HW structure 224 * 225 * This function will release NVM ownership. 226 */ 227void ice_release_nvm(struct ice_hw *hw) 228{ 229 if (hw->flash.blank_nvm_mode) 230 return; 231 232 ice_release_res(hw, ICE_NVM_RES_ID); 233} 234 235/** 236 * ice_get_flash_bank_offset - Get offset into requested flash bank 237 * @hw: pointer to the HW structure 238 * @bank: whether to read from the active or inactive flash bank 239 * @module: the module to read from 240 * 241 * Based on the module, lookup the module offset from the beginning of the 242 * flash. 243 * 244 * Returns the flash offset. Note that a value of zero is invalid and must be 245 * treated as an error. 246 */ 247static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module) 248{ 249 struct ice_bank_info *banks = &hw->flash.banks; 250 enum ice_flash_bank active_bank; 251 bool second_bank_active; 252 u32 offset, size; 253 254 switch (module) { 255 case ICE_SR_1ST_NVM_BANK_PTR: 256 offset = banks->nvm_ptr; 257 size = banks->nvm_size; 258 active_bank = banks->nvm_bank; 259 break; 260 case ICE_SR_1ST_OROM_BANK_PTR: 261 offset = banks->orom_ptr; 262 size = banks->orom_size; 263 active_bank = banks->orom_bank; 264 break; 265 case ICE_SR_NETLIST_BANK_PTR: 266 offset = banks->netlist_ptr; 267 size = banks->netlist_size; 268 active_bank = banks->netlist_bank; 269 break; 270 default: 271 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module); 272 return 0; 273 } 274 275 switch (active_bank) { 276 case ICE_1ST_FLASH_BANK: 277 second_bank_active = false; 278 break; 279 case ICE_2ND_FLASH_BANK: 280 second_bank_active = true; 281 break; 282 default: 283 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n", 284 active_bank); 285 return 0; 286 } 287 288 /* The second flash bank is stored immediately following the first 289 * bank. Based on whether the 1st or 2nd bank is active, and whether 290 * we want the active or inactive bank, calculate the desired offset. 291 */ 292 switch (bank) { 293 case ICE_ACTIVE_FLASH_BANK: 294 return offset + (second_bank_active ? size : 0); 295 case ICE_INACTIVE_FLASH_BANK: 296 return offset + (second_bank_active ? 0 : size); 297 } 298 299 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank); 300 return 0; 301} 302 303/** 304 * ice_read_flash_module - Read a word from one of the main NVM modules 305 * @hw: pointer to the HW structure 306 * @bank: which bank of the module to read 307 * @module: the module to read 308 * @offset: the offset into the module in bytes 309 * @data: storage for the word read from the flash 310 * @length: bytes of data to read 311 * 312 * Read data from the specified flash module. The bank parameter indicates 313 * whether or not to read from the active bank or the inactive bank of that 314 * module. 315 * 316 * The word will be read using flat NVM access, and relies on the 317 * hw->flash.banks data being setup by ice_determine_active_flash_banks() 318 * during initialization. 319 */ 320static int 321ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, 322 u32 offset, u8 *data, u32 length) 323{ 324 int status; 325 u32 start; 326 327 start = ice_get_flash_bank_offset(hw, bank, module); 328 if (!start) { 329 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n", 330 module); 331 return -EINVAL; 332 } 333 334 status = ice_acquire_nvm(hw, ICE_RES_READ); 335 if (status) 336 return status; 337 338 status = ice_read_flat_nvm(hw, start + offset, &length, data, false); 339 340 ice_release_nvm(hw); 341 342 return status; 343} 344 345/** 346 * ice_read_nvm_module - Read from the active main NVM module 347 * @hw: pointer to the HW structure 348 * @bank: whether to read from active or inactive NVM module 349 * @offset: offset into the NVM module to read, in words 350 * @data: storage for returned word value 351 * 352 * Read the specified word from the active NVM module. This includes the CSS 353 * header at the start of the NVM module. 354 */ 355static int 356ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) 357{ 358 __le16 data_local; 359 int status; 360 361 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16), 362 (__force u8 *)&data_local, sizeof(u16)); 363 if (!status) 364 *data = le16_to_cpu(data_local); 365 366 return status; 367} 368 369/** 370 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank 371 * @hw: pointer to the HW structure 372 * @bank: whether to read from the active or inactive NVM module 373 * @offset: offset into the Shadow RAM copy to read, in words 374 * @data: storage for returned word value 375 * 376 * Read the specified word from the copy of the Shadow RAM found in the 377 * specified NVM module. 378 */ 379static int 380ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) 381{ 382 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data); 383} 384 385/** 386 * ice_read_netlist_module - Read data from the netlist module area 387 * @hw: pointer to the HW structure 388 * @bank: whether to read from the active or inactive module 389 * @offset: offset into the netlist to read from 390 * @data: storage for returned word value 391 * 392 * Read a word from the specified netlist bank. 393 */ 394static int 395ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) 396{ 397 __le16 data_local; 398 int status; 399 400 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16), 401 (__force u8 *)&data_local, sizeof(u16)); 402 if (!status) 403 *data = le16_to_cpu(data_local); 404 405 return status; 406} 407 408/** 409 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary 410 * @hw: pointer to the HW structure 411 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 412 * @data: word read from the Shadow RAM 413 * 414 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq. 415 */ 416int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data) 417{ 418 int status; 419 420 status = ice_acquire_nvm(hw, ICE_RES_READ); 421 if (!status) { 422 status = ice_read_sr_word_aq(hw, offset, data); 423 ice_release_nvm(hw); 424 } 425 426 return status; 427} 428 429/** 430 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA 431 * @hw: pointer to hardware structure 432 * @module_tlv: pointer to module TLV to return 433 * @module_tlv_len: pointer to module TLV length to return 434 * @module_type: module type requested 435 * 436 * Finds the requested sub module TLV type from the Preserved Field 437 * Area (PFA) and returns the TLV pointer and length. The caller can 438 * use these to read the variable length TLV value. 439 */ 440int 441ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, 442 u16 module_type) 443{ 444 u16 pfa_len, pfa_ptr; 445 u16 next_tlv; 446 int status; 447 448 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr); 449 if (status) { 450 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n"); 451 return status; 452 } 453 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len); 454 if (status) { 455 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n"); 456 return status; 457 } 458 /* Starting with first TLV after PFA length, iterate through the list 459 * of TLVs to find the requested one. 460 */ 461 next_tlv = pfa_ptr + 1; 462 while (next_tlv < pfa_ptr + pfa_len) { 463 u16 tlv_sub_module_type; 464 u16 tlv_len; 465 466 /* Read TLV type */ 467 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type); 468 if (status) { 469 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n"); 470 break; 471 } 472 /* Read TLV length */ 473 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len); 474 if (status) { 475 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n"); 476 break; 477 } 478 if (tlv_sub_module_type == module_type) { 479 if (tlv_len) { 480 *module_tlv = next_tlv; 481 *module_tlv_len = tlv_len; 482 return 0; 483 } 484 return -EINVAL; 485 } 486 /* Check next TLV, i.e. current TLV pointer + length + 2 words 487 * (for current TLV's type and length) 488 */ 489 next_tlv = next_tlv + tlv_len + 2; 490 } 491 /* Module does not exist */ 492 return -ENOENT; 493} 494 495/** 496 * ice_read_pba_string - Reads part number string from NVM 497 * @hw: pointer to hardware structure 498 * @pba_num: stores the part number string from the NVM 499 * @pba_num_size: part number string buffer length 500 * 501 * Reads the part number string from the NVM. 502 */ 503int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size) 504{ 505 u16 pba_tlv, pba_tlv_len; 506 u16 pba_word, pba_size; 507 int status; 508 u16 i; 509 510 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len, 511 ICE_SR_PBA_BLOCK_PTR); 512 if (status) { 513 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n"); 514 return status; 515 } 516 517 /* pba_size is the next word */ 518 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size); 519 if (status) { 520 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n"); 521 return status; 522 } 523 524 if (pba_tlv_len < pba_size) { 525 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n"); 526 return -EINVAL; 527 } 528 529 /* Subtract one to get PBA word count (PBA Size word is included in 530 * total size) 531 */ 532 pba_size--; 533 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 534 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n"); 535 return -EINVAL; 536 } 537 538 for (i = 0; i < pba_size; i++) { 539 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word); 540 if (status) { 541 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i); 542 return status; 543 } 544 545 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 546 pba_num[(i * 2) + 1] = pba_word & 0xFF; 547 } 548 pba_num[(pba_size * 2)] = '\0'; 549 550 return status; 551} 552 553/** 554 * ice_get_nvm_ver_info - Read NVM version information 555 * @hw: pointer to the HW struct 556 * @bank: whether to read from the active or inactive flash bank 557 * @nvm: pointer to NVM info structure 558 * 559 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling 560 * in the NVM info structure. 561 */ 562static int 563ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm) 564{ 565 u16 eetrack_lo, eetrack_hi, ver; 566 int status; 567 568 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver); 569 if (status) { 570 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n"); 571 return status; 572 } 573 574 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT; 575 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT; 576 577 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); 578 if (status) { 579 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n"); 580 return status; 581 } 582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi); 583 if (status) { 584 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n"); 585 return status; 586 } 587 588 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; 589 590 return 0; 591} 592 593/** 594 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank 595 * @hw: pointer to the HW structure 596 * @nvm: storage for Option ROM version information 597 * 598 * Reads the NVM EETRACK ID, Map version, and security revision of the 599 * inactive NVM bank. Used to access version data for a pending update that 600 * has not yet been activated. 601 */ 602int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm) 603{ 604 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm); 605} 606 607/** 608 * ice_get_orom_civd_data - Get the combo version information from Option ROM 609 * @hw: pointer to the HW struct 610 * @bank: whether to read from the active or inactive flash module 611 * @civd: storage for the Option ROM CIVD data. 612 * 613 * Searches through the Option ROM flash contents to locate the CIVD data for 614 * the image. 615 */ 616static int 617ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, 618 struct ice_orom_civd_info *civd) 619{ 620 u8 *orom_data; 621 int status; 622 u32 offset; 623 624 /* The CIVD section is located in the Option ROM aligned to 512 bytes. 625 * The first 4 bytes must contain the ASCII characters "$CIV". 626 * A simple modulo 256 sum of all of the bytes of the structure must 627 * equal 0. 628 * 629 * The exact location is unknown and varies between images but is 630 * usually somewhere in the middle of the bank. We need to scan the 631 * Option ROM bank to locate it. 632 * 633 * It's significantly faster to read the entire Option ROM up front 634 * using the maximum page size, than to read each possible location 635 * with a separate firmware command. 636 */ 637 orom_data = vzalloc(hw->flash.banks.orom_size); 638 if (!orom_data) 639 return -ENOMEM; 640 641 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0, 642 orom_data, hw->flash.banks.orom_size); 643 if (status) { 644 vfree(orom_data); 645 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n"); 646 return status; 647 } 648 649 /* Scan the memory buffer to locate the CIVD data section */ 650 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { 651 struct ice_orom_civd_info *tmp; 652 u8 sum = 0, i; 653 654 tmp = (struct ice_orom_civd_info *)&orom_data[offset]; 655 656 /* Skip forward until we find a matching signature */ 657 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0) 658 continue; 659 660 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n", 661 offset); 662 663 /* Verify that the simple checksum is zero */ 664 for (i = 0; i < sizeof(*tmp); i++) 665 sum += ((u8 *)tmp)[i]; 666 667 if (sum) { 668 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n", 669 sum); 670 goto err_invalid_checksum; 671 } 672 673 *civd = *tmp; 674 vfree(orom_data); 675 return 0; 676 } 677 678 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n"); 679 680err_invalid_checksum: 681 vfree(orom_data); 682 return -EIO; 683} 684 685/** 686 * ice_get_orom_ver_info - Read Option ROM version information 687 * @hw: pointer to the HW struct 688 * @bank: whether to read from the active or inactive flash module 689 * @orom: pointer to Option ROM info structure 690 * 691 * Read Option ROM version and security revision from the Option ROM flash 692 * section. 693 */ 694static int 695ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom) 696{ 697 struct ice_orom_civd_info civd; 698 u32 combo_ver; 699 int status; 700 701 status = ice_get_orom_civd_data(hw, bank, &civd); 702 if (status) { 703 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n"); 704 return status; 705 } 706 707 combo_ver = le32_to_cpu(civd.combo_ver); 708 709 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT); 710 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK); 711 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT); 712 713 return 0; 714} 715 716/** 717 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank 718 * @hw: pointer to the HW structure 719 * @orom: storage for Option ROM version information 720 * 721 * Reads the Option ROM version and security revision data for the inactive 722 * section of flash. Used to access version data for a pending update that has 723 * not yet been activated. 724 */ 725int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom) 726{ 727 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom); 728} 729 730/** 731 * ice_get_netlist_info 732 * @hw: pointer to the HW struct 733 * @bank: whether to read from the active or inactive flash bank 734 * @netlist: pointer to netlist version info structure 735 * 736 * Get the netlist version information from the requested bank. Reads the Link 737 * Topology section to find the Netlist ID block and extract the relevant 738 * information into the netlist version structure. 739 */ 740static int 741ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank, 742 struct ice_netlist_info *netlist) 743{ 744 u16 module_id, length, node_count, i; 745 u16 *id_blk; 746 int status; 747 748 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id); 749 if (status) 750 return status; 751 752 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) { 753 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n", 754 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id); 755 return -EIO; 756 } 757 758 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length); 759 if (status) 760 return status; 761 762 /* sanity check that we have at least enough words to store the netlist ID block */ 763 if (length < ICE_NETLIST_ID_BLK_SIZE) { 764 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n", 765 ICE_NETLIST_ID_BLK_SIZE, length); 766 return -EIO; 767 } 768 769 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count); 770 if (status) 771 return status; 772 node_count &= ICE_LINK_TOPO_NODE_COUNT_M; 773 774 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL); 775 if (!id_blk) 776 return -ENOMEM; 777 778 /* Read out the entire Netlist ID Block at once. */ 779 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, 780 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16), 781 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16)); 782 if (status) 783 goto exit_error; 784 785 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++) 786 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]); 787 788 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 | 789 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW]; 790 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 | 791 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW]; 792 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 | 793 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW]; 794 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 | 795 id_blk[ICE_NETLIST_ID_BLK_REV_LOW]; 796 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER]; 797 /* Read the left most 4 bytes of SHA */ 798 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 | 799 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)]; 800 801exit_error: 802 kfree(id_blk); 803 804 return status; 805} 806 807/** 808 * ice_get_inactive_netlist_ver 809 * @hw: pointer to the HW struct 810 * @netlist: pointer to netlist version info structure 811 * 812 * Read the netlist version data from the inactive netlist bank. Used to 813 * extract version data of a pending flash update in order to display the 814 * version data. 815 */ 816int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist) 817{ 818 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist); 819} 820 821/** 822 * ice_discover_flash_size - Discover the available flash size. 823 * @hw: pointer to the HW struct 824 * 825 * The device flash could be up to 16MB in size. However, it is possible that 826 * the actual size is smaller. Use bisection to determine the accessible size 827 * of flash memory. 828 */ 829static int ice_discover_flash_size(struct ice_hw *hw) 830{ 831 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1; 832 int status; 833 834 status = ice_acquire_nvm(hw, ICE_RES_READ); 835 if (status) 836 return status; 837 838 while ((max_size - min_size) > 1) { 839 u32 offset = (max_size + min_size) / 2; 840 u32 len = 1; 841 u8 data; 842 843 status = ice_read_flat_nvm(hw, offset, &len, &data, false); 844 if (status == -EIO && 845 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) { 846 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n", 847 __func__, offset); 848 status = 0; 849 max_size = offset; 850 } else if (!status) { 851 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n", 852 __func__, offset); 853 min_size = offset; 854 } else { 855 /* an unexpected error occurred */ 856 goto err_read_flat_nvm; 857 } 858 } 859 860 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size); 861 862 hw->flash.flash_size = max_size; 863 864err_read_flat_nvm: 865 ice_release_nvm(hw); 866 867 return status; 868} 869 870/** 871 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word 872 * @hw: pointer to the HW structure 873 * @offset: the word offset of the Shadow RAM word to read 874 * @pointer: pointer value read from Shadow RAM 875 * 876 * Read the given Shadow RAM word, and convert it to a pointer value specified 877 * in bytes. This function assumes the specified offset is a valid pointer 878 * word. 879 * 880 * Each pointer word specifies whether it is stored in word size or 4KB 881 * sector size by using the highest bit. The reported pointer value will be in 882 * bytes, intended for flat NVM reads. 883 */ 884static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer) 885{ 886 int status; 887 u16 value; 888 889 status = ice_read_sr_word(hw, offset, &value); 890 if (status) 891 return status; 892 893 /* Determine if the pointer is in 4KB or word units */ 894 if (value & ICE_SR_NVM_PTR_4KB_UNITS) 895 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024; 896 else 897 *pointer = value * 2; 898 899 return 0; 900} 901 902/** 903 * ice_read_sr_area_size - Read an area size from a Shadow RAM word 904 * @hw: pointer to the HW structure 905 * @offset: the word offset of the Shadow RAM to read 906 * @size: size value read from the Shadow RAM 907 * 908 * Read the given Shadow RAM word, and convert it to an area size value 909 * specified in bytes. This function assumes the specified offset is a valid 910 * area size word. 911 * 912 * Each area size word is specified in 4KB sector units. This function reports 913 * the size in bytes, intended for flat NVM reads. 914 */ 915static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size) 916{ 917 int status; 918 u16 value; 919 920 status = ice_read_sr_word(hw, offset, &value); 921 if (status) 922 return status; 923 924 /* Area sizes are always specified in 4KB units */ 925 *size = value * 4 * 1024; 926 927 return 0; 928} 929 930/** 931 * ice_determine_active_flash_banks - Discover active bank for each module 932 * @hw: pointer to the HW struct 933 * 934 * Read the Shadow RAM control word and determine which banks are active for 935 * the NVM, OROM, and Netlist modules. Also read and calculate the associated 936 * pointer and size. These values are then cached into the ice_flash_info 937 * structure for later use in order to calculate the correct offset to read 938 * from the active module. 939 */ 940static int ice_determine_active_flash_banks(struct ice_hw *hw) 941{ 942 struct ice_bank_info *banks = &hw->flash.banks; 943 u16 ctrl_word; 944 int status; 945 946 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word); 947 if (status) { 948 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n"); 949 return status; 950 } 951 952 /* Check that the control word indicates validity */ 953 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) { 954 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n"); 955 return -EIO; 956 } 957 958 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK)) 959 banks->nvm_bank = ICE_1ST_FLASH_BANK; 960 else 961 banks->nvm_bank = ICE_2ND_FLASH_BANK; 962 963 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK)) 964 banks->orom_bank = ICE_1ST_FLASH_BANK; 965 else 966 banks->orom_bank = ICE_2ND_FLASH_BANK; 967 968 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK)) 969 banks->netlist_bank = ICE_1ST_FLASH_BANK; 970 else 971 banks->netlist_bank = ICE_2ND_FLASH_BANK; 972 973 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr); 974 if (status) { 975 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n"); 976 return status; 977 } 978 979 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size); 980 if (status) { 981 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n"); 982 return status; 983 } 984 985 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr); 986 if (status) { 987 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n"); 988 return status; 989 } 990 991 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size); 992 if (status) { 993 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n"); 994 return status; 995 } 996 997 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr); 998 if (status) { 999 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n"); 1000 return status; 1001 } 1002 1003 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size); 1004 if (status) { 1005 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n"); 1006 return status; 1007 } 1008 1009 return 0; 1010} 1011 1012/** 1013 * ice_init_nvm - initializes NVM setting 1014 * @hw: pointer to the HW struct 1015 * 1016 * This function reads and populates NVM settings such as Shadow RAM size, 1017 * max_timeout, and blank_nvm_mode 1018 */ 1019int ice_init_nvm(struct ice_hw *hw) 1020{ 1021 struct ice_flash_info *flash = &hw->flash; 1022 u32 fla, gens_stat; 1023 u8 sr_size; 1024 int status; 1025 1026 /* The SR size is stored regardless of the NVM programming mode 1027 * as the blank mode may be used in the factory line. 1028 */ 1029 gens_stat = rd32(hw, GLNVM_GENS); 1030 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S; 1031 1032 /* Switching to words (sr_size contains power of 2) */ 1033 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB; 1034 1035 /* Check if we are in the normal or blank NVM programming mode */ 1036 fla = rd32(hw, GLNVM_FLA); 1037 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */ 1038 flash->blank_nvm_mode = false; 1039 } else { 1040 /* Blank programming mode */ 1041 flash->blank_nvm_mode = true; 1042 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n"); 1043 return -EIO; 1044 } 1045 1046 status = ice_discover_flash_size(hw); 1047 if (status) { 1048 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n"); 1049 return status; 1050 } 1051 1052 status = ice_determine_active_flash_banks(hw); 1053 if (status) { 1054 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n"); 1055 return status; 1056 } 1057 1058 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm); 1059 if (status) { 1060 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n"); 1061 return status; 1062 } 1063 1064 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom); 1065 if (status) 1066 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n"); 1067 1068 /* read the netlist version information */ 1069 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist); 1070 if (status) 1071 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n"); 1072 1073 return 0; 1074} 1075 1076/** 1077 * ice_nvm_validate_checksum 1078 * @hw: pointer to the HW struct 1079 * 1080 * Verify NVM PFA checksum validity (0x0706) 1081 */ 1082int ice_nvm_validate_checksum(struct ice_hw *hw) 1083{ 1084 struct ice_aqc_nvm_checksum *cmd; 1085 struct ice_aq_desc desc; 1086 int status; 1087 1088 status = ice_acquire_nvm(hw, ICE_RES_READ); 1089 if (status) 1090 return status; 1091 1092 cmd = &desc.params.nvm_checksum; 1093 1094 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum); 1095 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY; 1096 1097 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1098 ice_release_nvm(hw); 1099 1100 if (!status) 1101 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT) 1102 status = -EIO; 1103 1104 return status; 1105} 1106 1107/** 1108 * ice_nvm_write_activate 1109 * @hw: pointer to the HW struct 1110 * @cmd_flags: flags for write activate command 1111 * @response_flags: response indicators from firmware 1112 * 1113 * Update the control word with the required banks' validity bits 1114 * and dumps the Shadow RAM to flash (0x0707) 1115 * 1116 * cmd_flags controls which banks to activate, the preservation level to use 1117 * when activating the NVM bank, and whether an EMP reset is required for 1118 * activation. 1119 * 1120 * Note that the 16bit cmd_flags value is split between two separate 1 byte 1121 * flag values in the descriptor. 1122 * 1123 * On successful return of the firmware command, the response_flags variable 1124 * is updated with the flags reported by firmware indicating certain status, 1125 * such as whether EMP reset is enabled. 1126 */ 1127int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags) 1128{ 1129 struct ice_aqc_nvm *cmd; 1130 struct ice_aq_desc desc; 1131 int err; 1132 1133 cmd = &desc.params.nvm; 1134 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate); 1135 1136 cmd->cmd_flags = (u8)(cmd_flags & 0xFF); 1137 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF); 1138 1139 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1140 if (!err && response_flags) 1141 *response_flags = cmd->cmd_flags; 1142 1143 return err; 1144} 1145 1146/** 1147 * ice_aq_nvm_update_empr 1148 * @hw: pointer to the HW struct 1149 * 1150 * Update empr (0x0709). This command allows SW to 1151 * request an EMPR to activate new FW. 1152 */ 1153int ice_aq_nvm_update_empr(struct ice_hw *hw) 1154{ 1155 struct ice_aq_desc desc; 1156 1157 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr); 1158 1159 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1160} 1161 1162/* ice_nvm_set_pkg_data 1163 * @hw: pointer to the HW struct 1164 * @del_pkg_data_flag: If is set then the current pkg_data store by FW 1165 * is deleted. 1166 * If bit is set to 1, then buffer should be size 0. 1167 * @data: pointer to buffer 1168 * @length: length of the buffer 1169 * @cd: pointer to command details structure or NULL 1170 * 1171 * Set package data (0x070A). This command is equivalent to the reception 1172 * of a PLDM FW Update GetPackageData cmd. This command should be sent 1173 * as part of the NVM update as the first cmd in the flow. 1174 */ 1175 1176int 1177ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data, 1178 u16 length, struct ice_sq_cd *cd) 1179{ 1180 struct ice_aqc_nvm_pkg_data *cmd; 1181 struct ice_aq_desc desc; 1182 1183 if (length != 0 && !data) 1184 return -EINVAL; 1185 1186 cmd = &desc.params.pkg_data; 1187 1188 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data); 1189 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1190 1191 if (del_pkg_data_flag) 1192 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE; 1193 1194 return ice_aq_send_cmd(hw, &desc, data, length, cd); 1195} 1196 1197/* ice_nvm_pass_component_tbl 1198 * @hw: pointer to the HW struct 1199 * @data: pointer to buffer 1200 * @length: length of the buffer 1201 * @transfer_flag: parameter for determining stage of the update 1202 * @comp_response: a pointer to the response from the 0x070B AQC. 1203 * @comp_response_code: a pointer to the response code from the 0x070B AQC. 1204 * @cd: pointer to command details structure or NULL 1205 * 1206 * Pass component table (0x070B). This command is equivalent to the reception 1207 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once 1208 * per component. It can be only sent after Set Package Data cmd and before 1209 * actual update. FW will assume these commands are going to be sent until 1210 * the TransferFlag is set to End or StartAndEnd. 1211 */ 1212 1213int 1214ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length, 1215 u8 transfer_flag, u8 *comp_response, 1216 u8 *comp_response_code, struct ice_sq_cd *cd) 1217{ 1218 struct ice_aqc_nvm_pass_comp_tbl *cmd; 1219 struct ice_aq_desc desc; 1220 int status; 1221 1222 if (!data || !comp_response || !comp_response_code) 1223 return -EINVAL; 1224 1225 cmd = &desc.params.pass_comp_tbl; 1226 1227 ice_fill_dflt_direct_cmd_desc(&desc, 1228 ice_aqc_opc_nvm_pass_component_tbl); 1229 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1230 1231 cmd->transfer_flag = transfer_flag; 1232 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 1233 1234 if (!status) { 1235 *comp_response = cmd->component_response; 1236 *comp_response_code = cmd->component_response_code; 1237 } 1238 return status; 1239} 1240