162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* Copyright(c) 2018 Intel Corporation. */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci#ifndef _I40E_XSK_H_ 562306a36Sopenharmony_ci#define _I40E_XSK_H_ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci/* This value should match the pragma in the loop_unrolled_for 862306a36Sopenharmony_ci * macro. Why 4? It is strictly empirical. It seems to be a good 962306a36Sopenharmony_ci * compromise between the advantage of having simultaneous outstanding 1062306a36Sopenharmony_ci * reads to the DMA array that can hide each others latency and the 1162306a36Sopenharmony_ci * disadvantage of having a larger code path. 1262306a36Sopenharmony_ci */ 1362306a36Sopenharmony_ci#define PKTS_PER_BATCH 4 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#ifdef __clang__ 1662306a36Sopenharmony_ci#define loop_unrolled_for _Pragma("clang loop unroll_count(4)") for 1762306a36Sopenharmony_ci#elif __GNUC__ >= 8 1862306a36Sopenharmony_ci#define loop_unrolled_for _Pragma("GCC unroll 4") for 1962306a36Sopenharmony_ci#else 2062306a36Sopenharmony_ci#define loop_unrolled_for for 2162306a36Sopenharmony_ci#endif 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_cistruct i40e_vsi; 2462306a36Sopenharmony_cistruct xsk_buff_pool; 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciint i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair); 2762306a36Sopenharmony_ciint i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair); 2862306a36Sopenharmony_ciint i40e_xsk_pool_setup(struct i40e_vsi *vsi, struct xsk_buff_pool *pool, 2962306a36Sopenharmony_ci u16 qid); 3062306a36Sopenharmony_cibool i40e_alloc_rx_buffers_zc(struct i40e_ring *rx_ring, u16 cleaned_count); 3162306a36Sopenharmony_ciint i40e_clean_rx_irq_zc(struct i40e_ring *rx_ring, int budget); 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_cibool i40e_clean_xdp_tx_irq(struct i40e_vsi *vsi, struct i40e_ring *tx_ring); 3462306a36Sopenharmony_ciint i40e_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 3562306a36Sopenharmony_ciint i40e_realloc_rx_bi_zc(struct i40e_vsi *vsi, bool zc); 3662306a36Sopenharmony_civoid i40e_clear_rx_bi_zc(struct i40e_ring *rx_ring); 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci#endif /* _I40E_XSK_H_ */ 39