1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4/* 80003ES2LAN Gigabit Ethernet Controller (Copper) 5 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 6 */ 7 8#include "e1000.h" 9 10/* A table for the GG82563 cable length where the range is defined 11 * with a lower bound at "index" and the upper bound at 12 * "index + 5". 13 */ 14static const u16 e1000_gg82563_cable_length_table[] = { 15 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF 16}; 17 18#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 19 ARRAY_SIZE(e1000_gg82563_cable_length_table) 20 21static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 22static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 23static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 24static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 25static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 26static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 27static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 28static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 29 u16 *data); 30static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 31 u16 data); 32static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 33 34/** 35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 36 * @hw: pointer to the HW structure 37 **/ 38static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 39{ 40 struct e1000_phy_info *phy = &hw->phy; 41 s32 ret_val; 42 43 if (hw->phy.media_type != e1000_media_type_copper) { 44 phy->type = e1000_phy_none; 45 return 0; 46 } else { 47 phy->ops.power_up = e1000_power_up_phy_copper; 48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 49 } 50 51 phy->addr = 1; 52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 53 phy->reset_delay_us = 100; 54 phy->type = e1000_phy_gg82563; 55 56 /* This can only be done after all function pointers are setup. */ 57 ret_val = e1000e_get_phy_id(hw); 58 59 /* Verify phy id */ 60 if (phy->id != GG82563_E_PHY_ID) 61 return -E1000_ERR_PHY; 62 63 return ret_val; 64} 65 66/** 67 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 68 * @hw: pointer to the HW structure 69 **/ 70static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 71{ 72 struct e1000_nvm_info *nvm = &hw->nvm; 73 u32 eecd = er32(EECD); 74 u16 size; 75 76 nvm->opcode_bits = 8; 77 nvm->delay_usec = 1; 78 switch (nvm->override) { 79 case e1000_nvm_override_spi_large: 80 nvm->page_size = 32; 81 nvm->address_bits = 16; 82 break; 83 case e1000_nvm_override_spi_small: 84 nvm->page_size = 8; 85 nvm->address_bits = 8; 86 break; 87 default: 88 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 89 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 90 break; 91 } 92 93 nvm->type = e1000_nvm_eeprom_spi; 94 95 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 96 E1000_EECD_SIZE_EX_SHIFT); 97 98 /* Added to a constant, "size" becomes the left-shift value 99 * for setting word_size. 100 */ 101 size += NVM_WORD_SIZE_BASE_SHIFT; 102 103 /* EEPROM access above 16k is unsupported */ 104 if (size > 14) 105 size = 14; 106 nvm->word_size = BIT(size); 107 108 return 0; 109} 110 111/** 112 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 113 * @hw: pointer to the HW structure 114 **/ 115static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 116{ 117 struct e1000_mac_info *mac = &hw->mac; 118 119 /* Set media type and media-dependent function pointers */ 120 switch (hw->adapter->pdev->device) { 121 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 122 hw->phy.media_type = e1000_media_type_internal_serdes; 123 mac->ops.check_for_link = e1000e_check_for_serdes_link; 124 mac->ops.setup_physical_interface = 125 e1000e_setup_fiber_serdes_link; 126 break; 127 default: 128 hw->phy.media_type = e1000_media_type_copper; 129 mac->ops.check_for_link = e1000e_check_for_copper_link; 130 mac->ops.setup_physical_interface = 131 e1000_setup_copper_link_80003es2lan; 132 break; 133 } 134 135 /* Set mta register count */ 136 mac->mta_reg_count = 128; 137 /* Set rar entry count */ 138 mac->rar_entry_count = E1000_RAR_ENTRIES; 139 /* FWSM register */ 140 mac->has_fwsm = true; 141 /* ARC supported; valid only if manageability features are enabled. */ 142 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK); 143 /* Adaptive IFS not supported */ 144 mac->adaptive_ifs = false; 145 146 /* set lan id for port to determine which phy lock to use */ 147 hw->mac.ops.set_lan_id(hw); 148 149 return 0; 150} 151 152static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) 153{ 154 struct e1000_hw *hw = &adapter->hw; 155 s32 rc; 156 157 rc = e1000_init_mac_params_80003es2lan(hw); 158 if (rc) 159 return rc; 160 161 rc = e1000_init_nvm_params_80003es2lan(hw); 162 if (rc) 163 return rc; 164 165 rc = e1000_init_phy_params_80003es2lan(hw); 166 if (rc) 167 return rc; 168 169 return 0; 170} 171 172/** 173 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 174 * @hw: pointer to the HW structure 175 * 176 * A wrapper to acquire access rights to the correct PHY. 177 **/ 178static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 179{ 180 u16 mask; 181 182 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 183 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 184} 185 186/** 187 * e1000_release_phy_80003es2lan - Release rights to access PHY 188 * @hw: pointer to the HW structure 189 * 190 * A wrapper to release access rights to the correct PHY. 191 **/ 192static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 193{ 194 u16 mask; 195 196 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 197 e1000_release_swfw_sync_80003es2lan(hw, mask); 198} 199 200/** 201 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 202 * @hw: pointer to the HW structure 203 * 204 * Acquire the semaphore to access the Kumeran interface. 205 * 206 **/ 207static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 208{ 209 u16 mask; 210 211 mask = E1000_SWFW_CSR_SM; 212 213 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 214} 215 216/** 217 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 218 * @hw: pointer to the HW structure 219 * 220 * Release the semaphore used to access the Kumeran interface 221 **/ 222static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 223{ 224 u16 mask; 225 226 mask = E1000_SWFW_CSR_SM; 227 228 e1000_release_swfw_sync_80003es2lan(hw, mask); 229} 230 231/** 232 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 233 * @hw: pointer to the HW structure 234 * 235 * Acquire the semaphore to access the EEPROM. 236 **/ 237static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 238{ 239 s32 ret_val; 240 241 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 242 if (ret_val) 243 return ret_val; 244 245 ret_val = e1000e_acquire_nvm(hw); 246 247 if (ret_val) 248 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 249 250 return ret_val; 251} 252 253/** 254 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 255 * @hw: pointer to the HW structure 256 * 257 * Release the semaphore used to access the EEPROM. 258 **/ 259static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 260{ 261 e1000e_release_nvm(hw); 262 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 263} 264 265/** 266 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 267 * @hw: pointer to the HW structure 268 * @mask: specifies which semaphore to acquire 269 * 270 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 271 * will also specify which port we're acquiring the lock for. 272 **/ 273static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 274{ 275 u32 swfw_sync; 276 u32 swmask = mask; 277 u32 fwmask = mask << 16; 278 s32 i = 0; 279 s32 timeout = 50; 280 281 while (i < timeout) { 282 if (e1000e_get_hw_semaphore(hw)) 283 return -E1000_ERR_SWFW_SYNC; 284 285 swfw_sync = er32(SW_FW_SYNC); 286 if (!(swfw_sync & (fwmask | swmask))) 287 break; 288 289 /* Firmware currently using resource (fwmask) 290 * or other software thread using resource (swmask) 291 */ 292 e1000e_put_hw_semaphore(hw); 293 mdelay(5); 294 i++; 295 } 296 297 if (i == timeout) { 298 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 299 return -E1000_ERR_SWFW_SYNC; 300 } 301 302 swfw_sync |= swmask; 303 ew32(SW_FW_SYNC, swfw_sync); 304 305 e1000e_put_hw_semaphore(hw); 306 307 return 0; 308} 309 310/** 311 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 312 * @hw: pointer to the HW structure 313 * @mask: specifies which semaphore to acquire 314 * 315 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 316 * will also specify which port we're releasing the lock for. 317 **/ 318static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 319{ 320 u32 swfw_sync; 321 322 while (e1000e_get_hw_semaphore(hw) != 0) 323 ; /* Empty */ 324 325 swfw_sync = er32(SW_FW_SYNC); 326 swfw_sync &= ~mask; 327 ew32(SW_FW_SYNC, swfw_sync); 328 329 e1000e_put_hw_semaphore(hw); 330} 331 332/** 333 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 334 * @hw: pointer to the HW structure 335 * @offset: offset of the register to read 336 * @data: pointer to the data returned from the operation 337 * 338 * Read the GG82563 PHY register. 339 **/ 340static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 341 u32 offset, u16 *data) 342{ 343 s32 ret_val; 344 u32 page_select; 345 u16 temp; 346 347 ret_val = e1000_acquire_phy_80003es2lan(hw); 348 if (ret_val) 349 return ret_val; 350 351 /* Select Configuration Page */ 352 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 353 page_select = GG82563_PHY_PAGE_SELECT; 354 } else { 355 /* Use Alternative Page Select register to access 356 * registers 30 and 31 357 */ 358 page_select = GG82563_PHY_PAGE_SELECT_ALT; 359 } 360 361 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 362 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 363 if (ret_val) { 364 e1000_release_phy_80003es2lan(hw); 365 return ret_val; 366 } 367 368 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 369 /* The "ready" bit in the MDIC register may be incorrectly set 370 * before the device has completed the "Page Select" MDI 371 * transaction. So we wait 200us after each MDI command... 372 */ 373 usleep_range(200, 400); 374 375 /* ...and verify the command was successful. */ 376 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 377 378 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 379 e1000_release_phy_80003es2lan(hw); 380 return -E1000_ERR_PHY; 381 } 382 383 usleep_range(200, 400); 384 385 ret_val = e1000e_read_phy_reg_mdic(hw, 386 MAX_PHY_REG_ADDRESS & offset, 387 data); 388 389 usleep_range(200, 400); 390 } else { 391 ret_val = e1000e_read_phy_reg_mdic(hw, 392 MAX_PHY_REG_ADDRESS & offset, 393 data); 394 } 395 396 e1000_release_phy_80003es2lan(hw); 397 398 return ret_val; 399} 400 401/** 402 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 403 * @hw: pointer to the HW structure 404 * @offset: offset of the register to read 405 * @data: value to write to the register 406 * 407 * Write to the GG82563 PHY register. 408 **/ 409static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 410 u32 offset, u16 data) 411{ 412 s32 ret_val; 413 u32 page_select; 414 u16 temp; 415 416 ret_val = e1000_acquire_phy_80003es2lan(hw); 417 if (ret_val) 418 return ret_val; 419 420 /* Select Configuration Page */ 421 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 422 page_select = GG82563_PHY_PAGE_SELECT; 423 } else { 424 /* Use Alternative Page Select register to access 425 * registers 30 and 31 426 */ 427 page_select = GG82563_PHY_PAGE_SELECT_ALT; 428 } 429 430 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 431 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 432 if (ret_val) { 433 e1000_release_phy_80003es2lan(hw); 434 return ret_val; 435 } 436 437 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 438 /* The "ready" bit in the MDIC register may be incorrectly set 439 * before the device has completed the "Page Select" MDI 440 * transaction. So we wait 200us after each MDI command... 441 */ 442 usleep_range(200, 400); 443 444 /* ...and verify the command was successful. */ 445 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 446 447 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 448 e1000_release_phy_80003es2lan(hw); 449 return -E1000_ERR_PHY; 450 } 451 452 usleep_range(200, 400); 453 454 ret_val = e1000e_write_phy_reg_mdic(hw, 455 MAX_PHY_REG_ADDRESS & 456 offset, data); 457 458 usleep_range(200, 400); 459 } else { 460 ret_val = e1000e_write_phy_reg_mdic(hw, 461 MAX_PHY_REG_ADDRESS & 462 offset, data); 463 } 464 465 e1000_release_phy_80003es2lan(hw); 466 467 return ret_val; 468} 469 470/** 471 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 472 * @hw: pointer to the HW structure 473 * @offset: offset of the register to read 474 * @words: number of words to write 475 * @data: buffer of data to write to the NVM 476 * 477 * Write "words" of data to the ESB2 NVM. 478 **/ 479static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 480 u16 words, u16 *data) 481{ 482 return e1000e_write_nvm_spi(hw, offset, words, data); 483} 484 485/** 486 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 487 * @hw: pointer to the HW structure 488 * 489 * Wait a specific amount of time for manageability processes to complete. 490 * This is a function pointer entry point called by the phy module. 491 **/ 492static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 493{ 494 s32 timeout = PHY_CFG_TIMEOUT; 495 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 496 497 if (hw->bus.func == 1) 498 mask = E1000_NVM_CFG_DONE_PORT_1; 499 500 while (timeout) { 501 if (er32(EEMNGCTL) & mask) 502 break; 503 usleep_range(1000, 2000); 504 timeout--; 505 } 506 if (!timeout) { 507 e_dbg("MNG configuration cycle has not completed.\n"); 508 return -E1000_ERR_RESET; 509 } 510 511 return 0; 512} 513 514/** 515 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 516 * @hw: pointer to the HW structure 517 * 518 * Force the speed and duplex settings onto the PHY. This is a 519 * function pointer entry point called by the phy module. 520 **/ 521static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 522{ 523 s32 ret_val; 524 u16 phy_data; 525 bool link; 526 527 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 528 * forced whenever speed and duplex are forced. 529 */ 530 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 531 if (ret_val) 532 return ret_val; 533 534 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 535 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); 536 if (ret_val) 537 return ret_val; 538 539 e_dbg("GG82563 PSCR: %X\n", phy_data); 540 541 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 542 if (ret_val) 543 return ret_val; 544 545 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 546 547 /* Reset the phy to commit changes. */ 548 phy_data |= BMCR_RESET; 549 550 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 551 if (ret_val) 552 return ret_val; 553 554 udelay(1); 555 556 if (hw->phy.autoneg_wait_to_complete) { 557 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n"); 558 559 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 560 100000, &link); 561 if (ret_val) 562 return ret_val; 563 564 if (!link) { 565 /* We didn't get link. 566 * Reset the DSP and cross our fingers. 567 */ 568 ret_val = e1000e_phy_reset_dsp(hw); 569 if (ret_val) 570 return ret_val; 571 } 572 573 /* Try once more */ 574 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 575 100000, &link); 576 if (ret_val) 577 return ret_val; 578 } 579 580 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 581 if (ret_val) 582 return ret_val; 583 584 /* Resetting the phy means we need to verify the TX_CLK corresponds 585 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 586 */ 587 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 588 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 589 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 590 else 591 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 592 593 /* In addition, we must re-enable CRS on Tx for both half and full 594 * duplex. 595 */ 596 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 597 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 598 599 return ret_val; 600} 601 602/** 603 * e1000_get_cable_length_80003es2lan - Set approximate cable length 604 * @hw: pointer to the HW structure 605 * 606 * Find the approximate cable length as measured by the GG82563 PHY. 607 * This is a function pointer entry point called by the phy module. 608 **/ 609static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 610{ 611 struct e1000_phy_info *phy = &hw->phy; 612 s32 ret_val; 613 u16 phy_data, index; 614 615 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 616 if (ret_val) 617 return ret_val; 618 619 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 620 621 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 622 return -E1000_ERR_PHY; 623 624 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 625 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 626 627 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 628 629 return 0; 630} 631 632/** 633 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 634 * @hw: pointer to the HW structure 635 * @speed: pointer to speed buffer 636 * @duplex: pointer to duplex buffer 637 * 638 * Retrieve the current speed and duplex configuration. 639 **/ 640static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 641 u16 *duplex) 642{ 643 s32 ret_val; 644 645 if (hw->phy.media_type == e1000_media_type_copper) { 646 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 647 hw->phy.ops.cfg_on_link_up(hw); 648 } else { 649 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, 650 speed, 651 duplex); 652 } 653 654 return ret_val; 655} 656 657/** 658 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 659 * @hw: pointer to the HW structure 660 * 661 * Perform a global reset to the ESB2 controller. 662 **/ 663static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 664{ 665 u32 ctrl; 666 s32 ret_val; 667 u16 kum_reg_data; 668 669 /* Prevent the PCI-E bus from sticking if there is no TLP connection 670 * on the last TLP read/write transaction when MAC is reset. 671 */ 672 ret_val = e1000e_disable_pcie_master(hw); 673 if (ret_val) 674 e_dbg("PCI-E Master disable polling has failed.\n"); 675 676 e_dbg("Masking off all interrupts\n"); 677 ew32(IMC, 0xffffffff); 678 679 ew32(RCTL, 0); 680 ew32(TCTL, E1000_TCTL_PSP); 681 e1e_flush(); 682 683 usleep_range(10000, 11000); 684 685 ctrl = er32(CTRL); 686 687 ret_val = e1000_acquire_phy_80003es2lan(hw); 688 if (ret_val) 689 return ret_val; 690 691 e_dbg("Issuing a global reset to MAC\n"); 692 ew32(CTRL, ctrl | E1000_CTRL_RST); 693 e1000_release_phy_80003es2lan(hw); 694 695 /* Disable IBIST slave mode (far-end loopback) */ 696 ret_val = 697 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 698 &kum_reg_data); 699 if (!ret_val) { 700 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 701 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 702 E1000_KMRNCTRLSTA_INBAND_PARAM, 703 kum_reg_data); 704 if (ret_val) 705 e_dbg("Error disabling far-end loopback\n"); 706 } else { 707 e_dbg("Error disabling far-end loopback\n"); 708 } 709 710 ret_val = e1000e_get_auto_rd_done(hw); 711 if (ret_val) 712 /* We don't want to continue accessing MAC registers. */ 713 return ret_val; 714 715 /* Clear any pending interrupt events. */ 716 ew32(IMC, 0xffffffff); 717 er32(ICR); 718 719 return e1000_check_alt_mac_addr_generic(hw); 720} 721 722/** 723 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 724 * @hw: pointer to the HW structure 725 * 726 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 727 **/ 728static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 729{ 730 struct e1000_mac_info *mac = &hw->mac; 731 u32 reg_data; 732 s32 ret_val; 733 u16 kum_reg_data; 734 u16 i; 735 736 e1000_initialize_hw_bits_80003es2lan(hw); 737 738 /* Initialize identification LED */ 739 ret_val = mac->ops.id_led_init(hw); 740 /* An error is not fatal and we should not stop init due to this */ 741 if (ret_val) 742 e_dbg("Error initializing identification LED\n"); 743 744 /* Disabling VLAN filtering */ 745 e_dbg("Initializing the IEEE VLAN\n"); 746 mac->ops.clear_vfta(hw); 747 748 /* Setup the receive address. */ 749 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 750 751 /* Zero out the Multicast HASH table */ 752 e_dbg("Zeroing the MTA\n"); 753 for (i = 0; i < mac->mta_reg_count; i++) 754 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 755 756 /* Setup link and flow control */ 757 ret_val = mac->ops.setup_link(hw); 758 if (ret_val) 759 return ret_val; 760 761 /* Disable IBIST slave mode (far-end loopback) */ 762 ret_val = 763 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 764 &kum_reg_data); 765 if (!ret_val) { 766 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 767 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 768 E1000_KMRNCTRLSTA_INBAND_PARAM, 769 kum_reg_data); 770 if (ret_val) 771 e_dbg("Error disabling far-end loopback\n"); 772 } else { 773 e_dbg("Error disabling far-end loopback\n"); 774 } 775 776 /* Set the transmit descriptor write-back policy */ 777 reg_data = er32(TXDCTL(0)); 778 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 779 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 780 ew32(TXDCTL(0), reg_data); 781 782 /* ...for both queues. */ 783 reg_data = er32(TXDCTL(1)); 784 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 785 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 786 ew32(TXDCTL(1), reg_data); 787 788 /* Enable retransmit on late collisions */ 789 reg_data = er32(TCTL); 790 reg_data |= E1000_TCTL_RTLC; 791 ew32(TCTL, reg_data); 792 793 /* Configure Gigabit Carry Extend Padding */ 794 reg_data = er32(TCTL_EXT); 795 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 796 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 797 ew32(TCTL_EXT, reg_data); 798 799 /* Configure Transmit Inter-Packet Gap */ 800 reg_data = er32(TIPG); 801 reg_data &= ~E1000_TIPG_IPGT_MASK; 802 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 803 ew32(TIPG, reg_data); 804 805 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 806 reg_data &= ~0x00100000; 807 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 808 809 /* default to true to enable the MDIC W/A */ 810 hw->dev_spec.e80003es2lan.mdic_wa_enable = true; 811 812 ret_val = 813 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 814 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 815 if (!ret_val) { 816 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 817 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 818 hw->dev_spec.e80003es2lan.mdic_wa_enable = false; 819 } 820 821 /* Clear all of the statistics registers (clear on read). It is 822 * important that we do this after we have tried to establish link 823 * because the symbol error count will increment wildly if there 824 * is no link. 825 */ 826 e1000_clear_hw_cntrs_80003es2lan(hw); 827 828 return ret_val; 829} 830 831/** 832 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 833 * @hw: pointer to the HW structure 834 * 835 * Initializes required hardware-dependent bits needed for normal operation. 836 **/ 837static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 838{ 839 u32 reg; 840 841 /* Transmit Descriptor Control 0 */ 842 reg = er32(TXDCTL(0)); 843 reg |= BIT(22); 844 ew32(TXDCTL(0), reg); 845 846 /* Transmit Descriptor Control 1 */ 847 reg = er32(TXDCTL(1)); 848 reg |= BIT(22); 849 ew32(TXDCTL(1), reg); 850 851 /* Transmit Arbitration Control 0 */ 852 reg = er32(TARC(0)); 853 reg &= ~(0xF << 27); /* 30:27 */ 854 if (hw->phy.media_type != e1000_media_type_copper) 855 reg &= ~BIT(20); 856 ew32(TARC(0), reg); 857 858 /* Transmit Arbitration Control 1 */ 859 reg = er32(TARC(1)); 860 if (er32(TCTL) & E1000_TCTL_MULR) 861 reg &= ~BIT(28); 862 else 863 reg |= BIT(28); 864 ew32(TARC(1), reg); 865 866 /* Disable IPv6 extension header parsing because some malformed 867 * IPv6 headers can hang the Rx. 868 */ 869 reg = er32(RFCTL); 870 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 871 ew32(RFCTL, reg); 872} 873 874/** 875 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 876 * @hw: pointer to the HW structure 877 * 878 * Setup some GG82563 PHY registers for obtaining link 879 **/ 880static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 881{ 882 struct e1000_phy_info *phy = &hw->phy; 883 s32 ret_val; 884 u32 reg; 885 u16 data; 886 887 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 888 if (ret_val) 889 return ret_val; 890 891 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 892 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 893 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 894 895 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 896 if (ret_val) 897 return ret_val; 898 899 /* Options: 900 * MDI/MDI-X = 0 (default) 901 * 0 - Auto for all speeds 902 * 1 - MDI mode 903 * 2 - MDI-X mode 904 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 905 */ 906 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); 907 if (ret_val) 908 return ret_val; 909 910 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 911 912 switch (phy->mdix) { 913 case 1: 914 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 915 break; 916 case 2: 917 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 918 break; 919 case 0: 920 default: 921 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 922 break; 923 } 924 925 /* Options: 926 * disable_polarity_correction = 0 (default) 927 * Automatic Correction for Reversed Cable Polarity 928 * 0 - Disabled 929 * 1 - Enabled 930 */ 931 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 932 if (phy->disable_polarity_correction) 933 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 934 935 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); 936 if (ret_val) 937 return ret_val; 938 939 /* SW Reset the PHY so all changes take effect */ 940 ret_val = hw->phy.ops.commit(hw); 941 if (ret_val) { 942 e_dbg("Error Resetting the PHY\n"); 943 return ret_val; 944 } 945 946 /* Bypass Rx and Tx FIFO's */ 947 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 948 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 949 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 950 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 951 if (ret_val) 952 return ret_val; 953 954 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 955 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 956 if (ret_val) 957 return ret_val; 958 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 959 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 960 if (ret_val) 961 return ret_val; 962 963 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); 964 if (ret_val) 965 return ret_val; 966 967 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 968 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); 969 if (ret_val) 970 return ret_val; 971 972 reg = er32(CTRL_EXT); 973 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 974 ew32(CTRL_EXT, reg); 975 976 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 977 if (ret_val) 978 return ret_val; 979 980 /* Do not init these registers when the HW is in IAMT mode, since the 981 * firmware will have already initialized them. We only initialize 982 * them if the HW is not in IAMT mode. 983 */ 984 if (!hw->mac.ops.check_mng_mode(hw)) { 985 /* Enable Electrical Idle on the PHY */ 986 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 987 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); 988 if (ret_val) 989 return ret_val; 990 991 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); 992 if (ret_val) 993 return ret_val; 994 995 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 996 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); 997 if (ret_val) 998 return ret_val; 999 } 1000 1001 /* Workaround: Disable padding in Kumeran interface in the MAC 1002 * and in the PHY to avoid CRC errors. 1003 */ 1004 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); 1005 if (ret_val) 1006 return ret_val; 1007 1008 data |= GG82563_ICR_DIS_PADDING; 1009 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); 1010 if (ret_val) 1011 return ret_val; 1012 1013 return 0; 1014} 1015 1016/** 1017 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1018 * @hw: pointer to the HW structure 1019 * 1020 * Essentially a wrapper for setting up all things "copper" related. 1021 * This is a function pointer entry point called by the mac module. 1022 **/ 1023static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1024{ 1025 u32 ctrl; 1026 s32 ret_val; 1027 u16 reg_data; 1028 1029 ctrl = er32(CTRL); 1030 ctrl |= E1000_CTRL_SLU; 1031 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1032 ew32(CTRL, ctrl); 1033 1034 /* Set the mac to wait the maximum time between each 1035 * iteration and increase the max iterations when 1036 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1037 */ 1038 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1039 0xFFFF); 1040 if (ret_val) 1041 return ret_val; 1042 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1043 ®_data); 1044 if (ret_val) 1045 return ret_val; 1046 reg_data |= 0x3F; 1047 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1048 reg_data); 1049 if (ret_val) 1050 return ret_val; 1051 ret_val = 1052 e1000_read_kmrn_reg_80003es2lan(hw, 1053 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1054 ®_data); 1055 if (ret_val) 1056 return ret_val; 1057 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1058 ret_val = 1059 e1000_write_kmrn_reg_80003es2lan(hw, 1060 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1061 reg_data); 1062 if (ret_val) 1063 return ret_val; 1064 1065 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1066 if (ret_val) 1067 return ret_val; 1068 1069 return e1000e_setup_copper_link(hw); 1070} 1071 1072/** 1073 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1074 * @hw: pointer to the HW structure 1075 * 1076 * Configure the KMRN interface by applying last minute quirks for 1077 * 10/100 operation. 1078 **/ 1079static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1080{ 1081 s32 ret_val = 0; 1082 u16 speed; 1083 u16 duplex; 1084 1085 if (hw->phy.media_type == e1000_media_type_copper) { 1086 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, 1087 &duplex); 1088 if (ret_val) 1089 return ret_val; 1090 1091 if (speed == SPEED_1000) 1092 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1093 else 1094 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1095 } 1096 1097 return ret_val; 1098} 1099 1100/** 1101 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1102 * @hw: pointer to the HW structure 1103 * @duplex: current duplex setting 1104 * 1105 * Configure the KMRN interface by applying last minute quirks for 1106 * 10/100 operation. 1107 **/ 1108static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1109{ 1110 s32 ret_val; 1111 u32 tipg; 1112 u32 i = 0; 1113 u16 reg_data, reg_data2; 1114 1115 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1116 ret_val = 1117 e1000_write_kmrn_reg_80003es2lan(hw, 1118 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1119 reg_data); 1120 if (ret_val) 1121 return ret_val; 1122 1123 /* Configure Transmit Inter-Packet Gap */ 1124 tipg = er32(TIPG); 1125 tipg &= ~E1000_TIPG_IPGT_MASK; 1126 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1127 ew32(TIPG, tipg); 1128 1129 do { 1130 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1131 if (ret_val) 1132 return ret_val; 1133 1134 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); 1135 if (ret_val) 1136 return ret_val; 1137 i++; 1138 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1139 1140 if (duplex == HALF_DUPLEX) 1141 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1142 else 1143 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1144 1145 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1146} 1147 1148/** 1149 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1150 * @hw: pointer to the HW structure 1151 * 1152 * Configure the KMRN interface by applying last minute quirks for 1153 * gigabit operation. 1154 **/ 1155static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1156{ 1157 s32 ret_val; 1158 u16 reg_data, reg_data2; 1159 u32 tipg; 1160 u32 i = 0; 1161 1162 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1163 ret_val = 1164 e1000_write_kmrn_reg_80003es2lan(hw, 1165 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1166 reg_data); 1167 if (ret_val) 1168 return ret_val; 1169 1170 /* Configure Transmit Inter-Packet Gap */ 1171 tipg = er32(TIPG); 1172 tipg &= ~E1000_TIPG_IPGT_MASK; 1173 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1174 ew32(TIPG, tipg); 1175 1176 do { 1177 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1178 if (ret_val) 1179 return ret_val; 1180 1181 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); 1182 if (ret_val) 1183 return ret_val; 1184 i++; 1185 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1186 1187 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1188 1189 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1190} 1191 1192/** 1193 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1194 * @hw: pointer to the HW structure 1195 * @offset: register offset to be read 1196 * @data: pointer to the read data 1197 * 1198 * Acquire semaphore, then read the PHY register at offset 1199 * using the kumeran interface. The information retrieved is stored in data. 1200 * Release the semaphore before exiting. 1201 **/ 1202static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1203 u16 *data) 1204{ 1205 u32 kmrnctrlsta; 1206 s32 ret_val; 1207 1208 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1209 if (ret_val) 1210 return ret_val; 1211 1212 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1213 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1214 ew32(KMRNCTRLSTA, kmrnctrlsta); 1215 e1e_flush(); 1216 1217 udelay(2); 1218 1219 kmrnctrlsta = er32(KMRNCTRLSTA); 1220 *data = (u16)kmrnctrlsta; 1221 1222 e1000_release_mac_csr_80003es2lan(hw); 1223 1224 return ret_val; 1225} 1226 1227/** 1228 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1229 * @hw: pointer to the HW structure 1230 * @offset: register offset to write to 1231 * @data: data to write at register offset 1232 * 1233 * Acquire semaphore, then write the data to PHY register 1234 * at the offset using the kumeran interface. Release semaphore 1235 * before exiting. 1236 **/ 1237static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1238 u16 data) 1239{ 1240 u32 kmrnctrlsta; 1241 s32 ret_val; 1242 1243 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1244 if (ret_val) 1245 return ret_val; 1246 1247 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1248 E1000_KMRNCTRLSTA_OFFSET) | data; 1249 ew32(KMRNCTRLSTA, kmrnctrlsta); 1250 e1e_flush(); 1251 1252 udelay(2); 1253 1254 e1000_release_mac_csr_80003es2lan(hw); 1255 1256 return ret_val; 1257} 1258 1259/** 1260 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1261 * @hw: pointer to the HW structure 1262 **/ 1263static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1264{ 1265 s32 ret_val; 1266 1267 /* If there's an alternate MAC address place it in RAR0 1268 * so that it will override the Si installed default perm 1269 * address. 1270 */ 1271 ret_val = e1000_check_alt_mac_addr_generic(hw); 1272 if (ret_val) 1273 return ret_val; 1274 1275 return e1000_read_mac_addr_generic(hw); 1276} 1277 1278/** 1279 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1280 * @hw: pointer to the HW structure 1281 * 1282 * In the case of a PHY power down to save power, or to turn off link during a 1283 * driver unload, or wake on lan is not enabled, remove the link. 1284 **/ 1285static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1286{ 1287 /* If the management interface is not enabled, then power down */ 1288 if (!(hw->mac.ops.check_mng_mode(hw) || 1289 hw->phy.ops.check_reset_block(hw))) 1290 e1000_power_down_phy_copper(hw); 1291} 1292 1293/** 1294 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1295 * @hw: pointer to the HW structure 1296 * 1297 * Clears the hardware counters by reading the counter registers. 1298 **/ 1299static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1300{ 1301 e1000e_clear_hw_cntrs_base(hw); 1302 1303 er32(PRC64); 1304 er32(PRC127); 1305 er32(PRC255); 1306 er32(PRC511); 1307 er32(PRC1023); 1308 er32(PRC1522); 1309 er32(PTC64); 1310 er32(PTC127); 1311 er32(PTC255); 1312 er32(PTC511); 1313 er32(PTC1023); 1314 er32(PTC1522); 1315 1316 er32(ALGNERRC); 1317 er32(RXERRC); 1318 er32(TNCRS); 1319 er32(CEXTERR); 1320 er32(TSCTC); 1321 er32(TSCTFC); 1322 1323 er32(MGTPRC); 1324 er32(MGTPDC); 1325 er32(MGTPTC); 1326 1327 er32(IAC); 1328 er32(ICRXOC); 1329 1330 er32(ICRXPTC); 1331 er32(ICRXATC); 1332 er32(ICTXPTC); 1333 er32(ICTXATC); 1334 er32(ICTXQEC); 1335 er32(ICTXQMTC); 1336 er32(ICRXDMTC); 1337} 1338 1339static const struct e1000_mac_operations es2_mac_ops = { 1340 .read_mac_addr = e1000_read_mac_addr_80003es2lan, 1341 .id_led_init = e1000e_id_led_init_generic, 1342 .blink_led = e1000e_blink_led_generic, 1343 .check_mng_mode = e1000e_check_mng_mode_generic, 1344 /* check_for_link dependent on media type */ 1345 .cleanup_led = e1000e_cleanup_led_generic, 1346 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, 1347 .get_bus_info = e1000e_get_bus_info_pcie, 1348 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1349 .get_link_up_info = e1000_get_link_up_info_80003es2lan, 1350 .led_on = e1000e_led_on_generic, 1351 .led_off = e1000e_led_off_generic, 1352 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1353 .write_vfta = e1000_write_vfta_generic, 1354 .clear_vfta = e1000_clear_vfta_generic, 1355 .reset_hw = e1000_reset_hw_80003es2lan, 1356 .init_hw = e1000_init_hw_80003es2lan, 1357 .setup_link = e1000e_setup_link_generic, 1358 /* setup_physical_interface dependent on media type */ 1359 .setup_led = e1000e_setup_led_generic, 1360 .config_collision_dist = e1000e_config_collision_dist_generic, 1361 .rar_set = e1000e_rar_set_generic, 1362 .rar_get_count = e1000e_rar_get_count_generic, 1363}; 1364 1365static const struct e1000_phy_operations es2_phy_ops = { 1366 .acquire = e1000_acquire_phy_80003es2lan, 1367 .check_polarity = e1000_check_polarity_m88, 1368 .check_reset_block = e1000e_check_reset_block_generic, 1369 .commit = e1000e_phy_sw_reset, 1370 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, 1371 .get_cfg_done = e1000_get_cfg_done_80003es2lan, 1372 .get_cable_length = e1000_get_cable_length_80003es2lan, 1373 .get_info = e1000e_get_phy_info_m88, 1374 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, 1375 .release = e1000_release_phy_80003es2lan, 1376 .reset = e1000e_phy_hw_reset_generic, 1377 .set_d0_lplu_state = NULL, 1378 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1379 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, 1380 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, 1381}; 1382 1383static const struct e1000_nvm_operations es2_nvm_ops = { 1384 .acquire = e1000_acquire_nvm_80003es2lan, 1385 .read = e1000e_read_nvm_eerd, 1386 .release = e1000_release_nvm_80003es2lan, 1387 .reload = e1000e_reload_nvm_generic, 1388 .update = e1000e_update_nvm_checksum_generic, 1389 .valid_led_default = e1000e_valid_led_default, 1390 .validate = e1000e_validate_nvm_checksum_generic, 1391 .write = e1000_write_nvm_80003es2lan, 1392}; 1393 1394const struct e1000_info e1000_es2_info = { 1395 .mac = e1000_80003es2lan, 1396 .flags = FLAG_HAS_HW_VLAN_FILTER 1397 | FLAG_HAS_JUMBO_FRAMES 1398 | FLAG_HAS_WOL 1399 | FLAG_APME_IN_CTRL3 1400 | FLAG_HAS_CTRLEXT_ON_LOAD 1401 | FLAG_RX_NEEDS_RESTART /* errata */ 1402 | FLAG_TARC_SET_BIT_ZERO /* errata */ 1403 | FLAG_APME_CHECK_PORT_B 1404 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */ 1405 .flags2 = FLAG2_DMA_BURST, 1406 .pba = 38, 1407 .max_hw_frame_size = DEFAULT_JUMBO, 1408 .get_variants = e1000_get_variants_80003es2lan, 1409 .mac_ops = &es2_mac_ops, 1410 .phy_ops = &es2_phy_ops, 1411 .nvm_ops = &es2_nvm_ops, 1412}; 1413