1// SPDX-License-Identifier: GPL-2.0-or-later 2/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ 3/* 4 Copyright (c) 2001, 2002 by D-Link Corporation 5 Written by Edward Peng.<edward_peng@dlink.com.tw> 6 Created 03-May-2001, base on Linux' sundance.c. 7 8*/ 9 10#include "dl2k.h" 11#include <linux/dma-mapping.h> 12 13#define dw32(reg, val) iowrite32(val, ioaddr + (reg)) 14#define dw16(reg, val) iowrite16(val, ioaddr + (reg)) 15#define dw8(reg, val) iowrite8(val, ioaddr + (reg)) 16#define dr32(reg) ioread32(ioaddr + (reg)) 17#define dr16(reg) ioread16(ioaddr + (reg)) 18#define dr8(reg) ioread8(ioaddr + (reg)) 19 20#define MAX_UNITS 8 21static int mtu[MAX_UNITS]; 22static int vlan[MAX_UNITS]; 23static int jumbo[MAX_UNITS]; 24static char *media[MAX_UNITS]; 25static int tx_flow=-1; 26static int rx_flow=-1; 27static int copy_thresh; 28static int rx_coalesce=10; /* Rx frame count each interrupt */ 29static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */ 30static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */ 31 32 33MODULE_AUTHOR ("Edward Peng"); 34MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter"); 35MODULE_LICENSE("GPL"); 36module_param_array(mtu, int, NULL, 0); 37module_param_array(media, charp, NULL, 0); 38module_param_array(vlan, int, NULL, 0); 39module_param_array(jumbo, int, NULL, 0); 40module_param(tx_flow, int, 0); 41module_param(rx_flow, int, 0); 42module_param(copy_thresh, int, 0); 43module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */ 44module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */ 45module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */ 46 47 48/* Enable the default interrupts */ 49#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \ 50 UpdateStats | LinkEvent) 51 52static void dl2k_enable_int(struct netdev_private *np) 53{ 54 void __iomem *ioaddr = np->ioaddr; 55 56 dw16(IntEnable, DEFAULT_INTR); 57} 58 59static const int max_intrloop = 50; 60static const int multicast_filter_limit = 0x40; 61 62static int rio_open (struct net_device *dev); 63static void rio_timer (struct timer_list *t); 64static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue); 65static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev); 66static irqreturn_t rio_interrupt (int irq, void *dev_instance); 67static void rio_free_tx (struct net_device *dev, int irq); 68static void tx_error (struct net_device *dev, int tx_status); 69static int receive_packet (struct net_device *dev); 70static void rio_error (struct net_device *dev, int int_status); 71static void set_multicast (struct net_device *dev); 72static struct net_device_stats *get_stats (struct net_device *dev); 73static int clear_stats (struct net_device *dev); 74static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 75static int rio_close (struct net_device *dev); 76static int find_miiphy (struct net_device *dev); 77static int parse_eeprom (struct net_device *dev); 78static int read_eeprom (struct netdev_private *, int eep_addr); 79static int mii_wait_link (struct net_device *dev, int wait); 80static int mii_set_media (struct net_device *dev); 81static int mii_get_media (struct net_device *dev); 82static int mii_set_media_pcs (struct net_device *dev); 83static int mii_get_media_pcs (struct net_device *dev); 84static int mii_read (struct net_device *dev, int phy_addr, int reg_num); 85static int mii_write (struct net_device *dev, int phy_addr, int reg_num, 86 u16 data); 87 88static const struct ethtool_ops ethtool_ops; 89 90static const struct net_device_ops netdev_ops = { 91 .ndo_open = rio_open, 92 .ndo_start_xmit = start_xmit, 93 .ndo_stop = rio_close, 94 .ndo_get_stats = get_stats, 95 .ndo_validate_addr = eth_validate_addr, 96 .ndo_set_mac_address = eth_mac_addr, 97 .ndo_set_rx_mode = set_multicast, 98 .ndo_eth_ioctl = rio_ioctl, 99 .ndo_tx_timeout = rio_tx_timeout, 100}; 101 102static int 103rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) 104{ 105 struct net_device *dev; 106 struct netdev_private *np; 107 static int card_idx; 108 int chip_idx = ent->driver_data; 109 int err, irq; 110 void __iomem *ioaddr; 111 void *ring_space; 112 dma_addr_t ring_dma; 113 114 err = pci_enable_device (pdev); 115 if (err) 116 return err; 117 118 irq = pdev->irq; 119 err = pci_request_regions (pdev, "dl2k"); 120 if (err) 121 goto err_out_disable; 122 123 pci_set_master (pdev); 124 125 err = -ENOMEM; 126 127 dev = alloc_etherdev (sizeof (*np)); 128 if (!dev) 129 goto err_out_res; 130 SET_NETDEV_DEV(dev, &pdev->dev); 131 132 np = netdev_priv(dev); 133 134 /* IO registers range. */ 135 ioaddr = pci_iomap(pdev, 0, 0); 136 if (!ioaddr) 137 goto err_out_dev; 138 np->eeprom_addr = ioaddr; 139 140#ifdef MEM_MAPPING 141 /* MM registers range. */ 142 ioaddr = pci_iomap(pdev, 1, 0); 143 if (!ioaddr) 144 goto err_out_iounmap; 145#endif 146 np->ioaddr = ioaddr; 147 np->chip_id = chip_idx; 148 np->pdev = pdev; 149 spin_lock_init (&np->tx_lock); 150 spin_lock_init (&np->rx_lock); 151 152 /* Parse manual configuration */ 153 np->an_enable = 1; 154 np->tx_coalesce = 1; 155 if (card_idx < MAX_UNITS) { 156 if (media[card_idx] != NULL) { 157 np->an_enable = 0; 158 if (strcmp (media[card_idx], "auto") == 0 || 159 strcmp (media[card_idx], "autosense") == 0 || 160 strcmp (media[card_idx], "0") == 0 ) { 161 np->an_enable = 2; 162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 || 163 strcmp (media[card_idx], "4") == 0) { 164 np->speed = 100; 165 np->full_duplex = 1; 166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 || 167 strcmp (media[card_idx], "3") == 0) { 168 np->speed = 100; 169 np->full_duplex = 0; 170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || 171 strcmp (media[card_idx], "2") == 0) { 172 np->speed = 10; 173 np->full_duplex = 1; 174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || 175 strcmp (media[card_idx], "1") == 0) { 176 np->speed = 10; 177 np->full_duplex = 0; 178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 || 179 strcmp (media[card_idx], "6") == 0) { 180 np->speed=1000; 181 np->full_duplex=1; 182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 || 183 strcmp (media[card_idx], "5") == 0) { 184 np->speed = 1000; 185 np->full_duplex = 0; 186 } else { 187 np->an_enable = 1; 188 } 189 } 190 if (jumbo[card_idx] != 0) { 191 np->jumbo = 1; 192 dev->mtu = MAX_JUMBO; 193 } else { 194 np->jumbo = 0; 195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE) 196 dev->mtu = mtu[card_idx]; 197 } 198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ? 199 vlan[card_idx] : 0; 200 if (rx_coalesce > 0 && rx_timeout > 0) { 201 np->rx_coalesce = rx_coalesce; 202 np->rx_timeout = rx_timeout; 203 np->coalesce = 1; 204 } 205 np->tx_flow = (tx_flow == 0) ? 0 : 1; 206 np->rx_flow = (rx_flow == 0) ? 0 : 1; 207 208 if (tx_coalesce < 1) 209 tx_coalesce = 1; 210 else if (tx_coalesce > TX_RING_SIZE-1) 211 tx_coalesce = TX_RING_SIZE - 1; 212 } 213 dev->netdev_ops = &netdev_ops; 214 dev->watchdog_timeo = TX_TIMEOUT; 215 dev->ethtool_ops = ðtool_ops; 216#if 0 217 dev->features = NETIF_F_IP_CSUM; 218#endif 219 /* MTU range: 68 - 1536 or 8000 */ 220 dev->min_mtu = ETH_MIN_MTU; 221 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE; 222 223 pci_set_drvdata (pdev, dev); 224 225 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma, 226 GFP_KERNEL); 227 if (!ring_space) 228 goto err_out_iounmap; 229 np->tx_ring = ring_space; 230 np->tx_ring_dma = ring_dma; 231 232 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma, 233 GFP_KERNEL); 234 if (!ring_space) 235 goto err_out_unmap_tx; 236 np->rx_ring = ring_space; 237 np->rx_ring_dma = ring_dma; 238 239 /* Parse eeprom data */ 240 parse_eeprom (dev); 241 242 /* Find PHY address */ 243 err = find_miiphy (dev); 244 if (err) 245 goto err_out_unmap_rx; 246 247 /* Fiber device? */ 248 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0; 249 np->link_status = 0; 250 /* Set media and reset PHY */ 251 if (np->phy_media) { 252 /* default Auto-Negotiation for fiber deivices */ 253 if (np->an_enable == 2) { 254 np->an_enable = 1; 255 } 256 } else { 257 /* Auto-Negotiation is mandatory for 1000BASE-T, 258 IEEE 802.3ab Annex 28D page 14 */ 259 if (np->speed == 1000) 260 np->an_enable = 1; 261 } 262 263 err = register_netdev (dev); 264 if (err) 265 goto err_out_unmap_rx; 266 267 card_idx++; 268 269 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n", 270 dev->name, np->name, dev->dev_addr, irq); 271 if (tx_coalesce > 1) 272 printk(KERN_INFO "tx_coalesce:\t%d packets\n", 273 tx_coalesce); 274 if (np->coalesce) 275 printk(KERN_INFO 276 "rx_coalesce:\t%d packets\n" 277 "rx_timeout: \t%d ns\n", 278 np->rx_coalesce, np->rx_timeout*640); 279 if (np->vlan) 280 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan); 281 return 0; 282 283err_out_unmap_rx: 284 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, 285 np->rx_ring_dma); 286err_out_unmap_tx: 287 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, 288 np->tx_ring_dma); 289err_out_iounmap: 290#ifdef MEM_MAPPING 291 pci_iounmap(pdev, np->ioaddr); 292#endif 293 pci_iounmap(pdev, np->eeprom_addr); 294err_out_dev: 295 free_netdev (dev); 296err_out_res: 297 pci_release_regions (pdev); 298err_out_disable: 299 pci_disable_device (pdev); 300 return err; 301} 302 303static int 304find_miiphy (struct net_device *dev) 305{ 306 struct netdev_private *np = netdev_priv(dev); 307 int i, phy_found = 0; 308 309 np->phy_addr = 1; 310 311 for (i = 31; i >= 0; i--) { 312 int mii_status = mii_read (dev, i, 1); 313 if (mii_status != 0xffff && mii_status != 0x0000) { 314 np->phy_addr = i; 315 phy_found++; 316 } 317 } 318 if (!phy_found) { 319 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name); 320 return -ENODEV; 321 } 322 return 0; 323} 324 325static int 326parse_eeprom (struct net_device *dev) 327{ 328 struct netdev_private *np = netdev_priv(dev); 329 void __iomem *ioaddr = np->ioaddr; 330 int i, j; 331 u8 sromdata[256]; 332 u8 *psib; 333 u32 crc; 334 PSROM_t psrom = (PSROM_t) sromdata; 335 336 int cid, next; 337 338 for (i = 0; i < 128; i++) 339 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i)); 340 341 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */ 342 /* Check CRC */ 343 crc = ~ether_crc_le (256 - 4, sromdata); 344 if (psrom->crc != cpu_to_le32(crc)) { 345 printk (KERN_ERR "%s: EEPROM data CRC error.\n", 346 dev->name); 347 return -1; 348 } 349 } 350 351 /* Set MAC address */ 352 eth_hw_addr_set(dev, psrom->mac_addr); 353 354 if (np->chip_id == CHIP_IP1000A) { 355 np->led_mode = psrom->led_mode; 356 return 0; 357 } 358 359 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) { 360 return 0; 361 } 362 363 /* Parse Software Information Block */ 364 i = 0x30; 365 psib = (u8 *) sromdata; 366 do { 367 cid = psib[i++]; 368 next = psib[i++]; 369 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) { 370 printk (KERN_ERR "Cell data error\n"); 371 return -1; 372 } 373 switch (cid) { 374 case 0: /* Format version */ 375 break; 376 case 1: /* End of cell */ 377 return 0; 378 case 2: /* Duplex Polarity */ 379 np->duplex_polarity = psib[i]; 380 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]); 381 break; 382 case 3: /* Wake Polarity */ 383 np->wake_polarity = psib[i]; 384 break; 385 case 9: /* Adapter description */ 386 j = (next - i > 255) ? 255 : next - i; 387 memcpy (np->name, &(psib[i]), j); 388 break; 389 case 4: 390 case 5: 391 case 6: 392 case 7: 393 case 8: /* Reversed */ 394 break; 395 default: /* Unknown cell */ 396 return -1; 397 } 398 i = next; 399 } while (1); 400 401 return 0; 402} 403 404static void rio_set_led_mode(struct net_device *dev) 405{ 406 struct netdev_private *np = netdev_priv(dev); 407 void __iomem *ioaddr = np->ioaddr; 408 u32 mode; 409 410 if (np->chip_id != CHIP_IP1000A) 411 return; 412 413 mode = dr32(ASICCtrl); 414 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED); 415 416 if (np->led_mode & 0x01) 417 mode |= IPG_AC_LED_MODE; 418 if (np->led_mode & 0x02) 419 mode |= IPG_AC_LED_MODE_BIT_1; 420 if (np->led_mode & 0x08) 421 mode |= IPG_AC_LED_SPEED; 422 423 dw32(ASICCtrl, mode); 424} 425 426static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) 427{ 428 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); 429} 430 431static void free_list(struct net_device *dev) 432{ 433 struct netdev_private *np = netdev_priv(dev); 434 struct sk_buff *skb; 435 int i; 436 437 /* Free all the skbuffs in the queue. */ 438 for (i = 0; i < RX_RING_SIZE; i++) { 439 skb = np->rx_skbuff[i]; 440 if (skb) { 441 dma_unmap_single(&np->pdev->dev, 442 desc_to_dma(&np->rx_ring[i]), 443 skb->len, DMA_FROM_DEVICE); 444 dev_kfree_skb(skb); 445 np->rx_skbuff[i] = NULL; 446 } 447 np->rx_ring[i].status = 0; 448 np->rx_ring[i].fraginfo = 0; 449 } 450 for (i = 0; i < TX_RING_SIZE; i++) { 451 skb = np->tx_skbuff[i]; 452 if (skb) { 453 dma_unmap_single(&np->pdev->dev, 454 desc_to_dma(&np->tx_ring[i]), 455 skb->len, DMA_TO_DEVICE); 456 dev_kfree_skb(skb); 457 np->tx_skbuff[i] = NULL; 458 } 459 } 460} 461 462static void rio_reset_ring(struct netdev_private *np) 463{ 464 int i; 465 466 np->cur_rx = 0; 467 np->cur_tx = 0; 468 np->old_rx = 0; 469 np->old_tx = 0; 470 471 for (i = 0; i < TX_RING_SIZE; i++) 472 np->tx_ring[i].status = cpu_to_le64(TFDDone); 473 474 for (i = 0; i < RX_RING_SIZE; i++) 475 np->rx_ring[i].status = 0; 476} 477 478 /* allocate and initialize Tx and Rx descriptors */ 479static int alloc_list(struct net_device *dev) 480{ 481 struct netdev_private *np = netdev_priv(dev); 482 int i; 483 484 rio_reset_ring(np); 485 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); 486 487 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ 488 for (i = 0; i < TX_RING_SIZE; i++) { 489 np->tx_skbuff[i] = NULL; 490 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma + 491 ((i + 1) % TX_RING_SIZE) * 492 sizeof(struct netdev_desc)); 493 } 494 495 /* Initialize Rx descriptors & allocate buffers */ 496 for (i = 0; i < RX_RING_SIZE; i++) { 497 /* Allocated fixed size of skbuff */ 498 struct sk_buff *skb; 499 500 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 501 np->rx_skbuff[i] = skb; 502 if (!skb) { 503 free_list(dev); 504 return -ENOMEM; 505 } 506 507 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma + 508 ((i + 1) % RX_RING_SIZE) * 509 sizeof(struct netdev_desc)); 510 /* Rubicon now supports 40 bits of addressing space. */ 511 np->rx_ring[i].fraginfo = 512 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data, 513 np->rx_buf_sz, DMA_FROM_DEVICE)); 514 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); 515 } 516 517 return 0; 518} 519 520static void rio_hw_init(struct net_device *dev) 521{ 522 struct netdev_private *np = netdev_priv(dev); 523 void __iomem *ioaddr = np->ioaddr; 524 int i; 525 u16 macctrl; 526 527 /* Reset all logic functions */ 528 dw16(ASICCtrl + 2, 529 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset); 530 mdelay(10); 531 532 rio_set_led_mode(dev); 533 534 /* DebugCtrl bit 4, 5, 9 must set */ 535 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230); 536 537 if (np->chip_id == CHIP_IP1000A && 538 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) { 539 /* PHY magic taken from ipg driver, undocumented registers */ 540 mii_write(dev, np->phy_addr, 31, 0x0001); 541 mii_write(dev, np->phy_addr, 27, 0x01e0); 542 mii_write(dev, np->phy_addr, 31, 0x0002); 543 mii_write(dev, np->phy_addr, 27, 0xeb8e); 544 mii_write(dev, np->phy_addr, 31, 0x0000); 545 mii_write(dev, np->phy_addr, 30, 0x005e); 546 /* advertise 1000BASE-T half & full duplex, prefer MASTER */ 547 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700); 548 } 549 550 if (np->phy_media) 551 mii_set_media_pcs(dev); 552 else 553 mii_set_media(dev); 554 555 /* Jumbo frame */ 556 if (np->jumbo != 0) 557 dw16(MaxFrameSize, MAX_JUMBO+14); 558 559 /* Set RFDListPtr */ 560 dw32(RFDListPtr0, np->rx_ring_dma); 561 dw32(RFDListPtr1, 0); 562 563 /* Set station address */ 564 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works 565 * too. However, it doesn't work on IP1000A so we use 16-bit access. 566 */ 567 for (i = 0; i < 3; i++) 568 dw16(StationAddr0 + 2 * i, 569 cpu_to_le16(((const u16 *)dev->dev_addr)[i])); 570 571 set_multicast (dev); 572 if (np->coalesce) { 573 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16); 574 } 575 /* Set RIO to poll every N*320nsec. */ 576 dw8(RxDMAPollPeriod, 0x20); 577 dw8(TxDMAPollPeriod, 0xff); 578 dw8(RxDMABurstThresh, 0x30); 579 dw8(RxDMAUrgentThresh, 0x30); 580 dw32(RmonStatMask, 0x0007ffff); 581 /* clear statistics */ 582 clear_stats (dev); 583 584 /* VLAN supported */ 585 if (np->vlan) { 586 /* priority field in RxDMAIntCtrl */ 587 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10); 588 /* VLANId */ 589 dw16(VLANId, np->vlan); 590 /* Length/Type should be 0x8100 */ 591 dw32(VLANTag, 0x8100 << 16 | np->vlan); 592 /* Enable AutoVLANuntagging, but disable AutoVLANtagging. 593 VLAN information tagged by TFC' VID, CFI fields. */ 594 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging); 595 } 596 597 /* Start Tx/Rx */ 598 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable); 599 600 macctrl = 0; 601 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 602 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 603 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; 604 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; 605 dw16(MACCtrl, macctrl); 606} 607 608static void rio_hw_stop(struct net_device *dev) 609{ 610 struct netdev_private *np = netdev_priv(dev); 611 void __iomem *ioaddr = np->ioaddr; 612 613 /* Disable interrupts */ 614 dw16(IntEnable, 0); 615 616 /* Stop Tx and Rx logics */ 617 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable); 618} 619 620static int rio_open(struct net_device *dev) 621{ 622 struct netdev_private *np = netdev_priv(dev); 623 const int irq = np->pdev->irq; 624 int i; 625 626 i = alloc_list(dev); 627 if (i) 628 return i; 629 630 rio_hw_init(dev); 631 632 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev); 633 if (i) { 634 rio_hw_stop(dev); 635 free_list(dev); 636 return i; 637 } 638 639 timer_setup(&np->timer, rio_timer, 0); 640 np->timer.expires = jiffies + 1 * HZ; 641 add_timer(&np->timer); 642 643 netif_start_queue (dev); 644 645 dl2k_enable_int(np); 646 return 0; 647} 648 649static void 650rio_timer (struct timer_list *t) 651{ 652 struct netdev_private *np = from_timer(np, t, timer); 653 struct net_device *dev = pci_get_drvdata(np->pdev); 654 unsigned int entry; 655 int next_tick = 1*HZ; 656 unsigned long flags; 657 658 spin_lock_irqsave(&np->rx_lock, flags); 659 /* Recover rx ring exhausted error */ 660 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) { 661 printk(KERN_INFO "Try to recover rx ring exhausted...\n"); 662 /* Re-allocate skbuffs to fill the descriptor ring */ 663 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) { 664 struct sk_buff *skb; 665 entry = np->old_rx % RX_RING_SIZE; 666 /* Dropped packets don't need to re-allocate */ 667 if (np->rx_skbuff[entry] == NULL) { 668 skb = netdev_alloc_skb_ip_align(dev, 669 np->rx_buf_sz); 670 if (skb == NULL) { 671 np->rx_ring[entry].fraginfo = 0; 672 printk (KERN_INFO 673 "%s: Still unable to re-allocate Rx skbuff.#%d\n", 674 dev->name, entry); 675 break; 676 } 677 np->rx_skbuff[entry] = skb; 678 np->rx_ring[entry].fraginfo = 679 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data, 680 np->rx_buf_sz, DMA_FROM_DEVICE)); 681 } 682 np->rx_ring[entry].fraginfo |= 683 cpu_to_le64((u64)np->rx_buf_sz << 48); 684 np->rx_ring[entry].status = 0; 685 } /* end for */ 686 } /* end if */ 687 spin_unlock_irqrestore (&np->rx_lock, flags); 688 np->timer.expires = jiffies + next_tick; 689 add_timer(&np->timer); 690} 691 692static void 693rio_tx_timeout (struct net_device *dev, unsigned int txqueue) 694{ 695 struct netdev_private *np = netdev_priv(dev); 696 void __iomem *ioaddr = np->ioaddr; 697 698 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n", 699 dev->name, dr32(TxStatus)); 700 rio_free_tx(dev, 0); 701 dev->if_port = 0; 702 netif_trans_update(dev); /* prevent tx timeout */ 703} 704 705static netdev_tx_t 706start_xmit (struct sk_buff *skb, struct net_device *dev) 707{ 708 struct netdev_private *np = netdev_priv(dev); 709 void __iomem *ioaddr = np->ioaddr; 710 struct netdev_desc *txdesc; 711 unsigned entry; 712 u64 tfc_vlan_tag = 0; 713 714 if (np->link_status == 0) { /* Link Down */ 715 dev_kfree_skb(skb); 716 return NETDEV_TX_OK; 717 } 718 entry = np->cur_tx % TX_RING_SIZE; 719 np->tx_skbuff[entry] = skb; 720 txdesc = &np->tx_ring[entry]; 721 722#if 0 723 if (skb->ip_summed == CHECKSUM_PARTIAL) { 724 txdesc->status |= 725 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable | 726 IPChecksumEnable); 727 } 728#endif 729 if (np->vlan) { 730 tfc_vlan_tag = VLANTagInsert | 731 ((u64)np->vlan << 32) | 732 ((u64)skb->priority << 45); 733 } 734 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data, 735 skb->len, DMA_TO_DEVICE)); 736 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48); 737 738 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode 739 * Work around: Always use 1 descriptor in 10Mbps mode */ 740 if (entry % np->tx_coalesce == 0 || np->speed == 10) 741 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 742 WordAlignDisable | 743 TxDMAIndicate | 744 (1 << FragCountShift)); 745 else 746 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 747 WordAlignDisable | 748 (1 << FragCountShift)); 749 750 /* TxDMAPollNow */ 751 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000); 752 /* Schedule ISR */ 753 dw32(CountDown, 10000); 754 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE; 755 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 756 < TX_QUEUE_LEN - 1 && np->speed != 10) { 757 /* do nothing */ 758 } else if (!netif_queue_stopped(dev)) { 759 netif_stop_queue (dev); 760 } 761 762 /* The first TFDListPtr */ 763 if (!dr32(TFDListPtr0)) { 764 dw32(TFDListPtr0, np->tx_ring_dma + 765 entry * sizeof (struct netdev_desc)); 766 dw32(TFDListPtr1, 0); 767 } 768 769 return NETDEV_TX_OK; 770} 771 772static irqreturn_t 773rio_interrupt (int irq, void *dev_instance) 774{ 775 struct net_device *dev = dev_instance; 776 struct netdev_private *np = netdev_priv(dev); 777 void __iomem *ioaddr = np->ioaddr; 778 unsigned int_status; 779 int cnt = max_intrloop; 780 int handled = 0; 781 782 while (1) { 783 int_status = dr16(IntStatus); 784 dw16(IntStatus, int_status); 785 int_status &= DEFAULT_INTR; 786 if (int_status == 0 || --cnt < 0) 787 break; 788 handled = 1; 789 /* Processing received packets */ 790 if (int_status & RxDMAComplete) 791 receive_packet (dev); 792 /* TxDMAComplete interrupt */ 793 if ((int_status & (TxDMAComplete|IntRequested))) { 794 int tx_status; 795 tx_status = dr32(TxStatus); 796 if (tx_status & 0x01) 797 tx_error (dev, tx_status); 798 /* Free used tx skbuffs */ 799 rio_free_tx (dev, 1); 800 } 801 802 /* Handle uncommon events */ 803 if (int_status & 804 (HostError | LinkEvent | UpdateStats)) 805 rio_error (dev, int_status); 806 } 807 if (np->cur_tx != np->old_tx) 808 dw32(CountDown, 100); 809 return IRQ_RETVAL(handled); 810} 811 812static void 813rio_free_tx (struct net_device *dev, int irq) 814{ 815 struct netdev_private *np = netdev_priv(dev); 816 int entry = np->old_tx % TX_RING_SIZE; 817 unsigned long flag = 0; 818 819 if (irq) 820 spin_lock(&np->tx_lock); 821 else 822 spin_lock_irqsave(&np->tx_lock, flag); 823 824 /* Free used tx skbuffs */ 825 while (entry != np->cur_tx) { 826 struct sk_buff *skb; 827 828 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone))) 829 break; 830 skb = np->tx_skbuff[entry]; 831 dma_unmap_single(&np->pdev->dev, 832 desc_to_dma(&np->tx_ring[entry]), skb->len, 833 DMA_TO_DEVICE); 834 if (irq) 835 dev_consume_skb_irq(skb); 836 else 837 dev_kfree_skb(skb); 838 839 np->tx_skbuff[entry] = NULL; 840 entry = (entry + 1) % TX_RING_SIZE; 841 } 842 if (irq) 843 spin_unlock(&np->tx_lock); 844 else 845 spin_unlock_irqrestore(&np->tx_lock, flag); 846 np->old_tx = entry; 847 848 /* If the ring is no longer full, clear tx_full and 849 call netif_wake_queue() */ 850 851 if (netif_queue_stopped(dev) && 852 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 853 < TX_QUEUE_LEN - 1 || np->speed == 10)) { 854 netif_wake_queue (dev); 855 } 856} 857 858static void 859tx_error (struct net_device *dev, int tx_status) 860{ 861 struct netdev_private *np = netdev_priv(dev); 862 void __iomem *ioaddr = np->ioaddr; 863 int frame_id; 864 int i; 865 866 frame_id = (tx_status & 0xffff0000); 867 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n", 868 dev->name, tx_status, frame_id); 869 dev->stats.tx_errors++; 870 /* Ttransmit Underrun */ 871 if (tx_status & 0x10) { 872 dev->stats.tx_fifo_errors++; 873 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10); 874 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */ 875 dw16(ASICCtrl + 2, 876 TxReset | DMAReset | FIFOReset | NetworkReset); 877 /* Wait for ResetBusy bit clear */ 878 for (i = 50; i > 0; i--) { 879 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 880 break; 881 mdelay (1); 882 } 883 rio_set_led_mode(dev); 884 rio_free_tx (dev, 1); 885 /* Reset TFDListPtr */ 886 dw32(TFDListPtr0, np->tx_ring_dma + 887 np->old_tx * sizeof (struct netdev_desc)); 888 dw32(TFDListPtr1, 0); 889 890 /* Let TxStartThresh stay default value */ 891 } 892 /* Late Collision */ 893 if (tx_status & 0x04) { 894 dev->stats.tx_fifo_errors++; 895 /* TxReset and clear FIFO */ 896 dw16(ASICCtrl + 2, TxReset | FIFOReset); 897 /* Wait reset done */ 898 for (i = 50; i > 0; i--) { 899 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 900 break; 901 mdelay (1); 902 } 903 rio_set_led_mode(dev); 904 /* Let TxStartThresh stay default value */ 905 } 906 /* Maximum Collisions */ 907 if (tx_status & 0x08) 908 dev->stats.collisions++; 909 /* Restart the Tx */ 910 dw32(MACCtrl, dr16(MACCtrl) | TxEnable); 911} 912 913static int 914receive_packet (struct net_device *dev) 915{ 916 struct netdev_private *np = netdev_priv(dev); 917 int entry = np->cur_rx % RX_RING_SIZE; 918 int cnt = 30; 919 920 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */ 921 while (1) { 922 struct netdev_desc *desc = &np->rx_ring[entry]; 923 int pkt_len; 924 u64 frame_status; 925 926 if (!(desc->status & cpu_to_le64(RFDDone)) || 927 !(desc->status & cpu_to_le64(FrameStart)) || 928 !(desc->status & cpu_to_le64(FrameEnd))) 929 break; 930 931 /* Chip omits the CRC. */ 932 frame_status = le64_to_cpu(desc->status); 933 pkt_len = frame_status & 0xffff; 934 if (--cnt < 0) 935 break; 936 /* Update rx error statistics, drop packet. */ 937 if (frame_status & RFS_Errors) { 938 dev->stats.rx_errors++; 939 if (frame_status & (RxRuntFrame | RxLengthError)) 940 dev->stats.rx_length_errors++; 941 if (frame_status & RxFCSError) 942 dev->stats.rx_crc_errors++; 943 if (frame_status & RxAlignmentError && np->speed != 1000) 944 dev->stats.rx_frame_errors++; 945 if (frame_status & RxFIFOOverrun) 946 dev->stats.rx_fifo_errors++; 947 } else { 948 struct sk_buff *skb; 949 950 /* Small skbuffs for short packets */ 951 if (pkt_len > copy_thresh) { 952 dma_unmap_single(&np->pdev->dev, 953 desc_to_dma(desc), 954 np->rx_buf_sz, 955 DMA_FROM_DEVICE); 956 skb_put (skb = np->rx_skbuff[entry], pkt_len); 957 np->rx_skbuff[entry] = NULL; 958 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) { 959 dma_sync_single_for_cpu(&np->pdev->dev, 960 desc_to_dma(desc), 961 np->rx_buf_sz, 962 DMA_FROM_DEVICE); 963 skb_copy_to_linear_data (skb, 964 np->rx_skbuff[entry]->data, 965 pkt_len); 966 skb_put (skb, pkt_len); 967 dma_sync_single_for_device(&np->pdev->dev, 968 desc_to_dma(desc), 969 np->rx_buf_sz, 970 DMA_FROM_DEVICE); 971 } 972 skb->protocol = eth_type_trans (skb, dev); 973#if 0 974 /* Checksum done by hw, but csum value unavailable. */ 975 if (np->pdev->pci_rev_id >= 0x0c && 976 !(frame_status & (TCPError | UDPError | IPError))) { 977 skb->ip_summed = CHECKSUM_UNNECESSARY; 978 } 979#endif 980 netif_rx (skb); 981 } 982 entry = (entry + 1) % RX_RING_SIZE; 983 } 984 spin_lock(&np->rx_lock); 985 np->cur_rx = entry; 986 /* Re-allocate skbuffs to fill the descriptor ring */ 987 entry = np->old_rx; 988 while (entry != np->cur_rx) { 989 struct sk_buff *skb; 990 /* Dropped packets don't need to re-allocate */ 991 if (np->rx_skbuff[entry] == NULL) { 992 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 993 if (skb == NULL) { 994 np->rx_ring[entry].fraginfo = 0; 995 printk (KERN_INFO 996 "%s: receive_packet: " 997 "Unable to re-allocate Rx skbuff.#%d\n", 998 dev->name, entry); 999 break; 1000 } 1001 np->rx_skbuff[entry] = skb; 1002 np->rx_ring[entry].fraginfo = 1003 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data, 1004 np->rx_buf_sz, DMA_FROM_DEVICE)); 1005 } 1006 np->rx_ring[entry].fraginfo |= 1007 cpu_to_le64((u64)np->rx_buf_sz << 48); 1008 np->rx_ring[entry].status = 0; 1009 entry = (entry + 1) % RX_RING_SIZE; 1010 } 1011 np->old_rx = entry; 1012 spin_unlock(&np->rx_lock); 1013 return 0; 1014} 1015 1016static void 1017rio_error (struct net_device *dev, int int_status) 1018{ 1019 struct netdev_private *np = netdev_priv(dev); 1020 void __iomem *ioaddr = np->ioaddr; 1021 u16 macctrl; 1022 1023 /* Link change event */ 1024 if (int_status & LinkEvent) { 1025 if (mii_wait_link (dev, 10) == 0) { 1026 printk (KERN_INFO "%s: Link up\n", dev->name); 1027 if (np->phy_media) 1028 mii_get_media_pcs (dev); 1029 else 1030 mii_get_media (dev); 1031 if (np->speed == 1000) 1032 np->tx_coalesce = tx_coalesce; 1033 else 1034 np->tx_coalesce = 1; 1035 macctrl = 0; 1036 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 1037 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 1038 macctrl |= (np->tx_flow) ? 1039 TxFlowControlEnable : 0; 1040 macctrl |= (np->rx_flow) ? 1041 RxFlowControlEnable : 0; 1042 dw16(MACCtrl, macctrl); 1043 np->link_status = 1; 1044 netif_carrier_on(dev); 1045 } else { 1046 printk (KERN_INFO "%s: Link off\n", dev->name); 1047 np->link_status = 0; 1048 netif_carrier_off(dev); 1049 } 1050 } 1051 1052 /* UpdateStats statistics registers */ 1053 if (int_status & UpdateStats) { 1054 get_stats (dev); 1055 } 1056 1057 /* PCI Error, a catastronphic error related to the bus interface 1058 occurs, set GlobalReset and HostReset to reset. */ 1059 if (int_status & HostError) { 1060 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n", 1061 dev->name, int_status); 1062 dw16(ASICCtrl + 2, GlobalReset | HostReset); 1063 mdelay (500); 1064 rio_set_led_mode(dev); 1065 } 1066} 1067 1068static struct net_device_stats * 1069get_stats (struct net_device *dev) 1070{ 1071 struct netdev_private *np = netdev_priv(dev); 1072 void __iomem *ioaddr = np->ioaddr; 1073#ifdef MEM_MAPPING 1074 int i; 1075#endif 1076 unsigned int stat_reg; 1077 1078 /* All statistics registers need to be acknowledged, 1079 else statistic overflow could cause problems */ 1080 1081 dev->stats.rx_packets += dr32(FramesRcvOk); 1082 dev->stats.tx_packets += dr32(FramesXmtOk); 1083 dev->stats.rx_bytes += dr32(OctetRcvOk); 1084 dev->stats.tx_bytes += dr32(OctetXmtOk); 1085 1086 dev->stats.multicast = dr32(McstFramesRcvdOk); 1087 dev->stats.collisions += dr32(SingleColFrames) 1088 + dr32(MultiColFrames); 1089 1090 /* detailed tx errors */ 1091 stat_reg = dr16(FramesAbortXSColls); 1092 dev->stats.tx_aborted_errors += stat_reg; 1093 dev->stats.tx_errors += stat_reg; 1094 1095 stat_reg = dr16(CarrierSenseErrors); 1096 dev->stats.tx_carrier_errors += stat_reg; 1097 dev->stats.tx_errors += stat_reg; 1098 1099 /* Clear all other statistic register. */ 1100 dr32(McstOctetXmtOk); 1101 dr16(BcstFramesXmtdOk); 1102 dr32(McstFramesXmtdOk); 1103 dr16(BcstFramesRcvdOk); 1104 dr16(MacControlFramesRcvd); 1105 dr16(FrameTooLongErrors); 1106 dr16(InRangeLengthErrors); 1107 dr16(FramesCheckSeqErrors); 1108 dr16(FramesLostRxErrors); 1109 dr32(McstOctetXmtOk); 1110 dr32(BcstOctetXmtOk); 1111 dr32(McstFramesXmtdOk); 1112 dr32(FramesWDeferredXmt); 1113 dr32(LateCollisions); 1114 dr16(BcstFramesXmtdOk); 1115 dr16(MacControlFramesXmtd); 1116 dr16(FramesWEXDeferal); 1117 1118#ifdef MEM_MAPPING 1119 for (i = 0x100; i <= 0x150; i += 4) 1120 dr32(i); 1121#endif 1122 dr16(TxJumboFrames); 1123 dr16(RxJumboFrames); 1124 dr16(TCPCheckSumErrors); 1125 dr16(UDPCheckSumErrors); 1126 dr16(IPCheckSumErrors); 1127 return &dev->stats; 1128} 1129 1130static int 1131clear_stats (struct net_device *dev) 1132{ 1133 struct netdev_private *np = netdev_priv(dev); 1134 void __iomem *ioaddr = np->ioaddr; 1135#ifdef MEM_MAPPING 1136 int i; 1137#endif 1138 1139 /* All statistics registers need to be acknowledged, 1140 else statistic overflow could cause problems */ 1141 dr32(FramesRcvOk); 1142 dr32(FramesXmtOk); 1143 dr32(OctetRcvOk); 1144 dr32(OctetXmtOk); 1145 1146 dr32(McstFramesRcvdOk); 1147 dr32(SingleColFrames); 1148 dr32(MultiColFrames); 1149 dr32(LateCollisions); 1150 /* detailed rx errors */ 1151 dr16(FrameTooLongErrors); 1152 dr16(InRangeLengthErrors); 1153 dr16(FramesCheckSeqErrors); 1154 dr16(FramesLostRxErrors); 1155 1156 /* detailed tx errors */ 1157 dr16(FramesAbortXSColls); 1158 dr16(CarrierSenseErrors); 1159 1160 /* Clear all other statistic register. */ 1161 dr32(McstOctetXmtOk); 1162 dr16(BcstFramesXmtdOk); 1163 dr32(McstFramesXmtdOk); 1164 dr16(BcstFramesRcvdOk); 1165 dr16(MacControlFramesRcvd); 1166 dr32(McstOctetXmtOk); 1167 dr32(BcstOctetXmtOk); 1168 dr32(McstFramesXmtdOk); 1169 dr32(FramesWDeferredXmt); 1170 dr16(BcstFramesXmtdOk); 1171 dr16(MacControlFramesXmtd); 1172 dr16(FramesWEXDeferal); 1173#ifdef MEM_MAPPING 1174 for (i = 0x100; i <= 0x150; i += 4) 1175 dr32(i); 1176#endif 1177 dr16(TxJumboFrames); 1178 dr16(RxJumboFrames); 1179 dr16(TCPCheckSumErrors); 1180 dr16(UDPCheckSumErrors); 1181 dr16(IPCheckSumErrors); 1182 return 0; 1183} 1184 1185static void 1186set_multicast (struct net_device *dev) 1187{ 1188 struct netdev_private *np = netdev_priv(dev); 1189 void __iomem *ioaddr = np->ioaddr; 1190 u32 hash_table[2]; 1191 u16 rx_mode = 0; 1192 1193 hash_table[0] = hash_table[1] = 0; 1194 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */ 1195 hash_table[1] |= 0x02000000; 1196 if (dev->flags & IFF_PROMISC) { 1197 /* Receive all frames promiscuously. */ 1198 rx_mode = ReceiveAllFrames; 1199 } else if ((dev->flags & IFF_ALLMULTI) || 1200 (netdev_mc_count(dev) > multicast_filter_limit)) { 1201 /* Receive broadcast and multicast frames */ 1202 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast; 1203 } else if (!netdev_mc_empty(dev)) { 1204 struct netdev_hw_addr *ha; 1205 /* Receive broadcast frames and multicast frames filtering 1206 by Hashtable */ 1207 rx_mode = 1208 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast; 1209 netdev_for_each_mc_addr(ha, dev) { 1210 int bit, index = 0; 1211 int crc = ether_crc_le(ETH_ALEN, ha->addr); 1212 /* The inverted high significant 6 bits of CRC are 1213 used as an index to hashtable */ 1214 for (bit = 0; bit < 6; bit++) 1215 if (crc & (1 << (31 - bit))) 1216 index |= (1 << bit); 1217 hash_table[index / 32] |= (1 << (index % 32)); 1218 } 1219 } else { 1220 rx_mode = ReceiveBroadcast | ReceiveUnicast; 1221 } 1222 if (np->vlan) { 1223 /* ReceiveVLANMatch field in ReceiveMode */ 1224 rx_mode |= ReceiveVLANMatch; 1225 } 1226 1227 dw32(HashTable0, hash_table[0]); 1228 dw32(HashTable1, hash_table[1]); 1229 dw16(ReceiveMode, rx_mode); 1230} 1231 1232static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1233{ 1234 struct netdev_private *np = netdev_priv(dev); 1235 1236 strscpy(info->driver, "dl2k", sizeof(info->driver)); 1237 strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); 1238} 1239 1240static int rio_get_link_ksettings(struct net_device *dev, 1241 struct ethtool_link_ksettings *cmd) 1242{ 1243 struct netdev_private *np = netdev_priv(dev); 1244 u32 supported, advertising; 1245 1246 if (np->phy_media) { 1247 /* fiber device */ 1248 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE; 1249 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE; 1250 cmd->base.port = PORT_FIBRE; 1251 } else { 1252 /* copper device */ 1253 supported = SUPPORTED_10baseT_Half | 1254 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half 1255 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | 1256 SUPPORTED_Autoneg | SUPPORTED_MII; 1257 advertising = ADVERTISED_10baseT_Half | 1258 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half | 1259 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full | 1260 ADVERTISED_Autoneg | ADVERTISED_MII; 1261 cmd->base.port = PORT_MII; 1262 } 1263 if (np->link_status) { 1264 cmd->base.speed = np->speed; 1265 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1266 } else { 1267 cmd->base.speed = SPEED_UNKNOWN; 1268 cmd->base.duplex = DUPLEX_UNKNOWN; 1269 } 1270 if (np->an_enable) 1271 cmd->base.autoneg = AUTONEG_ENABLE; 1272 else 1273 cmd->base.autoneg = AUTONEG_DISABLE; 1274 1275 cmd->base.phy_address = np->phy_addr; 1276 1277 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1278 supported); 1279 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1280 advertising); 1281 1282 return 0; 1283} 1284 1285static int rio_set_link_ksettings(struct net_device *dev, 1286 const struct ethtool_link_ksettings *cmd) 1287{ 1288 struct netdev_private *np = netdev_priv(dev); 1289 u32 speed = cmd->base.speed; 1290 u8 duplex = cmd->base.duplex; 1291 1292 netif_carrier_off(dev); 1293 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1294 if (np->an_enable) { 1295 return 0; 1296 } else { 1297 np->an_enable = 1; 1298 mii_set_media(dev); 1299 return 0; 1300 } 1301 } else { 1302 np->an_enable = 0; 1303 if (np->speed == 1000) { 1304 speed = SPEED_100; 1305 duplex = DUPLEX_FULL; 1306 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n"); 1307 } 1308 switch (speed) { 1309 case SPEED_10: 1310 np->speed = 10; 1311 np->full_duplex = (duplex == DUPLEX_FULL); 1312 break; 1313 case SPEED_100: 1314 np->speed = 100; 1315 np->full_duplex = (duplex == DUPLEX_FULL); 1316 break; 1317 case SPEED_1000: /* not supported */ 1318 default: 1319 return -EINVAL; 1320 } 1321 mii_set_media(dev); 1322 } 1323 return 0; 1324} 1325 1326static u32 rio_get_link(struct net_device *dev) 1327{ 1328 struct netdev_private *np = netdev_priv(dev); 1329 return np->link_status; 1330} 1331 1332static const struct ethtool_ops ethtool_ops = { 1333 .get_drvinfo = rio_get_drvinfo, 1334 .get_link = rio_get_link, 1335 .get_link_ksettings = rio_get_link_ksettings, 1336 .set_link_ksettings = rio_set_link_ksettings, 1337}; 1338 1339static int 1340rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 1341{ 1342 int phy_addr; 1343 struct netdev_private *np = netdev_priv(dev); 1344 struct mii_ioctl_data *miidata = if_mii(rq); 1345 1346 phy_addr = np->phy_addr; 1347 switch (cmd) { 1348 case SIOCGMIIPHY: 1349 miidata->phy_id = phy_addr; 1350 break; 1351 case SIOCGMIIREG: 1352 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num); 1353 break; 1354 case SIOCSMIIREG: 1355 if (!capable(CAP_NET_ADMIN)) 1356 return -EPERM; 1357 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in); 1358 break; 1359 default: 1360 return -EOPNOTSUPP; 1361 } 1362 return 0; 1363} 1364 1365#define EEP_READ 0x0200 1366#define EEP_BUSY 0x8000 1367/* Read the EEPROM word */ 1368/* We use I/O instruction to read/write eeprom to avoid fail on some machines */ 1369static int read_eeprom(struct netdev_private *np, int eep_addr) 1370{ 1371 void __iomem *ioaddr = np->eeprom_addr; 1372 int i = 1000; 1373 1374 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff)); 1375 while (i-- > 0) { 1376 if (!(dr16(EepromCtrl) & EEP_BUSY)) 1377 return dr16(EepromData); 1378 } 1379 return 0; 1380} 1381 1382enum phy_ctrl_bits { 1383 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04, 1384 MII_DUPLEX = 0x08, 1385}; 1386 1387#define mii_delay() dr8(PhyCtrl) 1388static void 1389mii_sendbit (struct net_device *dev, u32 data) 1390{ 1391 struct netdev_private *np = netdev_priv(dev); 1392 void __iomem *ioaddr = np->ioaddr; 1393 1394 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE; 1395 dw8(PhyCtrl, data); 1396 mii_delay (); 1397 dw8(PhyCtrl, data | MII_CLK); 1398 mii_delay (); 1399} 1400 1401static int 1402mii_getbit (struct net_device *dev) 1403{ 1404 struct netdev_private *np = netdev_priv(dev); 1405 void __iomem *ioaddr = np->ioaddr; 1406 u8 data; 1407 1408 data = (dr8(PhyCtrl) & 0xf8) | MII_READ; 1409 dw8(PhyCtrl, data); 1410 mii_delay (); 1411 dw8(PhyCtrl, data | MII_CLK); 1412 mii_delay (); 1413 return (dr8(PhyCtrl) >> 1) & 1; 1414} 1415 1416static void 1417mii_send_bits (struct net_device *dev, u32 data, int len) 1418{ 1419 int i; 1420 1421 for (i = len - 1; i >= 0; i--) { 1422 mii_sendbit (dev, data & (1 << i)); 1423 } 1424} 1425 1426static int 1427mii_read (struct net_device *dev, int phy_addr, int reg_num) 1428{ 1429 u32 cmd; 1430 int i; 1431 u32 retval = 0; 1432 1433 /* Preamble */ 1434 mii_send_bits (dev, 0xffffffff, 32); 1435 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1436 /* ST,OP = 0110'b for read operation */ 1437 cmd = (0x06 << 10 | phy_addr << 5 | reg_num); 1438 mii_send_bits (dev, cmd, 14); 1439 /* Turnaround */ 1440 if (mii_getbit (dev)) 1441 goto err_out; 1442 /* Read data */ 1443 for (i = 0; i < 16; i++) { 1444 retval |= mii_getbit (dev); 1445 retval <<= 1; 1446 } 1447 /* End cycle */ 1448 mii_getbit (dev); 1449 return (retval >> 1) & 0xffff; 1450 1451 err_out: 1452 return 0; 1453} 1454static int 1455mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data) 1456{ 1457 u32 cmd; 1458 1459 /* Preamble */ 1460 mii_send_bits (dev, 0xffffffff, 32); 1461 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1462 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1463 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; 1464 mii_send_bits (dev, cmd, 32); 1465 /* End cycle */ 1466 mii_getbit (dev); 1467 return 0; 1468} 1469static int 1470mii_wait_link (struct net_device *dev, int wait) 1471{ 1472 __u16 bmsr; 1473 int phy_addr; 1474 struct netdev_private *np; 1475 1476 np = netdev_priv(dev); 1477 phy_addr = np->phy_addr; 1478 1479 do { 1480 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1481 if (bmsr & BMSR_LSTATUS) 1482 return 0; 1483 mdelay (1); 1484 } while (--wait > 0); 1485 return -1; 1486} 1487static int 1488mii_get_media (struct net_device *dev) 1489{ 1490 __u16 negotiate; 1491 __u16 bmsr; 1492 __u16 mscr; 1493 __u16 mssr; 1494 int phy_addr; 1495 struct netdev_private *np; 1496 1497 np = netdev_priv(dev); 1498 phy_addr = np->phy_addr; 1499 1500 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1501 if (np->an_enable) { 1502 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1503 /* Auto-Negotiation not completed */ 1504 return -1; 1505 } 1506 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) & 1507 mii_read (dev, phy_addr, MII_LPA); 1508 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1509 mssr = mii_read (dev, phy_addr, MII_STAT1000); 1510 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { 1511 np->speed = 1000; 1512 np->full_duplex = 1; 1513 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1514 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { 1515 np->speed = 1000; 1516 np->full_duplex = 0; 1517 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); 1518 } else if (negotiate & ADVERTISE_100FULL) { 1519 np->speed = 100; 1520 np->full_duplex = 1; 1521 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); 1522 } else if (negotiate & ADVERTISE_100HALF) { 1523 np->speed = 100; 1524 np->full_duplex = 0; 1525 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); 1526 } else if (negotiate & ADVERTISE_10FULL) { 1527 np->speed = 10; 1528 np->full_duplex = 1; 1529 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); 1530 } else if (negotiate & ADVERTISE_10HALF) { 1531 np->speed = 10; 1532 np->full_duplex = 0; 1533 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); 1534 } 1535 if (negotiate & ADVERTISE_PAUSE_CAP) { 1536 np->tx_flow &= 1; 1537 np->rx_flow &= 1; 1538 } else if (negotiate & ADVERTISE_PAUSE_ASYM) { 1539 np->tx_flow = 0; 1540 np->rx_flow &= 1; 1541 } 1542 /* else tx_flow, rx_flow = user select */ 1543 } else { 1544 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1545 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) { 1546 case BMCR_SPEED1000: 1547 printk (KERN_INFO "Operating at 1000 Mbps, "); 1548 break; 1549 case BMCR_SPEED100: 1550 printk (KERN_INFO "Operating at 100 Mbps, "); 1551 break; 1552 case 0: 1553 printk (KERN_INFO "Operating at 10 Mbps, "); 1554 } 1555 if (bmcr & BMCR_FULLDPLX) { 1556 printk (KERN_CONT "Full duplex\n"); 1557 } else { 1558 printk (KERN_CONT "Half duplex\n"); 1559 } 1560 } 1561 if (np->tx_flow) 1562 printk(KERN_INFO "Enable Tx Flow Control\n"); 1563 else 1564 printk(KERN_INFO "Disable Tx Flow Control\n"); 1565 if (np->rx_flow) 1566 printk(KERN_INFO "Enable Rx Flow Control\n"); 1567 else 1568 printk(KERN_INFO "Disable Rx Flow Control\n"); 1569 1570 return 0; 1571} 1572 1573static int 1574mii_set_media (struct net_device *dev) 1575{ 1576 __u16 pscr; 1577 __u16 bmcr; 1578 __u16 bmsr; 1579 __u16 anar; 1580 int phy_addr; 1581 struct netdev_private *np; 1582 np = netdev_priv(dev); 1583 phy_addr = np->phy_addr; 1584 1585 /* Does user set speed? */ 1586 if (np->an_enable) { 1587 /* Advertise capabilities */ 1588 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1589 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1590 ~(ADVERTISE_100FULL | ADVERTISE_10FULL | 1591 ADVERTISE_100HALF | ADVERTISE_10HALF | 1592 ADVERTISE_100BASE4); 1593 if (bmsr & BMSR_100FULL) 1594 anar |= ADVERTISE_100FULL; 1595 if (bmsr & BMSR_100HALF) 1596 anar |= ADVERTISE_100HALF; 1597 if (bmsr & BMSR_100BASE4) 1598 anar |= ADVERTISE_100BASE4; 1599 if (bmsr & BMSR_10FULL) 1600 anar |= ADVERTISE_10FULL; 1601 if (bmsr & BMSR_10HALF) 1602 anar |= ADVERTISE_10HALF; 1603 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1604 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1605 1606 /* Enable Auto crossover */ 1607 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1608 pscr |= 3 << 5; /* 11'b */ 1609 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1610 1611 /* Soft reset PHY */ 1612 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1613 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1614 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1615 mdelay(1); 1616 } else { 1617 /* Force speed setting */ 1618 /* 1) Disable Auto crossover */ 1619 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1620 pscr &= ~(3 << 5); 1621 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1622 1623 /* 2) PHY Reset */ 1624 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1625 bmcr |= BMCR_RESET; 1626 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1627 1628 /* 3) Power Down */ 1629 bmcr = 0x1940; /* must be 0x1940 */ 1630 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1631 mdelay (100); /* wait a certain time */ 1632 1633 /* 4) Advertise nothing */ 1634 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1635 1636 /* 5) Set media and Power Up */ 1637 bmcr = BMCR_PDOWN; 1638 if (np->speed == 100) { 1639 bmcr |= BMCR_SPEED100; 1640 printk (KERN_INFO "Manual 100 Mbps, "); 1641 } else if (np->speed == 10) { 1642 printk (KERN_INFO "Manual 10 Mbps, "); 1643 } 1644 if (np->full_duplex) { 1645 bmcr |= BMCR_FULLDPLX; 1646 printk (KERN_CONT "Full duplex\n"); 1647 } else { 1648 printk (KERN_CONT "Half duplex\n"); 1649 } 1650#if 0 1651 /* Set 1000BaseT Master/Slave setting */ 1652 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1653 mscr |= MII_MSCR_CFG_ENABLE; 1654 mscr &= ~MII_MSCR_CFG_VALUE = 0; 1655#endif 1656 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1657 mdelay(10); 1658 } 1659 return 0; 1660} 1661 1662static int 1663mii_get_media_pcs (struct net_device *dev) 1664{ 1665 __u16 negotiate; 1666 __u16 bmsr; 1667 int phy_addr; 1668 struct netdev_private *np; 1669 1670 np = netdev_priv(dev); 1671 phy_addr = np->phy_addr; 1672 1673 bmsr = mii_read (dev, phy_addr, PCS_BMSR); 1674 if (np->an_enable) { 1675 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1676 /* Auto-Negotiation not completed */ 1677 return -1; 1678 } 1679 negotiate = mii_read (dev, phy_addr, PCS_ANAR) & 1680 mii_read (dev, phy_addr, PCS_ANLPAR); 1681 np->speed = 1000; 1682 if (negotiate & PCS_ANAR_FULL_DUPLEX) { 1683 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1684 np->full_duplex = 1; 1685 } else { 1686 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); 1687 np->full_duplex = 0; 1688 } 1689 if (negotiate & PCS_ANAR_PAUSE) { 1690 np->tx_flow &= 1; 1691 np->rx_flow &= 1; 1692 } else if (negotiate & PCS_ANAR_ASYMMETRIC) { 1693 np->tx_flow = 0; 1694 np->rx_flow &= 1; 1695 } 1696 /* else tx_flow, rx_flow = user select */ 1697 } else { 1698 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); 1699 printk (KERN_INFO "Operating at 1000 Mbps, "); 1700 if (bmcr & BMCR_FULLDPLX) { 1701 printk (KERN_CONT "Full duplex\n"); 1702 } else { 1703 printk (KERN_CONT "Half duplex\n"); 1704 } 1705 } 1706 if (np->tx_flow) 1707 printk(KERN_INFO "Enable Tx Flow Control\n"); 1708 else 1709 printk(KERN_INFO "Disable Tx Flow Control\n"); 1710 if (np->rx_flow) 1711 printk(KERN_INFO "Enable Rx Flow Control\n"); 1712 else 1713 printk(KERN_INFO "Disable Rx Flow Control\n"); 1714 1715 return 0; 1716} 1717 1718static int 1719mii_set_media_pcs (struct net_device *dev) 1720{ 1721 __u16 bmcr; 1722 __u16 esr; 1723 __u16 anar; 1724 int phy_addr; 1725 struct netdev_private *np; 1726 np = netdev_priv(dev); 1727 phy_addr = np->phy_addr; 1728 1729 /* Auto-Negotiation? */ 1730 if (np->an_enable) { 1731 /* Advertise capabilities */ 1732 esr = mii_read (dev, phy_addr, PCS_ESR); 1733 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1734 ~PCS_ANAR_HALF_DUPLEX & 1735 ~PCS_ANAR_FULL_DUPLEX; 1736 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) 1737 anar |= PCS_ANAR_HALF_DUPLEX; 1738 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) 1739 anar |= PCS_ANAR_FULL_DUPLEX; 1740 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; 1741 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1742 1743 /* Soft reset PHY */ 1744 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1745 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1746 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1747 mdelay(1); 1748 } else { 1749 /* Force speed setting */ 1750 /* PHY Reset */ 1751 bmcr = BMCR_RESET; 1752 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1753 mdelay(10); 1754 if (np->full_duplex) { 1755 bmcr = BMCR_FULLDPLX; 1756 printk (KERN_INFO "Manual full duplex\n"); 1757 } else { 1758 bmcr = 0; 1759 printk (KERN_INFO "Manual half duplex\n"); 1760 } 1761 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1762 mdelay(10); 1763 1764 /* Advertise nothing */ 1765 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1766 } 1767 return 0; 1768} 1769 1770 1771static int 1772rio_close (struct net_device *dev) 1773{ 1774 struct netdev_private *np = netdev_priv(dev); 1775 struct pci_dev *pdev = np->pdev; 1776 1777 netif_stop_queue (dev); 1778 1779 rio_hw_stop(dev); 1780 1781 free_irq(pdev->irq, dev); 1782 del_timer_sync (&np->timer); 1783 1784 free_list(dev); 1785 1786 return 0; 1787} 1788 1789static void 1790rio_remove1 (struct pci_dev *pdev) 1791{ 1792 struct net_device *dev = pci_get_drvdata (pdev); 1793 1794 if (dev) { 1795 struct netdev_private *np = netdev_priv(dev); 1796 1797 unregister_netdev (dev); 1798 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, 1799 np->rx_ring_dma); 1800 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, 1801 np->tx_ring_dma); 1802#ifdef MEM_MAPPING 1803 pci_iounmap(pdev, np->ioaddr); 1804#endif 1805 pci_iounmap(pdev, np->eeprom_addr); 1806 free_netdev (dev); 1807 pci_release_regions (pdev); 1808 pci_disable_device (pdev); 1809 } 1810} 1811 1812#ifdef CONFIG_PM_SLEEP 1813static int rio_suspend(struct device *device) 1814{ 1815 struct net_device *dev = dev_get_drvdata(device); 1816 struct netdev_private *np = netdev_priv(dev); 1817 1818 if (!netif_running(dev)) 1819 return 0; 1820 1821 netif_device_detach(dev); 1822 del_timer_sync(&np->timer); 1823 rio_hw_stop(dev); 1824 1825 return 0; 1826} 1827 1828static int rio_resume(struct device *device) 1829{ 1830 struct net_device *dev = dev_get_drvdata(device); 1831 struct netdev_private *np = netdev_priv(dev); 1832 1833 if (!netif_running(dev)) 1834 return 0; 1835 1836 rio_reset_ring(np); 1837 rio_hw_init(dev); 1838 np->timer.expires = jiffies + 1 * HZ; 1839 add_timer(&np->timer); 1840 netif_device_attach(dev); 1841 dl2k_enable_int(np); 1842 1843 return 0; 1844} 1845 1846static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume); 1847#define RIO_PM_OPS (&rio_pm_ops) 1848 1849#else 1850 1851#define RIO_PM_OPS NULL 1852 1853#endif /* CONFIG_PM_SLEEP */ 1854 1855static struct pci_driver rio_driver = { 1856 .name = "dl2k", 1857 .id_table = rio_pci_tbl, 1858 .probe = rio_probe1, 1859 .remove = rio_remove1, 1860 .driver.pm = RIO_PM_OPS, 1861}; 1862 1863module_pci_driver(rio_driver); 1864 1865/* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */ 1866