1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Linux network driver for QLogic BR-series Converged Network Adapter. 4 */ 5/* 6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 7 * Copyright (c) 2014-2015 QLogic Corporation 8 * All rights reserved 9 * www.qlogic.com 10 */ 11#include <linux/bitops.h> 12#include <linux/netdevice.h> 13#include <linux/skbuff.h> 14#include <linux/etherdevice.h> 15#include <linux/in.h> 16#include <linux/ethtool.h> 17#include <linux/if_vlan.h> 18#include <linux/if_ether.h> 19#include <linux/ip.h> 20#include <linux/prefetch.h> 21#include <linux/module.h> 22 23#include "bnad.h" 24#include "bna.h" 25#include "cna.h" 26 27static DEFINE_MUTEX(bnad_fwimg_mutex); 28 29/* 30 * Module params 31 */ 32static uint bnad_msix_disable; 33module_param(bnad_msix_disable, uint, 0444); 34MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode"); 35 36static uint bnad_ioc_auto_recover = 1; 37module_param(bnad_ioc_auto_recover, uint, 0444); 38MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery"); 39 40static uint bna_debugfs_enable = 1; 41module_param(bna_debugfs_enable, uint, 0644); 42MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1," 43 " Range[false:0|true:1]"); 44 45/* 46 * Global variables 47 */ 48static u32 bnad_rxqs_per_cq = 2; 49static atomic_t bna_id; 50static const u8 bnad_bcast_addr[] __aligned(2) = 51 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 52 53/* 54 * Local MACROS 55 */ 56#define BNAD_GET_MBOX_IRQ(_bnad) \ 57 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ 58 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \ 59 ((_bnad)->pcidev->irq)) 60 61#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \ 62do { \ 63 (_res_info)->res_type = BNA_RES_T_MEM; \ 64 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \ 65 (_res_info)->res_u.mem_info.num = (_num); \ 66 (_res_info)->res_u.mem_info.len = (_size); \ 67} while (0) 68 69/* 70 * Reinitialize completions in CQ, once Rx is taken down 71 */ 72static void 73bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb) 74{ 75 struct bna_cq_entry *cmpl; 76 int i; 77 78 for (i = 0; i < ccb->q_depth; i++) { 79 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i]; 80 cmpl->valid = 0; 81 } 82} 83 84/* Tx Datapath functions */ 85 86 87/* Caller should ensure that the entry at unmap_q[index] is valid */ 88static u32 89bnad_tx_buff_unmap(struct bnad *bnad, 90 struct bnad_tx_unmap *unmap_q, 91 u32 q_depth, u32 index) 92{ 93 struct bnad_tx_unmap *unmap; 94 struct sk_buff *skb; 95 int vector, nvecs; 96 97 unmap = &unmap_q[index]; 98 nvecs = unmap->nvecs; 99 100 skb = unmap->skb; 101 unmap->skb = NULL; 102 unmap->nvecs = 0; 103 dma_unmap_single(&bnad->pcidev->dev, 104 dma_unmap_addr(&unmap->vectors[0], dma_addr), 105 skb_headlen(skb), DMA_TO_DEVICE); 106 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0); 107 nvecs--; 108 109 vector = 0; 110 while (nvecs) { 111 vector++; 112 if (vector == BFI_TX_MAX_VECTORS_PER_WI) { 113 vector = 0; 114 BNA_QE_INDX_INC(index, q_depth); 115 unmap = &unmap_q[index]; 116 } 117 118 dma_unmap_page(&bnad->pcidev->dev, 119 dma_unmap_addr(&unmap->vectors[vector], dma_addr), 120 dma_unmap_len(&unmap->vectors[vector], dma_len), 121 DMA_TO_DEVICE); 122 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0); 123 nvecs--; 124 } 125 126 BNA_QE_INDX_INC(index, q_depth); 127 128 return index; 129} 130 131/* 132 * Frees all pending Tx Bufs 133 * At this point no activity is expected on the Q, 134 * so DMA unmap & freeing is fine. 135 */ 136static void 137bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb) 138{ 139 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 140 struct sk_buff *skb; 141 int i; 142 143 for (i = 0; i < tcb->q_depth; i++) { 144 skb = unmap_q[i].skb; 145 if (!skb) 146 continue; 147 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i); 148 149 dev_kfree_skb_any(skb); 150 } 151} 152 153/* 154 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion 155 * Can be called in a) Interrupt context 156 * b) Sending context 157 */ 158static u32 159bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb) 160{ 161 u32 sent_packets = 0, sent_bytes = 0; 162 u32 wis, unmap_wis, hw_cons, cons, q_depth; 163 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 164 struct bnad_tx_unmap *unmap; 165 struct sk_buff *skb; 166 167 /* Just return if TX is stopped */ 168 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 169 return 0; 170 171 hw_cons = *(tcb->hw_consumer_index); 172 rmb(); 173 cons = tcb->consumer_index; 174 q_depth = tcb->q_depth; 175 176 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth); 177 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth))); 178 179 while (wis) { 180 unmap = &unmap_q[cons]; 181 182 skb = unmap->skb; 183 184 sent_packets++; 185 sent_bytes += skb->len; 186 187 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs); 188 wis -= unmap_wis; 189 190 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons); 191 dev_kfree_skb_any(skb); 192 } 193 194 /* Update consumer pointers. */ 195 tcb->consumer_index = hw_cons; 196 197 tcb->txq->tx_packets += sent_packets; 198 tcb->txq->tx_bytes += sent_bytes; 199 200 return sent_packets; 201} 202 203static u32 204bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb) 205{ 206 struct net_device *netdev = bnad->netdev; 207 u32 sent = 0; 208 209 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) 210 return 0; 211 212 sent = bnad_txcmpl_process(bnad, tcb); 213 if (sent) { 214 if (netif_queue_stopped(netdev) && 215 netif_carrier_ok(netdev) && 216 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >= 217 BNAD_NETIF_WAKE_THRESHOLD) { 218 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) { 219 netif_wake_queue(netdev); 220 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 221 } 222 } 223 } 224 225 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 226 bna_ib_ack(tcb->i_dbell, sent); 227 228 smp_mb__before_atomic(); 229 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 230 231 return sent; 232} 233 234/* MSIX Tx Completion Handler */ 235static irqreturn_t 236bnad_msix_tx(int irq, void *data) 237{ 238 struct bna_tcb *tcb = (struct bna_tcb *)data; 239 struct bnad *bnad = tcb->bnad; 240 241 bnad_tx_complete(bnad, tcb); 242 243 return IRQ_HANDLED; 244} 245 246static inline void 247bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb) 248{ 249 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 250 251 unmap_q->reuse_pi = -1; 252 unmap_q->alloc_order = -1; 253 unmap_q->map_size = 0; 254 unmap_q->type = BNAD_RXBUF_NONE; 255} 256 257/* Default is page-based allocation. Multi-buffer support - TBD */ 258static int 259bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb) 260{ 261 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 262 int order; 263 264 bnad_rxq_alloc_uninit(bnad, rcb); 265 266 order = get_order(rcb->rxq->buffer_size); 267 268 unmap_q->type = BNAD_RXBUF_PAGE; 269 270 if (bna_is_small_rxq(rcb->id)) { 271 unmap_q->alloc_order = 0; 272 unmap_q->map_size = rcb->rxq->buffer_size; 273 } else { 274 if (rcb->rxq->multi_buffer) { 275 unmap_q->alloc_order = 0; 276 unmap_q->map_size = rcb->rxq->buffer_size; 277 unmap_q->type = BNAD_RXBUF_MULTI_BUFF; 278 } else { 279 unmap_q->alloc_order = order; 280 unmap_q->map_size = 281 (rcb->rxq->buffer_size > 2048) ? 282 PAGE_SIZE << order : 2048; 283 } 284 } 285 286 BUG_ON((PAGE_SIZE << order) % unmap_q->map_size); 287 288 return 0; 289} 290 291static inline void 292bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap) 293{ 294 if (!unmap->page) 295 return; 296 297 dma_unmap_page(&bnad->pcidev->dev, 298 dma_unmap_addr(&unmap->vector, dma_addr), 299 unmap->vector.len, DMA_FROM_DEVICE); 300 put_page(unmap->page); 301 unmap->page = NULL; 302 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 303 unmap->vector.len = 0; 304} 305 306static inline void 307bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap) 308{ 309 if (!unmap->skb) 310 return; 311 312 dma_unmap_single(&bnad->pcidev->dev, 313 dma_unmap_addr(&unmap->vector, dma_addr), 314 unmap->vector.len, DMA_FROM_DEVICE); 315 dev_kfree_skb_any(unmap->skb); 316 unmap->skb = NULL; 317 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 318 unmap->vector.len = 0; 319} 320 321static void 322bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb) 323{ 324 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 325 int i; 326 327 for (i = 0; i < rcb->q_depth; i++) { 328 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i]; 329 330 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 331 bnad_rxq_cleanup_skb(bnad, unmap); 332 else 333 bnad_rxq_cleanup_page(bnad, unmap); 334 } 335 bnad_rxq_alloc_uninit(bnad, rcb); 336} 337 338static u32 339bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 340{ 341 u32 alloced, prod, q_depth; 342 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 343 struct bnad_rx_unmap *unmap, *prev; 344 struct bna_rxq_entry *rxent; 345 struct page *page; 346 u32 page_offset, alloc_size; 347 dma_addr_t dma_addr; 348 349 prod = rcb->producer_index; 350 q_depth = rcb->q_depth; 351 352 alloc_size = PAGE_SIZE << unmap_q->alloc_order; 353 alloced = 0; 354 355 while (nalloc--) { 356 unmap = &unmap_q->unmap[prod]; 357 358 if (unmap_q->reuse_pi < 0) { 359 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 360 unmap_q->alloc_order); 361 page_offset = 0; 362 } else { 363 prev = &unmap_q->unmap[unmap_q->reuse_pi]; 364 page = prev->page; 365 page_offset = prev->page_offset + unmap_q->map_size; 366 get_page(page); 367 } 368 369 if (unlikely(!page)) { 370 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 371 rcb->rxq->rxbuf_alloc_failed++; 372 goto finishing; 373 } 374 375 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset, 376 unmap_q->map_size, DMA_FROM_DEVICE); 377 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 378 put_page(page); 379 BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); 380 rcb->rxq->rxbuf_map_failed++; 381 goto finishing; 382 } 383 384 unmap->page = page; 385 unmap->page_offset = page_offset; 386 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 387 unmap->vector.len = unmap_q->map_size; 388 page_offset += unmap_q->map_size; 389 390 if (page_offset < alloc_size) 391 unmap_q->reuse_pi = prod; 392 else 393 unmap_q->reuse_pi = -1; 394 395 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 396 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 397 BNA_QE_INDX_INC(prod, q_depth); 398 alloced++; 399 } 400 401finishing: 402 if (likely(alloced)) { 403 rcb->producer_index = prod; 404 smp_mb(); 405 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 406 bna_rxq_prod_indx_doorbell(rcb); 407 } 408 409 return alloced; 410} 411 412static u32 413bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 414{ 415 u32 alloced, prod, q_depth, buff_sz; 416 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 417 struct bnad_rx_unmap *unmap; 418 struct bna_rxq_entry *rxent; 419 struct sk_buff *skb; 420 dma_addr_t dma_addr; 421 422 buff_sz = rcb->rxq->buffer_size; 423 prod = rcb->producer_index; 424 q_depth = rcb->q_depth; 425 426 alloced = 0; 427 while (nalloc--) { 428 unmap = &unmap_q->unmap[prod]; 429 430 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz); 431 432 if (unlikely(!skb)) { 433 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 434 rcb->rxq->rxbuf_alloc_failed++; 435 goto finishing; 436 } 437 438 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 439 buff_sz, DMA_FROM_DEVICE); 440 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 441 dev_kfree_skb_any(skb); 442 BNAD_UPDATE_CTR(bnad, rxbuf_map_failed); 443 rcb->rxq->rxbuf_map_failed++; 444 goto finishing; 445 } 446 447 unmap->skb = skb; 448 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 449 unmap->vector.len = buff_sz; 450 451 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 452 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 453 BNA_QE_INDX_INC(prod, q_depth); 454 alloced++; 455 } 456 457finishing: 458 if (likely(alloced)) { 459 rcb->producer_index = prod; 460 smp_mb(); 461 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 462 bna_rxq_prod_indx_doorbell(rcb); 463 } 464 465 return alloced; 466} 467 468static inline void 469bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb) 470{ 471 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 472 u32 to_alloc; 473 474 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth); 475 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)) 476 return; 477 478 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 479 bnad_rxq_refill_skb(bnad, rcb, to_alloc); 480 else 481 bnad_rxq_refill_page(bnad, rcb, to_alloc); 482} 483 484#define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 485 BNA_CQ_EF_IPV6 | \ 486 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \ 487 BNA_CQ_EF_L4_CKSUM_OK) 488 489#define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 490 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 491#define flags_tcp6 (BNA_CQ_EF_IPV6 | \ 492 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 493#define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 494 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 495#define flags_udp6 (BNA_CQ_EF_IPV6 | \ 496 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 497 498static void 499bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb, 500 u32 sop_ci, u32 nvecs) 501{ 502 struct bnad_rx_unmap_q *unmap_q; 503 struct bnad_rx_unmap *unmap; 504 u32 ci, vec; 505 506 unmap_q = rcb->unmap_q; 507 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) { 508 unmap = &unmap_q->unmap[ci]; 509 BNA_QE_INDX_INC(ci, rcb->q_depth); 510 511 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 512 bnad_rxq_cleanup_skb(bnad, unmap); 513 else 514 bnad_rxq_cleanup_page(bnad, unmap); 515 } 516} 517 518static void 519bnad_cq_setup_skb_frags(struct bna_ccb *ccb, struct sk_buff *skb, u32 nvecs) 520{ 521 struct bna_rcb *rcb; 522 struct bnad *bnad; 523 struct bnad_rx_unmap_q *unmap_q; 524 struct bna_cq_entry *cq, *cmpl; 525 u32 ci, pi, totlen = 0; 526 527 cq = ccb->sw_q; 528 pi = ccb->producer_index; 529 cmpl = &cq[pi]; 530 531 rcb = bna_is_small_rxq(cmpl->rxq_id) ? ccb->rcb[1] : ccb->rcb[0]; 532 unmap_q = rcb->unmap_q; 533 bnad = rcb->bnad; 534 ci = rcb->consumer_index; 535 536 /* prefetch header */ 537 prefetch(page_address(unmap_q->unmap[ci].page) + 538 unmap_q->unmap[ci].page_offset); 539 540 while (nvecs--) { 541 struct bnad_rx_unmap *unmap; 542 u32 len; 543 544 unmap = &unmap_q->unmap[ci]; 545 BNA_QE_INDX_INC(ci, rcb->q_depth); 546 547 dma_unmap_page(&bnad->pcidev->dev, 548 dma_unmap_addr(&unmap->vector, dma_addr), 549 unmap->vector.len, DMA_FROM_DEVICE); 550 551 len = ntohs(cmpl->length); 552 skb->truesize += unmap->vector.len; 553 totlen += len; 554 555 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 556 unmap->page, unmap->page_offset, len); 557 558 unmap->page = NULL; 559 unmap->vector.len = 0; 560 561 BNA_QE_INDX_INC(pi, ccb->q_depth); 562 cmpl = &cq[pi]; 563 } 564 565 skb->len += totlen; 566 skb->data_len += totlen; 567} 568 569static inline void 570bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb, 571 struct bnad_rx_unmap *unmap, u32 len) 572{ 573 prefetch(skb->data); 574 575 dma_unmap_single(&bnad->pcidev->dev, 576 dma_unmap_addr(&unmap->vector, dma_addr), 577 unmap->vector.len, DMA_FROM_DEVICE); 578 579 skb_put(skb, len); 580 skb->protocol = eth_type_trans(skb, bnad->netdev); 581 582 unmap->skb = NULL; 583 unmap->vector.len = 0; 584} 585 586static u32 587bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget) 588{ 589 struct bna_cq_entry *cq, *cmpl, *next_cmpl; 590 struct bna_rcb *rcb = NULL; 591 struct bnad_rx_unmap_q *unmap_q; 592 struct bnad_rx_unmap *unmap = NULL; 593 struct sk_buff *skb = NULL; 594 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate; 595 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl; 596 u32 packets = 0, len = 0, totlen = 0; 597 u32 pi, vec, sop_ci = 0, nvecs = 0; 598 u32 flags, masked_flags; 599 600 prefetch(bnad->netdev); 601 602 cq = ccb->sw_q; 603 604 while (packets < budget) { 605 cmpl = &cq[ccb->producer_index]; 606 if (!cmpl->valid) 607 break; 608 /* The 'valid' field is set by the adapter, only after writing 609 * the other fields of completion entry. Hence, do not load 610 * other fields of completion entry *before* the 'valid' is 611 * loaded. Adding the rmb() here prevents the compiler and/or 612 * CPU from reordering the reads which would potentially result 613 * in reading stale values in completion entry. 614 */ 615 rmb(); 616 617 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length)); 618 619 if (bna_is_small_rxq(cmpl->rxq_id)) 620 rcb = ccb->rcb[1]; 621 else 622 rcb = ccb->rcb[0]; 623 624 unmap_q = rcb->unmap_q; 625 626 /* start of packet ci */ 627 sop_ci = rcb->consumer_index; 628 629 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) { 630 unmap = &unmap_q->unmap[sop_ci]; 631 skb = unmap->skb; 632 } else { 633 skb = napi_get_frags(&rx_ctrl->napi); 634 if (unlikely(!skb)) 635 break; 636 } 637 prefetch(skb); 638 639 flags = ntohl(cmpl->flags); 640 len = ntohs(cmpl->length); 641 totlen = len; 642 nvecs = 1; 643 644 /* Check all the completions for this frame. 645 * busy-wait doesn't help much, break here. 646 */ 647 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) && 648 (flags & BNA_CQ_EF_EOP) == 0) { 649 pi = ccb->producer_index; 650 do { 651 BNA_QE_INDX_INC(pi, ccb->q_depth); 652 next_cmpl = &cq[pi]; 653 654 if (!next_cmpl->valid) 655 break; 656 /* The 'valid' field is set by the adapter, only 657 * after writing the other fields of completion 658 * entry. Hence, do not load other fields of 659 * completion entry *before* the 'valid' is 660 * loaded. Adding the rmb() here prevents the 661 * compiler and/or CPU from reordering the reads 662 * which would potentially result in reading 663 * stale values in completion entry. 664 */ 665 rmb(); 666 667 len = ntohs(next_cmpl->length); 668 flags = ntohl(next_cmpl->flags); 669 670 nvecs++; 671 totlen += len; 672 } while ((flags & BNA_CQ_EF_EOP) == 0); 673 674 if (!next_cmpl->valid) 675 break; 676 } 677 packets++; 678 679 /* TODO: BNA_CQ_EF_LOCAL ? */ 680 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR | 681 BNA_CQ_EF_FCS_ERROR | 682 BNA_CQ_EF_TOO_LONG))) { 683 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs); 684 rcb->rxq->rx_packets_with_error++; 685 686 goto next; 687 } 688 689 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 690 bnad_cq_setup_skb(bnad, skb, unmap, len); 691 else 692 bnad_cq_setup_skb_frags(ccb, skb, nvecs); 693 694 rcb->rxq->rx_packets++; 695 rcb->rxq->rx_bytes += totlen; 696 ccb->bytes_per_intr += totlen; 697 698 masked_flags = flags & flags_cksum_prot_mask; 699 700 if (likely 701 ((bnad->netdev->features & NETIF_F_RXCSUM) && 702 ((masked_flags == flags_tcp4) || 703 (masked_flags == flags_udp4) || 704 (masked_flags == flags_tcp6) || 705 (masked_flags == flags_udp6)))) 706 skb->ip_summed = CHECKSUM_UNNECESSARY; 707 else 708 skb_checksum_none_assert(skb); 709 710 if ((flags & BNA_CQ_EF_VLAN) && 711 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) 712 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag)); 713 714 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) 715 netif_receive_skb(skb); 716 else 717 napi_gro_frags(&rx_ctrl->napi); 718 719next: 720 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth); 721 for (vec = 0; vec < nvecs; vec++) { 722 cmpl = &cq[ccb->producer_index]; 723 cmpl->valid = 0; 724 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth); 725 } 726 } 727 728 napi_gro_flush(&rx_ctrl->napi, false); 729 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) 730 bna_ib_ack_disable_irq(ccb->i_dbell, packets); 731 732 bnad_rxq_post(bnad, ccb->rcb[0]); 733 if (ccb->rcb[1]) 734 bnad_rxq_post(bnad, ccb->rcb[1]); 735 736 return packets; 737} 738 739static void 740bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb) 741{ 742 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl); 743 struct napi_struct *napi = &rx_ctrl->napi; 744 745 if (likely(napi_schedule_prep(napi))) { 746 __napi_schedule(napi); 747 rx_ctrl->rx_schedule++; 748 } 749} 750 751/* MSIX Rx Path Handler */ 752static irqreturn_t 753bnad_msix_rx(int irq, void *data) 754{ 755 struct bna_ccb *ccb = (struct bna_ccb *)data; 756 757 if (ccb) { 758 ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++; 759 bnad_netif_rx_schedule_poll(ccb->bnad, ccb); 760 } 761 762 return IRQ_HANDLED; 763} 764 765/* Interrupt handlers */ 766 767/* Mbox Interrupt Handlers */ 768static irqreturn_t 769bnad_msix_mbox_handler(int irq, void *data) 770{ 771 u32 intr_status; 772 unsigned long flags; 773 struct bnad *bnad = (struct bnad *)data; 774 775 spin_lock_irqsave(&bnad->bna_lock, flags); 776 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 777 spin_unlock_irqrestore(&bnad->bna_lock, flags); 778 return IRQ_HANDLED; 779 } 780 781 bna_intr_status_get(&bnad->bna, intr_status); 782 783 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 784 bna_mbox_handler(&bnad->bna, intr_status); 785 786 spin_unlock_irqrestore(&bnad->bna_lock, flags); 787 788 return IRQ_HANDLED; 789} 790 791static irqreturn_t 792bnad_isr(int irq, void *data) 793{ 794 int i, j; 795 u32 intr_status; 796 unsigned long flags; 797 struct bnad *bnad = (struct bnad *)data; 798 struct bnad_rx_info *rx_info; 799 struct bnad_rx_ctrl *rx_ctrl; 800 struct bna_tcb *tcb = NULL; 801 802 spin_lock_irqsave(&bnad->bna_lock, flags); 803 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 804 spin_unlock_irqrestore(&bnad->bna_lock, flags); 805 return IRQ_NONE; 806 } 807 808 bna_intr_status_get(&bnad->bna, intr_status); 809 810 if (unlikely(!intr_status)) { 811 spin_unlock_irqrestore(&bnad->bna_lock, flags); 812 return IRQ_NONE; 813 } 814 815 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 816 bna_mbox_handler(&bnad->bna, intr_status); 817 818 spin_unlock_irqrestore(&bnad->bna_lock, flags); 819 820 if (!BNA_IS_INTX_DATA_INTR(intr_status)) 821 return IRQ_HANDLED; 822 823 /* Process data interrupts */ 824 /* Tx processing */ 825 for (i = 0; i < bnad->num_tx; i++) { 826 for (j = 0; j < bnad->num_txq_per_tx; j++) { 827 tcb = bnad->tx_info[i].tcb[j]; 828 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 829 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]); 830 } 831 } 832 /* Rx processing */ 833 for (i = 0; i < bnad->num_rx; i++) { 834 rx_info = &bnad->rx_info[i]; 835 if (!rx_info->rx) 836 continue; 837 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 838 rx_ctrl = &rx_info->rx_ctrl[j]; 839 if (rx_ctrl->ccb) 840 bnad_netif_rx_schedule_poll(bnad, 841 rx_ctrl->ccb); 842 } 843 } 844 return IRQ_HANDLED; 845} 846 847/* 848 * Called in interrupt / callback context 849 * with bna_lock held, so cfg_flags access is OK 850 */ 851static void 852bnad_enable_mbox_irq(struct bnad *bnad) 853{ 854 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 855 856 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled); 857} 858 859/* 860 * Called with bnad->bna_lock held b'cos of 861 * bnad->cfg_flags access. 862 */ 863static void 864bnad_disable_mbox_irq(struct bnad *bnad) 865{ 866 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 867 868 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 869} 870 871static void 872bnad_set_netdev_perm_addr(struct bnad *bnad) 873{ 874 struct net_device *netdev = bnad->netdev; 875 876 ether_addr_copy(netdev->perm_addr, bnad->perm_addr); 877 if (is_zero_ether_addr(netdev->dev_addr)) 878 eth_hw_addr_set(netdev, bnad->perm_addr); 879} 880 881/* Control Path Handlers */ 882 883/* Callbacks */ 884void 885bnad_cb_mbox_intr_enable(struct bnad *bnad) 886{ 887 bnad_enable_mbox_irq(bnad); 888} 889 890void 891bnad_cb_mbox_intr_disable(struct bnad *bnad) 892{ 893 bnad_disable_mbox_irq(bnad); 894} 895 896void 897bnad_cb_ioceth_ready(struct bnad *bnad) 898{ 899 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 900 complete(&bnad->bnad_completions.ioc_comp); 901} 902 903void 904bnad_cb_ioceth_failed(struct bnad *bnad) 905{ 906 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL; 907 complete(&bnad->bnad_completions.ioc_comp); 908} 909 910void 911bnad_cb_ioceth_disabled(struct bnad *bnad) 912{ 913 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 914 complete(&bnad->bnad_completions.ioc_comp); 915} 916 917static void 918bnad_cb_enet_disabled(void *arg) 919{ 920 struct bnad *bnad = (struct bnad *)arg; 921 922 netif_carrier_off(bnad->netdev); 923 complete(&bnad->bnad_completions.enet_comp); 924} 925 926void 927bnad_cb_ethport_link_status(struct bnad *bnad, 928 enum bna_link_status link_status) 929{ 930 bool link_up = false; 931 932 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP); 933 934 if (link_status == BNA_CEE_UP) { 935 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 936 BNAD_UPDATE_CTR(bnad, cee_toggle); 937 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 938 } else { 939 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 940 BNAD_UPDATE_CTR(bnad, cee_toggle); 941 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 942 } 943 944 if (link_up) { 945 if (!netif_carrier_ok(bnad->netdev)) { 946 uint tx_id, tcb_id; 947 netdev_info(bnad->netdev, "link up\n"); 948 netif_carrier_on(bnad->netdev); 949 BNAD_UPDATE_CTR(bnad, link_toggle); 950 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) { 951 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx; 952 tcb_id++) { 953 struct bna_tcb *tcb = 954 bnad->tx_info[tx_id].tcb[tcb_id]; 955 u32 txq_id; 956 if (!tcb) 957 continue; 958 959 txq_id = tcb->id; 960 961 if (test_bit(BNAD_TXQ_TX_STARTED, 962 &tcb->flags)) { 963 /* 964 * Force an immediate 965 * Transmit Schedule */ 966 netif_wake_subqueue( 967 bnad->netdev, 968 txq_id); 969 BNAD_UPDATE_CTR(bnad, 970 netif_queue_wakeup); 971 } else { 972 netif_stop_subqueue( 973 bnad->netdev, 974 txq_id); 975 BNAD_UPDATE_CTR(bnad, 976 netif_queue_stop); 977 } 978 } 979 } 980 } 981 } else { 982 if (netif_carrier_ok(bnad->netdev)) { 983 netdev_info(bnad->netdev, "link down\n"); 984 netif_carrier_off(bnad->netdev); 985 BNAD_UPDATE_CTR(bnad, link_toggle); 986 } 987 } 988} 989 990static void 991bnad_cb_tx_disabled(void *arg, struct bna_tx *tx) 992{ 993 struct bnad *bnad = (struct bnad *)arg; 994 995 complete(&bnad->bnad_completions.tx_comp); 996} 997 998static void 999bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb) 1000{ 1001 struct bnad_tx_info *tx_info = 1002 (struct bnad_tx_info *)tcb->txq->tx->priv; 1003 1004 tcb->priv = tcb; 1005 tx_info->tcb[tcb->id] = tcb; 1006} 1007 1008static void 1009bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb) 1010{ 1011 struct bnad_tx_info *tx_info = 1012 (struct bnad_tx_info *)tcb->txq->tx->priv; 1013 1014 tx_info->tcb[tcb->id] = NULL; 1015 tcb->priv = NULL; 1016} 1017 1018static void 1019bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb) 1020{ 1021 struct bnad_rx_info *rx_info = 1022 (struct bnad_rx_info *)ccb->cq->rx->priv; 1023 1024 rx_info->rx_ctrl[ccb->id].ccb = ccb; 1025 ccb->ctrl = &rx_info->rx_ctrl[ccb->id]; 1026} 1027 1028static void 1029bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb) 1030{ 1031 struct bnad_rx_info *rx_info = 1032 (struct bnad_rx_info *)ccb->cq->rx->priv; 1033 1034 rx_info->rx_ctrl[ccb->id].ccb = NULL; 1035} 1036 1037static void 1038bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx) 1039{ 1040 struct bnad_tx_info *tx_info = tx->priv; 1041 struct bna_tcb *tcb; 1042 u32 txq_id; 1043 int i; 1044 1045 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1046 tcb = tx_info->tcb[i]; 1047 if (!tcb) 1048 continue; 1049 txq_id = tcb->id; 1050 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 1051 netif_stop_subqueue(bnad->netdev, txq_id); 1052 } 1053} 1054 1055static void 1056bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx) 1057{ 1058 struct bnad_tx_info *tx_info = tx->priv; 1059 struct bna_tcb *tcb; 1060 u32 txq_id; 1061 int i; 1062 1063 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1064 tcb = tx_info->tcb[i]; 1065 if (!tcb) 1066 continue; 1067 txq_id = tcb->id; 1068 1069 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)); 1070 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 1071 BUG_ON(*(tcb->hw_consumer_index) != 0); 1072 1073 if (netif_carrier_ok(bnad->netdev)) { 1074 netif_wake_subqueue(bnad->netdev, txq_id); 1075 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 1076 } 1077 } 1078 1079 /* 1080 * Workaround for first ioceth enable failure & we 1081 * get a 0 MAC address. We try to get the MAC address 1082 * again here. 1083 */ 1084 if (is_zero_ether_addr(bnad->perm_addr)) { 1085 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr); 1086 bnad_set_netdev_perm_addr(bnad); 1087 } 1088} 1089 1090/* 1091 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm. 1092 */ 1093static void 1094bnad_tx_cleanup(struct delayed_work *work) 1095{ 1096 struct bnad_tx_info *tx_info = 1097 container_of(work, struct bnad_tx_info, tx_cleanup_work); 1098 struct bnad *bnad = NULL; 1099 struct bna_tcb *tcb; 1100 unsigned long flags; 1101 u32 i, pending = 0; 1102 1103 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1104 tcb = tx_info->tcb[i]; 1105 if (!tcb) 1106 continue; 1107 1108 bnad = tcb->bnad; 1109 1110 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 1111 pending++; 1112 continue; 1113 } 1114 1115 bnad_txq_cleanup(bnad, tcb); 1116 1117 smp_mb__before_atomic(); 1118 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 1119 } 1120 1121 if (pending) { 1122 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 1123 msecs_to_jiffies(1)); 1124 return; 1125 } 1126 1127 spin_lock_irqsave(&bnad->bna_lock, flags); 1128 bna_tx_cleanup_complete(tx_info->tx); 1129 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1130} 1131 1132static void 1133bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx) 1134{ 1135 struct bnad_tx_info *tx_info = tx->priv; 1136 struct bna_tcb *tcb; 1137 int i; 1138 1139 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1140 tcb = tx_info->tcb[i]; 1141 if (!tcb) 1142 continue; 1143 } 1144 1145 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0); 1146} 1147 1148static void 1149bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx) 1150{ 1151 struct bnad_rx_info *rx_info = rx->priv; 1152 struct bna_ccb *ccb; 1153 struct bnad_rx_ctrl *rx_ctrl; 1154 int i; 1155 1156 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1157 rx_ctrl = &rx_info->rx_ctrl[i]; 1158 ccb = rx_ctrl->ccb; 1159 if (!ccb) 1160 continue; 1161 1162 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags); 1163 1164 if (ccb->rcb[1]) 1165 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags); 1166 } 1167} 1168 1169/* 1170 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm. 1171 */ 1172static void 1173bnad_rx_cleanup(void *work) 1174{ 1175 struct bnad_rx_info *rx_info = 1176 container_of(work, struct bnad_rx_info, rx_cleanup_work); 1177 struct bnad_rx_ctrl *rx_ctrl; 1178 struct bnad *bnad = NULL; 1179 unsigned long flags; 1180 u32 i; 1181 1182 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1183 rx_ctrl = &rx_info->rx_ctrl[i]; 1184 1185 if (!rx_ctrl->ccb) 1186 continue; 1187 1188 bnad = rx_ctrl->ccb->bnad; 1189 1190 /* 1191 * Wait till the poll handler has exited 1192 * and nothing can be scheduled anymore 1193 */ 1194 napi_disable(&rx_ctrl->napi); 1195 1196 bnad_cq_cleanup(bnad, rx_ctrl->ccb); 1197 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]); 1198 if (rx_ctrl->ccb->rcb[1]) 1199 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]); 1200 } 1201 1202 spin_lock_irqsave(&bnad->bna_lock, flags); 1203 bna_rx_cleanup_complete(rx_info->rx); 1204 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1205} 1206 1207static void 1208bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx) 1209{ 1210 struct bnad_rx_info *rx_info = rx->priv; 1211 struct bna_ccb *ccb; 1212 struct bnad_rx_ctrl *rx_ctrl; 1213 int i; 1214 1215 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1216 rx_ctrl = &rx_info->rx_ctrl[i]; 1217 ccb = rx_ctrl->ccb; 1218 if (!ccb) 1219 continue; 1220 1221 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags); 1222 1223 if (ccb->rcb[1]) 1224 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags); 1225 } 1226 1227 queue_work(bnad->work_q, &rx_info->rx_cleanup_work); 1228} 1229 1230static void 1231bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx) 1232{ 1233 struct bnad_rx_info *rx_info = rx->priv; 1234 struct bna_ccb *ccb; 1235 struct bna_rcb *rcb; 1236 struct bnad_rx_ctrl *rx_ctrl; 1237 int i, j; 1238 1239 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1240 rx_ctrl = &rx_info->rx_ctrl[i]; 1241 ccb = rx_ctrl->ccb; 1242 if (!ccb) 1243 continue; 1244 1245 napi_enable(&rx_ctrl->napi); 1246 1247 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) { 1248 rcb = ccb->rcb[j]; 1249 if (!rcb) 1250 continue; 1251 1252 bnad_rxq_alloc_init(bnad, rcb); 1253 set_bit(BNAD_RXQ_STARTED, &rcb->flags); 1254 set_bit(BNAD_RXQ_POST_OK, &rcb->flags); 1255 bnad_rxq_post(bnad, rcb); 1256 } 1257 } 1258} 1259 1260static void 1261bnad_cb_rx_disabled(void *arg, struct bna_rx *rx) 1262{ 1263 struct bnad *bnad = (struct bnad *)arg; 1264 1265 complete(&bnad->bnad_completions.rx_comp); 1266} 1267 1268static void 1269bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx) 1270{ 1271 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS; 1272 complete(&bnad->bnad_completions.mcast_comp); 1273} 1274 1275void 1276bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status, 1277 struct bna_stats *stats) 1278{ 1279 if (status == BNA_CB_SUCCESS) 1280 BNAD_UPDATE_CTR(bnad, hw_stats_updates); 1281 1282 if (!netif_running(bnad->netdev) || 1283 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1284 return; 1285 1286 mod_timer(&bnad->stats_timer, 1287 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1288} 1289 1290static void 1291bnad_cb_enet_mtu_set(struct bnad *bnad) 1292{ 1293 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS; 1294 complete(&bnad->bnad_completions.mtu_comp); 1295} 1296 1297void 1298bnad_cb_completion(void *arg, enum bfa_status status) 1299{ 1300 struct bnad_iocmd_comp *iocmd_comp = 1301 (struct bnad_iocmd_comp *)arg; 1302 1303 iocmd_comp->comp_status = (u32) status; 1304 complete(&iocmd_comp->comp); 1305} 1306 1307/* Resource allocation, free functions */ 1308 1309static void 1310bnad_mem_free(struct bnad *bnad, 1311 struct bna_mem_info *mem_info) 1312{ 1313 int i; 1314 dma_addr_t dma_pa; 1315 1316 if (mem_info->mdl == NULL) 1317 return; 1318 1319 for (i = 0; i < mem_info->num; i++) { 1320 if (mem_info->mdl[i].kva != NULL) { 1321 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1322 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma), 1323 dma_pa); 1324 dma_free_coherent(&bnad->pcidev->dev, 1325 mem_info->mdl[i].len, 1326 mem_info->mdl[i].kva, dma_pa); 1327 } else 1328 kfree(mem_info->mdl[i].kva); 1329 } 1330 } 1331 kfree(mem_info->mdl); 1332 mem_info->mdl = NULL; 1333} 1334 1335static int 1336bnad_mem_alloc(struct bnad *bnad, 1337 struct bna_mem_info *mem_info) 1338{ 1339 int i; 1340 dma_addr_t dma_pa; 1341 1342 if ((mem_info->num == 0) || (mem_info->len == 0)) { 1343 mem_info->mdl = NULL; 1344 return 0; 1345 } 1346 1347 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr), 1348 GFP_KERNEL); 1349 if (mem_info->mdl == NULL) 1350 return -ENOMEM; 1351 1352 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1353 for (i = 0; i < mem_info->num; i++) { 1354 mem_info->mdl[i].len = mem_info->len; 1355 mem_info->mdl[i].kva = 1356 dma_alloc_coherent(&bnad->pcidev->dev, 1357 mem_info->len, &dma_pa, 1358 GFP_KERNEL); 1359 if (mem_info->mdl[i].kva == NULL) 1360 goto err_return; 1361 1362 BNA_SET_DMA_ADDR(dma_pa, 1363 &(mem_info->mdl[i].dma)); 1364 } 1365 } else { 1366 for (i = 0; i < mem_info->num; i++) { 1367 mem_info->mdl[i].len = mem_info->len; 1368 mem_info->mdl[i].kva = kzalloc(mem_info->len, 1369 GFP_KERNEL); 1370 if (mem_info->mdl[i].kva == NULL) 1371 goto err_return; 1372 } 1373 } 1374 1375 return 0; 1376 1377err_return: 1378 bnad_mem_free(bnad, mem_info); 1379 return -ENOMEM; 1380} 1381 1382/* Free IRQ for Mailbox */ 1383static void 1384bnad_mbox_irq_free(struct bnad *bnad) 1385{ 1386 int irq; 1387 unsigned long flags; 1388 1389 spin_lock_irqsave(&bnad->bna_lock, flags); 1390 bnad_disable_mbox_irq(bnad); 1391 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1392 1393 irq = BNAD_GET_MBOX_IRQ(bnad); 1394 free_irq(irq, bnad); 1395} 1396 1397/* 1398 * Allocates IRQ for Mailbox, but keep it disabled 1399 * This will be enabled once we get the mbox enable callback 1400 * from bna 1401 */ 1402static int 1403bnad_mbox_irq_alloc(struct bnad *bnad) 1404{ 1405 int err = 0; 1406 unsigned long irq_flags, flags; 1407 u32 irq; 1408 irq_handler_t irq_handler; 1409 1410 spin_lock_irqsave(&bnad->bna_lock, flags); 1411 if (bnad->cfg_flags & BNAD_CF_MSIX) { 1412 irq_handler = (irq_handler_t)bnad_msix_mbox_handler; 1413 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 1414 irq_flags = 0; 1415 } else { 1416 irq_handler = (irq_handler_t)bnad_isr; 1417 irq = bnad->pcidev->irq; 1418 irq_flags = IRQF_SHARED; 1419 } 1420 1421 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1422 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME); 1423 1424 /* 1425 * Set the Mbox IRQ disable flag, so that the IRQ handler 1426 * called from request_irq() for SHARED IRQs do not execute 1427 */ 1428 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 1429 1430 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 1431 1432 err = request_irq(irq, irq_handler, irq_flags, 1433 bnad->mbox_irq_name, bnad); 1434 1435 return err; 1436} 1437 1438static void 1439bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info) 1440{ 1441 kfree(intr_info->idl); 1442 intr_info->idl = NULL; 1443} 1444 1445/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */ 1446static int 1447bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src, 1448 u32 txrx_id, struct bna_intr_info *intr_info) 1449{ 1450 int i, vector_start = 0; 1451 u32 cfg_flags; 1452 unsigned long flags; 1453 1454 spin_lock_irqsave(&bnad->bna_lock, flags); 1455 cfg_flags = bnad->cfg_flags; 1456 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1457 1458 if (cfg_flags & BNAD_CF_MSIX) { 1459 intr_info->intr_type = BNA_INTR_T_MSIX; 1460 intr_info->idl = kcalloc(intr_info->num, 1461 sizeof(struct bna_intr_descr), 1462 GFP_KERNEL); 1463 if (!intr_info->idl) 1464 return -ENOMEM; 1465 1466 switch (src) { 1467 case BNAD_INTR_TX: 1468 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id; 1469 break; 1470 1471 case BNAD_INTR_RX: 1472 vector_start = BNAD_MAILBOX_MSIX_VECTORS + 1473 (bnad->num_tx * bnad->num_txq_per_tx) + 1474 txrx_id; 1475 break; 1476 1477 default: 1478 BUG(); 1479 } 1480 1481 for (i = 0; i < intr_info->num; i++) 1482 intr_info->idl[i].vector = vector_start + i; 1483 } else { 1484 intr_info->intr_type = BNA_INTR_T_INTX; 1485 intr_info->num = 1; 1486 intr_info->idl = kcalloc(intr_info->num, 1487 sizeof(struct bna_intr_descr), 1488 GFP_KERNEL); 1489 if (!intr_info->idl) 1490 return -ENOMEM; 1491 1492 switch (src) { 1493 case BNAD_INTR_TX: 1494 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK; 1495 break; 1496 1497 case BNAD_INTR_RX: 1498 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK; 1499 break; 1500 } 1501 } 1502 return 0; 1503} 1504 1505/* NOTE: Should be called for MSIX only 1506 * Unregisters Tx MSIX vector(s) from the kernel 1507 */ 1508static void 1509bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info, 1510 int num_txqs) 1511{ 1512 int i; 1513 int vector_num; 1514 1515 for (i = 0; i < num_txqs; i++) { 1516 if (tx_info->tcb[i] == NULL) 1517 continue; 1518 1519 vector_num = tx_info->tcb[i]->intr_vector; 1520 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]); 1521 } 1522} 1523 1524/* NOTE: Should be called for MSIX only 1525 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1526 */ 1527static int 1528bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info, 1529 u32 tx_id, int num_txqs) 1530{ 1531 int i; 1532 int err; 1533 int vector_num; 1534 1535 for (i = 0; i < num_txqs; i++) { 1536 vector_num = tx_info->tcb[i]->intr_vector; 1537 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name, 1538 tx_id + tx_info->tcb[i]->id); 1539 err = request_irq(bnad->msix_table[vector_num].vector, 1540 (irq_handler_t)bnad_msix_tx, 0, 1541 tx_info->tcb[i]->name, 1542 tx_info->tcb[i]); 1543 if (err) 1544 goto err_return; 1545 } 1546 1547 return 0; 1548 1549err_return: 1550 if (i > 0) 1551 bnad_tx_msix_unregister(bnad, tx_info, (i - 1)); 1552 return -1; 1553} 1554 1555/* NOTE: Should be called for MSIX only 1556 * Unregisters Rx MSIX vector(s) from the kernel 1557 */ 1558static void 1559bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info, 1560 int num_rxps) 1561{ 1562 int i; 1563 int vector_num; 1564 1565 for (i = 0; i < num_rxps; i++) { 1566 if (rx_info->rx_ctrl[i].ccb == NULL) 1567 continue; 1568 1569 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1570 free_irq(bnad->msix_table[vector_num].vector, 1571 rx_info->rx_ctrl[i].ccb); 1572 } 1573} 1574 1575/* NOTE: Should be called for MSIX only 1576 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1577 */ 1578static int 1579bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info, 1580 u32 rx_id, int num_rxps) 1581{ 1582 int i; 1583 int err; 1584 int vector_num; 1585 1586 for (i = 0; i < num_rxps; i++) { 1587 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1588 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d", 1589 bnad->netdev->name, 1590 rx_id + rx_info->rx_ctrl[i].ccb->id); 1591 err = request_irq(bnad->msix_table[vector_num].vector, 1592 (irq_handler_t)bnad_msix_rx, 0, 1593 rx_info->rx_ctrl[i].ccb->name, 1594 rx_info->rx_ctrl[i].ccb); 1595 if (err) 1596 goto err_return; 1597 } 1598 1599 return 0; 1600 1601err_return: 1602 if (i > 0) 1603 bnad_rx_msix_unregister(bnad, rx_info, (i - 1)); 1604 return -1; 1605} 1606 1607/* Free Tx object Resources */ 1608static void 1609bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1610{ 1611 int i; 1612 1613 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1614 if (res_info[i].res_type == BNA_RES_T_MEM) 1615 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1616 else if (res_info[i].res_type == BNA_RES_T_INTR) 1617 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1618 } 1619} 1620 1621/* Allocates memory and interrupt resources for Tx object */ 1622static int 1623bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1624 u32 tx_id) 1625{ 1626 int i, err = 0; 1627 1628 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1629 if (res_info[i].res_type == BNA_RES_T_MEM) 1630 err = bnad_mem_alloc(bnad, 1631 &res_info[i].res_u.mem_info); 1632 else if (res_info[i].res_type == BNA_RES_T_INTR) 1633 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id, 1634 &res_info[i].res_u.intr_info); 1635 if (err) 1636 goto err_return; 1637 } 1638 return 0; 1639 1640err_return: 1641 bnad_tx_res_free(bnad, res_info); 1642 return err; 1643} 1644 1645/* Free Rx object Resources */ 1646static void 1647bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1648{ 1649 int i; 1650 1651 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1652 if (res_info[i].res_type == BNA_RES_T_MEM) 1653 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1654 else if (res_info[i].res_type == BNA_RES_T_INTR) 1655 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1656 } 1657} 1658 1659/* Allocates memory and interrupt resources for Rx object */ 1660static int 1661bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1662 uint rx_id) 1663{ 1664 int i, err = 0; 1665 1666 /* All memory needs to be allocated before setup_ccbs */ 1667 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1668 if (res_info[i].res_type == BNA_RES_T_MEM) 1669 err = bnad_mem_alloc(bnad, 1670 &res_info[i].res_u.mem_info); 1671 else if (res_info[i].res_type == BNA_RES_T_INTR) 1672 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id, 1673 &res_info[i].res_u.intr_info); 1674 if (err) 1675 goto err_return; 1676 } 1677 return 0; 1678 1679err_return: 1680 bnad_rx_res_free(bnad, res_info); 1681 return err; 1682} 1683 1684/* Timer callbacks */ 1685/* a) IOC timer */ 1686static void 1687bnad_ioc_timeout(struct timer_list *t) 1688{ 1689 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.ioc_timer); 1690 unsigned long flags; 1691 1692 spin_lock_irqsave(&bnad->bna_lock, flags); 1693 bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc); 1694 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1695} 1696 1697static void 1698bnad_ioc_hb_check(struct timer_list *t) 1699{ 1700 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.hb_timer); 1701 unsigned long flags; 1702 1703 spin_lock_irqsave(&bnad->bna_lock, flags); 1704 bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc); 1705 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1706} 1707 1708static void 1709bnad_iocpf_timeout(struct timer_list *t) 1710{ 1711 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.iocpf_timer); 1712 unsigned long flags; 1713 1714 spin_lock_irqsave(&bnad->bna_lock, flags); 1715 bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc); 1716 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1717} 1718 1719static void 1720bnad_iocpf_sem_timeout(struct timer_list *t) 1721{ 1722 struct bnad *bnad = from_timer(bnad, t, bna.ioceth.ioc.sem_timer); 1723 unsigned long flags; 1724 1725 spin_lock_irqsave(&bnad->bna_lock, flags); 1726 bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc); 1727 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1728} 1729 1730/* 1731 * All timer routines use bnad->bna_lock to protect against 1732 * the following race, which may occur in case of no locking: 1733 * Time CPU m CPU n 1734 * 0 1 = test_bit 1735 * 1 clear_bit 1736 * 2 del_timer_sync 1737 * 3 mod_timer 1738 */ 1739 1740/* b) Dynamic Interrupt Moderation Timer */ 1741static void 1742bnad_dim_timeout(struct timer_list *t) 1743{ 1744 struct bnad *bnad = from_timer(bnad, t, dim_timer); 1745 struct bnad_rx_info *rx_info; 1746 struct bnad_rx_ctrl *rx_ctrl; 1747 int i, j; 1748 unsigned long flags; 1749 1750 if (!netif_carrier_ok(bnad->netdev)) 1751 return; 1752 1753 spin_lock_irqsave(&bnad->bna_lock, flags); 1754 for (i = 0; i < bnad->num_rx; i++) { 1755 rx_info = &bnad->rx_info[i]; 1756 if (!rx_info->rx) 1757 continue; 1758 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 1759 rx_ctrl = &rx_info->rx_ctrl[j]; 1760 if (!rx_ctrl->ccb) 1761 continue; 1762 bna_rx_dim_update(rx_ctrl->ccb); 1763 } 1764 } 1765 1766 /* Check for BNAD_CF_DIM_ENABLED, does not eliminate a race */ 1767 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) 1768 mod_timer(&bnad->dim_timer, 1769 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1770 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1771} 1772 1773/* c) Statistics Timer */ 1774static void 1775bnad_stats_timeout(struct timer_list *t) 1776{ 1777 struct bnad *bnad = from_timer(bnad, t, stats_timer); 1778 unsigned long flags; 1779 1780 if (!netif_running(bnad->netdev) || 1781 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1782 return; 1783 1784 spin_lock_irqsave(&bnad->bna_lock, flags); 1785 bna_hw_stats_get(&bnad->bna); 1786 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1787} 1788 1789/* 1790 * Set up timer for DIM 1791 * Called with bnad->bna_lock held 1792 */ 1793void 1794bnad_dim_timer_start(struct bnad *bnad) 1795{ 1796 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 1797 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 1798 timer_setup(&bnad->dim_timer, bnad_dim_timeout, 0); 1799 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 1800 mod_timer(&bnad->dim_timer, 1801 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1802 } 1803} 1804 1805/* 1806 * Set up timer for statistics 1807 * Called with mutex_lock(&bnad->conf_mutex) held 1808 */ 1809static void 1810bnad_stats_timer_start(struct bnad *bnad) 1811{ 1812 unsigned long flags; 1813 1814 spin_lock_irqsave(&bnad->bna_lock, flags); 1815 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) { 1816 timer_setup(&bnad->stats_timer, bnad_stats_timeout, 0); 1817 mod_timer(&bnad->stats_timer, 1818 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1819 } 1820 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1821} 1822 1823/* 1824 * Stops the stats timer 1825 * Called with mutex_lock(&bnad->conf_mutex) held 1826 */ 1827static void 1828bnad_stats_timer_stop(struct bnad *bnad) 1829{ 1830 int to_del = 0; 1831 unsigned long flags; 1832 1833 spin_lock_irqsave(&bnad->bna_lock, flags); 1834 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1835 to_del = 1; 1836 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1837 if (to_del) 1838 del_timer_sync(&bnad->stats_timer); 1839} 1840 1841/* Utilities */ 1842 1843static void 1844bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list) 1845{ 1846 int i = 1; /* Index 0 has broadcast address */ 1847 struct netdev_hw_addr *mc_addr; 1848 1849 netdev_for_each_mc_addr(mc_addr, netdev) { 1850 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]); 1851 i++; 1852 } 1853} 1854 1855static int 1856bnad_napi_poll_rx(struct napi_struct *napi, int budget) 1857{ 1858 struct bnad_rx_ctrl *rx_ctrl = 1859 container_of(napi, struct bnad_rx_ctrl, napi); 1860 struct bnad *bnad = rx_ctrl->bnad; 1861 int rcvd = 0; 1862 1863 rx_ctrl->rx_poll_ctr++; 1864 1865 if (!netif_carrier_ok(bnad->netdev)) 1866 goto poll_exit; 1867 1868 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget); 1869 if (rcvd >= budget) 1870 return rcvd; 1871 1872poll_exit: 1873 napi_complete_done(napi, rcvd); 1874 1875 rx_ctrl->rx_complete++; 1876 1877 if (rx_ctrl->ccb) 1878 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb); 1879 1880 return rcvd; 1881} 1882 1883static void 1884bnad_napi_add(struct bnad *bnad, u32 rx_id) 1885{ 1886 struct bnad_rx_ctrl *rx_ctrl; 1887 int i; 1888 1889 /* Initialize & enable NAPI */ 1890 for (i = 0; i < bnad->num_rxp_per_rx; i++) { 1891 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i]; 1892 netif_napi_add(bnad->netdev, &rx_ctrl->napi, 1893 bnad_napi_poll_rx); 1894 } 1895} 1896 1897static void 1898bnad_napi_delete(struct bnad *bnad, u32 rx_id) 1899{ 1900 int i; 1901 1902 /* First disable and then clean up */ 1903 for (i = 0; i < bnad->num_rxp_per_rx; i++) 1904 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi); 1905} 1906 1907/* Should be held with conf_lock held */ 1908void 1909bnad_destroy_tx(struct bnad *bnad, u32 tx_id) 1910{ 1911 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1912 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1913 unsigned long flags; 1914 1915 if (!tx_info->tx) 1916 return; 1917 1918 init_completion(&bnad->bnad_completions.tx_comp); 1919 spin_lock_irqsave(&bnad->bna_lock, flags); 1920 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled); 1921 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1922 wait_for_completion(&bnad->bnad_completions.tx_comp); 1923 1924 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX) 1925 bnad_tx_msix_unregister(bnad, tx_info, 1926 bnad->num_txq_per_tx); 1927 1928 spin_lock_irqsave(&bnad->bna_lock, flags); 1929 bna_tx_destroy(tx_info->tx); 1930 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1931 1932 tx_info->tx = NULL; 1933 tx_info->tx_id = 0; 1934 1935 bnad_tx_res_free(bnad, res_info); 1936} 1937 1938/* Should be held with conf_lock held */ 1939int 1940bnad_setup_tx(struct bnad *bnad, u32 tx_id) 1941{ 1942 int err; 1943 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1944 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1945 struct bna_intr_info *intr_info = 1946 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; 1947 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id]; 1948 static const struct bna_tx_event_cbfn tx_cbfn = { 1949 .tcb_setup_cbfn = bnad_cb_tcb_setup, 1950 .tcb_destroy_cbfn = bnad_cb_tcb_destroy, 1951 .tx_stall_cbfn = bnad_cb_tx_stall, 1952 .tx_resume_cbfn = bnad_cb_tx_resume, 1953 .tx_cleanup_cbfn = bnad_cb_tx_cleanup, 1954 }; 1955 1956 struct bna_tx *tx; 1957 unsigned long flags; 1958 1959 tx_info->tx_id = tx_id; 1960 1961 /* Initialize the Tx object configuration */ 1962 tx_config->num_txq = bnad->num_txq_per_tx; 1963 tx_config->txq_depth = bnad->txq_depth; 1964 tx_config->tx_type = BNA_TX_T_REGULAR; 1965 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo; 1966 1967 /* Get BNA's resource requirement for one tx object */ 1968 spin_lock_irqsave(&bnad->bna_lock, flags); 1969 bna_tx_res_req(bnad->num_txq_per_tx, 1970 bnad->txq_depth, res_info); 1971 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1972 1973 /* Fill Unmap Q memory requirements */ 1974 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ], 1975 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) * 1976 bnad->txq_depth)); 1977 1978 /* Allocate resources */ 1979 err = bnad_tx_res_alloc(bnad, res_info, tx_id); 1980 if (err) 1981 return err; 1982 1983 /* Ask BNA to create one Tx object, supplying required resources */ 1984 spin_lock_irqsave(&bnad->bna_lock, flags); 1985 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info, 1986 tx_info); 1987 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1988 if (!tx) { 1989 err = -ENOMEM; 1990 goto err_return; 1991 } 1992 tx_info->tx = tx; 1993 1994 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work, 1995 (work_func_t)bnad_tx_cleanup); 1996 1997 /* Register ISR for the Tx object */ 1998 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 1999 err = bnad_tx_msix_register(bnad, tx_info, 2000 tx_id, bnad->num_txq_per_tx); 2001 if (err) 2002 goto cleanup_tx; 2003 } 2004 2005 spin_lock_irqsave(&bnad->bna_lock, flags); 2006 bna_tx_enable(tx); 2007 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2008 2009 return 0; 2010 2011cleanup_tx: 2012 spin_lock_irqsave(&bnad->bna_lock, flags); 2013 bna_tx_destroy(tx_info->tx); 2014 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2015 tx_info->tx = NULL; 2016 tx_info->tx_id = 0; 2017err_return: 2018 bnad_tx_res_free(bnad, res_info); 2019 return err; 2020} 2021 2022/* Setup the rx config for bna_rx_create */ 2023/* bnad decides the configuration */ 2024static void 2025bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config) 2026{ 2027 memset(rx_config, 0, sizeof(*rx_config)); 2028 rx_config->rx_type = BNA_RX_T_REGULAR; 2029 rx_config->num_paths = bnad->num_rxp_per_rx; 2030 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo; 2031 2032 if (bnad->num_rxp_per_rx > 1) { 2033 rx_config->rss_status = BNA_STATUS_T_ENABLED; 2034 rx_config->rss_config.hash_type = 2035 (BFI_ENET_RSS_IPV6 | 2036 BFI_ENET_RSS_IPV6_TCP | 2037 BFI_ENET_RSS_IPV4 | 2038 BFI_ENET_RSS_IPV4_TCP); 2039 rx_config->rss_config.hash_mask = 2040 bnad->num_rxp_per_rx - 1; 2041 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key, 2042 sizeof(rx_config->rss_config.toeplitz_hash_key)); 2043 } else { 2044 rx_config->rss_status = BNA_STATUS_T_DISABLED; 2045 memset(&rx_config->rss_config, 0, 2046 sizeof(rx_config->rss_config)); 2047 } 2048 2049 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu); 2050 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED; 2051 2052 /* BNA_RXP_SINGLE - one data-buffer queue 2053 * BNA_RXP_SLR - one small-buffer and one large-buffer queues 2054 * BNA_RXP_HDS - one header-buffer and one data-buffer queues 2055 */ 2056 /* TODO: configurable param for queue type */ 2057 rx_config->rxp_type = BNA_RXP_SLR; 2058 2059 if (BNAD_PCI_DEV_IS_CAT2(bnad) && 2060 rx_config->frame_size > 4096) { 2061 /* though size_routing_enable is set in SLR, 2062 * small packets may get routed to same rxq. 2063 * set buf_size to 2048 instead of PAGE_SIZE. 2064 */ 2065 rx_config->q0_buf_size = 2048; 2066 /* this should be in multiples of 2 */ 2067 rx_config->q0_num_vecs = 4; 2068 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs; 2069 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED; 2070 } else { 2071 rx_config->q0_buf_size = rx_config->frame_size; 2072 rx_config->q0_num_vecs = 1; 2073 rx_config->q0_depth = bnad->rxq_depth; 2074 } 2075 2076 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */ 2077 if (rx_config->rxp_type == BNA_RXP_SLR) { 2078 rx_config->q1_depth = bnad->rxq_depth; 2079 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE; 2080 } 2081 2082 rx_config->vlan_strip_status = 2083 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ? 2084 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED; 2085} 2086 2087static void 2088bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id) 2089{ 2090 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2091 int i; 2092 2093 for (i = 0; i < bnad->num_rxp_per_rx; i++) 2094 rx_info->rx_ctrl[i].bnad = bnad; 2095} 2096 2097/* Called with mutex_lock(&bnad->conf_mutex) held */ 2098static u32 2099bnad_reinit_rx(struct bnad *bnad) 2100{ 2101 struct net_device *netdev = bnad->netdev; 2102 u32 err = 0, current_err = 0; 2103 u32 rx_id = 0, count = 0; 2104 unsigned long flags; 2105 2106 /* destroy and create new rx objects */ 2107 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { 2108 if (!bnad->rx_info[rx_id].rx) 2109 continue; 2110 bnad_destroy_rx(bnad, rx_id); 2111 } 2112 2113 spin_lock_irqsave(&bnad->bna_lock, flags); 2114 bna_enet_mtu_set(&bnad->bna.enet, 2115 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); 2116 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2117 2118 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) { 2119 count++; 2120 current_err = bnad_setup_rx(bnad, rx_id); 2121 if (current_err && !err) { 2122 err = current_err; 2123 netdev_err(netdev, "RXQ:%u setup failed\n", rx_id); 2124 } 2125 } 2126 2127 /* restore rx configuration */ 2128 if (bnad->rx_info[0].rx && !err) { 2129 bnad_restore_vlans(bnad, 0); 2130 bnad_enable_default_bcast(bnad); 2131 spin_lock_irqsave(&bnad->bna_lock, flags); 2132 bnad_mac_addr_set_locked(bnad, netdev->dev_addr); 2133 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2134 bnad_set_rx_mode(netdev); 2135 } 2136 2137 return count; 2138} 2139 2140/* Called with bnad_conf_lock() held */ 2141void 2142bnad_destroy_rx(struct bnad *bnad, u32 rx_id) 2143{ 2144 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2145 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 2146 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 2147 unsigned long flags; 2148 int to_del = 0; 2149 2150 if (!rx_info->rx) 2151 return; 2152 2153 if (0 == rx_id) { 2154 spin_lock_irqsave(&bnad->bna_lock, flags); 2155 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 2156 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 2157 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 2158 to_del = 1; 2159 } 2160 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2161 if (to_del) 2162 del_timer_sync(&bnad->dim_timer); 2163 } 2164 2165 init_completion(&bnad->bnad_completions.rx_comp); 2166 spin_lock_irqsave(&bnad->bna_lock, flags); 2167 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled); 2168 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2169 wait_for_completion(&bnad->bnad_completions.rx_comp); 2170 2171 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX) 2172 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths); 2173 2174 bnad_napi_delete(bnad, rx_id); 2175 2176 spin_lock_irqsave(&bnad->bna_lock, flags); 2177 bna_rx_destroy(rx_info->rx); 2178 2179 rx_info->rx = NULL; 2180 rx_info->rx_id = 0; 2181 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2182 2183 bnad_rx_res_free(bnad, res_info); 2184} 2185 2186/* Called with mutex_lock(&bnad->conf_mutex) held */ 2187int 2188bnad_setup_rx(struct bnad *bnad, u32 rx_id) 2189{ 2190 int err; 2191 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2192 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 2193 struct bna_intr_info *intr_info = 2194 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; 2195 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 2196 static const struct bna_rx_event_cbfn rx_cbfn = { 2197 .rcb_setup_cbfn = NULL, 2198 .rcb_destroy_cbfn = NULL, 2199 .ccb_setup_cbfn = bnad_cb_ccb_setup, 2200 .ccb_destroy_cbfn = bnad_cb_ccb_destroy, 2201 .rx_stall_cbfn = bnad_cb_rx_stall, 2202 .rx_cleanup_cbfn = bnad_cb_rx_cleanup, 2203 .rx_post_cbfn = bnad_cb_rx_post, 2204 }; 2205 struct bna_rx *rx; 2206 unsigned long flags; 2207 2208 rx_info->rx_id = rx_id; 2209 2210 /* Initialize the Rx object configuration */ 2211 bnad_init_rx_config(bnad, rx_config); 2212 2213 /* Get BNA's resource requirement for one Rx object */ 2214 spin_lock_irqsave(&bnad->bna_lock, flags); 2215 bna_rx_res_req(rx_config, res_info); 2216 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2217 2218 /* Fill Unmap Q memory requirements */ 2219 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ], 2220 rx_config->num_paths, 2221 (rx_config->q0_depth * 2222 sizeof(struct bnad_rx_unmap)) + 2223 sizeof(struct bnad_rx_unmap_q)); 2224 2225 if (rx_config->rxp_type != BNA_RXP_SINGLE) { 2226 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ], 2227 rx_config->num_paths, 2228 (rx_config->q1_depth * 2229 sizeof(struct bnad_rx_unmap) + 2230 sizeof(struct bnad_rx_unmap_q))); 2231 } 2232 /* Allocate resource */ 2233 err = bnad_rx_res_alloc(bnad, res_info, rx_id); 2234 if (err) 2235 return err; 2236 2237 bnad_rx_ctrl_init(bnad, rx_id); 2238 2239 /* Ask BNA to create one Rx object, supplying required resources */ 2240 spin_lock_irqsave(&bnad->bna_lock, flags); 2241 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info, 2242 rx_info); 2243 if (!rx) { 2244 err = -ENOMEM; 2245 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2246 goto err_return; 2247 } 2248 rx_info->rx = rx; 2249 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2250 2251 INIT_WORK(&rx_info->rx_cleanup_work, 2252 (work_func_t)(bnad_rx_cleanup)); 2253 2254 /* 2255 * Init NAPI, so that state is set to NAPI_STATE_SCHED, 2256 * so that IRQ handler cannot schedule NAPI at this point. 2257 */ 2258 bnad_napi_add(bnad, rx_id); 2259 2260 /* Register ISR for the Rx object */ 2261 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 2262 err = bnad_rx_msix_register(bnad, rx_info, rx_id, 2263 rx_config->num_paths); 2264 if (err) 2265 goto err_return; 2266 } 2267 2268 spin_lock_irqsave(&bnad->bna_lock, flags); 2269 if (0 == rx_id) { 2270 /* Set up Dynamic Interrupt Moderation Vector */ 2271 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) 2272 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector); 2273 2274 /* Enable VLAN filtering only on the default Rx */ 2275 bna_rx_vlanfilter_enable(rx); 2276 2277 /* Start the DIM timer */ 2278 bnad_dim_timer_start(bnad); 2279 } 2280 2281 bna_rx_enable(rx); 2282 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2283 2284 return 0; 2285 2286err_return: 2287 bnad_destroy_rx(bnad, rx_id); 2288 return err; 2289} 2290 2291/* Called with conf_lock & bnad->bna_lock held */ 2292void 2293bnad_tx_coalescing_timeo_set(struct bnad *bnad) 2294{ 2295 struct bnad_tx_info *tx_info; 2296 2297 tx_info = &bnad->tx_info[0]; 2298 if (!tx_info->tx) 2299 return; 2300 2301 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo); 2302} 2303 2304/* Called with conf_lock & bnad->bna_lock held */ 2305void 2306bnad_rx_coalescing_timeo_set(struct bnad *bnad) 2307{ 2308 struct bnad_rx_info *rx_info; 2309 int i; 2310 2311 for (i = 0; i < bnad->num_rx; i++) { 2312 rx_info = &bnad->rx_info[i]; 2313 if (!rx_info->rx) 2314 continue; 2315 bna_rx_coalescing_timeo_set(rx_info->rx, 2316 bnad->rx_coalescing_timeo); 2317 } 2318} 2319 2320/* 2321 * Called with bnad->bna_lock held 2322 */ 2323int 2324bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr) 2325{ 2326 int ret; 2327 2328 if (!is_valid_ether_addr(mac_addr)) 2329 return -EADDRNOTAVAIL; 2330 2331 /* If datapath is down, pretend everything went through */ 2332 if (!bnad->rx_info[0].rx) 2333 return 0; 2334 2335 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr); 2336 if (ret != BNA_CB_SUCCESS) 2337 return -EADDRNOTAVAIL; 2338 2339 return 0; 2340} 2341 2342/* Should be called with conf_lock held */ 2343int 2344bnad_enable_default_bcast(struct bnad *bnad) 2345{ 2346 struct bnad_rx_info *rx_info = &bnad->rx_info[0]; 2347 int ret; 2348 unsigned long flags; 2349 2350 init_completion(&bnad->bnad_completions.mcast_comp); 2351 2352 spin_lock_irqsave(&bnad->bna_lock, flags); 2353 ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr, 2354 bnad_cb_rx_mcast_add); 2355 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2356 2357 if (ret == BNA_CB_SUCCESS) 2358 wait_for_completion(&bnad->bnad_completions.mcast_comp); 2359 else 2360 return -ENODEV; 2361 2362 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS) 2363 return -ENODEV; 2364 2365 return 0; 2366} 2367 2368/* Called with mutex_lock(&bnad->conf_mutex) held */ 2369void 2370bnad_restore_vlans(struct bnad *bnad, u32 rx_id) 2371{ 2372 u16 vid; 2373 unsigned long flags; 2374 2375 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) { 2376 spin_lock_irqsave(&bnad->bna_lock, flags); 2377 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid); 2378 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2379 } 2380} 2381 2382/* Statistics utilities */ 2383void 2384bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2385{ 2386 int i, j; 2387 2388 for (i = 0; i < bnad->num_rx; i++) { 2389 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 2390 if (bnad->rx_info[i].rx_ctrl[j].ccb) { 2391 stats->rx_packets += bnad->rx_info[i]. 2392 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets; 2393 stats->rx_bytes += bnad->rx_info[i]. 2394 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes; 2395 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] && 2396 bnad->rx_info[i].rx_ctrl[j].ccb-> 2397 rcb[1]->rxq) { 2398 stats->rx_packets += 2399 bnad->rx_info[i].rx_ctrl[j]. 2400 ccb->rcb[1]->rxq->rx_packets; 2401 stats->rx_bytes += 2402 bnad->rx_info[i].rx_ctrl[j]. 2403 ccb->rcb[1]->rxq->rx_bytes; 2404 } 2405 } 2406 } 2407 } 2408 for (i = 0; i < bnad->num_tx; i++) { 2409 for (j = 0; j < bnad->num_txq_per_tx; j++) { 2410 if (bnad->tx_info[i].tcb[j]) { 2411 stats->tx_packets += 2412 bnad->tx_info[i].tcb[j]->txq->tx_packets; 2413 stats->tx_bytes += 2414 bnad->tx_info[i].tcb[j]->txq->tx_bytes; 2415 } 2416 } 2417 } 2418} 2419 2420/* 2421 * Must be called with the bna_lock held. 2422 */ 2423void 2424bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2425{ 2426 struct bfi_enet_stats_mac *mac_stats; 2427 u32 bmap; 2428 int i; 2429 2430 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats; 2431 stats->rx_errors = 2432 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error + 2433 mac_stats->rx_frame_length_error + mac_stats->rx_code_error + 2434 mac_stats->rx_undersize; 2435 stats->tx_errors = mac_stats->tx_fcs_error + 2436 mac_stats->tx_undersize; 2437 stats->rx_dropped = mac_stats->rx_drop; 2438 stats->tx_dropped = mac_stats->tx_drop; 2439 stats->multicast = mac_stats->rx_multicast; 2440 stats->collisions = mac_stats->tx_total_collision; 2441 2442 stats->rx_length_errors = mac_stats->rx_frame_length_error; 2443 2444 /* receive ring buffer overflow ?? */ 2445 2446 stats->rx_crc_errors = mac_stats->rx_fcs_error; 2447 stats->rx_frame_errors = mac_stats->rx_alignment_error; 2448 /* recv'r fifo overrun */ 2449 bmap = bna_rx_rid_mask(&bnad->bna); 2450 for (i = 0; bmap; i++) { 2451 if (bmap & 1) { 2452 stats->rx_fifo_errors += 2453 bnad->stats.bna_stats-> 2454 hw_stats.rxf_stats[i].frame_drops; 2455 break; 2456 } 2457 bmap >>= 1; 2458 } 2459} 2460 2461static void 2462bnad_mbox_irq_sync(struct bnad *bnad) 2463{ 2464 u32 irq; 2465 unsigned long flags; 2466 2467 spin_lock_irqsave(&bnad->bna_lock, flags); 2468 if (bnad->cfg_flags & BNAD_CF_MSIX) 2469 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 2470 else 2471 irq = bnad->pcidev->irq; 2472 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2473 2474 synchronize_irq(irq); 2475} 2476 2477/* Utility used by bnad_start_xmit, for doing TSO */ 2478static int 2479bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb) 2480{ 2481 int err; 2482 2483 err = skb_cow_head(skb, 0); 2484 if (err < 0) { 2485 BNAD_UPDATE_CTR(bnad, tso_err); 2486 return err; 2487 } 2488 2489 /* 2490 * For TSO, the TCP checksum field is seeded with pseudo-header sum 2491 * excluding the length field. 2492 */ 2493 if (vlan_get_protocol(skb) == htons(ETH_P_IP)) { 2494 struct iphdr *iph = ip_hdr(skb); 2495 2496 /* Do we really need these? */ 2497 iph->tot_len = 0; 2498 iph->check = 0; 2499 2500 tcp_hdr(skb)->check = 2501 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 2502 IPPROTO_TCP, 0); 2503 BNAD_UPDATE_CTR(bnad, tso4); 2504 } else { 2505 tcp_v6_gso_csum_prep(skb); 2506 BNAD_UPDATE_CTR(bnad, tso6); 2507 } 2508 2509 return 0; 2510} 2511 2512/* 2513 * Initialize Q numbers depending on Rx Paths 2514 * Called with bnad->bna_lock held, because of cfg_flags 2515 * access. 2516 */ 2517static void 2518bnad_q_num_init(struct bnad *bnad) 2519{ 2520 int rxps; 2521 2522 rxps = min((uint)num_online_cpus(), 2523 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX)); 2524 2525 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) 2526 rxps = 1; /* INTx */ 2527 2528 bnad->num_rx = 1; 2529 bnad->num_tx = 1; 2530 bnad->num_rxp_per_rx = rxps; 2531 bnad->num_txq_per_tx = BNAD_TXQ_NUM; 2532} 2533 2534/* 2535 * Adjusts the Q numbers, given a number of msix vectors 2536 * Give preference to RSS as opposed to Tx priority Queues, 2537 * in such a case, just use 1 Tx Q 2538 * Called with bnad->bna_lock held b'cos of cfg_flags access 2539 */ 2540static void 2541bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp) 2542{ 2543 bnad->num_txq_per_tx = 1; 2544 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) + 2545 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) && 2546 (bnad->cfg_flags & BNAD_CF_MSIX)) { 2547 bnad->num_rxp_per_rx = msix_vectors - 2548 (bnad->num_tx * bnad->num_txq_per_tx) - 2549 BNAD_MAILBOX_MSIX_VECTORS; 2550 } else 2551 bnad->num_rxp_per_rx = 1; 2552} 2553 2554/* Enable / disable ioceth */ 2555static int 2556bnad_ioceth_disable(struct bnad *bnad) 2557{ 2558 unsigned long flags; 2559 int err = 0; 2560 2561 spin_lock_irqsave(&bnad->bna_lock, flags); 2562 init_completion(&bnad->bnad_completions.ioc_comp); 2563 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP); 2564 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2565 2566 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2567 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2568 2569 err = bnad->bnad_completions.ioc_comp_status; 2570 return err; 2571} 2572 2573static int 2574bnad_ioceth_enable(struct bnad *bnad) 2575{ 2576 int err = 0; 2577 unsigned long flags; 2578 2579 spin_lock_irqsave(&bnad->bna_lock, flags); 2580 init_completion(&bnad->bnad_completions.ioc_comp); 2581 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING; 2582 bna_ioceth_enable(&bnad->bna.ioceth); 2583 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2584 2585 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2586 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2587 2588 err = bnad->bnad_completions.ioc_comp_status; 2589 2590 return err; 2591} 2592 2593/* Free BNA resources */ 2594static void 2595bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info, 2596 u32 res_val_max) 2597{ 2598 int i; 2599 2600 for (i = 0; i < res_val_max; i++) 2601 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 2602} 2603 2604/* Allocates memory and interrupt resources for BNA */ 2605static int 2606bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 2607 u32 res_val_max) 2608{ 2609 int i, err; 2610 2611 for (i = 0; i < res_val_max; i++) { 2612 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info); 2613 if (err) 2614 goto err_return; 2615 } 2616 return 0; 2617 2618err_return: 2619 bnad_res_free(bnad, res_info, res_val_max); 2620 return err; 2621} 2622 2623/* Interrupt enable / disable */ 2624static void 2625bnad_enable_msix(struct bnad *bnad) 2626{ 2627 int i, ret; 2628 unsigned long flags; 2629 2630 spin_lock_irqsave(&bnad->bna_lock, flags); 2631 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 2632 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2633 return; 2634 } 2635 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2636 2637 if (bnad->msix_table) 2638 return; 2639 2640 bnad->msix_table = 2641 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL); 2642 2643 if (!bnad->msix_table) 2644 goto intx_mode; 2645 2646 for (i = 0; i < bnad->msix_num; i++) 2647 bnad->msix_table[i].entry = i; 2648 2649 ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table, 2650 1, bnad->msix_num); 2651 if (ret < 0) { 2652 goto intx_mode; 2653 } else if (ret < bnad->msix_num) { 2654 dev_warn(&bnad->pcidev->dev, 2655 "%d MSI-X vectors allocated < %d requested\n", 2656 ret, bnad->msix_num); 2657 2658 spin_lock_irqsave(&bnad->bna_lock, flags); 2659 /* ret = #of vectors that we got */ 2660 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2, 2661 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2); 2662 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2663 2664 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP + 2665 BNAD_MAILBOX_MSIX_VECTORS; 2666 2667 if (bnad->msix_num > ret) { 2668 pci_disable_msix(bnad->pcidev); 2669 goto intx_mode; 2670 } 2671 } 2672 2673 pci_intx(bnad->pcidev, 0); 2674 2675 return; 2676 2677intx_mode: 2678 dev_warn(&bnad->pcidev->dev, 2679 "MSI-X enable failed - operating in INTx mode\n"); 2680 2681 kfree(bnad->msix_table); 2682 bnad->msix_table = NULL; 2683 bnad->msix_num = 0; 2684 spin_lock_irqsave(&bnad->bna_lock, flags); 2685 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2686 bnad_q_num_init(bnad); 2687 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2688} 2689 2690static void 2691bnad_disable_msix(struct bnad *bnad) 2692{ 2693 u32 cfg_flags; 2694 unsigned long flags; 2695 2696 spin_lock_irqsave(&bnad->bna_lock, flags); 2697 cfg_flags = bnad->cfg_flags; 2698 if (bnad->cfg_flags & BNAD_CF_MSIX) 2699 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2700 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2701 2702 if (cfg_flags & BNAD_CF_MSIX) { 2703 pci_disable_msix(bnad->pcidev); 2704 kfree(bnad->msix_table); 2705 bnad->msix_table = NULL; 2706 } 2707} 2708 2709/* Netdev entry points */ 2710static int 2711bnad_open(struct net_device *netdev) 2712{ 2713 int err; 2714 struct bnad *bnad = netdev_priv(netdev); 2715 struct bna_pause_config pause_config; 2716 unsigned long flags; 2717 2718 mutex_lock(&bnad->conf_mutex); 2719 2720 /* Tx */ 2721 err = bnad_setup_tx(bnad, 0); 2722 if (err) 2723 goto err_return; 2724 2725 /* Rx */ 2726 err = bnad_setup_rx(bnad, 0); 2727 if (err) 2728 goto cleanup_tx; 2729 2730 /* Port */ 2731 pause_config.tx_pause = 0; 2732 pause_config.rx_pause = 0; 2733 2734 spin_lock_irqsave(&bnad->bna_lock, flags); 2735 bna_enet_mtu_set(&bnad->bna.enet, 2736 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL); 2737 bna_enet_pause_config(&bnad->bna.enet, &pause_config); 2738 bna_enet_enable(&bnad->bna.enet); 2739 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2740 2741 /* Enable broadcast */ 2742 bnad_enable_default_bcast(bnad); 2743 2744 /* Restore VLANs, if any */ 2745 bnad_restore_vlans(bnad, 0); 2746 2747 /* Set the UCAST address */ 2748 spin_lock_irqsave(&bnad->bna_lock, flags); 2749 bnad_mac_addr_set_locked(bnad, netdev->dev_addr); 2750 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2751 2752 /* Start the stats timer */ 2753 bnad_stats_timer_start(bnad); 2754 2755 mutex_unlock(&bnad->conf_mutex); 2756 2757 return 0; 2758 2759cleanup_tx: 2760 bnad_destroy_tx(bnad, 0); 2761 2762err_return: 2763 mutex_unlock(&bnad->conf_mutex); 2764 return err; 2765} 2766 2767static int 2768bnad_stop(struct net_device *netdev) 2769{ 2770 struct bnad *bnad = netdev_priv(netdev); 2771 unsigned long flags; 2772 2773 mutex_lock(&bnad->conf_mutex); 2774 2775 /* Stop the stats timer */ 2776 bnad_stats_timer_stop(bnad); 2777 2778 init_completion(&bnad->bnad_completions.enet_comp); 2779 2780 spin_lock_irqsave(&bnad->bna_lock, flags); 2781 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP, 2782 bnad_cb_enet_disabled); 2783 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2784 2785 wait_for_completion(&bnad->bnad_completions.enet_comp); 2786 2787 bnad_destroy_tx(bnad, 0); 2788 bnad_destroy_rx(bnad, 0); 2789 2790 /* Synchronize mailbox IRQ */ 2791 bnad_mbox_irq_sync(bnad); 2792 2793 mutex_unlock(&bnad->conf_mutex); 2794 2795 return 0; 2796} 2797 2798/* TX */ 2799/* Returns 0 for success */ 2800static int 2801bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb, 2802 struct sk_buff *skb, struct bna_txq_entry *txqent) 2803{ 2804 u16 flags = 0; 2805 u32 gso_size; 2806 u16 vlan_tag = 0; 2807 2808 if (skb_vlan_tag_present(skb)) { 2809 vlan_tag = (u16)skb_vlan_tag_get(skb); 2810 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2811 } 2812 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) { 2813 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT) 2814 | (vlan_tag & 0x1fff); 2815 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2816 } 2817 txqent->hdr.wi.vlan_tag = htons(vlan_tag); 2818 2819 if (skb_is_gso(skb)) { 2820 gso_size = skb_shinfo(skb)->gso_size; 2821 if (unlikely(gso_size > bnad->netdev->mtu)) { 2822 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long); 2823 return -EINVAL; 2824 } 2825 if (unlikely((gso_size + skb_tcp_all_headers(skb)) >= skb->len)) { 2826 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); 2827 txqent->hdr.wi.lso_mss = 0; 2828 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short); 2829 } else { 2830 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO); 2831 txqent->hdr.wi.lso_mss = htons(gso_size); 2832 } 2833 2834 if (bnad_tso_prepare(bnad, skb)) { 2835 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare); 2836 return -EINVAL; 2837 } 2838 2839 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM); 2840 txqent->hdr.wi.l4_hdr_size_n_offset = 2841 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET( 2842 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb))); 2843 } else { 2844 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND); 2845 txqent->hdr.wi.lso_mss = 0; 2846 2847 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) { 2848 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long); 2849 return -EINVAL; 2850 } 2851 2852 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2853 __be16 net_proto = vlan_get_protocol(skb); 2854 u8 proto = 0; 2855 2856 if (net_proto == htons(ETH_P_IP)) 2857 proto = ip_hdr(skb)->protocol; 2858#ifdef NETIF_F_IPV6_CSUM 2859 else if (net_proto == htons(ETH_P_IPV6)) { 2860 /* nexthdr may not be TCP immediately. */ 2861 proto = ipv6_hdr(skb)->nexthdr; 2862 } 2863#endif 2864 if (proto == IPPROTO_TCP) { 2865 flags |= BNA_TXQ_WI_CF_TCP_CKSUM; 2866 txqent->hdr.wi.l4_hdr_size_n_offset = 2867 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2868 (0, skb_transport_offset(skb))); 2869 2870 BNAD_UPDATE_CTR(bnad, tcpcsum_offload); 2871 2872 if (unlikely(skb_headlen(skb) < 2873 skb_tcp_all_headers(skb))) { 2874 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr); 2875 return -EINVAL; 2876 } 2877 } else if (proto == IPPROTO_UDP) { 2878 flags |= BNA_TXQ_WI_CF_UDP_CKSUM; 2879 txqent->hdr.wi.l4_hdr_size_n_offset = 2880 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2881 (0, skb_transport_offset(skb))); 2882 2883 BNAD_UPDATE_CTR(bnad, udpcsum_offload); 2884 if (unlikely(skb_headlen(skb) < 2885 skb_transport_offset(skb) + 2886 sizeof(struct udphdr))) { 2887 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr); 2888 return -EINVAL; 2889 } 2890 } else { 2891 2892 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err); 2893 return -EINVAL; 2894 } 2895 } else 2896 txqent->hdr.wi.l4_hdr_size_n_offset = 0; 2897 } 2898 2899 txqent->hdr.wi.flags = htons(flags); 2900 txqent->hdr.wi.frame_length = htonl(skb->len); 2901 2902 return 0; 2903} 2904 2905/* 2906 * bnad_start_xmit : Netdev entry point for Transmit 2907 * Called under lock held by net_device 2908 */ 2909static netdev_tx_t 2910bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2911{ 2912 struct bnad *bnad = netdev_priv(netdev); 2913 u32 txq_id = 0; 2914 struct bna_tcb *tcb = NULL; 2915 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap; 2916 u32 prod, q_depth, vect_id; 2917 u32 wis, vectors, len; 2918 int i; 2919 dma_addr_t dma_addr; 2920 struct bna_txq_entry *txqent; 2921 2922 len = skb_headlen(skb); 2923 2924 /* Sanity checks for the skb */ 2925 2926 if (unlikely(skb->len <= ETH_HLEN)) { 2927 dev_kfree_skb_any(skb); 2928 BNAD_UPDATE_CTR(bnad, tx_skb_too_short); 2929 return NETDEV_TX_OK; 2930 } 2931 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) { 2932 dev_kfree_skb_any(skb); 2933 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2934 return NETDEV_TX_OK; 2935 } 2936 if (unlikely(len == 0)) { 2937 dev_kfree_skb_any(skb); 2938 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2939 return NETDEV_TX_OK; 2940 } 2941 2942 tcb = bnad->tx_info[0].tcb[txq_id]; 2943 2944 /* 2945 * Takes care of the Tx that is scheduled between clearing the flag 2946 * and the netif_tx_stop_all_queues() call. 2947 */ 2948 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) { 2949 dev_kfree_skb_any(skb); 2950 BNAD_UPDATE_CTR(bnad, tx_skb_stopping); 2951 return NETDEV_TX_OK; 2952 } 2953 2954 q_depth = tcb->q_depth; 2955 prod = tcb->producer_index; 2956 unmap_q = tcb->unmap_q; 2957 2958 vectors = 1 + skb_shinfo(skb)->nr_frags; 2959 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */ 2960 2961 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) { 2962 dev_kfree_skb_any(skb); 2963 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors); 2964 return NETDEV_TX_OK; 2965 } 2966 2967 /* Check for available TxQ resources */ 2968 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2969 if ((*tcb->hw_consumer_index != tcb->consumer_index) && 2970 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 2971 u32 sent; 2972 sent = bnad_txcmpl_process(bnad, tcb); 2973 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 2974 bna_ib_ack(tcb->i_dbell, sent); 2975 smp_mb__before_atomic(); 2976 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 2977 } else { 2978 netif_stop_queue(netdev); 2979 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2980 } 2981 2982 smp_mb(); 2983 /* 2984 * Check again to deal with race condition between 2985 * netif_stop_queue here, and netif_wake_queue in 2986 * interrupt handler which is not inside netif tx lock. 2987 */ 2988 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2989 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2990 return NETDEV_TX_BUSY; 2991 } else { 2992 netif_wake_queue(netdev); 2993 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 2994 } 2995 } 2996 2997 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 2998 head_unmap = &unmap_q[prod]; 2999 3000 /* Program the opcode, flags, frame_len, num_vectors in WI */ 3001 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) { 3002 dev_kfree_skb_any(skb); 3003 return NETDEV_TX_OK; 3004 } 3005 txqent->hdr.wi.reserved = 0; 3006 txqent->hdr.wi.num_vectors = vectors; 3007 3008 head_unmap->skb = skb; 3009 head_unmap->nvecs = 0; 3010 3011 /* Program the vectors */ 3012 unmap = head_unmap; 3013 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 3014 len, DMA_TO_DEVICE); 3015 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 3016 dev_kfree_skb_any(skb); 3017 BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); 3018 return NETDEV_TX_OK; 3019 } 3020 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr); 3021 txqent->vector[0].length = htons(len); 3022 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr); 3023 head_unmap->nvecs++; 3024 3025 for (i = 0, vect_id = 0; i < vectors - 1; i++) { 3026 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3027 u32 size = skb_frag_size(frag); 3028 3029 if (unlikely(size == 0)) { 3030 /* Undo the changes starting at tcb->producer_index */ 3031 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, 3032 tcb->producer_index); 3033 dev_kfree_skb_any(skb); 3034 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero); 3035 return NETDEV_TX_OK; 3036 } 3037 3038 len += size; 3039 3040 vect_id++; 3041 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) { 3042 vect_id = 0; 3043 BNA_QE_INDX_INC(prod, q_depth); 3044 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 3045 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION); 3046 unmap = &unmap_q[prod]; 3047 } 3048 3049 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag, 3050 0, size, DMA_TO_DEVICE); 3051 if (dma_mapping_error(&bnad->pcidev->dev, dma_addr)) { 3052 /* Undo the changes starting at tcb->producer_index */ 3053 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, 3054 tcb->producer_index); 3055 dev_kfree_skb_any(skb); 3056 BNAD_UPDATE_CTR(bnad, tx_skb_map_failed); 3057 return NETDEV_TX_OK; 3058 } 3059 3060 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size); 3061 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); 3062 txqent->vector[vect_id].length = htons(size); 3063 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr, 3064 dma_addr); 3065 head_unmap->nvecs++; 3066 } 3067 3068 if (unlikely(len != skb->len)) { 3069 /* Undo the changes starting at tcb->producer_index */ 3070 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index); 3071 dev_kfree_skb_any(skb); 3072 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch); 3073 return NETDEV_TX_OK; 3074 } 3075 3076 BNA_QE_INDX_INC(prod, q_depth); 3077 tcb->producer_index = prod; 3078 3079 wmb(); 3080 3081 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 3082 return NETDEV_TX_OK; 3083 3084 skb_tx_timestamp(skb); 3085 3086 bna_txq_prod_indx_doorbell(tcb); 3087 3088 return NETDEV_TX_OK; 3089} 3090 3091/* 3092 * Used spin_lock to synchronize reading of stats structures, which 3093 * is written by BNA under the same lock. 3094 */ 3095static void 3096bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats) 3097{ 3098 struct bnad *bnad = netdev_priv(netdev); 3099 unsigned long flags; 3100 3101 spin_lock_irqsave(&bnad->bna_lock, flags); 3102 3103 bnad_netdev_qstats_fill(bnad, stats); 3104 bnad_netdev_hwstats_fill(bnad, stats); 3105 3106 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3107} 3108 3109static void 3110bnad_set_rx_ucast_fltr(struct bnad *bnad) 3111{ 3112 struct net_device *netdev = bnad->netdev; 3113 int uc_count = netdev_uc_count(netdev); 3114 enum bna_cb_status ret; 3115 u8 *mac_list; 3116 struct netdev_hw_addr *ha; 3117 int entry; 3118 3119 if (netdev_uc_empty(bnad->netdev)) { 3120 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); 3121 return; 3122 } 3123 3124 if (uc_count > bna_attr(&bnad->bna)->num_ucmac) 3125 goto mode_default; 3126 3127 mac_list = kcalloc(ETH_ALEN, uc_count, GFP_ATOMIC); 3128 if (mac_list == NULL) 3129 goto mode_default; 3130 3131 entry = 0; 3132 netdev_for_each_uc_addr(ha, netdev) { 3133 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]); 3134 entry++; 3135 } 3136 3137 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list); 3138 kfree(mac_list); 3139 3140 if (ret != BNA_CB_SUCCESS) 3141 goto mode_default; 3142 3143 return; 3144 3145 /* ucast packets not in UCAM are routed to default function */ 3146mode_default: 3147 bnad->cfg_flags |= BNAD_CF_DEFAULT; 3148 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL); 3149} 3150 3151static void 3152bnad_set_rx_mcast_fltr(struct bnad *bnad) 3153{ 3154 struct net_device *netdev = bnad->netdev; 3155 int mc_count = netdev_mc_count(netdev); 3156 enum bna_cb_status ret; 3157 u8 *mac_list; 3158 3159 if (netdev->flags & IFF_ALLMULTI) 3160 goto mode_allmulti; 3161 3162 if (netdev_mc_empty(netdev)) 3163 return; 3164 3165 if (mc_count > bna_attr(&bnad->bna)->num_mcmac) 3166 goto mode_allmulti; 3167 3168 mac_list = kcalloc(mc_count + 1, ETH_ALEN, GFP_ATOMIC); 3169 3170 if (mac_list == NULL) 3171 goto mode_allmulti; 3172 3173 ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]); 3174 3175 /* copy rest of the MCAST addresses */ 3176 bnad_netdev_mc_list_get(netdev, mac_list); 3177 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list); 3178 kfree(mac_list); 3179 3180 if (ret != BNA_CB_SUCCESS) 3181 goto mode_allmulti; 3182 3183 return; 3184 3185mode_allmulti: 3186 bnad->cfg_flags |= BNAD_CF_ALLMULTI; 3187 bna_rx_mcast_delall(bnad->rx_info[0].rx); 3188} 3189 3190void 3191bnad_set_rx_mode(struct net_device *netdev) 3192{ 3193 struct bnad *bnad = netdev_priv(netdev); 3194 enum bna_rxmode new_mode, mode_mask; 3195 unsigned long flags; 3196 3197 spin_lock_irqsave(&bnad->bna_lock, flags); 3198 3199 if (bnad->rx_info[0].rx == NULL) { 3200 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3201 return; 3202 } 3203 3204 /* clear bnad flags to update it with new settings */ 3205 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT | 3206 BNAD_CF_ALLMULTI); 3207 3208 new_mode = 0; 3209 if (netdev->flags & IFF_PROMISC) { 3210 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT; 3211 bnad->cfg_flags |= BNAD_CF_PROMISC; 3212 } else { 3213 bnad_set_rx_mcast_fltr(bnad); 3214 3215 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) 3216 new_mode |= BNA_RXMODE_ALLMULTI; 3217 3218 bnad_set_rx_ucast_fltr(bnad); 3219 3220 if (bnad->cfg_flags & BNAD_CF_DEFAULT) 3221 new_mode |= BNA_RXMODE_DEFAULT; 3222 } 3223 3224 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT | 3225 BNA_RXMODE_ALLMULTI; 3226 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask); 3227 3228 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3229} 3230 3231/* 3232 * bna_lock is used to sync writes to netdev->addr 3233 * conf_lock cannot be used since this call may be made 3234 * in a non-blocking context. 3235 */ 3236static int 3237bnad_set_mac_address(struct net_device *netdev, void *addr) 3238{ 3239 int err; 3240 struct bnad *bnad = netdev_priv(netdev); 3241 struct sockaddr *sa = (struct sockaddr *)addr; 3242 unsigned long flags; 3243 3244 spin_lock_irqsave(&bnad->bna_lock, flags); 3245 3246 err = bnad_mac_addr_set_locked(bnad, sa->sa_data); 3247 if (!err) 3248 eth_hw_addr_set(netdev, sa->sa_data); 3249 3250 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3251 3252 return err; 3253} 3254 3255static int 3256bnad_mtu_set(struct bnad *bnad, int frame_size) 3257{ 3258 unsigned long flags; 3259 3260 init_completion(&bnad->bnad_completions.mtu_comp); 3261 3262 spin_lock_irqsave(&bnad->bna_lock, flags); 3263 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set); 3264 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3265 3266 wait_for_completion(&bnad->bnad_completions.mtu_comp); 3267 3268 return bnad->bnad_completions.mtu_comp_status; 3269} 3270 3271static int 3272bnad_change_mtu(struct net_device *netdev, int new_mtu) 3273{ 3274 int err, mtu; 3275 struct bnad *bnad = netdev_priv(netdev); 3276 u32 frame, new_frame; 3277 3278 mutex_lock(&bnad->conf_mutex); 3279 3280 mtu = netdev->mtu; 3281 netdev->mtu = new_mtu; 3282 3283 frame = BNAD_FRAME_SIZE(mtu); 3284 new_frame = BNAD_FRAME_SIZE(new_mtu); 3285 3286 /* check if multi-buffer needs to be enabled */ 3287 if (BNAD_PCI_DEV_IS_CAT2(bnad) && 3288 netif_running(bnad->netdev)) { 3289 /* only when transition is over 4K */ 3290 if ((frame <= 4096 && new_frame > 4096) || 3291 (frame > 4096 && new_frame <= 4096)) 3292 bnad_reinit_rx(bnad); 3293 } 3294 3295 err = bnad_mtu_set(bnad, new_frame); 3296 if (err) 3297 err = -EBUSY; 3298 3299 mutex_unlock(&bnad->conf_mutex); 3300 return err; 3301} 3302 3303static int 3304bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 3305{ 3306 struct bnad *bnad = netdev_priv(netdev); 3307 unsigned long flags; 3308 3309 if (!bnad->rx_info[0].rx) 3310 return 0; 3311 3312 mutex_lock(&bnad->conf_mutex); 3313 3314 spin_lock_irqsave(&bnad->bna_lock, flags); 3315 bna_rx_vlan_add(bnad->rx_info[0].rx, vid); 3316 set_bit(vid, bnad->active_vlans); 3317 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3318 3319 mutex_unlock(&bnad->conf_mutex); 3320 3321 return 0; 3322} 3323 3324static int 3325bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 3326{ 3327 struct bnad *bnad = netdev_priv(netdev); 3328 unsigned long flags; 3329 3330 if (!bnad->rx_info[0].rx) 3331 return 0; 3332 3333 mutex_lock(&bnad->conf_mutex); 3334 3335 spin_lock_irqsave(&bnad->bna_lock, flags); 3336 clear_bit(vid, bnad->active_vlans); 3337 bna_rx_vlan_del(bnad->rx_info[0].rx, vid); 3338 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3339 3340 mutex_unlock(&bnad->conf_mutex); 3341 3342 return 0; 3343} 3344 3345static int bnad_set_features(struct net_device *dev, netdev_features_t features) 3346{ 3347 struct bnad *bnad = netdev_priv(dev); 3348 netdev_features_t changed = features ^ dev->features; 3349 3350 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) { 3351 unsigned long flags; 3352 3353 spin_lock_irqsave(&bnad->bna_lock, flags); 3354 3355 if (features & NETIF_F_HW_VLAN_CTAG_RX) 3356 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx); 3357 else 3358 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx); 3359 3360 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3361 } 3362 3363 return 0; 3364} 3365 3366#ifdef CONFIG_NET_POLL_CONTROLLER 3367static void 3368bnad_netpoll(struct net_device *netdev) 3369{ 3370 struct bnad *bnad = netdev_priv(netdev); 3371 struct bnad_rx_info *rx_info; 3372 struct bnad_rx_ctrl *rx_ctrl; 3373 u32 curr_mask; 3374 int i, j; 3375 3376 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 3377 bna_intx_disable(&bnad->bna, curr_mask); 3378 bnad_isr(bnad->pcidev->irq, netdev); 3379 bna_intx_enable(&bnad->bna, curr_mask); 3380 } else { 3381 /* 3382 * Tx processing may happen in sending context, so no need 3383 * to explicitly process completions here 3384 */ 3385 3386 /* Rx processing */ 3387 for (i = 0; i < bnad->num_rx; i++) { 3388 rx_info = &bnad->rx_info[i]; 3389 if (!rx_info->rx) 3390 continue; 3391 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 3392 rx_ctrl = &rx_info->rx_ctrl[j]; 3393 if (rx_ctrl->ccb) 3394 bnad_netif_rx_schedule_poll(bnad, 3395 rx_ctrl->ccb); 3396 } 3397 } 3398 } 3399} 3400#endif 3401 3402static const struct net_device_ops bnad_netdev_ops = { 3403 .ndo_open = bnad_open, 3404 .ndo_stop = bnad_stop, 3405 .ndo_start_xmit = bnad_start_xmit, 3406 .ndo_get_stats64 = bnad_get_stats64, 3407 .ndo_set_rx_mode = bnad_set_rx_mode, 3408 .ndo_validate_addr = eth_validate_addr, 3409 .ndo_set_mac_address = bnad_set_mac_address, 3410 .ndo_change_mtu = bnad_change_mtu, 3411 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid, 3412 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid, 3413 .ndo_set_features = bnad_set_features, 3414#ifdef CONFIG_NET_POLL_CONTROLLER 3415 .ndo_poll_controller = bnad_netpoll 3416#endif 3417}; 3418 3419static void 3420bnad_netdev_init(struct bnad *bnad) 3421{ 3422 struct net_device *netdev = bnad->netdev; 3423 3424 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3425 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3426 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX | 3427 NETIF_F_HW_VLAN_CTAG_RX; 3428 3429 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | 3430 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3431 NETIF_F_TSO | NETIF_F_TSO6; 3432 3433 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER | 3434 NETIF_F_HIGHDMA; 3435 3436 netdev->mem_start = bnad->mmio_start; 3437 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1; 3438 3439 /* MTU range: 46 - 9000 */ 3440 netdev->min_mtu = ETH_ZLEN - ETH_HLEN; 3441 netdev->max_mtu = BNAD_JUMBO_MTU; 3442 3443 netdev->netdev_ops = &bnad_netdev_ops; 3444 bnad_set_ethtool_ops(netdev); 3445} 3446 3447/* 3448 * 1. Initialize the bnad structure 3449 * 2. Setup netdev pointer in pci_dev 3450 * 3. Initialize no. of TxQ & CQs & MSIX vectors 3451 * 4. Initialize work queue. 3452 */ 3453static int 3454bnad_init(struct bnad *bnad, 3455 struct pci_dev *pdev, struct net_device *netdev) 3456{ 3457 unsigned long flags; 3458 3459 SET_NETDEV_DEV(netdev, &pdev->dev); 3460 pci_set_drvdata(pdev, netdev); 3461 3462 bnad->netdev = netdev; 3463 bnad->pcidev = pdev; 3464 bnad->mmio_start = pci_resource_start(pdev, 0); 3465 bnad->mmio_len = pci_resource_len(pdev, 0); 3466 bnad->bar0 = ioremap(bnad->mmio_start, bnad->mmio_len); 3467 if (!bnad->bar0) { 3468 dev_err(&pdev->dev, "ioremap for bar0 failed\n"); 3469 return -ENOMEM; 3470 } 3471 dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0, 3472 (unsigned long long) bnad->mmio_len); 3473 3474 spin_lock_irqsave(&bnad->bna_lock, flags); 3475 if (!bnad_msix_disable) 3476 bnad->cfg_flags = BNAD_CF_MSIX; 3477 3478 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED; 3479 3480 bnad_q_num_init(bnad); 3481 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3482 3483 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) + 3484 (bnad->num_rx * bnad->num_rxp_per_rx) + 3485 BNAD_MAILBOX_MSIX_VECTORS; 3486 3487 bnad->txq_depth = BNAD_TXQ_DEPTH; 3488 bnad->rxq_depth = BNAD_RXQ_DEPTH; 3489 3490 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO; 3491 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO; 3492 3493 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id); 3494 bnad->work_q = create_singlethread_workqueue(bnad->wq_name); 3495 if (!bnad->work_q) { 3496 iounmap(bnad->bar0); 3497 return -ENOMEM; 3498 } 3499 3500 return 0; 3501} 3502 3503/* 3504 * Must be called after bnad_pci_uninit() 3505 * so that iounmap() and pci_set_drvdata(NULL) 3506 * happens only after PCI uninitialization. 3507 */ 3508static void 3509bnad_uninit(struct bnad *bnad) 3510{ 3511 if (bnad->work_q) { 3512 destroy_workqueue(bnad->work_q); 3513 bnad->work_q = NULL; 3514 } 3515 3516 if (bnad->bar0) 3517 iounmap(bnad->bar0); 3518} 3519 3520/* 3521 * Initialize locks 3522 a) Per ioceth mutes used for serializing configuration 3523 changes from OS interface 3524 b) spin lock used to protect bna state machine 3525 */ 3526static void 3527bnad_lock_init(struct bnad *bnad) 3528{ 3529 spin_lock_init(&bnad->bna_lock); 3530 mutex_init(&bnad->conf_mutex); 3531} 3532 3533static void 3534bnad_lock_uninit(struct bnad *bnad) 3535{ 3536 mutex_destroy(&bnad->conf_mutex); 3537} 3538 3539/* PCI Initialization */ 3540static int 3541bnad_pci_init(struct bnad *bnad, struct pci_dev *pdev) 3542{ 3543 int err; 3544 3545 err = pci_enable_device(pdev); 3546 if (err) 3547 return err; 3548 err = pci_request_regions(pdev, BNAD_NAME); 3549 if (err) 3550 goto disable_device; 3551 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3552 if (err) 3553 goto release_regions; 3554 pci_set_master(pdev); 3555 return 0; 3556 3557release_regions: 3558 pci_release_regions(pdev); 3559disable_device: 3560 pci_disable_device(pdev); 3561 3562 return err; 3563} 3564 3565static void 3566bnad_pci_uninit(struct pci_dev *pdev) 3567{ 3568 pci_release_regions(pdev); 3569 pci_disable_device(pdev); 3570} 3571 3572static int 3573bnad_pci_probe(struct pci_dev *pdev, 3574 const struct pci_device_id *pcidev_id) 3575{ 3576 int err; 3577 struct bnad *bnad; 3578 struct bna *bna; 3579 struct net_device *netdev; 3580 struct bfa_pcidev pcidev_info; 3581 unsigned long flags; 3582 3583 mutex_lock(&bnad_fwimg_mutex); 3584 if (!cna_get_firmware_buf(pdev)) { 3585 mutex_unlock(&bnad_fwimg_mutex); 3586 dev_err(&pdev->dev, "failed to load firmware image!\n"); 3587 return -ENODEV; 3588 } 3589 mutex_unlock(&bnad_fwimg_mutex); 3590 3591 /* 3592 * Allocates sizeof(struct net_device + struct bnad) 3593 * bnad = netdev->priv 3594 */ 3595 netdev = alloc_etherdev(sizeof(struct bnad)); 3596 if (!netdev) { 3597 err = -ENOMEM; 3598 return err; 3599 } 3600 bnad = netdev_priv(netdev); 3601 bnad_lock_init(bnad); 3602 bnad->id = atomic_inc_return(&bna_id) - 1; 3603 3604 mutex_lock(&bnad->conf_mutex); 3605 /* PCI initialization */ 3606 err = bnad_pci_init(bnad, pdev); 3607 if (err) 3608 goto unlock_mutex; 3609 3610 /* 3611 * Initialize bnad structure 3612 * Setup relation between pci_dev & netdev 3613 */ 3614 err = bnad_init(bnad, pdev, netdev); 3615 if (err) 3616 goto pci_uninit; 3617 3618 /* Initialize netdev structure, set up ethtool ops */ 3619 bnad_netdev_init(bnad); 3620 3621 /* Set link to down state */ 3622 netif_carrier_off(netdev); 3623 3624 /* Setup the debugfs node for this bfad */ 3625 if (bna_debugfs_enable) 3626 bnad_debugfs_init(bnad); 3627 3628 /* Get resource requirement form bna */ 3629 spin_lock_irqsave(&bnad->bna_lock, flags); 3630 bna_res_req(&bnad->res_info[0]); 3631 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3632 3633 /* Allocate resources from bna */ 3634 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3635 if (err) 3636 goto drv_uninit; 3637 3638 bna = &bnad->bna; 3639 3640 /* Setup pcidev_info for bna_init() */ 3641 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn); 3642 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn); 3643 pcidev_info.device_id = bnad->pcidev->device; 3644 pcidev_info.pci_bar_kva = bnad->bar0; 3645 3646 spin_lock_irqsave(&bnad->bna_lock, flags); 3647 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]); 3648 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3649 3650 bnad->stats.bna_stats = &bna->stats; 3651 3652 bnad_enable_msix(bnad); 3653 err = bnad_mbox_irq_alloc(bnad); 3654 if (err) 3655 goto res_free; 3656 3657 /* Set up timers */ 3658 timer_setup(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout, 0); 3659 timer_setup(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check, 0); 3660 timer_setup(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout, 0); 3661 timer_setup(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout, 3662 0); 3663 3664 /* 3665 * Start the chip 3666 * If the call back comes with error, we bail out. 3667 * This is a catastrophic error. 3668 */ 3669 err = bnad_ioceth_enable(bnad); 3670 if (err) { 3671 dev_err(&pdev->dev, "initialization failed err=%d\n", err); 3672 goto probe_success; 3673 } 3674 3675 spin_lock_irqsave(&bnad->bna_lock, flags); 3676 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3677 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) { 3678 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1, 3679 bna_attr(bna)->num_rxp - 1); 3680 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3681 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) 3682 err = -EIO; 3683 } 3684 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3685 if (err) 3686 goto disable_ioceth; 3687 3688 spin_lock_irqsave(&bnad->bna_lock, flags); 3689 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]); 3690 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3691 3692 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3693 if (err) { 3694 err = -EIO; 3695 goto disable_ioceth; 3696 } 3697 3698 spin_lock_irqsave(&bnad->bna_lock, flags); 3699 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]); 3700 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3701 3702 /* Get the burnt-in mac */ 3703 spin_lock_irqsave(&bnad->bna_lock, flags); 3704 bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr); 3705 bnad_set_netdev_perm_addr(bnad); 3706 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3707 3708 mutex_unlock(&bnad->conf_mutex); 3709 3710 /* Finally, reguister with net_device layer */ 3711 err = register_netdev(netdev); 3712 if (err) { 3713 dev_err(&pdev->dev, "registering net device failed\n"); 3714 goto probe_uninit; 3715 } 3716 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags); 3717 3718 return 0; 3719 3720probe_success: 3721 mutex_unlock(&bnad->conf_mutex); 3722 return 0; 3723 3724probe_uninit: 3725 mutex_lock(&bnad->conf_mutex); 3726 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3727disable_ioceth: 3728 bnad_ioceth_disable(bnad); 3729 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3730 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); 3731 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); 3732 spin_lock_irqsave(&bnad->bna_lock, flags); 3733 bna_uninit(bna); 3734 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3735 bnad_mbox_irq_free(bnad); 3736 bnad_disable_msix(bnad); 3737res_free: 3738 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3739drv_uninit: 3740 /* Remove the debugfs node for this bnad */ 3741 kfree(bnad->regdata); 3742 bnad_debugfs_uninit(bnad); 3743 bnad_uninit(bnad); 3744pci_uninit: 3745 bnad_pci_uninit(pdev); 3746unlock_mutex: 3747 mutex_unlock(&bnad->conf_mutex); 3748 bnad_lock_uninit(bnad); 3749 free_netdev(netdev); 3750 return err; 3751} 3752 3753static void 3754bnad_pci_remove(struct pci_dev *pdev) 3755{ 3756 struct net_device *netdev = pci_get_drvdata(pdev); 3757 struct bnad *bnad; 3758 struct bna *bna; 3759 unsigned long flags; 3760 3761 if (!netdev) 3762 return; 3763 3764 bnad = netdev_priv(netdev); 3765 bna = &bnad->bna; 3766 3767 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags)) 3768 unregister_netdev(netdev); 3769 3770 mutex_lock(&bnad->conf_mutex); 3771 bnad_ioceth_disable(bnad); 3772 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3773 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); 3774 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); 3775 spin_lock_irqsave(&bnad->bna_lock, flags); 3776 bna_uninit(bna); 3777 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3778 3779 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3780 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3781 bnad_mbox_irq_free(bnad); 3782 bnad_disable_msix(bnad); 3783 bnad_pci_uninit(pdev); 3784 mutex_unlock(&bnad->conf_mutex); 3785 bnad_lock_uninit(bnad); 3786 /* Remove the debugfs node for this bnad */ 3787 kfree(bnad->regdata); 3788 bnad_debugfs_uninit(bnad); 3789 bnad_uninit(bnad); 3790 free_netdev(netdev); 3791} 3792 3793static const struct pci_device_id bnad_pci_id_table[] = { 3794 { 3795 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3796 PCI_DEVICE_ID_BROCADE_CT), 3797 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3798 .class_mask = 0xffff00 3799 }, 3800 { 3801 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3802 BFA_PCI_DEVICE_ID_CT2), 3803 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3804 .class_mask = 0xffff00 3805 }, 3806 {0, }, 3807}; 3808 3809MODULE_DEVICE_TABLE(pci, bnad_pci_id_table); 3810 3811static struct pci_driver bnad_pci_driver = { 3812 .name = BNAD_NAME, 3813 .id_table = bnad_pci_id_table, 3814 .probe = bnad_pci_probe, 3815 .remove = bnad_pci_remove, 3816}; 3817 3818static int __init 3819bnad_module_init(void) 3820{ 3821 int err; 3822 3823 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover); 3824 3825 err = pci_register_driver(&bnad_pci_driver); 3826 if (err < 0) { 3827 pr_err("bna: PCI driver registration failed err=%d\n", err); 3828 return err; 3829 } 3830 3831 return 0; 3832} 3833 3834static void __exit 3835bnad_module_exit(void) 3836{ 3837 pci_unregister_driver(&bnad_pci_driver); 3838 release_firmware(bfi_fw); 3839} 3840 3841module_init(bnad_module_init); 3842module_exit(bnad_module_exit); 3843 3844MODULE_AUTHOR("Brocade"); 3845MODULE_LICENSE("GPL"); 3846MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver"); 3847MODULE_FIRMWARE(CNA_FW_FILE_CT); 3848MODULE_FIRMWARE(CNA_FW_FILE_CT2); 3849