1// SPDX-License-Identifier: GPL-2.0 2#define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4#include <asm/byteorder.h> 5#include <linux/brcmphy.h> 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/etherdevice.h> 9#include <linux/netdevice.h> 10#include <linux/of_net.h> 11#include <linux/of_mdio.h> 12#include <linux/phy.h> 13#include <linux/phy_fixed.h> 14#include <linux/ptp_classify.h> 15#include <linux/platform_device.h> 16#include <net/ip.h> 17#include <net/ipv6.h> 18 19#include "bcmasp.h" 20#include "bcmasp_intf_defs.h" 21 22static int incr_ring(int index, int ring_count) 23{ 24 index++; 25 if (index == ring_count) 26 return 0; 27 28 return index; 29} 30 31/* Points to last byte of descriptor */ 32static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 33 int ring_count) 34{ 35 dma_addr_t end = beg + (ring_count * DESC_SIZE); 36 37 addr += DESC_SIZE; 38 if (addr > end) 39 return beg + DESC_SIZE - 1; 40 41 return addr; 42} 43 44/* Points to first byte of descriptor */ 45static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 46 int ring_count) 47{ 48 dma_addr_t end = beg + (ring_count * DESC_SIZE); 49 50 addr += DESC_SIZE; 51 if (addr >= end) 52 return beg; 53 54 return addr; 55} 56 57static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 58{ 59 if (en) { 60 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 61 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 62 TX_EPKT_C_CFG_MISC_PT | 63 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 64 TX_EPKT_C_CFG_MISC); 65 } else { 66 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 67 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 68 } 69} 70 71static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 72{ 73 if (en) 74 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 75 RX_EDPKT_CFG_ENABLE); 76 else 77 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 78} 79 80static void bcmasp_set_rx_mode(struct net_device *dev) 81{ 82 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 83 struct bcmasp_intf *intf = netdev_priv(dev); 84 struct netdev_hw_addr *ha; 85 int ret; 86 87 spin_lock_bh(&intf->parent->mda_lock); 88 89 bcmasp_disable_all_filters(intf); 90 91 if (dev->flags & IFF_PROMISC) 92 goto set_promisc; 93 94 bcmasp_set_promisc(intf, 0); 95 96 bcmasp_set_broad(intf, 1); 97 98 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 99 100 if (dev->flags & IFF_ALLMULTI) { 101 bcmasp_set_allmulti(intf, 1); 102 } else { 103 bcmasp_set_allmulti(intf, 0); 104 105 netdev_for_each_mc_addr(ha, dev) { 106 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 107 if (ret) { 108 intf->mib.mc_filters_full_cnt++; 109 goto set_promisc; 110 } 111 } 112 } 113 114 netdev_for_each_uc_addr(ha, dev) { 115 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 116 if (ret) { 117 intf->mib.uc_filters_full_cnt++; 118 goto set_promisc; 119 } 120 } 121 122 spin_unlock_bh(&intf->parent->mda_lock); 123 return; 124 125set_promisc: 126 bcmasp_set_promisc(intf, 1); 127 intf->mib.promisc_filters_cnt++; 128 129 /* disable all filters used by this port */ 130 bcmasp_disable_all_filters(intf); 131 132 spin_unlock_bh(&intf->parent->mda_lock); 133} 134 135static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 136{ 137 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 138 139 txcb->skb = NULL; 140 dma_unmap_addr_set(txcb, dma_addr, 0); 141 dma_unmap_len_set(txcb, dma_len, 0); 142 txcb->last = false; 143} 144 145static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 146{ 147 int next_index, i; 148 149 /* Check if we have enough room for cnt descriptors */ 150 for (i = 0; i < cnt; i++) { 151 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 152 if (next_index == intf->tx_spb_clean_index) 153 return 1; 154 } 155 156 return 0; 157} 158 159static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162{ 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228help: 229 skb_checksum_help(skb); 230 231 return skb; 232} 233 234static unsigned long bcmasp_rx_edpkt_dma_rq(struct bcmasp_intf *intf) 235{ 236 return rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID); 237} 238 239static void bcmasp_rx_edpkt_cfg_wq(struct bcmasp_intf *intf, dma_addr_t addr) 240{ 241 rx_edpkt_cfg_wq(intf, addr, RX_EDPKT_RING_BUFFER_READ); 242} 243 244static void bcmasp_rx_edpkt_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 245{ 246 rx_edpkt_dma_wq(intf, addr, RX_EDPKT_DMA_READ); 247} 248 249static unsigned long bcmasp_tx_spb_dma_rq(struct bcmasp_intf *intf) 250{ 251 return tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 252} 253 254static void bcmasp_tx_spb_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 255{ 256 tx_spb_dma_wq(intf, addr, TX_SPB_DMA_VALID); 257} 258 259static const struct bcmasp_intf_ops bcmasp_intf_ops = { 260 .rx_desc_read = bcmasp_rx_edpkt_dma_rq, 261 .rx_buffer_write = bcmasp_rx_edpkt_cfg_wq, 262 .rx_desc_write = bcmasp_rx_edpkt_dma_wq, 263 .tx_read = bcmasp_tx_spb_dma_rq, 264 .tx_write = bcmasp_tx_spb_dma_wq, 265}; 266 267static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 268{ 269 struct bcmasp_intf *intf = netdev_priv(dev); 270 unsigned int total_bytes, size; 271 int spb_index, nr_frags, i, j; 272 struct bcmasp_tx_cb *txcb; 273 dma_addr_t mapping, valid; 274 struct bcmasp_desc *desc; 275 bool csum_hw = false; 276 struct device *kdev; 277 skb_frag_t *frag; 278 279 kdev = &intf->parent->pdev->dev; 280 281 nr_frags = skb_shinfo(skb)->nr_frags; 282 283 if (tx_spb_ring_full(intf, nr_frags + 1)) { 284 netif_stop_queue(dev); 285 if (net_ratelimit()) 286 netdev_err(dev, "Tx Ring Full!\n"); 287 return NETDEV_TX_BUSY; 288 } 289 290 /* Save skb len before adding csum offload header */ 291 total_bytes = skb->len; 292 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 293 if (!skb) 294 return NETDEV_TX_OK; 295 296 spb_index = intf->tx_spb_index; 297 valid = intf->tx_spb_dma_valid; 298 for (i = 0; i <= nr_frags; i++) { 299 if (!i) { 300 size = skb_headlen(skb); 301 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 302 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 303 return NETDEV_TX_OK; 304 size = skb->len; 305 } 306 mapping = dma_map_single(kdev, skb->data, size, 307 DMA_TO_DEVICE); 308 } else { 309 frag = &skb_shinfo(skb)->frags[i - 1]; 310 size = skb_frag_size(frag); 311 mapping = skb_frag_dma_map(kdev, frag, 0, size, 312 DMA_TO_DEVICE); 313 } 314 315 if (dma_mapping_error(kdev, mapping)) { 316 intf->mib.tx_dma_failed++; 317 spb_index = intf->tx_spb_index; 318 for (j = 0; j < i; j++) { 319 bcmasp_clean_txcb(intf, spb_index); 320 spb_index = incr_ring(spb_index, 321 DESC_RING_COUNT); 322 } 323 /* Rewind so we do not have a hole */ 324 spb_index = intf->tx_spb_index; 325 return NETDEV_TX_OK; 326 } 327 328 txcb = &intf->tx_cbs[spb_index]; 329 desc = &intf->tx_spb_cpu[spb_index]; 330 memset(desc, 0, sizeof(*desc)); 331 txcb->skb = skb; 332 txcb->bytes_sent = total_bytes; 333 dma_unmap_addr_set(txcb, dma_addr, mapping); 334 dma_unmap_len_set(txcb, dma_len, size); 335 if (!i) { 336 desc->flags |= DESC_SOF; 337 if (csum_hw) 338 desc->flags |= DESC_EPKT_CMD; 339 } 340 341 if (i == nr_frags) { 342 desc->flags |= DESC_EOF; 343 txcb->last = true; 344 } 345 346 desc->buf = mapping; 347 desc->size = size; 348 desc->flags |= DESC_INT_EN; 349 350 netif_dbg(intf, tx_queued, dev, 351 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 352 __func__, &mapping, desc->size, desc->flags, 353 spb_index); 354 355 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 356 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 357 DESC_RING_COUNT); 358 } 359 360 /* Ensure all descriptors have been written to DRAM for the 361 * hardware to see up-to-date contents. 362 */ 363 wmb(); 364 365 intf->tx_spb_index = spb_index; 366 intf->tx_spb_dma_valid = valid; 367 bcmasp_intf_tx_write(intf, intf->tx_spb_dma_valid); 368 369 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 370 netif_stop_queue(dev); 371 372 return NETDEV_TX_OK; 373} 374 375static void bcmasp_netif_start(struct net_device *dev) 376{ 377 struct bcmasp_intf *intf = netdev_priv(dev); 378 379 bcmasp_set_rx_mode(dev); 380 napi_enable(&intf->tx_napi); 381 napi_enable(&intf->rx_napi); 382 383 bcmasp_enable_rx_irq(intf, 1); 384 bcmasp_enable_tx_irq(intf, 1); 385 386 phy_start(dev->phydev); 387} 388 389static void umac_reset(struct bcmasp_intf *intf) 390{ 391 umac_wl(intf, 0x0, UMC_CMD); 392 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 393 usleep_range(10, 100); 394 umac_wl(intf, 0x0, UMC_CMD); 395} 396 397static void umac_set_hw_addr(struct bcmasp_intf *intf, 398 const unsigned char *addr) 399{ 400 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 401 addr[3]; 402 u32 mac1 = (addr[4] << 8) | addr[5]; 403 404 umac_wl(intf, mac0, UMC_MAC0); 405 umac_wl(intf, mac1, UMC_MAC1); 406} 407 408static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 409 unsigned int enable) 410{ 411 u32 reg; 412 413 reg = umac_rl(intf, UMC_CMD); 414 if (enable) 415 reg |= mask; 416 else 417 reg &= ~mask; 418 umac_wl(intf, reg, UMC_CMD); 419 420 /* UniMAC stops on a packet boundary, wait for a full-sized packet 421 * to be processed (1 msec). 422 */ 423 if (enable == 0) 424 usleep_range(1000, 2000); 425} 426 427static void umac_init(struct bcmasp_intf *intf) 428{ 429 umac_wl(intf, 0x800, UMC_FRM_LEN); 430 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 431 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 432 umac_enable_set(intf, UMC_CMD_PROMISC, 1); 433} 434 435static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 436{ 437 struct bcmasp_intf *intf = 438 container_of(napi, struct bcmasp_intf, tx_napi); 439 struct bcmasp_intf_stats64 *stats = &intf->stats64; 440 struct device *kdev = &intf->parent->pdev->dev; 441 unsigned long read, released = 0; 442 struct bcmasp_tx_cb *txcb; 443 struct bcmasp_desc *desc; 444 dma_addr_t mapping; 445 446 read = bcmasp_intf_tx_read(intf); 447 while (intf->tx_spb_dma_read != read) { 448 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 449 mapping = dma_unmap_addr(txcb, dma_addr); 450 451 dma_unmap_single(kdev, mapping, 452 dma_unmap_len(txcb, dma_len), 453 DMA_TO_DEVICE); 454 455 if (txcb->last) { 456 dev_consume_skb_any(txcb->skb); 457 458 u64_stats_update_begin(&stats->syncp); 459 u64_stats_inc(&stats->tx_packets); 460 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 461 u64_stats_update_end(&stats->syncp); 462 } 463 464 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 465 466 netif_dbg(intf, tx_done, intf->ndev, 467 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 468 __func__, &mapping, desc->size, desc->flags, 469 intf->tx_spb_clean_index); 470 471 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 472 released++; 473 474 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 475 DESC_RING_COUNT); 476 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 477 intf->tx_spb_dma_addr, 478 DESC_RING_COUNT); 479 } 480 481 /* Ensure all descriptors have been written to DRAM for the hardware 482 * to see updated contents. 483 */ 484 wmb(); 485 486 napi_complete(&intf->tx_napi); 487 488 bcmasp_enable_tx_irq(intf, 1); 489 490 if (released) 491 netif_wake_queue(intf->ndev); 492 493 return 0; 494} 495 496static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 497{ 498 struct bcmasp_intf *intf = 499 container_of(napi, struct bcmasp_intf, rx_napi); 500 struct bcmasp_intf_stats64 *stats = &intf->stats64; 501 struct device *kdev = &intf->parent->pdev->dev; 502 unsigned long processed = 0; 503 struct bcmasp_desc *desc; 504 struct sk_buff *skb; 505 dma_addr_t valid; 506 void *data; 507 u64 flags; 508 u32 len; 509 510 valid = bcmasp_intf_rx_desc_read(intf) + 1; 511 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 512 valid = intf->rx_edpkt_dma_addr; 513 514 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 515 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 516 517 /* Ensure that descriptor has been fully written to DRAM by 518 * hardware before reading by the CPU 519 */ 520 rmb(); 521 522 /* Calculate virt addr by offsetting from physical addr */ 523 data = intf->rx_ring_cpu + 524 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 525 526 flags = DESC_FLAGS(desc->buf); 527 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 528 if (net_ratelimit()) { 529 netif_err(intf, rx_status, intf->ndev, 530 "flags=0x%llx\n", flags); 531 } 532 533 u64_stats_update_begin(&stats->syncp); 534 if (flags & DESC_CRC_ERR) 535 u64_stats_inc(&stats->rx_crc_errs); 536 if (flags & DESC_RX_SYM_ERR) 537 u64_stats_inc(&stats->rx_sym_errs); 538 u64_stats_update_end(&stats->syncp); 539 540 goto next; 541 } 542 543 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 544 DMA_FROM_DEVICE); 545 546 len = desc->size; 547 548 skb = napi_alloc_skb(napi, len); 549 if (!skb) { 550 u64_stats_update_begin(&stats->syncp); 551 u64_stats_inc(&stats->rx_dropped); 552 u64_stats_update_end(&stats->syncp); 553 intf->mib.alloc_rx_skb_failed++; 554 555 goto next; 556 } 557 558 skb_put(skb, len); 559 memcpy(skb->data, data, len); 560 561 skb_pull(skb, 2); 562 len -= 2; 563 if (likely(intf->crc_fwd)) { 564 skb_trim(skb, len - ETH_FCS_LEN); 565 len -= ETH_FCS_LEN; 566 } 567 568 if ((intf->ndev->features & NETIF_F_RXCSUM) && 569 (desc->buf & DESC_CHKSUM)) 570 skb->ip_summed = CHECKSUM_UNNECESSARY; 571 572 skb->protocol = eth_type_trans(skb, intf->ndev); 573 574 napi_gro_receive(napi, skb); 575 576 u64_stats_update_begin(&stats->syncp); 577 u64_stats_inc(&stats->rx_packets); 578 u64_stats_add(&stats->rx_bytes, len); 579 u64_stats_update_end(&stats->syncp); 580 581next: 582 bcmasp_intf_rx_buffer_write(intf, (DESC_ADDR(desc->buf) + 583 desc->size)); 584 585 processed++; 586 intf->rx_edpkt_dma_read = 587 incr_first_byte(intf->rx_edpkt_dma_read, 588 intf->rx_edpkt_dma_addr, 589 DESC_RING_COUNT); 590 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 591 DESC_RING_COUNT); 592 } 593 594 bcmasp_intf_rx_desc_write(intf, intf->rx_edpkt_dma_read); 595 596 if (processed < budget) { 597 napi_complete_done(&intf->rx_napi, processed); 598 bcmasp_enable_rx_irq(intf, 1); 599 } 600 601 return processed; 602} 603 604static void bcmasp_adj_link(struct net_device *dev) 605{ 606 struct bcmasp_intf *intf = netdev_priv(dev); 607 struct phy_device *phydev = dev->phydev; 608 u32 cmd_bits = 0, reg; 609 int changed = 0; 610 611 if (intf->old_link != phydev->link) { 612 changed = 1; 613 intf->old_link = phydev->link; 614 } 615 616 if (intf->old_duplex != phydev->duplex) { 617 changed = 1; 618 intf->old_duplex = phydev->duplex; 619 } 620 621 switch (phydev->speed) { 622 case SPEED_2500: 623 cmd_bits = UMC_CMD_SPEED_2500; 624 break; 625 case SPEED_1000: 626 cmd_bits = UMC_CMD_SPEED_1000; 627 break; 628 case SPEED_100: 629 cmd_bits = UMC_CMD_SPEED_100; 630 break; 631 case SPEED_10: 632 cmd_bits = UMC_CMD_SPEED_10; 633 break; 634 default: 635 break; 636 } 637 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 638 639 if (phydev->duplex == DUPLEX_HALF) 640 cmd_bits |= UMC_CMD_HD_EN; 641 642 if (intf->old_pause != phydev->pause) { 643 changed = 1; 644 intf->old_pause = phydev->pause; 645 } 646 647 if (!phydev->pause) 648 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 649 650 if (!changed) 651 return; 652 653 if (phydev->link) { 654 reg = umac_rl(intf, UMC_CMD); 655 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 656 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 657 UMC_CMD_TX_PAUSE_IGNORE); 658 reg |= cmd_bits; 659 umac_wl(intf, reg, UMC_CMD); 660 661 intf->eee.eee_active = phy_init_eee(phydev, 0) >= 0; 662 bcmasp_eee_enable_set(intf, intf->eee.eee_active); 663 } 664 665 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 666 if (phydev->link) 667 reg |= RGMII_LINK; 668 else 669 reg &= ~RGMII_LINK; 670 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 671 672 if (changed) 673 phy_print_status(phydev); 674} 675 676static int bcmasp_init_rx(struct bcmasp_intf *intf) 677{ 678 struct device *kdev = &intf->parent->pdev->dev; 679 struct page *buffer_pg; 680 dma_addr_t dma; 681 void *p; 682 u32 reg; 683 int ret; 684 685 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 686 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 687 688 dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 689 DMA_FROM_DEVICE); 690 if (dma_mapping_error(kdev, dma)) { 691 __free_pages(buffer_pg, intf->rx_buf_order); 692 return -ENOMEM; 693 } 694 intf->rx_ring_cpu = page_to_virt(buffer_pg); 695 intf->rx_ring_dma = dma; 696 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 697 698 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->rx_edpkt_dma_addr, 699 GFP_KERNEL); 700 if (!p) { 701 ret = -ENOMEM; 702 goto free_rx_ring; 703 } 704 intf->rx_edpkt_cpu = p; 705 706 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 707 708 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 709 intf->rx_edpkt_index = 0; 710 711 /* Make sure channels are disabled */ 712 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 713 714 /* Rx SPB */ 715 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 716 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 717 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 718 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 719 RX_EDPKT_RING_BUFFER_END); 720 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 721 RX_EDPKT_RING_BUFFER_VALID); 722 723 /* EDPKT */ 724 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 725 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 726 (RX_EDPKT_CFG_CFG0_64_ALN << 727 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 728 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 729 RX_EDPKT_CFG_CFG0); 730 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 731 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 732 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 733 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 734 RX_EDPKT_DMA_END); 735 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 736 RX_EDPKT_DMA_VALID); 737 738 reg = UMAC2FB_CFG_DEFAULT_EN | 739 ((intf->channel + 11) << UMAC2FB_CFG_CHID_SHIFT); 740 reg |= (0xd << UMAC2FB_CFG_OK_SEND_SHIFT); 741 umac2fb_wl(intf, reg, UMAC2FB_CFG); 742 743 return 0; 744 745free_rx_ring: 746 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 747 DMA_FROM_DEVICE); 748 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 749 750 return ret; 751} 752 753static void bcmasp_reclaim_free_all_rx(struct bcmasp_intf *intf) 754{ 755 struct device *kdev = &intf->parent->pdev->dev; 756 757 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 758 intf->rx_edpkt_dma_addr); 759 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 760 DMA_FROM_DEVICE); 761 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 762} 763 764static int bcmasp_init_tx(struct bcmasp_intf *intf) 765{ 766 struct device *kdev = &intf->parent->pdev->dev; 767 void *p; 768 int ret; 769 770 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->tx_spb_dma_addr, 771 GFP_KERNEL); 772 if (!p) 773 return -ENOMEM; 774 775 intf->tx_spb_cpu = p; 776 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 777 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 778 779 intf->tx_cbs = kcalloc(DESC_RING_COUNT, sizeof(struct bcmasp_tx_cb), 780 GFP_KERNEL); 781 if (!intf->tx_cbs) { 782 ret = -ENOMEM; 783 goto free_tx_spb; 784 } 785 786 intf->tx_spb_index = 0; 787 intf->tx_spb_clean_index = 0; 788 789 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 790 791 /* Make sure channels are disabled */ 792 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 793 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 794 795 /* Tx SPB */ 796 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 797 TX_SPB_CTRL_XF_CTRL2); 798 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 799 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 800 tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 801 802 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 803 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 804 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 805 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 806 807 return 0; 808 809free_tx_spb: 810 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 811 intf->tx_spb_dma_addr); 812 813 return ret; 814} 815 816static void bcmasp_reclaim_free_all_tx(struct bcmasp_intf *intf) 817{ 818 struct device *kdev = &intf->parent->pdev->dev; 819 820 /* Free descriptors */ 821 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 822 intf->tx_spb_dma_addr); 823 824 /* Free cbs */ 825 kfree(intf->tx_cbs); 826} 827 828static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 829{ 830 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 831 RGMII_EPHY_CFG_IDDQ_GLOBAL; 832 u32 reg; 833 834 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 835 if (enable) { 836 reg &= ~RGMII_EPHY_CK25_DIS; 837 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 838 mdelay(1); 839 840 reg &= ~mask; 841 reg |= RGMII_EPHY_RESET; 842 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 843 mdelay(1); 844 845 reg &= ~RGMII_EPHY_RESET; 846 } else { 847 reg |= mask | RGMII_EPHY_RESET; 848 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 849 mdelay(1); 850 reg |= RGMII_EPHY_CK25_DIS; 851 } 852 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 853 mdelay(1); 854 855 /* Set or clear the LED control override to avoid lighting up LEDs 856 * while the EPHY is powered off and drawing unnecessary current. 857 */ 858 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 859 if (enable) 860 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 861 else 862 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 863 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 864} 865 866static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 867{ 868 u32 reg; 869 870 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 871 reg &= ~RGMII_OOB_DIS; 872 if (enable) 873 reg |= RGMII_MODE_EN; 874 else 875 reg &= ~RGMII_MODE_EN; 876 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 877} 878 879static void bcmasp_netif_deinit(struct net_device *dev) 880{ 881 struct bcmasp_intf *intf = netdev_priv(dev); 882 u32 reg, timeout = 1000; 883 884 napi_disable(&intf->tx_napi); 885 886 bcmasp_enable_tx(intf, 0); 887 888 /* Flush any TX packets in the pipe */ 889 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 890 do { 891 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 892 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 893 break; 894 usleep_range(1000, 2000); 895 } while (timeout-- > 0); 896 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 897 898 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 899 900 phy_stop(dev->phydev); 901 902 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 903 904 bcmasp_flush_rx_port(intf); 905 usleep_range(1000, 2000); 906 bcmasp_enable_rx(intf, 0); 907 908 napi_disable(&intf->rx_napi); 909 910 /* Disable interrupts */ 911 bcmasp_enable_tx_irq(intf, 0); 912 bcmasp_enable_rx_irq(intf, 0); 913 914 netif_napi_del(&intf->tx_napi); 915 bcmasp_reclaim_free_all_tx(intf); 916 917 netif_napi_del(&intf->rx_napi); 918 bcmasp_reclaim_free_all_rx(intf); 919} 920 921static int bcmasp_stop(struct net_device *dev) 922{ 923 struct bcmasp_intf *intf = netdev_priv(dev); 924 925 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 926 927 /* Stop tx from updating HW */ 928 netif_tx_disable(dev); 929 930 bcmasp_netif_deinit(dev); 931 932 phy_disconnect(dev->phydev); 933 934 /* Disable internal EPHY or external PHY */ 935 if (intf->internal_phy) 936 bcmasp_ephy_enable_set(intf, false); 937 else 938 bcmasp_rgmii_mode_en_set(intf, false); 939 940 /* Disable the interface clocks */ 941 bcmasp_core_clock_set_intf(intf, false); 942 943 clk_disable_unprepare(intf->parent->clk); 944 945 return 0; 946} 947 948static void bcmasp_configure_port(struct bcmasp_intf *intf) 949{ 950 u32 reg, id_mode_dis = 0; 951 952 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 953 reg &= ~RGMII_PORT_MODE_MASK; 954 955 switch (intf->phy_interface) { 956 case PHY_INTERFACE_MODE_RGMII: 957 /* RGMII_NO_ID: TXC transitions at the same time as TXD 958 * (requires PCB or receiver-side delay) 959 * RGMII: Add 2ns delay on TXC (90 degree shift) 960 * 961 * ID is implicitly disabled for 100Mbps (RG)MII operation. 962 */ 963 id_mode_dis = RGMII_ID_MODE_DIS; 964 fallthrough; 965 case PHY_INTERFACE_MODE_RGMII_TXID: 966 reg |= RGMII_PORT_MODE_EXT_GPHY; 967 break; 968 case PHY_INTERFACE_MODE_MII: 969 reg |= RGMII_PORT_MODE_EXT_EPHY; 970 break; 971 default: 972 break; 973 } 974 975 if (intf->internal_phy) 976 reg |= RGMII_PORT_MODE_EPHY; 977 978 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 979 980 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 981 reg &= ~RGMII_ID_MODE_DIS; 982 reg |= id_mode_dis; 983 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 984} 985 986static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 987{ 988 struct bcmasp_intf *intf = netdev_priv(dev); 989 phy_interface_t phy_iface = intf->phy_interface; 990 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 991 PHY_BRCM_DIS_TXCRXC_NOENRGY | 992 PHY_BRCM_IDDQ_SUSPEND; 993 struct phy_device *phydev = NULL; 994 int ret; 995 996 /* Always enable interface clocks */ 997 bcmasp_core_clock_set_intf(intf, true); 998 999 /* Enable internal PHY or external PHY before any MAC activity */ 1000 if (intf->internal_phy) 1001 bcmasp_ephy_enable_set(intf, true); 1002 else 1003 bcmasp_rgmii_mode_en_set(intf, true); 1004 bcmasp_configure_port(intf); 1005 1006 /* This is an ugly quirk but we have not been correctly 1007 * interpreting the phy_interface values and we have done that 1008 * across different drivers, so at least we are consistent in 1009 * our mistakes. 1010 * 1011 * When the Generic PHY driver is in use either the PHY has 1012 * been strapped or programmed correctly by the boot loader so 1013 * we should stick to our incorrect interpretation since we 1014 * have validated it. 1015 * 1016 * Now when a dedicated PHY driver is in use, we need to 1017 * reverse the meaning of the phy_interface_mode values to 1018 * something that the PHY driver will interpret and act on such 1019 * that we have two mistakes canceling themselves so to speak. 1020 * We only do this for the two modes that GENET driver 1021 * officially supports on Broadcom STB chips: 1022 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1023 * Other modes are not *officially* supported with the boot 1024 * loader and the scripted environment generating Device Tree 1025 * blobs for those platforms. 1026 * 1027 * Note that internal PHY and fixed-link configurations are not 1028 * affected because they use different phy_interface_t values 1029 * or the Generic PHY driver. 1030 */ 1031 switch (phy_iface) { 1032 case PHY_INTERFACE_MODE_RGMII: 1033 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1034 break; 1035 case PHY_INTERFACE_MODE_RGMII_TXID: 1036 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 if (phy_connect) { 1043 phydev = of_phy_connect(dev, intf->phy_dn, 1044 bcmasp_adj_link, phy_flags, 1045 phy_iface); 1046 if (!phydev) { 1047 ret = -ENODEV; 1048 netdev_err(dev, "could not attach to PHY\n"); 1049 goto err_phy_disable; 1050 } 1051 1052 /* Indicate that the MAC is responsible for PHY PM */ 1053 phydev->mac_managed_pm = true; 1054 } else if (!intf->wolopts) { 1055 ret = phy_resume(dev->phydev); 1056 if (ret) 1057 goto err_phy_disable; 1058 } 1059 1060 umac_reset(intf); 1061 1062 umac_init(intf); 1063 1064 /* Disable the UniMAC RX/TX */ 1065 umac_enable_set(intf, (UMC_CMD_RX_EN | UMC_CMD_TX_EN), 0); 1066 1067 umac_set_hw_addr(intf, dev->dev_addr); 1068 1069 intf->old_duplex = -1; 1070 intf->old_link = -1; 1071 intf->old_pause = -1; 1072 1073 ret = bcmasp_init_tx(intf); 1074 if (ret) 1075 goto err_phy_disconnect; 1076 1077 /* Turn on asp */ 1078 bcmasp_enable_tx(intf, 1); 1079 1080 ret = bcmasp_init_rx(intf); 1081 if (ret) 1082 goto err_reclaim_tx; 1083 1084 bcmasp_enable_rx(intf, 1); 1085 1086 /* Turn on UniMAC TX/RX */ 1087 umac_enable_set(intf, (UMC_CMD_RX_EN | UMC_CMD_TX_EN), 1); 1088 1089 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1090 1091 bcmasp_netif_start(dev); 1092 1093 netif_start_queue(dev); 1094 1095 return 0; 1096 1097err_reclaim_tx: 1098 bcmasp_reclaim_free_all_tx(intf); 1099err_phy_disconnect: 1100 if (phydev) 1101 phy_disconnect(phydev); 1102err_phy_disable: 1103 if (intf->internal_phy) 1104 bcmasp_ephy_enable_set(intf, false); 1105 else 1106 bcmasp_rgmii_mode_en_set(intf, false); 1107 return ret; 1108} 1109 1110static int bcmasp_open(struct net_device *dev) 1111{ 1112 struct bcmasp_intf *intf = netdev_priv(dev); 1113 int ret; 1114 1115 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1116 1117 ret = clk_prepare_enable(intf->parent->clk); 1118 if (ret) 1119 return ret; 1120 1121 ret = bcmasp_netif_init(dev, true); 1122 if (ret) 1123 clk_disable_unprepare(intf->parent->clk); 1124 1125 return ret; 1126} 1127 1128static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1129{ 1130 struct bcmasp_intf *intf = netdev_priv(dev); 1131 1132 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1133 intf->mib.tx_timeout_cnt++; 1134} 1135 1136static int bcmasp_get_phys_port_name(struct net_device *dev, 1137 char *name, size_t len) 1138{ 1139 struct bcmasp_intf *intf = netdev_priv(dev); 1140 1141 if (snprintf(name, len, "p%d", intf->port) >= len) 1142 return -EINVAL; 1143 1144 return 0; 1145} 1146 1147static void bcmasp_get_stats64(struct net_device *dev, 1148 struct rtnl_link_stats64 *stats) 1149{ 1150 struct bcmasp_intf *intf = netdev_priv(dev); 1151 struct bcmasp_intf_stats64 *lstats; 1152 unsigned int start; 1153 1154 lstats = &intf->stats64; 1155 1156 do { 1157 start = u64_stats_fetch_begin(&lstats->syncp); 1158 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1159 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1160 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1161 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1162 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1163 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1164 1165 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1166 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1167 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1168} 1169 1170static const struct net_device_ops bcmasp_netdev_ops = { 1171 .ndo_open = bcmasp_open, 1172 .ndo_stop = bcmasp_stop, 1173 .ndo_start_xmit = bcmasp_xmit, 1174 .ndo_tx_timeout = bcmasp_tx_timeout, 1175 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1176 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1177 .ndo_eth_ioctl = phy_do_ioctl_running, 1178 .ndo_set_mac_address = eth_mac_addr, 1179 .ndo_get_stats64 = bcmasp_get_stats64, 1180}; 1181 1182static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1183{ 1184 /* Per port */ 1185 intf->res.umac = priv->base + UMC_OFFSET(intf); 1186 intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1187 (intf->port * 0x4)); 1188 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1189 1190 /* Per ch */ 1191 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1192 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1193 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1194 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1195 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1196 1197 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1198 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1199} 1200 1201#define MAX_IRQ_STR_LEN 64 1202struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1203 struct device_node *ndev_dn, int i) 1204{ 1205 struct device *dev = &priv->pdev->dev; 1206 struct bcmasp_intf *intf; 1207 struct net_device *ndev; 1208 int ch, port, ret; 1209 1210 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1211 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1212 goto err; 1213 } 1214 1215 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1216 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1217 goto err; 1218 } 1219 1220 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1221 if (!ndev) { 1222 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1223 goto err; 1224 } 1225 intf = netdev_priv(ndev); 1226 1227 intf->parent = priv; 1228 intf->ndev = ndev; 1229 intf->channel = ch; 1230 intf->port = port; 1231 intf->ndev_dn = ndev_dn; 1232 intf->index = i; 1233 1234 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1235 if (ret < 0) { 1236 dev_err(dev, "invalid PHY mode property\n"); 1237 goto err_free_netdev; 1238 } 1239 1240 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1241 intf->internal_phy = true; 1242 1243 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1244 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1245 ret = of_phy_register_fixed_link(ndev_dn); 1246 if (ret) { 1247 dev_warn(dev, "%s: failed to register fixed PHY\n", 1248 ndev_dn->name); 1249 goto err_free_netdev; 1250 } 1251 intf->phy_dn = ndev_dn; 1252 } 1253 1254 /* Map resource */ 1255 bcmasp_map_res(priv, intf); 1256 1257 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1258 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1259 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1260 (intf->port != 1 && intf->internal_phy)) { 1261 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1262 phy_modes(intf->phy_interface), intf->port); 1263 ret = -EINVAL; 1264 goto err_free_netdev; 1265 } 1266 1267 ret = of_get_ethdev_address(ndev_dn, ndev); 1268 if (ret) { 1269 netdev_warn(ndev, "using random Ethernet MAC\n"); 1270 eth_hw_addr_random(ndev); 1271 } 1272 1273 SET_NETDEV_DEV(ndev, dev); 1274 intf->ops = &bcmasp_intf_ops; 1275 ndev->netdev_ops = &bcmasp_netdev_ops; 1276 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1277 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1278 NETIF_MSG_PROBE | 1279 NETIF_MSG_LINK); 1280 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1281 NETIF_F_RXCSUM; 1282 ndev->hw_features |= ndev->features; 1283 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1284 1285 return intf; 1286 1287err_free_netdev: 1288 free_netdev(ndev); 1289err: 1290 return NULL; 1291} 1292 1293void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1294{ 1295 if (intf->ndev->reg_state == NETREG_REGISTERED) 1296 unregister_netdev(intf->ndev); 1297 if (of_phy_is_fixed_link(intf->ndev_dn)) 1298 of_phy_deregister_fixed_link(intf->ndev_dn); 1299 free_netdev(intf->ndev); 1300} 1301 1302static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1303{ 1304 struct net_device *ndev = intf->ndev; 1305 u32 reg; 1306 1307 reg = umac_rl(intf, UMC_MPD_CTRL); 1308 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1309 reg |= UMC_MPD_CTRL_MPD_EN; 1310 reg &= ~UMC_MPD_CTRL_PSW_EN; 1311 if (intf->wolopts & WAKE_MAGICSECURE) { 1312 /* Program the SecureOn password */ 1313 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1314 UMC_PSW_MS); 1315 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1316 UMC_PSW_LS); 1317 reg |= UMC_MPD_CTRL_PSW_EN; 1318 } 1319 umac_wl(intf, reg, UMC_MPD_CTRL); 1320 1321 if (intf->wolopts & WAKE_FILTER) 1322 bcmasp_netfilt_suspend(intf); 1323 1324 /* UniMAC receive needs to be turned on */ 1325 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1326 1327 if (intf->parent->wol_irq > 0) { 1328 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1329 ASP_WAKEUP_INTR2_MASK_CLEAR); 1330 } 1331 1332 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1333} 1334 1335int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1336{ 1337 struct device *kdev = &intf->parent->pdev->dev; 1338 struct net_device *dev = intf->ndev; 1339 int ret = 0; 1340 1341 if (!netif_running(dev)) 1342 return 0; 1343 1344 netif_device_detach(dev); 1345 1346 bcmasp_netif_deinit(dev); 1347 1348 if (!intf->wolopts) { 1349 ret = phy_suspend(dev->phydev); 1350 if (ret) 1351 goto out; 1352 1353 if (intf->internal_phy) 1354 bcmasp_ephy_enable_set(intf, false); 1355 else 1356 bcmasp_rgmii_mode_en_set(intf, false); 1357 1358 /* If Wake-on-LAN is disabled, we can safely 1359 * disable the network interface clocks. 1360 */ 1361 bcmasp_core_clock_set_intf(intf, false); 1362 } 1363 1364 if (device_may_wakeup(kdev) && intf->wolopts) 1365 bcmasp_suspend_to_wol(intf); 1366 1367 clk_disable_unprepare(intf->parent->clk); 1368 1369 return ret; 1370 1371out: 1372 bcmasp_netif_init(dev, false); 1373 return ret; 1374} 1375 1376static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1377{ 1378 u32 reg; 1379 1380 reg = umac_rl(intf, UMC_MPD_CTRL); 1381 reg &= ~UMC_MPD_CTRL_MPD_EN; 1382 umac_wl(intf, reg, UMC_MPD_CTRL); 1383 1384 if (intf->parent->wol_irq > 0) { 1385 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1386 ASP_WAKEUP_INTR2_MASK_SET); 1387 } 1388} 1389 1390int bcmasp_interface_resume(struct bcmasp_intf *intf) 1391{ 1392 struct net_device *dev = intf->ndev; 1393 int ret; 1394 1395 if (!netif_running(dev)) 1396 return 0; 1397 1398 ret = clk_prepare_enable(intf->parent->clk); 1399 if (ret) 1400 return ret; 1401 1402 ret = bcmasp_netif_init(dev, false); 1403 if (ret) 1404 goto out; 1405 1406 bcmasp_resume_from_wol(intf); 1407 1408 if (intf->eee.eee_enabled) 1409 bcmasp_eee_enable_set(intf, true); 1410 1411 netif_device_attach(dev); 1412 1413 return 0; 1414 1415out: 1416 clk_disable_unprepare(intf->parent->clk); 1417 return ret; 1418} 1419