162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Applied Micro X-Gene SoC Ethernet v2 Driver
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (c) 2017, Applied Micro Circuits Corporation
662306a36Sopenharmony_ci * Author(s): Iyappan Subramanian <isubramanian@apm.com>
762306a36Sopenharmony_ci *	      Keyur Chudgar <kchudgar@apm.com>
862306a36Sopenharmony_ci */
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#ifndef __XGENE_ENET_V2_MAC_H__
1162306a36Sopenharmony_ci#define __XGENE_ENET_V2_MAC_H__
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci/* Register offsets */
1462306a36Sopenharmony_ci#define MAC_CONFIG_1		0xa000
1562306a36Sopenharmony_ci#define MAC_CONFIG_2		0xa004
1662306a36Sopenharmony_ci#define MII_MGMT_CONFIG		0xa020
1762306a36Sopenharmony_ci#define MII_MGMT_COMMAND	0xa024
1862306a36Sopenharmony_ci#define MII_MGMT_ADDRESS	0xa028
1962306a36Sopenharmony_ci#define MII_MGMT_CONTROL	0xa02c
2062306a36Sopenharmony_ci#define MII_MGMT_STATUS		0xa030
2162306a36Sopenharmony_ci#define MII_MGMT_INDICATORS	0xa034
2262306a36Sopenharmony_ci#define INTERFACE_CONTROL	0xa038
2362306a36Sopenharmony_ci#define STATION_ADDR0		0xa040
2462306a36Sopenharmony_ci#define STATION_ADDR1		0xa044
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci#define RGMII_REG_0		0x27e0
2762306a36Sopenharmony_ci#define ICM_CONFIG0_REG_0	0x2c00
2862306a36Sopenharmony_ci#define ICM_CONFIG2_REG_0	0x2c08
2962306a36Sopenharmony_ci#define ECM_CONFIG0_REG_0	0x2d00
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ci/* Register fields */
3262306a36Sopenharmony_ci#define SOFT_RESET		BIT(31)
3362306a36Sopenharmony_ci#define TX_EN			BIT(0)
3462306a36Sopenharmony_ci#define RX_EN			BIT(2)
3562306a36Sopenharmony_ci#define PAD_CRC			BIT(2)
3662306a36Sopenharmony_ci#define CRC_EN			BIT(1)
3762306a36Sopenharmony_ci#define FULL_DUPLEX		BIT(0)
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci#define INTF_MODE_POS		8
4062306a36Sopenharmony_ci#define INTF_MODE_LEN		2
4162306a36Sopenharmony_ci#define HD_MODE_POS		25
4262306a36Sopenharmony_ci#define HD_MODE_LEN		2
4362306a36Sopenharmony_ci#define CFG_MACMODE_POS		18
4462306a36Sopenharmony_ci#define CFG_MACMODE_LEN		2
4562306a36Sopenharmony_ci#define CFG_WAITASYNCRD_POS	0
4662306a36Sopenharmony_ci#define CFG_WAITASYNCRD_LEN	16
4762306a36Sopenharmony_ci#define CFG_SPEED_125_POS	24
4862306a36Sopenharmony_ci#define CFG_WFIFOFULLTHR_POS	0
4962306a36Sopenharmony_ci#define CFG_WFIFOFULLTHR_LEN	7
5062306a36Sopenharmony_ci#define MGMT_CLOCK_SEL_POS	0
5162306a36Sopenharmony_ci#define MGMT_CLOCK_SEL_LEN	3
5262306a36Sopenharmony_ci#define PHY_ADDR_POS		8
5362306a36Sopenharmony_ci#define PHY_ADDR_LEN		5
5462306a36Sopenharmony_ci#define REG_ADDR_POS		0
5562306a36Sopenharmony_ci#define REG_ADDR_LEN		5
5662306a36Sopenharmony_ci#define MII_MGMT_BUSY		BIT(0)
5762306a36Sopenharmony_ci#define MII_READ_CYCLE		BIT(0)
5862306a36Sopenharmony_ci#define CFG_WAITASYNCRD_EN	BIT(16)
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_cistatic inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
6162306a36Sopenharmony_ci{
6262306a36Sopenharmony_ci	u32 mask = GENMASK(pos + len, pos);
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_ci	*var &= ~mask;
6562306a36Sopenharmony_ci	*var |= ((val << pos) & mask);
6662306a36Sopenharmony_ci}
6762306a36Sopenharmony_ci
6862306a36Sopenharmony_cistatic inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
6962306a36Sopenharmony_ci{
7062306a36Sopenharmony_ci	u32 mask = GENMASK(pos + len, pos);
7162306a36Sopenharmony_ci
7262306a36Sopenharmony_ci	return (var & mask) >> pos;
7362306a36Sopenharmony_ci}
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci#define SET_REG_BITS(var, field, val)					\
7662306a36Sopenharmony_ci	xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci#define SET_REG_BIT(var, field, val)					\
7962306a36Sopenharmony_ci	xgene_set_reg_bits(var, field ## _POS, 1, val)
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ci#define GET_REG_BITS(var, field)					\
8262306a36Sopenharmony_ci	xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
8362306a36Sopenharmony_ci
8462306a36Sopenharmony_ci#define GET_REG_BIT(var, field)		((var) & (field))
8562306a36Sopenharmony_ci
8662306a36Sopenharmony_cistruct xge_pdata;
8762306a36Sopenharmony_ci
8862306a36Sopenharmony_civoid xge_mac_reset(struct xge_pdata *pdata);
8962306a36Sopenharmony_civoid xge_mac_set_speed(struct xge_pdata *pdata);
9062306a36Sopenharmony_civoid xge_mac_enable(struct xge_pdata *pdata);
9162306a36Sopenharmony_civoid xge_mac_disable(struct xge_pdata *pdata);
9262306a36Sopenharmony_civoid xge_mac_init(struct xge_pdata *pdata);
9362306a36Sopenharmony_civoid xge_mac_set_station_addr(struct xge_pdata *pdata);
9462306a36Sopenharmony_ci
9562306a36Sopenharmony_ci#endif /* __XGENE_ENET_V2_MAC_H__ */
96