162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Applied Micro X-Gene SoC Ethernet v2 Driver 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2017, Applied Micro Circuits Corporation 662306a36Sopenharmony_ci * Author(s): Iyappan Subramanian <isubramanian@apm.com> 762306a36Sopenharmony_ci * Keyur Chudgar <kchudgar@apm.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef __XGENE_ENET_V2_ENET_H__ 1162306a36Sopenharmony_ci#define __XGENE_ENET_V2_ENET_H__ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#define ENET_CLKEN 0xc008 1462306a36Sopenharmony_ci#define ENET_SRST 0xc000 1562306a36Sopenharmony_ci#define ENET_SHIM 0xc010 1662306a36Sopenharmony_ci#define CFG_MEM_RAM_SHUTDOWN 0xd070 1762306a36Sopenharmony_ci#define BLOCK_MEM_RDY 0xd074 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci#define MEM_RDY 0xffffffff 2062306a36Sopenharmony_ci#define DEVM_ARAUX_COH BIT(19) 2162306a36Sopenharmony_ci#define DEVM_AWAUX_COH BIT(3) 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define CFG_FORCE_LINK_STATUS_EN 0x229c 2462306a36Sopenharmony_ci#define FORCE_LINK_STATUS 0x22a0 2562306a36Sopenharmony_ci#define CFG_LINK_AGGR_RESUME 0x27c8 2662306a36Sopenharmony_ci#define RX_DV_GATE_REG 0x2dfc 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_civoid xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val); 2962306a36Sopenharmony_ciu32 xge_rd_csr(struct xge_pdata *pdata, u32 offset); 3062306a36Sopenharmony_ciint xge_port_reset(struct net_device *ndev); 3162306a36Sopenharmony_civoid xge_port_init(struct net_device *ndev); 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif /* __XGENE_ENET_V2_ENET__H__ */ 34