162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci/* Register Base Addresses */ 462306a36Sopenharmony_ci#define XRS_DEVICE_ID_BASE 0x0 562306a36Sopenharmony_ci#define XRS_GPIO_BASE 0x10000 662306a36Sopenharmony_ci#define XRS_PORT_OFFSET 0x10000 762306a36Sopenharmony_ci#define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x)) 862306a36Sopenharmony_ci#define XRS_RTC_BASE 0x280000 962306a36Sopenharmony_ci#define XRS_TS_OFFSET 0x8000 1062306a36Sopenharmony_ci#define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x)) 1162306a36Sopenharmony_ci#define XRS_SWITCH_CONF_BASE 0x300000 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* Device Identification Registers */ 1462306a36Sopenharmony_ci#define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0) 1562306a36Sopenharmony_ci#define XRS_DEV_ID1 (XRS_DEVICE_ID_BASE + 2) 1662306a36Sopenharmony_ci#define XRS_INT_ID0 (XRS_DEVICE_ID_BASE + 4) 1762306a36Sopenharmony_ci#define XRS_INT_ID1 (XRS_DEVICE_ID_BASE + 6) 1862306a36Sopenharmony_ci#define XRS_REV_ID (XRS_DEVICE_ID_BASE + 8) 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci/* GPIO Registers */ 2162306a36Sopenharmony_ci#define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000) 2262306a36Sopenharmony_ci#define XRS_INPUT_STATUS0 (XRS_GPIO_BASE + 0x1002) 2362306a36Sopenharmony_ci#define XRS_CONFIG1 (XRS_GPIO_BASE + 0x1004) 2462306a36Sopenharmony_ci#define XRS_INPUT_STATUS1 (XRS_GPIO_BASE + 0x1006) 2562306a36Sopenharmony_ci#define XRS_CONFIG2 (XRS_GPIO_BASE + 0x1008) 2662306a36Sopenharmony_ci#define XRS_INPUT_STATUS2 (XRS_GPIO_BASE + 0x100a) 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci/* Port Configuration Registers */ 2962306a36Sopenharmony_ci#define XRS_PORT_GEN_BASE(x) (XRS_PORT_BASE(x) + 0x0) 3062306a36Sopenharmony_ci#define XRS_PORT_HSR_BASE(x) (XRS_PORT_BASE(x) + 0x2000) 3162306a36Sopenharmony_ci#define XRS_PORT_PTP_BASE(x) (XRS_PORT_BASE(x) + 0x4000) 3262306a36Sopenharmony_ci#define XRS_PORT_CNT_BASE(x) (XRS_PORT_BASE(x) + 0x6000) 3362306a36Sopenharmony_ci#define XRS_PORT_IPO_BASE(x) (XRS_PORT_BASE(x) + 0x8000) 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* Port Configuration Registers - General and State */ 3662306a36Sopenharmony_ci#define XRS_PORT_STATE(x) (XRS_PORT_GEN_BASE(x) + 0x0) 3762306a36Sopenharmony_ci#define XRS_PORT_FORWARDING 0 3862306a36Sopenharmony_ci#define XRS_PORT_LEARNING 1 3962306a36Sopenharmony_ci#define XRS_PORT_DISABLED 2 4062306a36Sopenharmony_ci#define XRS_PORT_MODE_NORMAL 0 4162306a36Sopenharmony_ci#define XRS_PORT_MODE_MANAGEMENT 1 4262306a36Sopenharmony_ci#define XRS_PORT_SPEED_1000 0x12 4362306a36Sopenharmony_ci#define XRS_PORT_SPEED_100 0x20 4462306a36Sopenharmony_ci#define XRS_PORT_SPEED_10 0x30 4562306a36Sopenharmony_ci#define XRS_PORT_VLAN(x) (XRS_PORT_GEN_BASE(x) + 0x10) 4662306a36Sopenharmony_ci#define XRS_PORT_VLAN0_MAPPING(x) (XRS_PORT_GEN_BASE(x) + 0x12) 4762306a36Sopenharmony_ci#define XRS_PORT_FWD_MASK(x) (XRS_PORT_GEN_BASE(x) + 0x14) 4862306a36Sopenharmony_ci#define XRS_PORT_VLAN_PRIO(x) (XRS_PORT_GEN_BASE(x) + 0x16) 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci/* Port Configuration Registers - HSR/PRP */ 5162306a36Sopenharmony_ci#define XRS_HSR_CFG(x) (XRS_PORT_HSR_BASE(x) + 0x0) 5262306a36Sopenharmony_ci#define XRS_HSR_CFG_HSR_PRP BIT(0) 5362306a36Sopenharmony_ci#define XRS_HSR_CFG_HSR 0 5462306a36Sopenharmony_ci#define XRS_HSR_CFG_PRP BIT(8) 5562306a36Sopenharmony_ci#define XRS_HSR_CFG_LANID_A 0 5662306a36Sopenharmony_ci#define XRS_HSR_CFG_LANID_B BIT(10) 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci/* Port Configuration Registers - PTP */ 5962306a36Sopenharmony_ci#define XRS_PTP_RX_SYNC_DELAY_NS_LO(x) (XRS_PORT_PTP_BASE(x) + 0x2) 6062306a36Sopenharmony_ci#define XRS_PTP_RX_SYNC_DELAY_NS_HI(x) (XRS_PORT_PTP_BASE(x) + 0x4) 6162306a36Sopenharmony_ci#define XRS_PTP_RX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0xa) 6262306a36Sopenharmony_ci#define XRS_PTP_TX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0x12) 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci/* Port Configuration Registers - Counter */ 6562306a36Sopenharmony_ci#define XRS_CNT_CTRL(x) (XRS_PORT_CNT_BASE(x) + 0x0) 6662306a36Sopenharmony_ci#define XRS_RX_GOOD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x200) 6762306a36Sopenharmony_ci#define XRS_RX_GOOD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x202) 6862306a36Sopenharmony_ci#define XRS_RX_BAD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x204) 6962306a36Sopenharmony_ci#define XRS_RX_BAD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x206) 7062306a36Sopenharmony_ci#define XRS_RX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x208) 7162306a36Sopenharmony_ci#define XRS_RX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x20a) 7262306a36Sopenharmony_ci#define XRS_RX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x20c) 7362306a36Sopenharmony_ci#define XRS_RX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x20e) 7462306a36Sopenharmony_ci#define XRS_RX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x210) 7562306a36Sopenharmony_ci#define XRS_RX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x212) 7662306a36Sopenharmony_ci#define XRS_RX_UNDERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x214) 7762306a36Sopenharmony_ci#define XRS_RX_UNDERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x216) 7862306a36Sopenharmony_ci#define XRS_RX_FRAGMENTS_L (XRS_PORT_CNT_BASE(0) + 0x218) 7962306a36Sopenharmony_ci#define XRS_RX_FRAGMENTS_H (XRS_PORT_CNT_BASE(0) + 0x21a) 8062306a36Sopenharmony_ci#define XRS_RX_OVERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x21c) 8162306a36Sopenharmony_ci#define XRS_RX_OVERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x21e) 8262306a36Sopenharmony_ci#define XRS_RX_JABBER_L (XRS_PORT_CNT_BASE(0) + 0x220) 8362306a36Sopenharmony_ci#define XRS_RX_JABBER_H (XRS_PORT_CNT_BASE(0) + 0x222) 8462306a36Sopenharmony_ci#define XRS_RX_ERR_L (XRS_PORT_CNT_BASE(0) + 0x224) 8562306a36Sopenharmony_ci#define XRS_RX_ERR_H (XRS_PORT_CNT_BASE(0) + 0x226) 8662306a36Sopenharmony_ci#define XRS_RX_CRC_L (XRS_PORT_CNT_BASE(0) + 0x228) 8762306a36Sopenharmony_ci#define XRS_RX_CRC_H (XRS_PORT_CNT_BASE(0) + 0x22a) 8862306a36Sopenharmony_ci#define XRS_RX_64_L (XRS_PORT_CNT_BASE(0) + 0x22c) 8962306a36Sopenharmony_ci#define XRS_RX_64_H (XRS_PORT_CNT_BASE(0) + 0x22e) 9062306a36Sopenharmony_ci#define XRS_RX_65_127_L (XRS_PORT_CNT_BASE(0) + 0x230) 9162306a36Sopenharmony_ci#define XRS_RX_65_127_H (XRS_PORT_CNT_BASE(0) + 0x232) 9262306a36Sopenharmony_ci#define XRS_RX_128_255_L (XRS_PORT_CNT_BASE(0) + 0x234) 9362306a36Sopenharmony_ci#define XRS_RX_128_255_H (XRS_PORT_CNT_BASE(0) + 0x236) 9462306a36Sopenharmony_ci#define XRS_RX_256_511_L (XRS_PORT_CNT_BASE(0) + 0x238) 9562306a36Sopenharmony_ci#define XRS_RX_256_511_H (XRS_PORT_CNT_BASE(0) + 0x23a) 9662306a36Sopenharmony_ci#define XRS_RX_512_1023_L (XRS_PORT_CNT_BASE(0) + 0x23c) 9762306a36Sopenharmony_ci#define XRS_RX_512_1023_H (XRS_PORT_CNT_BASE(0) + 0x23e) 9862306a36Sopenharmony_ci#define XRS_RX_1024_1536_L (XRS_PORT_CNT_BASE(0) + 0x240) 9962306a36Sopenharmony_ci#define XRS_RX_1024_1536_H (XRS_PORT_CNT_BASE(0) + 0x242) 10062306a36Sopenharmony_ci#define XRS_RX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x244) 10162306a36Sopenharmony_ci#define XRS_RX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x246) 10262306a36Sopenharmony_ci#define XRS_RX_WRONGLAN_L (XRS_PORT_CNT_BASE(0) + 0x248) 10362306a36Sopenharmony_ci#define XRS_RX_WRONGLAN_H (XRS_PORT_CNT_BASE(0) + 0x24a) 10462306a36Sopenharmony_ci#define XRS_RX_DUPLICATE_L (XRS_PORT_CNT_BASE(0) + 0x24c) 10562306a36Sopenharmony_ci#define XRS_RX_DUPLICATE_H (XRS_PORT_CNT_BASE(0) + 0x24e) 10662306a36Sopenharmony_ci#define XRS_TX_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x280) 10762306a36Sopenharmony_ci#define XRS_TX_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x282) 10862306a36Sopenharmony_ci#define XRS_TX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x284) 10962306a36Sopenharmony_ci#define XRS_TX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x286) 11062306a36Sopenharmony_ci#define XRS_TX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x288) 11162306a36Sopenharmony_ci#define XRS_TX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x28a) 11262306a36Sopenharmony_ci#define XRS_TX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x28c) 11362306a36Sopenharmony_ci#define XRS_TX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x28e) 11462306a36Sopenharmony_ci#define XRS_TX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x290) 11562306a36Sopenharmony_ci#define XRS_TX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x292) 11662306a36Sopenharmony_ci#define XRS_PRIQ_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c0) 11762306a36Sopenharmony_ci#define XRS_PRIQ_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c2) 11862306a36Sopenharmony_ci#define XRS_EARLY_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c4) 11962306a36Sopenharmony_ci#define XRS_EARLY_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c6) 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci/* Port Configuration Registers - Inbound Policy 0 - 15 */ 12262306a36Sopenharmony_ci#define XRS_ETH_ADDR_CFG(x, p) (XRS_PORT_IPO_BASE(x) + \ 12362306a36Sopenharmony_ci (p) * 0x20 + 0x0) 12462306a36Sopenharmony_ci#define XRS_ETH_ADDR_FWD_ALLOW(x, p) (XRS_PORT_IPO_BASE(x) + \ 12562306a36Sopenharmony_ci (p) * 0x20 + 0x2) 12662306a36Sopenharmony_ci#define XRS_ETH_ADDR_FWD_MIRROR(x, p) (XRS_PORT_IPO_BASE(x) + \ 12762306a36Sopenharmony_ci (p) * 0x20 + 0x4) 12862306a36Sopenharmony_ci#define XRS_ETH_ADDR_0(x, p) (XRS_PORT_IPO_BASE(x) + \ 12962306a36Sopenharmony_ci (p) * 0x20 + 0x8) 13062306a36Sopenharmony_ci#define XRS_ETH_ADDR_1(x, p) (XRS_PORT_IPO_BASE(x) + \ 13162306a36Sopenharmony_ci (p) * 0x20 + 0xa) 13262306a36Sopenharmony_ci#define XRS_ETH_ADDR_2(x, p) (XRS_PORT_IPO_BASE(x) + \ 13362306a36Sopenharmony_ci (p) * 0x20 + 0xc) 13462306a36Sopenharmony_ci 13562306a36Sopenharmony_ci/* RTC Registers */ 13662306a36Sopenharmony_ci#define XRS_CUR_NSEC0 (XRS_RTC_BASE + 0x1004) 13762306a36Sopenharmony_ci#define XRS_CUR_NSEC1 (XRS_RTC_BASE + 0x1006) 13862306a36Sopenharmony_ci#define XRS_CUR_SEC0 (XRS_RTC_BASE + 0x1008) 13962306a36Sopenharmony_ci#define XRS_CUR_SEC1 (XRS_RTC_BASE + 0x100a) 14062306a36Sopenharmony_ci#define XRS_CUR_SEC2 (XRS_RTC_BASE + 0x100c) 14162306a36Sopenharmony_ci#define XRS_TIME_CC0 (XRS_RTC_BASE + 0x1010) 14262306a36Sopenharmony_ci#define XRS_TIME_CC1 (XRS_RTC_BASE + 0x1012) 14362306a36Sopenharmony_ci#define XRS_TIME_CC2 (XRS_RTC_BASE + 0x1014) 14462306a36Sopenharmony_ci#define XRS_STEP_SIZE0 (XRS_RTC_BASE + 0x1020) 14562306a36Sopenharmony_ci#define XRS_STEP_SIZE1 (XRS_RTC_BASE + 0x1022) 14662306a36Sopenharmony_ci#define XRS_STEP_SIZE2 (XRS_RTC_BASE + 0x1024) 14762306a36Sopenharmony_ci#define XRS_ADJUST_NSEC0 (XRS_RTC_BASE + 0x1034) 14862306a36Sopenharmony_ci#define XRS_ADJUST_NSEC1 (XRS_RTC_BASE + 0x1036) 14962306a36Sopenharmony_ci#define XRS_ADJUST_SEC0 (XRS_RTC_BASE + 0x1038) 15062306a36Sopenharmony_ci#define XRS_ADJUST_SEC1 (XRS_RTC_BASE + 0x103a) 15162306a36Sopenharmony_ci#define XRS_ADJUST_SEC2 (XRS_RTC_BASE + 0x103c) 15262306a36Sopenharmony_ci#define XRS_TIME_CMD (XRS_RTC_BASE + 0x1040) 15362306a36Sopenharmony_ci 15462306a36Sopenharmony_ci/* Time Stamper Registers */ 15562306a36Sopenharmony_ci#define XRS_TS_CTRL(x) (XRS_TS_BASE(x) + 0x1000) 15662306a36Sopenharmony_ci#define XRS_TS_INT_MASK(x) (XRS_TS_BASE(x) + 0x1008) 15762306a36Sopenharmony_ci#define XRS_TS_INT_STATUS(x) (XRS_TS_BASE(x) + 0x1010) 15862306a36Sopenharmony_ci#define XRS_TS_NSEC0(x) (XRS_TS_BASE(x) + 0x1104) 15962306a36Sopenharmony_ci#define XRS_TS_NSEC1(x) (XRS_TS_BASE(x) + 0x1106) 16062306a36Sopenharmony_ci#define XRS_TS_SEC0(x) (XRS_TS_BASE(x) + 0x1108) 16162306a36Sopenharmony_ci#define XRS_TS_SEC1(x) (XRS_TS_BASE(x) + 0x110a) 16262306a36Sopenharmony_ci#define XRS_TS_SEC2(x) (XRS_TS_BASE(x) + 0x110c) 16362306a36Sopenharmony_ci#define XRS_PNCT0(x) (XRS_TS_BASE(x) + 0x1110) 16462306a36Sopenharmony_ci#define XRS_PNCT1(x) (XRS_TS_BASE(x) + 0x1112) 16562306a36Sopenharmony_ci 16662306a36Sopenharmony_ci/* Switch Configuration Registers */ 16762306a36Sopenharmony_ci#define XRS_SWITCH_GEN_BASE (XRS_SWITCH_CONF_BASE + 0x0) 16862306a36Sopenharmony_ci#define XRS_SWITCH_TS_BASE (XRS_SWITCH_CONF_BASE + 0x2000) 16962306a36Sopenharmony_ci#define XRS_SWITCH_VLAN_BASE (XRS_SWITCH_CONF_BASE + 0x4000) 17062306a36Sopenharmony_ci 17162306a36Sopenharmony_ci/* Switch Configuration Registers - General */ 17262306a36Sopenharmony_ci#define XRS_GENERAL (XRS_SWITCH_GEN_BASE + 0x10) 17362306a36Sopenharmony_ci#define XRS_GENERAL_TIME_TRAILER BIT(9) 17462306a36Sopenharmony_ci#define XRS_GENERAL_MOD_SYNC BIT(10) 17562306a36Sopenharmony_ci#define XRS_GENERAL_CUT_THRU BIT(13) 17662306a36Sopenharmony_ci#define XRS_GENERAL_CLR_MAC_TBL BIT(14) 17762306a36Sopenharmony_ci#define XRS_GENERAL_RESET BIT(15) 17862306a36Sopenharmony_ci#define XRS_MT_CLEAR_MASK (XRS_SWITCH_GEN_BASE + 0x12) 17962306a36Sopenharmony_ci#define XRS_ADDRESS_AGING (XRS_SWITCH_GEN_BASE + 0x20) 18062306a36Sopenharmony_ci#define XRS_TS_CTRL_TX (XRS_SWITCH_GEN_BASE + 0x28) 18162306a36Sopenharmony_ci#define XRS_TS_CTRL_RX (XRS_SWITCH_GEN_BASE + 0x2a) 18262306a36Sopenharmony_ci#define XRS_INT_MASK (XRS_SWITCH_GEN_BASE + 0x2c) 18362306a36Sopenharmony_ci#define XRS_INT_STATUS (XRS_SWITCH_GEN_BASE + 0x2e) 18462306a36Sopenharmony_ci#define XRS_MAC_TABLE0 (XRS_SWITCH_GEN_BASE + 0x200) 18562306a36Sopenharmony_ci#define XRS_MAC_TABLE1 (XRS_SWITCH_GEN_BASE + 0x202) 18662306a36Sopenharmony_ci#define XRS_MAC_TABLE2 (XRS_SWITCH_GEN_BASE + 0x204) 18762306a36Sopenharmony_ci#define XRS_MAC_TABLE3 (XRS_SWITCH_GEN_BASE + 0x206) 18862306a36Sopenharmony_ci 18962306a36Sopenharmony_ci/* Switch Configuration Registers - Frame Timestamp */ 19062306a36Sopenharmony_ci#define XRS_TX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0) 19162306a36Sopenharmony_ci#define XRS_TX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2) 19262306a36Sopenharmony_ci#define XRS_TX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4) 19362306a36Sopenharmony_ci#define XRS_TX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6) 19462306a36Sopenharmony_ci#define XRS_TX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 19562306a36Sopenharmony_ci 0x2 * (h) + 0xe) 19662306a36Sopenharmony_ci#define XRS_RX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 19762306a36Sopenharmony_ci 0x200) 19862306a36Sopenharmony_ci#define XRS_RX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 19962306a36Sopenharmony_ci 0x202) 20062306a36Sopenharmony_ci#define XRS_RX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 20162306a36Sopenharmony_ci 0x204) 20262306a36Sopenharmony_ci#define XRS_RX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 20362306a36Sopenharmony_ci 0x206) 20462306a36Sopenharmony_ci#define XRS_RX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 20562306a36Sopenharmony_ci 0x2 * (h) + 0xe) 20662306a36Sopenharmony_ci 20762306a36Sopenharmony_ci/* Switch Configuration Registers - VLAN */ 20862306a36Sopenharmony_ci#define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v)) 209