1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2016 John Crispin <john@phrozen.org> 7 */ 8 9#include <linux/netdevice.h> 10#include <net/dsa.h> 11#include <linux/if_bridge.h> 12 13#include "qca8k.h" 14 15#define MIB_DESC(_s, _o, _n) \ 16 { \ 17 .size = (_s), \ 18 .offset = (_o), \ 19 .name = (_n), \ 20 } 21 22const struct qca8k_mib_desc ar8327_mib[] = { 23 MIB_DESC(1, 0x00, "RxBroad"), 24 MIB_DESC(1, 0x04, "RxPause"), 25 MIB_DESC(1, 0x08, "RxMulti"), 26 MIB_DESC(1, 0x0c, "RxFcsErr"), 27 MIB_DESC(1, 0x10, "RxAlignErr"), 28 MIB_DESC(1, 0x14, "RxRunt"), 29 MIB_DESC(1, 0x18, "RxFragment"), 30 MIB_DESC(1, 0x1c, "Rx64Byte"), 31 MIB_DESC(1, 0x20, "Rx128Byte"), 32 MIB_DESC(1, 0x24, "Rx256Byte"), 33 MIB_DESC(1, 0x28, "Rx512Byte"), 34 MIB_DESC(1, 0x2c, "Rx1024Byte"), 35 MIB_DESC(1, 0x30, "Rx1518Byte"), 36 MIB_DESC(1, 0x34, "RxMaxByte"), 37 MIB_DESC(1, 0x38, "RxTooLong"), 38 MIB_DESC(2, 0x3c, "RxGoodByte"), 39 MIB_DESC(2, 0x44, "RxBadByte"), 40 MIB_DESC(1, 0x4c, "RxOverFlow"), 41 MIB_DESC(1, 0x50, "Filtered"), 42 MIB_DESC(1, 0x54, "TxBroad"), 43 MIB_DESC(1, 0x58, "TxPause"), 44 MIB_DESC(1, 0x5c, "TxMulti"), 45 MIB_DESC(1, 0x60, "TxUnderRun"), 46 MIB_DESC(1, 0x64, "Tx64Byte"), 47 MIB_DESC(1, 0x68, "Tx128Byte"), 48 MIB_DESC(1, 0x6c, "Tx256Byte"), 49 MIB_DESC(1, 0x70, "Tx512Byte"), 50 MIB_DESC(1, 0x74, "Tx1024Byte"), 51 MIB_DESC(1, 0x78, "Tx1518Byte"), 52 MIB_DESC(1, 0x7c, "TxMaxByte"), 53 MIB_DESC(1, 0x80, "TxOverSize"), 54 MIB_DESC(2, 0x84, "TxByte"), 55 MIB_DESC(1, 0x8c, "TxCollision"), 56 MIB_DESC(1, 0x90, "TxAbortCol"), 57 MIB_DESC(1, 0x94, "TxMultiCol"), 58 MIB_DESC(1, 0x98, "TxSingleCol"), 59 MIB_DESC(1, 0x9c, "TxExcDefer"), 60 MIB_DESC(1, 0xa0, "TxDefer"), 61 MIB_DESC(1, 0xa4, "TxLateCol"), 62 MIB_DESC(1, 0xa8, "RXUnicast"), 63 MIB_DESC(1, 0xac, "TXUnicast"), 64}; 65 66int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) 67{ 68 return regmap_read(priv->regmap, reg, val); 69} 70 71int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) 72{ 73 return regmap_write(priv->regmap, reg, val); 74} 75 76int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) 77{ 78 return regmap_update_bits(priv->regmap, reg, mask, write_val); 79} 80 81static const struct regmap_range qca8k_readable_ranges[] = { 82 regmap_reg_range(0x0000, 0x00e4), /* Global control */ 83 regmap_reg_range(0x0100, 0x0168), /* EEE control */ 84 regmap_reg_range(0x0200, 0x0270), /* Parser control */ 85 regmap_reg_range(0x0400, 0x0454), /* ACL */ 86 regmap_reg_range(0x0600, 0x0718), /* Lookup */ 87 regmap_reg_range(0x0800, 0x0b70), /* QM */ 88 regmap_reg_range(0x0c00, 0x0c80), /* PKT */ 89 regmap_reg_range(0x0e00, 0x0e98), /* L3 */ 90 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */ 91 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */ 92 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */ 93 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */ 94 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */ 95 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */ 96 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */ 97}; 98 99const struct regmap_access_table qca8k_readable_table = { 100 .yes_ranges = qca8k_readable_ranges, 101 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges), 102}; 103 104static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) 105{ 106 u32 val; 107 108 return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, 109 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); 110} 111 112static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) 113{ 114 u32 reg[QCA8K_ATU_TABLE_SIZE]; 115 int ret; 116 117 /* load the ARL table into an array */ 118 ret = regmap_bulk_read(priv->regmap, QCA8K_REG_ATU_DATA0, reg, 119 QCA8K_ATU_TABLE_SIZE); 120 if (ret) 121 return ret; 122 123 /* vid - 83:72 */ 124 fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); 125 /* aging - 67:64 */ 126 fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); 127 /* portmask - 54:48 */ 128 fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); 129 /* mac - 47:0 */ 130 fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); 131 fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); 132 fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); 133 fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); 134 fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); 135 fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); 136 137 return 0; 138} 139 140static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, 141 const u8 *mac, u8 aging) 142{ 143 u32 reg[QCA8K_ATU_TABLE_SIZE] = { 0 }; 144 145 /* vid - 83:72 */ 146 reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid); 147 /* aging - 67:64 */ 148 reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging); 149 /* portmask - 54:48 */ 150 reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask); 151 /* mac - 47:0 */ 152 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]); 153 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]); 154 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]); 155 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]); 156 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]); 157 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); 158 159 /* load the array into the ARL table */ 160 regmap_bulk_write(priv->regmap, QCA8K_REG_ATU_DATA0, reg, 161 QCA8K_ATU_TABLE_SIZE); 162} 163 164static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, 165 int port) 166{ 167 u32 reg; 168 int ret; 169 170 /* Set the command and FDB index */ 171 reg = QCA8K_ATU_FUNC_BUSY; 172 reg |= cmd; 173 if (port >= 0) { 174 reg |= QCA8K_ATU_FUNC_PORT_EN; 175 reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port); 176 } 177 178 /* Write the function register triggering the table access */ 179 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); 180 if (ret) 181 return ret; 182 183 /* wait for completion */ 184 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); 185 if (ret) 186 return ret; 187 188 /* Check for table full violation when adding an entry */ 189 if (cmd == QCA8K_FDB_LOAD) { 190 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); 191 if (ret < 0) 192 return ret; 193 if (reg & QCA8K_ATU_FUNC_FULL) 194 return -1; 195 } 196 197 return 0; 198} 199 200static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, 201 int port) 202{ 203 int ret; 204 205 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); 206 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); 207 if (ret < 0) 208 return ret; 209 210 return qca8k_fdb_read(priv, fdb); 211} 212 213static int qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, 214 u16 port_mask, u16 vid, u8 aging) 215{ 216 int ret; 217 218 mutex_lock(&priv->reg_mutex); 219 qca8k_fdb_write(priv, vid, port_mask, mac, aging); 220 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 221 mutex_unlock(&priv->reg_mutex); 222 223 return ret; 224} 225 226static int qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, 227 u16 port_mask, u16 vid) 228{ 229 int ret; 230 231 mutex_lock(&priv->reg_mutex); 232 qca8k_fdb_write(priv, vid, port_mask, mac, 0); 233 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 234 mutex_unlock(&priv->reg_mutex); 235 236 return ret; 237} 238 239void qca8k_fdb_flush(struct qca8k_priv *priv) 240{ 241 mutex_lock(&priv->reg_mutex); 242 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); 243 mutex_unlock(&priv->reg_mutex); 244} 245 246static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask, 247 const u8 *mac, u16 vid, u8 aging) 248{ 249 struct qca8k_fdb fdb = { 0 }; 250 int ret; 251 252 mutex_lock(&priv->reg_mutex); 253 254 qca8k_fdb_write(priv, vid, 0, mac, 0); 255 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); 256 if (ret < 0) 257 goto exit; 258 259 ret = qca8k_fdb_read(priv, &fdb); 260 if (ret < 0) 261 goto exit; 262 263 /* Rule exist. Delete first */ 264 if (fdb.aging) { 265 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 266 if (ret) 267 goto exit; 268 } else { 269 fdb.aging = aging; 270 } 271 272 /* Add port to fdb portmask */ 273 fdb.port_mask |= port_mask; 274 275 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); 276 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 277 278exit: 279 mutex_unlock(&priv->reg_mutex); 280 return ret; 281} 282 283static int qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask, 284 const u8 *mac, u16 vid) 285{ 286 struct qca8k_fdb fdb = { 0 }; 287 int ret; 288 289 mutex_lock(&priv->reg_mutex); 290 291 qca8k_fdb_write(priv, vid, 0, mac, 0); 292 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); 293 if (ret < 0) 294 goto exit; 295 296 ret = qca8k_fdb_read(priv, &fdb); 297 if (ret < 0) 298 goto exit; 299 300 /* Rule doesn't exist. Why delete? */ 301 if (!fdb.aging) { 302 ret = -EINVAL; 303 goto exit; 304 } 305 306 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 307 if (ret) 308 goto exit; 309 310 /* Only port in the rule is this port. Don't re insert */ 311 if (fdb.port_mask == port_mask) 312 goto exit; 313 314 /* Remove port from port mask */ 315 fdb.port_mask &= ~port_mask; 316 317 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); 318 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 319 320exit: 321 mutex_unlock(&priv->reg_mutex); 322 return ret; 323} 324 325static int qca8k_vlan_access(struct qca8k_priv *priv, 326 enum qca8k_vlan_cmd cmd, u16 vid) 327{ 328 u32 reg; 329 int ret; 330 331 /* Set the command and VLAN index */ 332 reg = QCA8K_VTU_FUNC1_BUSY; 333 reg |= cmd; 334 reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid); 335 336 /* Write the function register triggering the table access */ 337 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); 338 if (ret) 339 return ret; 340 341 /* wait for completion */ 342 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); 343 if (ret) 344 return ret; 345 346 /* Check for table full violation when adding an entry */ 347 if (cmd == QCA8K_VLAN_LOAD) { 348 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); 349 if (ret < 0) 350 return ret; 351 if (reg & QCA8K_VTU_FUNC1_FULL) 352 return -ENOMEM; 353 } 354 355 return 0; 356} 357 358static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, 359 bool untagged) 360{ 361 u32 reg; 362 int ret; 363 364 /* We do the right thing with VLAN 0 and treat it as untagged while 365 * preserving the tag on egress. 366 */ 367 if (vid == 0) 368 return 0; 369 370 mutex_lock(&priv->reg_mutex); 371 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); 372 if (ret < 0) 373 goto out; 374 375 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); 376 if (ret < 0) 377 goto out; 378 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; 379 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); 380 if (untagged) 381 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port); 382 else 383 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port); 384 385 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); 386 if (ret) 387 goto out; 388 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); 389 390out: 391 mutex_unlock(&priv->reg_mutex); 392 393 return ret; 394} 395 396static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) 397{ 398 u32 reg, mask; 399 int ret, i; 400 bool del; 401 402 mutex_lock(&priv->reg_mutex); 403 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); 404 if (ret < 0) 405 goto out; 406 407 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); 408 if (ret < 0) 409 goto out; 410 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); 411 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port); 412 413 /* Check if we're the last member to be removed */ 414 del = true; 415 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 416 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i); 417 418 if ((reg & mask) != mask) { 419 del = false; 420 break; 421 } 422 } 423 424 if (del) { 425 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); 426 } else { 427 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); 428 if (ret) 429 goto out; 430 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); 431 } 432 433out: 434 mutex_unlock(&priv->reg_mutex); 435 436 return ret; 437} 438 439int qca8k_mib_init(struct qca8k_priv *priv) 440{ 441 int ret; 442 443 mutex_lock(&priv->reg_mutex); 444 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, 445 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, 446 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) | 447 QCA8K_MIB_BUSY); 448 if (ret) 449 goto exit; 450 451 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); 452 if (ret) 453 goto exit; 454 455 ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); 456 if (ret) 457 goto exit; 458 459 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); 460 461exit: 462 mutex_unlock(&priv->reg_mutex); 463 return ret; 464} 465 466void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) 467{ 468 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; 469 470 /* Port 0 and 6 have no internal PHY */ 471 if (port > 0 && port < 6) 472 mask |= QCA8K_PORT_STATUS_LINK_AUTO; 473 474 if (enable) 475 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); 476 else 477 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); 478} 479 480void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, 481 uint8_t *data) 482{ 483 struct qca8k_priv *priv = ds->priv; 484 int i; 485 486 if (stringset != ETH_SS_STATS) 487 return; 488 489 for (i = 0; i < priv->info->mib_count; i++) 490 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, 491 ETH_GSTRING_LEN); 492} 493 494void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, 495 uint64_t *data) 496{ 497 struct qca8k_priv *priv = ds->priv; 498 const struct qca8k_mib_desc *mib; 499 u32 reg, i, val; 500 u32 hi = 0; 501 int ret; 502 503 if (priv->mgmt_master && priv->info->ops->autocast_mib && 504 priv->info->ops->autocast_mib(ds, port, data) > 0) 505 return; 506 507 for (i = 0; i < priv->info->mib_count; i++) { 508 mib = &ar8327_mib[i]; 509 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; 510 511 ret = qca8k_read(priv, reg, &val); 512 if (ret < 0) 513 continue; 514 515 if (mib->size == 2) { 516 ret = qca8k_read(priv, reg + 4, &hi); 517 if (ret < 0) 518 continue; 519 } 520 521 data[i] = val; 522 if (mib->size == 2) 523 data[i] |= (u64)hi << 32; 524 } 525} 526 527int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) 528{ 529 struct qca8k_priv *priv = ds->priv; 530 531 if (sset != ETH_SS_STATS) 532 return 0; 533 534 return priv->info->mib_count; 535} 536 537int qca8k_set_mac_eee(struct dsa_switch *ds, int port, 538 struct ethtool_eee *eee) 539{ 540 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); 541 struct qca8k_priv *priv = ds->priv; 542 u32 reg; 543 int ret; 544 545 mutex_lock(&priv->reg_mutex); 546 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); 547 if (ret < 0) 548 goto exit; 549 550 if (eee->eee_enabled) 551 reg |= lpi_en; 552 else 553 reg &= ~lpi_en; 554 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); 555 556exit: 557 mutex_unlock(&priv->reg_mutex); 558 return ret; 559} 560 561int qca8k_get_mac_eee(struct dsa_switch *ds, int port, 562 struct ethtool_eee *e) 563{ 564 /* Nothing to do on the port's MAC */ 565 return 0; 566} 567 568static int qca8k_port_configure_learning(struct dsa_switch *ds, int port, 569 bool learning) 570{ 571 struct qca8k_priv *priv = ds->priv; 572 573 if (learning) 574 return regmap_set_bits(priv->regmap, 575 QCA8K_PORT_LOOKUP_CTRL(port), 576 QCA8K_PORT_LOOKUP_LEARN); 577 else 578 return regmap_clear_bits(priv->regmap, 579 QCA8K_PORT_LOOKUP_CTRL(port), 580 QCA8K_PORT_LOOKUP_LEARN); 581} 582 583void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 584{ 585 struct dsa_port *dp = dsa_to_port(ds, port); 586 struct qca8k_priv *priv = ds->priv; 587 bool learning = false; 588 u32 stp_state; 589 590 switch (state) { 591 case BR_STATE_DISABLED: 592 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED; 593 break; 594 case BR_STATE_BLOCKING: 595 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING; 596 break; 597 case BR_STATE_LISTENING: 598 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING; 599 break; 600 case BR_STATE_LEARNING: 601 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING; 602 learning = dp->learning; 603 break; 604 case BR_STATE_FORWARDING: 605 learning = dp->learning; 606 fallthrough; 607 default: 608 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD; 609 break; 610 } 611 612 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 613 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); 614 615 qca8k_port_configure_learning(ds, port, learning); 616} 617 618int qca8k_port_pre_bridge_flags(struct dsa_switch *ds, int port, 619 struct switchdev_brport_flags flags, 620 struct netlink_ext_ack *extack) 621{ 622 if (flags.mask & ~BR_LEARNING) 623 return -EINVAL; 624 625 return 0; 626} 627 628int qca8k_port_bridge_flags(struct dsa_switch *ds, int port, 629 struct switchdev_brport_flags flags, 630 struct netlink_ext_ack *extack) 631{ 632 int ret; 633 634 if (flags.mask & BR_LEARNING) { 635 ret = qca8k_port_configure_learning(ds, port, 636 flags.val & BR_LEARNING); 637 if (ret) 638 return ret; 639 } 640 641 return 0; 642} 643 644int qca8k_port_bridge_join(struct dsa_switch *ds, int port, 645 struct dsa_bridge bridge, 646 bool *tx_fwd_offload, 647 struct netlink_ext_ack *extack) 648{ 649 struct qca8k_priv *priv = ds->priv; 650 int port_mask, cpu_port; 651 int i, ret; 652 653 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 654 port_mask = BIT(cpu_port); 655 656 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 657 if (dsa_is_cpu_port(ds, i)) 658 continue; 659 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 660 continue; 661 /* Add this port to the portvlan mask of the other ports 662 * in the bridge 663 */ 664 ret = regmap_set_bits(priv->regmap, 665 QCA8K_PORT_LOOKUP_CTRL(i), 666 BIT(port)); 667 if (ret) 668 return ret; 669 if (i != port) 670 port_mask |= BIT(i); 671 } 672 673 /* Add all other ports to this ports portvlan mask */ 674 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 675 QCA8K_PORT_LOOKUP_MEMBER, port_mask); 676 677 return ret; 678} 679 680void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, 681 struct dsa_bridge bridge) 682{ 683 struct qca8k_priv *priv = ds->priv; 684 int cpu_port, i; 685 686 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 687 688 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 689 if (dsa_is_cpu_port(ds, i)) 690 continue; 691 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 692 continue; 693 /* Remove this port to the portvlan mask of the other ports 694 * in the bridge 695 */ 696 regmap_clear_bits(priv->regmap, 697 QCA8K_PORT_LOOKUP_CTRL(i), 698 BIT(port)); 699 } 700 701 /* Set the cpu port to be the only one in the portvlan mask of 702 * this port 703 */ 704 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 705 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); 706} 707 708void qca8k_port_fast_age(struct dsa_switch *ds, int port) 709{ 710 struct qca8k_priv *priv = ds->priv; 711 712 mutex_lock(&priv->reg_mutex); 713 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); 714 mutex_unlock(&priv->reg_mutex); 715} 716 717int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 718{ 719 struct qca8k_priv *priv = ds->priv; 720 unsigned int secs = msecs / 1000; 721 u32 val; 722 723 /* AGE_TIME reg is set in 7s step */ 724 val = secs / 7; 725 726 /* Handle case with 0 as val to NOT disable 727 * learning 728 */ 729 if (!val) 730 val = 1; 731 732 return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, 733 QCA8K_ATU_AGE_TIME_MASK, 734 QCA8K_ATU_AGE_TIME(val)); 735} 736 737int qca8k_port_enable(struct dsa_switch *ds, int port, 738 struct phy_device *phy) 739{ 740 struct qca8k_priv *priv = ds->priv; 741 742 qca8k_port_set_status(priv, port, 1); 743 priv->port_enabled_map |= BIT(port); 744 745 if (dsa_is_user_port(ds, port)) 746 phy_support_asym_pause(phy); 747 748 return 0; 749} 750 751void qca8k_port_disable(struct dsa_switch *ds, int port) 752{ 753 struct qca8k_priv *priv = ds->priv; 754 755 qca8k_port_set_status(priv, port, 0); 756 priv->port_enabled_map &= ~BIT(port); 757} 758 759int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 760{ 761 struct qca8k_priv *priv = ds->priv; 762 int ret; 763 764 /* We have only have a general MTU setting. 765 * DSA always set the CPU port's MTU to the largest MTU of the slave 766 * ports. 767 * Setting MTU just for the CPU port is sufficient to correctly set a 768 * value for every port. 769 */ 770 if (!dsa_is_cpu_port(ds, port)) 771 return 0; 772 773 /* To change the MAX_FRAME_SIZE the cpu ports must be off or 774 * the switch panics. 775 * Turn off both cpu ports before applying the new value to prevent 776 * this. 777 */ 778 if (priv->port_enabled_map & BIT(0)) 779 qca8k_port_set_status(priv, 0, 0); 780 781 if (priv->port_enabled_map & BIT(6)) 782 qca8k_port_set_status(priv, 6, 0); 783 784 /* Include L2 header / FCS length */ 785 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + 786 ETH_HLEN + ETH_FCS_LEN); 787 788 if (priv->port_enabled_map & BIT(0)) 789 qca8k_port_set_status(priv, 0, 1); 790 791 if (priv->port_enabled_map & BIT(6)) 792 qca8k_port_set_status(priv, 6, 1); 793 794 return ret; 795} 796 797int qca8k_port_max_mtu(struct dsa_switch *ds, int port) 798{ 799 return QCA8K_MAX_MTU; 800} 801 802int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, 803 u16 port_mask, u16 vid) 804{ 805 /* Set the vid to the port vlan id if no vid is set */ 806 if (!vid) 807 vid = QCA8K_PORT_VID_DEF; 808 809 return qca8k_fdb_add(priv, addr, port_mask, vid, 810 QCA8K_ATU_STATUS_STATIC); 811} 812 813int qca8k_port_fdb_add(struct dsa_switch *ds, int port, 814 const unsigned char *addr, u16 vid, 815 struct dsa_db db) 816{ 817 struct qca8k_priv *priv = ds->priv; 818 u16 port_mask = BIT(port); 819 820 return qca8k_port_fdb_insert(priv, addr, port_mask, vid); 821} 822 823int qca8k_port_fdb_del(struct dsa_switch *ds, int port, 824 const unsigned char *addr, u16 vid, 825 struct dsa_db db) 826{ 827 struct qca8k_priv *priv = ds->priv; 828 u16 port_mask = BIT(port); 829 830 if (!vid) 831 vid = QCA8K_PORT_VID_DEF; 832 833 return qca8k_fdb_del(priv, addr, port_mask, vid); 834} 835 836int qca8k_port_fdb_dump(struct dsa_switch *ds, int port, 837 dsa_fdb_dump_cb_t *cb, void *data) 838{ 839 struct qca8k_priv *priv = ds->priv; 840 struct qca8k_fdb _fdb = { 0 }; 841 int cnt = QCA8K_NUM_FDB_RECORDS; 842 bool is_static; 843 int ret = 0; 844 845 mutex_lock(&priv->reg_mutex); 846 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { 847 if (!_fdb.aging) 848 break; 849 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC); 850 ret = cb(_fdb.mac, _fdb.vid, is_static, data); 851 if (ret) 852 break; 853 } 854 mutex_unlock(&priv->reg_mutex); 855 856 return 0; 857} 858 859int qca8k_port_mdb_add(struct dsa_switch *ds, int port, 860 const struct switchdev_obj_port_mdb *mdb, 861 struct dsa_db db) 862{ 863 struct qca8k_priv *priv = ds->priv; 864 const u8 *addr = mdb->addr; 865 u16 vid = mdb->vid; 866 867 if (!vid) 868 vid = QCA8K_PORT_VID_DEF; 869 870 return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid, 871 QCA8K_ATU_STATUS_STATIC); 872} 873 874int qca8k_port_mdb_del(struct dsa_switch *ds, int port, 875 const struct switchdev_obj_port_mdb *mdb, 876 struct dsa_db db) 877{ 878 struct qca8k_priv *priv = ds->priv; 879 const u8 *addr = mdb->addr; 880 u16 vid = mdb->vid; 881 882 if (!vid) 883 vid = QCA8K_PORT_VID_DEF; 884 885 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); 886} 887 888int qca8k_port_mirror_add(struct dsa_switch *ds, int port, 889 struct dsa_mall_mirror_tc_entry *mirror, 890 bool ingress, struct netlink_ext_ack *extack) 891{ 892 struct qca8k_priv *priv = ds->priv; 893 int monitor_port, ret; 894 u32 reg, val; 895 896 /* Check for existent entry */ 897 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 898 return -EEXIST; 899 900 ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val); 901 if (ret) 902 return ret; 903 904 /* QCA83xx can have only one port set to mirror mode. 905 * Check that the correct port is requested and return error otherwise. 906 * When no mirror port is set, the values is set to 0xF 907 */ 908 monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 909 if (monitor_port != 0xF && monitor_port != mirror->to_local_port) 910 return -EEXIST; 911 912 /* Set the monitor port */ 913 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 914 mirror->to_local_port); 915 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 916 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 917 if (ret) 918 return ret; 919 920 if (ingress) { 921 reg = QCA8K_PORT_LOOKUP_CTRL(port); 922 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN; 923 } else { 924 reg = QCA8K_REG_PORT_HOL_CTRL1(port); 925 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; 926 } 927 928 ret = regmap_update_bits(priv->regmap, reg, val, val); 929 if (ret) 930 return ret; 931 932 /* Track mirror port for tx and rx to decide when the 933 * mirror port has to be disabled. 934 */ 935 if (ingress) 936 priv->mirror_rx |= BIT(port); 937 else 938 priv->mirror_tx |= BIT(port); 939 940 return 0; 941} 942 943void qca8k_port_mirror_del(struct dsa_switch *ds, int port, 944 struct dsa_mall_mirror_tc_entry *mirror) 945{ 946 struct qca8k_priv *priv = ds->priv; 947 u32 reg, val; 948 int ret; 949 950 if (mirror->ingress) { 951 reg = QCA8K_PORT_LOOKUP_CTRL(port); 952 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN; 953 } else { 954 reg = QCA8K_REG_PORT_HOL_CTRL1(port); 955 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; 956 } 957 958 ret = regmap_clear_bits(priv->regmap, reg, val); 959 if (ret) 960 goto err; 961 962 if (mirror->ingress) 963 priv->mirror_rx &= ~BIT(port); 964 else 965 priv->mirror_tx &= ~BIT(port); 966 967 /* No port set to send packet to mirror port. Disable mirror port */ 968 if (!priv->mirror_rx && !priv->mirror_tx) { 969 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF); 970 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 971 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 972 if (ret) 973 goto err; 974 } 975err: 976 dev_err(priv->dev, "Failed to del mirror port from %d", port); 977} 978 979int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, 980 bool vlan_filtering, 981 struct netlink_ext_ack *extack) 982{ 983 struct qca8k_priv *priv = ds->priv; 984 int ret; 985 986 if (vlan_filtering) { 987 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 988 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, 989 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); 990 } else { 991 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 992 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, 993 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); 994 } 995 996 return ret; 997} 998 999int qca8k_port_vlan_add(struct dsa_switch *ds, int port, 1000 const struct switchdev_obj_port_vlan *vlan, 1001 struct netlink_ext_ack *extack) 1002{ 1003 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1004 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1005 struct qca8k_priv *priv = ds->priv; 1006 int ret; 1007 1008 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); 1009 if (ret) { 1010 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); 1011 return ret; 1012 } 1013 1014 if (pvid) { 1015 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), 1016 QCA8K_EGREES_VLAN_PORT_MASK(port), 1017 QCA8K_EGREES_VLAN_PORT(port, vlan->vid)); 1018 if (ret) 1019 return ret; 1020 1021 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), 1022 QCA8K_PORT_VLAN_CVID(vlan->vid) | 1023 QCA8K_PORT_VLAN_SVID(vlan->vid)); 1024 } 1025 1026 return ret; 1027} 1028 1029int qca8k_port_vlan_del(struct dsa_switch *ds, int port, 1030 const struct switchdev_obj_port_vlan *vlan) 1031{ 1032 struct qca8k_priv *priv = ds->priv; 1033 int ret; 1034 1035 ret = qca8k_vlan_del(priv, port, vlan->vid); 1036 if (ret) 1037 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); 1038 1039 return ret; 1040} 1041 1042static bool qca8k_lag_can_offload(struct dsa_switch *ds, 1043 struct dsa_lag lag, 1044 struct netdev_lag_upper_info *info, 1045 struct netlink_ext_ack *extack) 1046{ 1047 struct dsa_port *dp; 1048 int members = 0; 1049 1050 if (!lag.id) 1051 return false; 1052 1053 dsa_lag_foreach_port(dp, ds->dst, &lag) 1054 /* Includes the port joining the LAG */ 1055 members++; 1056 1057 if (members > QCA8K_NUM_PORTS_FOR_LAG) { 1058 NL_SET_ERR_MSG_MOD(extack, 1059 "Cannot offload more than 4 LAG ports"); 1060 return false; 1061 } 1062 1063 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1064 NL_SET_ERR_MSG_MOD(extack, 1065 "Can only offload LAG using hash TX type"); 1066 return false; 1067 } 1068 1069 if (info->hash_type != NETDEV_LAG_HASH_L2 && 1070 info->hash_type != NETDEV_LAG_HASH_L23) { 1071 NL_SET_ERR_MSG_MOD(extack, 1072 "Can only offload L2 or L2+L3 TX hash"); 1073 return false; 1074 } 1075 1076 return true; 1077} 1078 1079static int qca8k_lag_setup_hash(struct dsa_switch *ds, 1080 struct dsa_lag lag, 1081 struct netdev_lag_upper_info *info) 1082{ 1083 struct net_device *lag_dev = lag.dev; 1084 struct qca8k_priv *priv = ds->priv; 1085 bool unique_lag = true; 1086 unsigned int i; 1087 u32 hash = 0; 1088 1089 switch (info->hash_type) { 1090 case NETDEV_LAG_HASH_L23: 1091 hash |= QCA8K_TRUNK_HASH_SIP_EN; 1092 hash |= QCA8K_TRUNK_HASH_DIP_EN; 1093 fallthrough; 1094 case NETDEV_LAG_HASH_L2: 1095 hash |= QCA8K_TRUNK_HASH_SA_EN; 1096 hash |= QCA8K_TRUNK_HASH_DA_EN; 1097 break; 1098 default: /* We should NEVER reach this */ 1099 return -EOPNOTSUPP; 1100 } 1101 1102 /* Check if we are the unique configured LAG */ 1103 dsa_lags_foreach_id(i, ds->dst) 1104 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) { 1105 unique_lag = false; 1106 break; 1107 } 1108 1109 /* Hash Mode is global. Make sure the same Hash Mode 1110 * is set to all the 4 possible lag. 1111 * If we are the unique LAG we can set whatever hash 1112 * mode we want. 1113 * To change hash mode it's needed to remove all LAG 1114 * and change the mode with the latest. 1115 */ 1116 if (unique_lag) { 1117 priv->lag_hash_mode = hash; 1118 } else if (priv->lag_hash_mode != hash) { 1119 netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is not supported\n"); 1120 return -EOPNOTSUPP; 1121 } 1122 1123 return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL, 1124 QCA8K_TRUNK_HASH_MASK, hash); 1125} 1126 1127static int qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port, 1128 struct dsa_lag lag, bool delete) 1129{ 1130 struct qca8k_priv *priv = ds->priv; 1131 int ret, id, i; 1132 u32 val; 1133 1134 /* DSA LAG IDs are one-based, hardware is zero-based */ 1135 id = lag.id - 1; 1136 1137 /* Read current port member */ 1138 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val); 1139 if (ret) 1140 return ret; 1141 1142 /* Shift val to the correct trunk */ 1143 val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id); 1144 val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK; 1145 if (delete) 1146 val &= ~BIT(port); 1147 else 1148 val |= BIT(port); 1149 1150 /* Update port member. With empty portmap disable trunk */ 1151 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, 1152 QCA8K_REG_GOL_TRUNK_MEMBER(id) | 1153 QCA8K_REG_GOL_TRUNK_EN(id), 1154 !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) | 1155 val << QCA8K_REG_GOL_TRUNK_SHIFT(id)); 1156 1157 /* Search empty member if adding or port on deleting */ 1158 for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) { 1159 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val); 1160 if (ret) 1161 return ret; 1162 1163 val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i); 1164 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK; 1165 1166 if (delete) { 1167 /* If port flagged to be disabled assume this member is 1168 * empty 1169 */ 1170 if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) 1171 continue; 1172 1173 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK; 1174 if (val != port) 1175 continue; 1176 } else { 1177 /* If port flagged to be enabled assume this member is 1178 * already set 1179 */ 1180 if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) 1181 continue; 1182 } 1183 1184 /* We have found the member to add/remove */ 1185 break; 1186 } 1187 1188 /* Set port in the correct port mask or disable port if in delete mode */ 1189 return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), 1190 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) | 1191 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i), 1192 !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) | 1193 port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i)); 1194} 1195 1196int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag, 1197 struct netdev_lag_upper_info *info, 1198 struct netlink_ext_ack *extack) 1199{ 1200 int ret; 1201 1202 if (!qca8k_lag_can_offload(ds, lag, info, extack)) 1203 return -EOPNOTSUPP; 1204 1205 ret = qca8k_lag_setup_hash(ds, lag, info); 1206 if (ret) 1207 return ret; 1208 1209 return qca8k_lag_refresh_portmap(ds, port, lag, false); 1210} 1211 1212int qca8k_port_lag_leave(struct dsa_switch *ds, int port, 1213 struct dsa_lag lag) 1214{ 1215 return qca8k_lag_refresh_portmap(ds, port, lag, true); 1216} 1217 1218int qca8k_read_switch_id(struct qca8k_priv *priv) 1219{ 1220 u32 val; 1221 u8 id; 1222 int ret; 1223 1224 if (!priv->info) 1225 return -ENODEV; 1226 1227 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); 1228 if (ret < 0) 1229 return -ENODEV; 1230 1231 id = QCA8K_MASK_CTRL_DEVICE_ID(val); 1232 if (id != priv->info->id) { 1233 dev_err(priv->dev, 1234 "Switch id detected %x but expected %x", 1235 id, priv->info->id); 1236 return -ENODEV; 1237 } 1238 1239 priv->switch_id = id; 1240 1241 /* Save revision to communicate to the internal PHY driver */ 1242 priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val); 1243 1244 return 0; 1245} 1246