162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Marvell 88E6xxx PHY access
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (c) 2008 Marvell Semiconductor
662306a36Sopenharmony_ci *
762306a36Sopenharmony_ci * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
862306a36Sopenharmony_ci */
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#ifndef _MV88E6XXX_PHY_H
1162306a36Sopenharmony_ci#define _MV88E6XXX_PHY_H
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#define MV88E6XXX_PHY_PAGE		0x16
1462306a36Sopenharmony_ci#define MV88E6XXX_PHY_PAGE_COPPER	0x00
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci/* PHY Registers accesses implementations */
1762306a36Sopenharmony_ciint mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
1862306a36Sopenharmony_ci		       int addr, int reg, u16 *val);
1962306a36Sopenharmony_ciint mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
2062306a36Sopenharmony_ci			int addr, int reg, u16 val);
2162306a36Sopenharmony_ciint mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
2262306a36Sopenharmony_ci			   int addr, int reg, u16 *val);
2362306a36Sopenharmony_ciint mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
2462306a36Sopenharmony_ci			    int addr, int reg, u16 val);
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci/* Generic PHY operations */
2762306a36Sopenharmony_ciint mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
2862306a36Sopenharmony_ci		       int reg, u16 *val);
2962306a36Sopenharmony_ciint mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
3062306a36Sopenharmony_ci			int reg, u16 val);
3162306a36Sopenharmony_ciint mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
3262306a36Sopenharmony_ci			   int reg, u16 *val);
3362306a36Sopenharmony_ciint mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
3462306a36Sopenharmony_ci			    int reg, u16 val);
3562306a36Sopenharmony_ciint mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
3662306a36Sopenharmony_ci			    u8 page, int reg, u16 *val);
3762306a36Sopenharmony_ciint mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
3862306a36Sopenharmony_ci			     u8 page, int reg, u16 val);
3962306a36Sopenharmony_civoid mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip);
4062306a36Sopenharmony_civoid mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip);
4162306a36Sopenharmony_ciint mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip);
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci#endif /*_MV88E6XXX_PHY_H */
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