1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13#include <linux/bitfield.h> 14#include <linux/delay.h> 15#include <linux/dsa/mv88e6xxx.h> 16#include <linux/etherdevice.h> 17#include <linux/ethtool.h> 18#include <linux/if_bridge.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <linux/irqdomain.h> 22#include <linux/jiffies.h> 23#include <linux/list.h> 24#include <linux/mdio.h> 25#include <linux/module.h> 26#include <linux/of.h> 27#include <linux/of_irq.h> 28#include <linux/of_mdio.h> 29#include <linux/platform_data/mv88e6xxx.h> 30#include <linux/netdevice.h> 31#include <linux/gpio/consumer.h> 32#include <linux/phylink.h> 33#include <net/dsa.h> 34 35#include "chip.h" 36#include "devlink.h" 37#include "global1.h" 38#include "global2.h" 39#include "hwtstamp.h" 40#include "phy.h" 41#include "port.h" 42#include "ptp.h" 43#include "serdes.h" 44#include "smi.h" 45 46static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47{ 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52} 53 54int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55{ 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68} 69 70int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71{ 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84} 85 86int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88{ 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121} 122 123int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125{ 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128} 129 130struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131{ 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140} 141 142static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143{ 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148} 149 150static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151{ 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156} 157 158static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159{ 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198} 199 200static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201{ 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205} 206 207static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208{ 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212} 213 214static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215{ 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232out: 233 mv88e6xxx_reg_unlock(chip); 234} 235 236static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242}; 243 244static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247{ 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255} 256 257static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260}; 261 262/* To be called with reg_lock held */ 263static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264{ 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278} 279 280static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281{ 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291} 292 293static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294{ 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341} 342 343static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344{ 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372} 373 374static void mv88e6xxx_irq_poll(struct kthread_work *work) 375{ 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383} 384 385static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386{ 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404} 405 406static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407{ 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414} 415 416static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418{ 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436} 437 438static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441{ 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471} 472 473static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474{ 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478} 479 480static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481{ 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500} 501 502static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510}; 511 512static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514{ 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529} 530 531static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533{ 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543} 544 545static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558}; 559 560static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561{ 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567} 568 569static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 570 struct phylink_config *config) 571{ 572 unsigned long *supported = config->supported_interfaces; 573 574 /* Translate the default cmode */ 575 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 576 577 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 578} 579 580static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582{ 583 unsigned long *supported = config->supported_interfaces; 584 585 /* Translate the default cmode */ 586 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 587 588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 589 MAC_1000FD; 590} 591 592static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 593{ 594 u16 reg, val; 595 int err; 596 597 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 598 if (err) 599 return err; 600 601 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 602 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 603 return 0xf; 604 605 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 606 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 607 if (err) 608 return err; 609 610 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 611 if (err) 612 return err; 613 614 /* Restore PHY_DETECT value */ 615 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 616 if (err) 617 return err; 618 619 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 620} 621 622static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 623 struct phylink_config *config) 624{ 625 unsigned long *supported = config->supported_interfaces; 626 int err, cmode; 627 628 /* Translate the default cmode */ 629 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 630 631 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 632 MAC_1000FD; 633 634 /* Port 4 supports automedia if the serdes is associated with it. */ 635 if (port == 4) { 636 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 637 if (err < 0) 638 dev_err(chip->dev, "p%d: failed to read scratch\n", 639 port); 640 if (err <= 0) 641 return; 642 643 cmode = mv88e6352_get_port4_serdes_cmode(chip); 644 if (cmode < 0) 645 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 646 port); 647 else 648 mv88e6xxx_translate_cmode(cmode, supported); 649 } 650} 651 652static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 653 struct phylink_config *config) 654{ 655 unsigned long *supported = config->supported_interfaces; 656 657 /* Translate the default cmode */ 658 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 659 660 /* No ethtool bits for 200Mbps */ 661 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 662 MAC_1000FD; 663 664 /* The C_Mode field is programmable on port 5 */ 665 if (port == 5) { 666 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 667 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 668 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 669 670 config->mac_capabilities |= MAC_2500FD; 671 } 672} 673 674static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 675 struct phylink_config *config) 676{ 677 unsigned long *supported = config->supported_interfaces; 678 679 /* Translate the default cmode */ 680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 681 682 /* No ethtool bits for 200Mbps */ 683 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 684 MAC_1000FD; 685 686 /* The C_Mode field is programmable on ports 9 and 10 */ 687 if (port == 9 || port == 10) { 688 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 689 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 690 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 691 692 config->mac_capabilities |= MAC_2500FD; 693 } 694} 695 696static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 697 struct phylink_config *config) 698{ 699 unsigned long *supported = config->supported_interfaces; 700 701 mv88e6390_phylink_get_caps(chip, port, config); 702 703 /* For the 6x90X, ports 2-7 can be in automedia mode. 704 * (Note that 6x90 doesn't support RXAUI nor XAUI). 705 * 706 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 707 * configured for 1000BASE-X, SGMII or 2500BASE-X. 708 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 709 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 710 * 711 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 712 * configured for 1000BASE-X, SGMII or 2500BASE-X. 713 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 714 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 715 * 716 * For now, be permissive (as the old code was) and allow 1000BASE-X 717 * on ports 2..7. 718 */ 719 if (port >= 2 && port <= 7) 720 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 721 722 /* The C_Mode field can also be programmed for 10G speeds */ 723 if (port == 9 || port == 10) { 724 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 725 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 726 727 config->mac_capabilities |= MAC_10000FD; 728 } 729} 730 731static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 732 struct phylink_config *config) 733{ 734 unsigned long *supported = config->supported_interfaces; 735 bool is_6191x = 736 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 737 bool is_6361 = 738 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 739 740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 741 742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 743 MAC_1000FD; 744 745 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 746 if (port == 0 || port == 9 || port == 10) { 747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 749 750 /* 6191X supports >1G modes only on port 10 */ 751 if (!is_6191x || port == 10) { 752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 753 config->mac_capabilities |= MAC_2500FD; 754 755 /* 6361 only supports up to 2500BaseX */ 756 if (!is_6361) { 757 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 758 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 759 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 760 config->mac_capabilities |= MAC_5000FD | 761 MAC_10000FD; 762 } 763 } 764 } 765 766 if (port == 0) { 767 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 768 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 769 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 770 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 771 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 772 } 773} 774 775static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 776 struct phylink_config *config) 777{ 778 struct mv88e6xxx_chip *chip = ds->priv; 779 780 mv88e6xxx_reg_lock(chip); 781 chip->info->ops->phylink_get_caps(chip, port, config); 782 mv88e6xxx_reg_unlock(chip); 783 784 if (mv88e6xxx_phy_is_internal(chip, port)) { 785 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 786 config->supported_interfaces); 787 /* Internal ports with no phy-mode need GMII for PHYLIB */ 788 __set_bit(PHY_INTERFACE_MODE_GMII, 789 config->supported_interfaces); 790 } 791} 792 793static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, 794 int port, 795 phy_interface_t interface) 796{ 797 struct mv88e6xxx_chip *chip = ds->priv; 798 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 799 800 if (chip->info->ops->pcs_ops) 801 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, 802 interface); 803 804 return pcs; 805} 806 807static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 808 unsigned int mode, phy_interface_t interface) 809{ 810 struct mv88e6xxx_chip *chip = ds->priv; 811 int err = 0; 812 813 /* In inband mode, the link may come up at any time while the link 814 * is not forced down. Force the link down while we reconfigure the 815 * interface mode. 816 */ 817 if (mode == MLO_AN_INBAND && 818 chip->ports[port].interface != interface && 819 chip->info->ops->port_set_link) { 820 mv88e6xxx_reg_lock(chip); 821 err = chip->info->ops->port_set_link(chip, port, 822 LINK_FORCED_DOWN); 823 mv88e6xxx_reg_unlock(chip); 824 } 825 826 return err; 827} 828 829static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 830 unsigned int mode, 831 const struct phylink_link_state *state) 832{ 833 struct mv88e6xxx_chip *chip = ds->priv; 834 int err = 0; 835 836 mv88e6xxx_reg_lock(chip); 837 838 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 839 err = mv88e6xxx_port_config_interface(chip, port, 840 state->interface); 841 if (err && err != -EOPNOTSUPP) 842 goto err_unlock; 843 } 844 845err_unlock: 846 mv88e6xxx_reg_unlock(chip); 847 848 if (err && err != -EOPNOTSUPP) 849 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 850} 851 852static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 853 unsigned int mode, phy_interface_t interface) 854{ 855 struct mv88e6xxx_chip *chip = ds->priv; 856 int err = 0; 857 858 /* Undo the forced down state above after completing configuration 859 * irrespective of its state on entry, which allows the link to come 860 * up in the in-band case where there is no separate SERDES. Also 861 * ensure that the link can come up if the PPU is in use and we are 862 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 863 */ 864 mv88e6xxx_reg_lock(chip); 865 866 if (chip->info->ops->port_set_link && 867 ((mode == MLO_AN_INBAND && 868 chip->ports[port].interface != interface) || 869 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 870 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 871 872 mv88e6xxx_reg_unlock(chip); 873 874 chip->ports[port].interface = interface; 875 876 return err; 877} 878 879static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 880 unsigned int mode, 881 phy_interface_t interface) 882{ 883 struct mv88e6xxx_chip *chip = ds->priv; 884 const struct mv88e6xxx_ops *ops; 885 int err = 0; 886 887 ops = chip->info->ops; 888 889 mv88e6xxx_reg_lock(chip); 890 /* Force the link down if we know the port may not be automatically 891 * updated by the switch or if we are using fixed-link mode. 892 */ 893 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 894 mode == MLO_AN_FIXED) && ops->port_sync_link) 895 err = ops->port_sync_link(chip, port, mode, false); 896 897 if (!err && ops->port_set_speed_duplex) 898 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 899 DUPLEX_UNFORCED); 900 mv88e6xxx_reg_unlock(chip); 901 902 if (err) 903 dev_err(chip->dev, 904 "p%d: failed to force MAC link down\n", port); 905} 906 907static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 908 unsigned int mode, phy_interface_t interface, 909 struct phy_device *phydev, 910 int speed, int duplex, 911 bool tx_pause, bool rx_pause) 912{ 913 struct mv88e6xxx_chip *chip = ds->priv; 914 const struct mv88e6xxx_ops *ops; 915 int err = 0; 916 917 ops = chip->info->ops; 918 919 mv88e6xxx_reg_lock(chip); 920 /* Configure and force the link up if we know that the port may not 921 * automatically updated by the switch or if we are using fixed-link 922 * mode. 923 */ 924 if (!mv88e6xxx_port_ppu_updates(chip, port) || 925 mode == MLO_AN_FIXED) { 926 if (ops->port_set_speed_duplex) { 927 err = ops->port_set_speed_duplex(chip, port, 928 speed, duplex); 929 if (err && err != -EOPNOTSUPP) 930 goto error; 931 } 932 933 if (ops->port_sync_link) 934 err = ops->port_sync_link(chip, port, mode, true); 935 } 936error: 937 mv88e6xxx_reg_unlock(chip); 938 939 if (err && err != -EOPNOTSUPP) 940 dev_err(ds->dev, 941 "p%d: failed to configure MAC link up\n", port); 942} 943 944static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 945{ 946 if (!chip->info->ops->stats_snapshot) 947 return -EOPNOTSUPP; 948 949 return chip->info->ops->stats_snapshot(chip, port); 950} 951 952static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 953 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 954 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 955 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 956 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 957 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 958 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 959 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 960 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 961 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 962 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 963 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 964 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 965 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 966 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 967 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 968 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 969 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 970 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 971 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 972 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 973 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 974 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 975 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 976 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 977 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 978 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 979 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 980 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 981 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 982 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 983 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 984 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 985 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 986 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 987 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 988 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 989 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 990 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 991 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 992 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 993 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 994 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 995 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 996 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 997 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 998 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 999 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1000 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1001 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1002 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1003 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1004 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1005 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1006 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1007 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1008 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1009 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1010 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1011 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1012}; 1013 1014static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1015 struct mv88e6xxx_hw_stat *s, 1016 int port, u16 bank1_select, 1017 u16 histogram) 1018{ 1019 u32 low; 1020 u32 high = 0; 1021 u16 reg = 0; 1022 int err; 1023 u64 value; 1024 1025 switch (s->type) { 1026 case STATS_TYPE_PORT: 1027 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1028 if (err) 1029 return U64_MAX; 1030 1031 low = reg; 1032 if (s->size == 4) { 1033 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1034 if (err) 1035 return U64_MAX; 1036 low |= ((u32)reg) << 16; 1037 } 1038 break; 1039 case STATS_TYPE_BANK1: 1040 reg = bank1_select; 1041 fallthrough; 1042 case STATS_TYPE_BANK0: 1043 reg |= s->reg | histogram; 1044 mv88e6xxx_g1_stats_read(chip, reg, &low); 1045 if (s->size == 8) 1046 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1047 break; 1048 default: 1049 return U64_MAX; 1050 } 1051 value = (((u64)high) << 32) | low; 1052 return value; 1053} 1054 1055static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1056 uint8_t *data, int types) 1057{ 1058 struct mv88e6xxx_hw_stat *stat; 1059 int i, j; 1060 1061 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1062 stat = &mv88e6xxx_hw_stats[i]; 1063 if (stat->type & types) { 1064 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1065 ETH_GSTRING_LEN); 1066 j++; 1067 } 1068 } 1069 1070 return j; 1071} 1072 1073static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1074 uint8_t *data) 1075{ 1076 return mv88e6xxx_stats_get_strings(chip, data, 1077 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1078} 1079 1080static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1081 uint8_t *data) 1082{ 1083 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1084} 1085 1086static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1087 uint8_t *data) 1088{ 1089 return mv88e6xxx_stats_get_strings(chip, data, 1090 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1091} 1092 1093static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1094 "atu_member_violation", 1095 "atu_miss_violation", 1096 "atu_full_violation", 1097 "vtu_member_violation", 1098 "vtu_miss_violation", 1099}; 1100 1101static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1102{ 1103 unsigned int i; 1104 1105 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1106 strscpy(data + i * ETH_GSTRING_LEN, 1107 mv88e6xxx_atu_vtu_stats_strings[i], 1108 ETH_GSTRING_LEN); 1109} 1110 1111static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1112 u32 stringset, uint8_t *data) 1113{ 1114 struct mv88e6xxx_chip *chip = ds->priv; 1115 int count = 0; 1116 1117 if (stringset != ETH_SS_STATS) 1118 return; 1119 1120 mv88e6xxx_reg_lock(chip); 1121 1122 if (chip->info->ops->stats_get_strings) 1123 count = chip->info->ops->stats_get_strings(chip, data); 1124 1125 if (chip->info->ops->serdes_get_strings) { 1126 data += count * ETH_GSTRING_LEN; 1127 count = chip->info->ops->serdes_get_strings(chip, port, data); 1128 } 1129 1130 data += count * ETH_GSTRING_LEN; 1131 mv88e6xxx_atu_vtu_get_strings(data); 1132 1133 mv88e6xxx_reg_unlock(chip); 1134} 1135 1136static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1137 int types) 1138{ 1139 struct mv88e6xxx_hw_stat *stat; 1140 int i, j; 1141 1142 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1143 stat = &mv88e6xxx_hw_stats[i]; 1144 if (stat->type & types) 1145 j++; 1146 } 1147 return j; 1148} 1149 1150static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1151{ 1152 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1153 STATS_TYPE_PORT); 1154} 1155 1156static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1157{ 1158 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1159} 1160 1161static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1162{ 1163 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1164 STATS_TYPE_BANK1); 1165} 1166 1167static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1168{ 1169 struct mv88e6xxx_chip *chip = ds->priv; 1170 int serdes_count = 0; 1171 int count = 0; 1172 1173 if (sset != ETH_SS_STATS) 1174 return 0; 1175 1176 mv88e6xxx_reg_lock(chip); 1177 if (chip->info->ops->stats_get_sset_count) 1178 count = chip->info->ops->stats_get_sset_count(chip); 1179 if (count < 0) 1180 goto out; 1181 1182 if (chip->info->ops->serdes_get_sset_count) 1183 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1184 port); 1185 if (serdes_count < 0) { 1186 count = serdes_count; 1187 goto out; 1188 } 1189 count += serdes_count; 1190 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1191 1192out: 1193 mv88e6xxx_reg_unlock(chip); 1194 1195 return count; 1196} 1197 1198static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1199 uint64_t *data, int types, 1200 u16 bank1_select, u16 histogram) 1201{ 1202 struct mv88e6xxx_hw_stat *stat; 1203 int i, j; 1204 1205 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1206 stat = &mv88e6xxx_hw_stats[i]; 1207 if (stat->type & types) { 1208 mv88e6xxx_reg_lock(chip); 1209 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1210 bank1_select, 1211 histogram); 1212 mv88e6xxx_reg_unlock(chip); 1213 1214 j++; 1215 } 1216 } 1217 return j; 1218} 1219 1220static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1221 uint64_t *data) 1222{ 1223 return mv88e6xxx_stats_get_stats(chip, port, data, 1224 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1225 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1226} 1227 1228static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1229 uint64_t *data) 1230{ 1231 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1232 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1233} 1234 1235static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1236 uint64_t *data) 1237{ 1238 return mv88e6xxx_stats_get_stats(chip, port, data, 1239 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1240 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1241 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1242} 1243 1244static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1245 uint64_t *data) 1246{ 1247 return mv88e6xxx_stats_get_stats(chip, port, data, 1248 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1249 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1250 0); 1251} 1252 1253static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1254 uint64_t *data) 1255{ 1256 *data++ = chip->ports[port].atu_member_violation; 1257 *data++ = chip->ports[port].atu_miss_violation; 1258 *data++ = chip->ports[port].atu_full_violation; 1259 *data++ = chip->ports[port].vtu_member_violation; 1260 *data++ = chip->ports[port].vtu_miss_violation; 1261} 1262 1263static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1264 uint64_t *data) 1265{ 1266 int count = 0; 1267 1268 if (chip->info->ops->stats_get_stats) 1269 count = chip->info->ops->stats_get_stats(chip, port, data); 1270 1271 mv88e6xxx_reg_lock(chip); 1272 if (chip->info->ops->serdes_get_stats) { 1273 data += count; 1274 count = chip->info->ops->serdes_get_stats(chip, port, data); 1275 } 1276 data += count; 1277 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1278 mv88e6xxx_reg_unlock(chip); 1279} 1280 1281static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1282 uint64_t *data) 1283{ 1284 struct mv88e6xxx_chip *chip = ds->priv; 1285 int ret; 1286 1287 mv88e6xxx_reg_lock(chip); 1288 1289 ret = mv88e6xxx_stats_snapshot(chip, port); 1290 mv88e6xxx_reg_unlock(chip); 1291 1292 if (ret < 0) 1293 return; 1294 1295 mv88e6xxx_get_stats(chip, port, data); 1296 1297} 1298 1299static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1300{ 1301 struct mv88e6xxx_chip *chip = ds->priv; 1302 int len; 1303 1304 len = 32 * sizeof(u16); 1305 if (chip->info->ops->serdes_get_regs_len) 1306 len += chip->info->ops->serdes_get_regs_len(chip, port); 1307 1308 return len; 1309} 1310 1311static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1312 struct ethtool_regs *regs, void *_p) 1313{ 1314 struct mv88e6xxx_chip *chip = ds->priv; 1315 int err; 1316 u16 reg; 1317 u16 *p = _p; 1318 int i; 1319 1320 regs->version = chip->info->prod_num; 1321 1322 memset(p, 0xff, 32 * sizeof(u16)); 1323 1324 mv88e6xxx_reg_lock(chip); 1325 1326 for (i = 0; i < 32; i++) { 1327 1328 err = mv88e6xxx_port_read(chip, port, i, ®); 1329 if (!err) 1330 p[i] = reg; 1331 } 1332 1333 if (chip->info->ops->serdes_get_regs) 1334 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1335 1336 mv88e6xxx_reg_unlock(chip); 1337} 1338 1339static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1340 struct ethtool_eee *e) 1341{ 1342 /* Nothing to do on the port's MAC */ 1343 return 0; 1344} 1345 1346static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1347 struct ethtool_eee *e) 1348{ 1349 /* Nothing to do on the port's MAC */ 1350 return 0; 1351} 1352 1353/* Mask of the local ports allowed to receive frames from a given fabric port */ 1354static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1355{ 1356 struct dsa_switch *ds = chip->ds; 1357 struct dsa_switch_tree *dst = ds->dst; 1358 struct dsa_port *dp, *other_dp; 1359 bool found = false; 1360 u16 pvlan; 1361 1362 /* dev is a physical switch */ 1363 if (dev <= dst->last_switch) { 1364 list_for_each_entry(dp, &dst->ports, list) { 1365 if (dp->ds->index == dev && dp->index == port) { 1366 /* dp might be a DSA link or a user port, so it 1367 * might or might not have a bridge. 1368 * Use the "found" variable for both cases. 1369 */ 1370 found = true; 1371 break; 1372 } 1373 } 1374 /* dev is a virtual bridge */ 1375 } else { 1376 list_for_each_entry(dp, &dst->ports, list) { 1377 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1378 1379 if (!bridge_num) 1380 continue; 1381 1382 if (bridge_num + dst->last_switch != dev) 1383 continue; 1384 1385 found = true; 1386 break; 1387 } 1388 } 1389 1390 /* Prevent frames from unknown switch or virtual bridge */ 1391 if (!found) 1392 return 0; 1393 1394 /* Frames from DSA links and CPU ports can egress any local port */ 1395 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1396 return mv88e6xxx_port_mask(chip); 1397 1398 pvlan = 0; 1399 1400 /* Frames from standalone user ports can only egress on the 1401 * upstream port. 1402 */ 1403 if (!dsa_port_bridge_dev_get(dp)) 1404 return BIT(dsa_switch_upstream_port(ds)); 1405 1406 /* Frames from bridged user ports can egress any local DSA 1407 * links and CPU ports, as well as any local member of their 1408 * bridge group. 1409 */ 1410 dsa_switch_for_each_port(other_dp, ds) 1411 if (other_dp->type == DSA_PORT_TYPE_CPU || 1412 other_dp->type == DSA_PORT_TYPE_DSA || 1413 dsa_port_bridge_same(dp, other_dp)) 1414 pvlan |= BIT(other_dp->index); 1415 1416 return pvlan; 1417} 1418 1419static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1420{ 1421 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1422 1423 /* prevent frames from going back out of the port they came in on */ 1424 output_ports &= ~BIT(port); 1425 1426 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1427} 1428 1429static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1430 u8 state) 1431{ 1432 struct mv88e6xxx_chip *chip = ds->priv; 1433 int err; 1434 1435 mv88e6xxx_reg_lock(chip); 1436 err = mv88e6xxx_port_set_state(chip, port, state); 1437 mv88e6xxx_reg_unlock(chip); 1438 1439 if (err) 1440 dev_err(ds->dev, "p%d: failed to update state\n", port); 1441} 1442 1443static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1444{ 1445 int err; 1446 1447 if (chip->info->ops->ieee_pri_map) { 1448 err = chip->info->ops->ieee_pri_map(chip); 1449 if (err) 1450 return err; 1451 } 1452 1453 if (chip->info->ops->ip_pri_map) { 1454 err = chip->info->ops->ip_pri_map(chip); 1455 if (err) 1456 return err; 1457 } 1458 1459 return 0; 1460} 1461 1462static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1463{ 1464 struct dsa_switch *ds = chip->ds; 1465 int target, port; 1466 int err; 1467 1468 if (!chip->info->global2_addr) 1469 return 0; 1470 1471 /* Initialize the routing port to the 32 possible target devices */ 1472 for (target = 0; target < 32; target++) { 1473 port = dsa_routing_port(ds, target); 1474 if (port == ds->num_ports) 1475 port = 0x1f; 1476 1477 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1478 if (err) 1479 return err; 1480 } 1481 1482 if (chip->info->ops->set_cascade_port) { 1483 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1484 err = chip->info->ops->set_cascade_port(chip, port); 1485 if (err) 1486 return err; 1487 } 1488 1489 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1490 if (err) 1491 return err; 1492 1493 return 0; 1494} 1495 1496static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1497{ 1498 /* Clear all trunk masks and mapping */ 1499 if (chip->info->global2_addr) 1500 return mv88e6xxx_g2_trunk_clear(chip); 1501 1502 return 0; 1503} 1504 1505static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1506{ 1507 if (chip->info->ops->rmu_disable) 1508 return chip->info->ops->rmu_disable(chip); 1509 1510 return 0; 1511} 1512 1513static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1514{ 1515 if (chip->info->ops->pot_clear) 1516 return chip->info->ops->pot_clear(chip); 1517 1518 return 0; 1519} 1520 1521static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1522{ 1523 if (chip->info->ops->mgmt_rsvd2cpu) 1524 return chip->info->ops->mgmt_rsvd2cpu(chip); 1525 1526 return 0; 1527} 1528 1529static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1530{ 1531 int err; 1532 1533 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1534 if (err) 1535 return err; 1536 1537 /* The chips that have a "learn2all" bit in Global1, ATU 1538 * Control are precisely those whose port registers have a 1539 * Message Port bit in Port Control 1 and hence implement 1540 * ->port_setup_message_port. 1541 */ 1542 if (chip->info->ops->port_setup_message_port) { 1543 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1544 if (err) 1545 return err; 1546 } 1547 1548 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1549} 1550 1551static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1552{ 1553 int port; 1554 int err; 1555 1556 if (!chip->info->ops->irl_init_all) 1557 return 0; 1558 1559 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1560 /* Disable ingress rate limiting by resetting all per port 1561 * ingress rate limit resources to their initial state. 1562 */ 1563 err = chip->info->ops->irl_init_all(chip, port); 1564 if (err) 1565 return err; 1566 } 1567 1568 return 0; 1569} 1570 1571static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1572{ 1573 if (chip->info->ops->set_switch_mac) { 1574 u8 addr[ETH_ALEN]; 1575 1576 eth_random_addr(addr); 1577 1578 return chip->info->ops->set_switch_mac(chip, addr); 1579 } 1580 1581 return 0; 1582} 1583 1584static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1585{ 1586 struct dsa_switch_tree *dst = chip->ds->dst; 1587 struct dsa_switch *ds; 1588 struct dsa_port *dp; 1589 u16 pvlan = 0; 1590 1591 if (!mv88e6xxx_has_pvt(chip)) 1592 return 0; 1593 1594 /* Skip the local source device, which uses in-chip port VLAN */ 1595 if (dev != chip->ds->index) { 1596 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1597 1598 ds = dsa_switch_find(dst->index, dev); 1599 dp = ds ? dsa_to_port(ds, port) : NULL; 1600 if (dp && dp->lag) { 1601 /* As the PVT is used to limit flooding of 1602 * FORWARD frames, which use the LAG ID as the 1603 * source port, we must translate dev/port to 1604 * the special "LAG device" in the PVT, using 1605 * the LAG ID (one-based) as the port number 1606 * (zero-based). 1607 */ 1608 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1609 port = dsa_port_lag_id_get(dp) - 1; 1610 } 1611 } 1612 1613 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1614} 1615 1616static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1617{ 1618 int dev, port; 1619 int err; 1620 1621 if (!mv88e6xxx_has_pvt(chip)) 1622 return 0; 1623 1624 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1625 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1626 */ 1627 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1628 if (err) 1629 return err; 1630 1631 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1632 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1633 err = mv88e6xxx_pvt_map(chip, dev, port); 1634 if (err) 1635 return err; 1636 } 1637 } 1638 1639 return 0; 1640} 1641 1642static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1643 u16 fid) 1644{ 1645 if (dsa_to_port(chip->ds, port)->lag) 1646 /* Hardware is incapable of fast-aging a LAG through a 1647 * regular ATU move operation. Until we have something 1648 * more fancy in place this is a no-op. 1649 */ 1650 return -EOPNOTSUPP; 1651 1652 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1653} 1654 1655static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1656{ 1657 struct mv88e6xxx_chip *chip = ds->priv; 1658 int err; 1659 1660 mv88e6xxx_reg_lock(chip); 1661 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1662 mv88e6xxx_reg_unlock(chip); 1663 1664 if (err) 1665 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1666 port, err); 1667} 1668 1669static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1670{ 1671 if (!mv88e6xxx_max_vid(chip)) 1672 return 0; 1673 1674 return mv88e6xxx_g1_vtu_flush(chip); 1675} 1676 1677static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1678 struct mv88e6xxx_vtu_entry *entry) 1679{ 1680 int err; 1681 1682 if (!chip->info->ops->vtu_getnext) 1683 return -EOPNOTSUPP; 1684 1685 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1686 entry->valid = false; 1687 1688 err = chip->info->ops->vtu_getnext(chip, entry); 1689 1690 if (entry->vid != vid) 1691 entry->valid = false; 1692 1693 return err; 1694} 1695 1696int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1697 int (*cb)(struct mv88e6xxx_chip *chip, 1698 const struct mv88e6xxx_vtu_entry *entry, 1699 void *priv), 1700 void *priv) 1701{ 1702 struct mv88e6xxx_vtu_entry entry = { 1703 .vid = mv88e6xxx_max_vid(chip), 1704 .valid = false, 1705 }; 1706 int err; 1707 1708 if (!chip->info->ops->vtu_getnext) 1709 return -EOPNOTSUPP; 1710 1711 do { 1712 err = chip->info->ops->vtu_getnext(chip, &entry); 1713 if (err) 1714 return err; 1715 1716 if (!entry.valid) 1717 break; 1718 1719 err = cb(chip, &entry, priv); 1720 if (err) 1721 return err; 1722 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1723 1724 return 0; 1725} 1726 1727static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1728 struct mv88e6xxx_vtu_entry *entry) 1729{ 1730 if (!chip->info->ops->vtu_loadpurge) 1731 return -EOPNOTSUPP; 1732 1733 return chip->info->ops->vtu_loadpurge(chip, entry); 1734} 1735 1736static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1737 const struct mv88e6xxx_vtu_entry *entry, 1738 void *_fid_bitmap) 1739{ 1740 unsigned long *fid_bitmap = _fid_bitmap; 1741 1742 set_bit(entry->fid, fid_bitmap); 1743 return 0; 1744} 1745 1746int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1747{ 1748 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1749 1750 /* Every FID has an associated VID, so walking the VTU 1751 * will discover the full set of FIDs in use. 1752 */ 1753 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1754} 1755 1756static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1757{ 1758 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1759 int err; 1760 1761 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1762 if (err) 1763 return err; 1764 1765 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1766 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1767 return -ENOSPC; 1768 1769 /* Clear the database */ 1770 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1771} 1772 1773static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1774 struct mv88e6xxx_stu_entry *entry) 1775{ 1776 if (!chip->info->ops->stu_loadpurge) 1777 return -EOPNOTSUPP; 1778 1779 return chip->info->ops->stu_loadpurge(chip, entry); 1780} 1781 1782static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1783{ 1784 struct mv88e6xxx_stu_entry stu = { 1785 .valid = true, 1786 .sid = 0 1787 }; 1788 1789 if (!mv88e6xxx_has_stu(chip)) 1790 return 0; 1791 1792 /* Make sure that SID 0 is always valid. This is used by VTU 1793 * entries that do not make use of the STU, e.g. when creating 1794 * a VLAN upper on a port that is also part of a VLAN 1795 * filtering bridge. 1796 */ 1797 return mv88e6xxx_stu_loadpurge(chip, &stu); 1798} 1799 1800static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1801{ 1802 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1803 struct mv88e6xxx_mst *mst; 1804 1805 __set_bit(0, busy); 1806 1807 list_for_each_entry(mst, &chip->msts, node) 1808 __set_bit(mst->stu.sid, busy); 1809 1810 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1811 1812 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1813} 1814 1815static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1816{ 1817 struct mv88e6xxx_mst *mst, *tmp; 1818 int err; 1819 1820 if (!sid) 1821 return 0; 1822 1823 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1824 if (mst->stu.sid != sid) 1825 continue; 1826 1827 if (!refcount_dec_and_test(&mst->refcnt)) 1828 return 0; 1829 1830 mst->stu.valid = false; 1831 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1832 if (err) { 1833 refcount_set(&mst->refcnt, 1); 1834 return err; 1835 } 1836 1837 list_del(&mst->node); 1838 kfree(mst); 1839 return 0; 1840 } 1841 1842 return -ENOENT; 1843} 1844 1845static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1846 u16 msti, u8 *sid) 1847{ 1848 struct mv88e6xxx_mst *mst; 1849 int err, i; 1850 1851 if (!mv88e6xxx_has_stu(chip)) { 1852 err = -EOPNOTSUPP; 1853 goto err; 1854 } 1855 1856 if (!msti) { 1857 *sid = 0; 1858 return 0; 1859 } 1860 1861 list_for_each_entry(mst, &chip->msts, node) { 1862 if (mst->br == br && mst->msti == msti) { 1863 refcount_inc(&mst->refcnt); 1864 *sid = mst->stu.sid; 1865 return 0; 1866 } 1867 } 1868 1869 err = mv88e6xxx_sid_get(chip, sid); 1870 if (err) 1871 goto err; 1872 1873 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1874 if (!mst) { 1875 err = -ENOMEM; 1876 goto err; 1877 } 1878 1879 INIT_LIST_HEAD(&mst->node); 1880 refcount_set(&mst->refcnt, 1); 1881 mst->br = br; 1882 mst->msti = msti; 1883 mst->stu.valid = true; 1884 mst->stu.sid = *sid; 1885 1886 /* The bridge starts out all ports in the disabled state. But 1887 * a STU state of disabled means to go by the port-global 1888 * state. So we set all user port's initial state to blocking, 1889 * to match the bridge's behavior. 1890 */ 1891 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1892 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1893 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1894 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1895 1896 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1897 if (err) 1898 goto err_free; 1899 1900 list_add_tail(&mst->node, &chip->msts); 1901 return 0; 1902 1903err_free: 1904 kfree(mst); 1905err: 1906 return err; 1907} 1908 1909static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1910 const struct switchdev_mst_state *st) 1911{ 1912 struct dsa_port *dp = dsa_to_port(ds, port); 1913 struct mv88e6xxx_chip *chip = ds->priv; 1914 struct mv88e6xxx_mst *mst; 1915 u8 state; 1916 int err; 1917 1918 if (!mv88e6xxx_has_stu(chip)) 1919 return -EOPNOTSUPP; 1920 1921 switch (st->state) { 1922 case BR_STATE_DISABLED: 1923 case BR_STATE_BLOCKING: 1924 case BR_STATE_LISTENING: 1925 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1926 break; 1927 case BR_STATE_LEARNING: 1928 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1929 break; 1930 case BR_STATE_FORWARDING: 1931 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1932 break; 1933 default: 1934 return -EINVAL; 1935 } 1936 1937 list_for_each_entry(mst, &chip->msts, node) { 1938 if (mst->br == dsa_port_bridge_dev_get(dp) && 1939 mst->msti == st->msti) { 1940 if (mst->stu.state[port] == state) 1941 return 0; 1942 1943 mst->stu.state[port] = state; 1944 mv88e6xxx_reg_lock(chip); 1945 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1946 mv88e6xxx_reg_unlock(chip); 1947 return err; 1948 } 1949 } 1950 1951 return -ENOENT; 1952} 1953 1954static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1955 u16 vid) 1956{ 1957 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1958 struct mv88e6xxx_chip *chip = ds->priv; 1959 struct mv88e6xxx_vtu_entry vlan; 1960 int err; 1961 1962 /* DSA and CPU ports have to be members of multiple vlans */ 1963 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1964 return 0; 1965 1966 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1967 if (err) 1968 return err; 1969 1970 if (!vlan.valid) 1971 return 0; 1972 1973 dsa_switch_for_each_user_port(other_dp, ds) { 1974 struct net_device *other_br; 1975 1976 if (vlan.member[other_dp->index] == 1977 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1978 continue; 1979 1980 if (dsa_port_bridge_same(dp, other_dp)) 1981 break; /* same bridge, check next VLAN */ 1982 1983 other_br = dsa_port_bridge_dev_get(other_dp); 1984 if (!other_br) 1985 continue; 1986 1987 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1988 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1989 return -EOPNOTSUPP; 1990 } 1991 1992 return 0; 1993} 1994 1995static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1996{ 1997 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1998 struct net_device *br = dsa_port_bridge_dev_get(dp); 1999 struct mv88e6xxx_port *p = &chip->ports[port]; 2000 u16 pvid = MV88E6XXX_VID_STANDALONE; 2001 bool drop_untagged = false; 2002 int err; 2003 2004 if (br) { 2005 if (br_vlan_enabled(br)) { 2006 pvid = p->bridge_pvid.vid; 2007 drop_untagged = !p->bridge_pvid.valid; 2008 } else { 2009 pvid = MV88E6XXX_VID_BRIDGED; 2010 } 2011 } 2012 2013 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2014 if (err) 2015 return err; 2016 2017 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2018} 2019 2020static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2021 bool vlan_filtering, 2022 struct netlink_ext_ack *extack) 2023{ 2024 struct mv88e6xxx_chip *chip = ds->priv; 2025 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2026 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2027 int err; 2028 2029 if (!mv88e6xxx_max_vid(chip)) 2030 return -EOPNOTSUPP; 2031 2032 mv88e6xxx_reg_lock(chip); 2033 2034 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2035 if (err) 2036 goto unlock; 2037 2038 err = mv88e6xxx_port_commit_pvid(chip, port); 2039 if (err) 2040 goto unlock; 2041 2042unlock: 2043 mv88e6xxx_reg_unlock(chip); 2044 2045 return err; 2046} 2047 2048static int 2049mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2050 const struct switchdev_obj_port_vlan *vlan) 2051{ 2052 struct mv88e6xxx_chip *chip = ds->priv; 2053 int err; 2054 2055 if (!mv88e6xxx_max_vid(chip)) 2056 return -EOPNOTSUPP; 2057 2058 /* If the requested port doesn't belong to the same bridge as the VLAN 2059 * members, do not support it (yet) and fallback to software VLAN. 2060 */ 2061 mv88e6xxx_reg_lock(chip); 2062 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2063 mv88e6xxx_reg_unlock(chip); 2064 2065 return err; 2066} 2067 2068static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2069 const unsigned char *addr, u16 vid, 2070 u8 state) 2071{ 2072 struct mv88e6xxx_atu_entry entry; 2073 struct mv88e6xxx_vtu_entry vlan; 2074 u16 fid; 2075 int err; 2076 2077 /* Ports have two private address databases: one for when the port is 2078 * standalone and one for when the port is under a bridge and the 2079 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2080 * address database to remain 100% empty, so we never load an ATU entry 2081 * into a standalone port's database. Therefore, translate the null 2082 * VLAN ID into the port's database used for VLAN-unaware bridging. 2083 */ 2084 if (vid == 0) { 2085 fid = MV88E6XXX_FID_BRIDGED; 2086 } else { 2087 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2088 if (err) 2089 return err; 2090 2091 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2092 if (!vlan.valid) 2093 return -EOPNOTSUPP; 2094 2095 fid = vlan.fid; 2096 } 2097 2098 entry.state = 0; 2099 ether_addr_copy(entry.mac, addr); 2100 eth_addr_dec(entry.mac); 2101 2102 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2103 if (err) 2104 return err; 2105 2106 /* Initialize a fresh ATU entry if it isn't found */ 2107 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2108 memset(&entry, 0, sizeof(entry)); 2109 ether_addr_copy(entry.mac, addr); 2110 } 2111 2112 /* Purge the ATU entry only if no port is using it anymore */ 2113 if (!state) { 2114 entry.portvec &= ~BIT(port); 2115 if (!entry.portvec) 2116 entry.state = 0; 2117 } else { 2118 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2119 entry.portvec = BIT(port); 2120 else 2121 entry.portvec |= BIT(port); 2122 2123 entry.state = state; 2124 } 2125 2126 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2127} 2128 2129static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2130 const struct mv88e6xxx_policy *policy) 2131{ 2132 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2133 enum mv88e6xxx_policy_action action = policy->action; 2134 const u8 *addr = policy->addr; 2135 u16 vid = policy->vid; 2136 u8 state; 2137 int err; 2138 int id; 2139 2140 if (!chip->info->ops->port_set_policy) 2141 return -EOPNOTSUPP; 2142 2143 switch (mapping) { 2144 case MV88E6XXX_POLICY_MAPPING_DA: 2145 case MV88E6XXX_POLICY_MAPPING_SA: 2146 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2147 state = 0; /* Dissociate the port and address */ 2148 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2149 is_multicast_ether_addr(addr)) 2150 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2151 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2152 is_unicast_ether_addr(addr)) 2153 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2154 else 2155 return -EOPNOTSUPP; 2156 2157 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2158 state); 2159 if (err) 2160 return err; 2161 break; 2162 default: 2163 return -EOPNOTSUPP; 2164 } 2165 2166 /* Skip the port's policy clearing if the mapping is still in use */ 2167 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2168 idr_for_each_entry(&chip->policies, policy, id) 2169 if (policy->port == port && 2170 policy->mapping == mapping && 2171 policy->action != action) 2172 return 0; 2173 2174 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2175} 2176 2177static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2178 struct ethtool_rx_flow_spec *fs) 2179{ 2180 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2181 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2182 enum mv88e6xxx_policy_mapping mapping; 2183 enum mv88e6xxx_policy_action action; 2184 struct mv88e6xxx_policy *policy; 2185 u16 vid = 0; 2186 u8 *addr; 2187 int err; 2188 int id; 2189 2190 if (fs->location != RX_CLS_LOC_ANY) 2191 return -EINVAL; 2192 2193 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2194 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2195 else 2196 return -EOPNOTSUPP; 2197 2198 switch (fs->flow_type & ~FLOW_EXT) { 2199 case ETHER_FLOW: 2200 if (!is_zero_ether_addr(mac_mask->h_dest) && 2201 is_zero_ether_addr(mac_mask->h_source)) { 2202 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2203 addr = mac_entry->h_dest; 2204 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2205 !is_zero_ether_addr(mac_mask->h_source)) { 2206 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2207 addr = mac_entry->h_source; 2208 } else { 2209 /* Cannot support DA and SA mapping in the same rule */ 2210 return -EOPNOTSUPP; 2211 } 2212 break; 2213 default: 2214 return -EOPNOTSUPP; 2215 } 2216 2217 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2218 if (fs->m_ext.vlan_tci != htons(0xffff)) 2219 return -EOPNOTSUPP; 2220 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2221 } 2222 2223 idr_for_each_entry(&chip->policies, policy, id) { 2224 if (policy->port == port && policy->mapping == mapping && 2225 policy->action == action && policy->vid == vid && 2226 ether_addr_equal(policy->addr, addr)) 2227 return -EEXIST; 2228 } 2229 2230 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2231 if (!policy) 2232 return -ENOMEM; 2233 2234 fs->location = 0; 2235 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2236 GFP_KERNEL); 2237 if (err) { 2238 devm_kfree(chip->dev, policy); 2239 return err; 2240 } 2241 2242 memcpy(&policy->fs, fs, sizeof(*fs)); 2243 ether_addr_copy(policy->addr, addr); 2244 policy->mapping = mapping; 2245 policy->action = action; 2246 policy->port = port; 2247 policy->vid = vid; 2248 2249 err = mv88e6xxx_policy_apply(chip, port, policy); 2250 if (err) { 2251 idr_remove(&chip->policies, fs->location); 2252 devm_kfree(chip->dev, policy); 2253 return err; 2254 } 2255 2256 return 0; 2257} 2258 2259static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2260 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2261{ 2262 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2263 struct mv88e6xxx_chip *chip = ds->priv; 2264 struct mv88e6xxx_policy *policy; 2265 int err; 2266 int id; 2267 2268 mv88e6xxx_reg_lock(chip); 2269 2270 switch (rxnfc->cmd) { 2271 case ETHTOOL_GRXCLSRLCNT: 2272 rxnfc->data = 0; 2273 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2274 rxnfc->rule_cnt = 0; 2275 idr_for_each_entry(&chip->policies, policy, id) 2276 if (policy->port == port) 2277 rxnfc->rule_cnt++; 2278 err = 0; 2279 break; 2280 case ETHTOOL_GRXCLSRULE: 2281 err = -ENOENT; 2282 policy = idr_find(&chip->policies, fs->location); 2283 if (policy) { 2284 memcpy(fs, &policy->fs, sizeof(*fs)); 2285 err = 0; 2286 } 2287 break; 2288 case ETHTOOL_GRXCLSRLALL: 2289 rxnfc->data = 0; 2290 rxnfc->rule_cnt = 0; 2291 idr_for_each_entry(&chip->policies, policy, id) 2292 if (policy->port == port) 2293 rule_locs[rxnfc->rule_cnt++] = id; 2294 err = 0; 2295 break; 2296 default: 2297 err = -EOPNOTSUPP; 2298 break; 2299 } 2300 2301 mv88e6xxx_reg_unlock(chip); 2302 2303 return err; 2304} 2305 2306static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2307 struct ethtool_rxnfc *rxnfc) 2308{ 2309 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2310 struct mv88e6xxx_chip *chip = ds->priv; 2311 struct mv88e6xxx_policy *policy; 2312 int err; 2313 2314 mv88e6xxx_reg_lock(chip); 2315 2316 switch (rxnfc->cmd) { 2317 case ETHTOOL_SRXCLSRLINS: 2318 err = mv88e6xxx_policy_insert(chip, port, fs); 2319 break; 2320 case ETHTOOL_SRXCLSRLDEL: 2321 err = -ENOENT; 2322 policy = idr_remove(&chip->policies, fs->location); 2323 if (policy) { 2324 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2325 err = mv88e6xxx_policy_apply(chip, port, policy); 2326 devm_kfree(chip->dev, policy); 2327 } 2328 break; 2329 default: 2330 err = -EOPNOTSUPP; 2331 break; 2332 } 2333 2334 mv88e6xxx_reg_unlock(chip); 2335 2336 return err; 2337} 2338 2339static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2340 u16 vid) 2341{ 2342 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2343 u8 broadcast[ETH_ALEN]; 2344 2345 eth_broadcast_addr(broadcast); 2346 2347 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2348} 2349 2350static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2351{ 2352 int port; 2353 int err; 2354 2355 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2356 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2357 struct net_device *brport; 2358 2359 if (dsa_is_unused_port(chip->ds, port)) 2360 continue; 2361 2362 brport = dsa_port_to_bridge_port(dp); 2363 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2364 /* Skip bridged user ports where broadcast 2365 * flooding is disabled. 2366 */ 2367 continue; 2368 2369 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2370 if (err) 2371 return err; 2372 } 2373 2374 return 0; 2375} 2376 2377struct mv88e6xxx_port_broadcast_sync_ctx { 2378 int port; 2379 bool flood; 2380}; 2381 2382static int 2383mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2384 const struct mv88e6xxx_vtu_entry *vlan, 2385 void *_ctx) 2386{ 2387 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2388 u8 broadcast[ETH_ALEN]; 2389 u8 state; 2390 2391 if (ctx->flood) 2392 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2393 else 2394 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2395 2396 eth_broadcast_addr(broadcast); 2397 2398 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2399 vlan->vid, state); 2400} 2401 2402static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2403 bool flood) 2404{ 2405 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2406 .port = port, 2407 .flood = flood, 2408 }; 2409 struct mv88e6xxx_vtu_entry vid0 = { 2410 .vid = 0, 2411 }; 2412 int err; 2413 2414 /* Update the port's private database... */ 2415 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2416 if (err) 2417 return err; 2418 2419 /* ...and the database for all VLANs. */ 2420 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2421 &ctx); 2422} 2423 2424static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2425 u16 vid, u8 member, bool warn) 2426{ 2427 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2428 struct mv88e6xxx_vtu_entry vlan; 2429 int i, err; 2430 2431 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2432 if (err) 2433 return err; 2434 2435 if (!vlan.valid) { 2436 memset(&vlan, 0, sizeof(vlan)); 2437 2438 if (vid == MV88E6XXX_VID_STANDALONE) 2439 vlan.policy = true; 2440 2441 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2442 if (err) 2443 return err; 2444 2445 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2446 if (i == port) 2447 vlan.member[i] = member; 2448 else 2449 vlan.member[i] = non_member; 2450 2451 vlan.vid = vid; 2452 vlan.valid = true; 2453 2454 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2455 if (err) 2456 return err; 2457 2458 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2459 if (err) 2460 return err; 2461 } else if (vlan.member[port] != member) { 2462 vlan.member[port] = member; 2463 2464 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2465 if (err) 2466 return err; 2467 } else if (warn) { 2468 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2469 port, vid); 2470 } 2471 2472 return 0; 2473} 2474 2475static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2476 const struct switchdev_obj_port_vlan *vlan, 2477 struct netlink_ext_ack *extack) 2478{ 2479 struct mv88e6xxx_chip *chip = ds->priv; 2480 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2481 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2482 struct mv88e6xxx_port *p = &chip->ports[port]; 2483 bool warn; 2484 u8 member; 2485 int err; 2486 2487 if (!vlan->vid) 2488 return 0; 2489 2490 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2491 if (err) 2492 return err; 2493 2494 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2495 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2496 else if (untagged) 2497 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2498 else 2499 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2500 2501 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2502 * and then the CPU port. Do not warn for duplicates for the CPU port. 2503 */ 2504 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2505 2506 mv88e6xxx_reg_lock(chip); 2507 2508 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2509 if (err) { 2510 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2511 vlan->vid, untagged ? 'u' : 't'); 2512 goto out; 2513 } 2514 2515 if (pvid) { 2516 p->bridge_pvid.vid = vlan->vid; 2517 p->bridge_pvid.valid = true; 2518 2519 err = mv88e6xxx_port_commit_pvid(chip, port); 2520 if (err) 2521 goto out; 2522 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2523 /* The old pvid was reinstalled as a non-pvid VLAN */ 2524 p->bridge_pvid.valid = false; 2525 2526 err = mv88e6xxx_port_commit_pvid(chip, port); 2527 if (err) 2528 goto out; 2529 } 2530 2531out: 2532 mv88e6xxx_reg_unlock(chip); 2533 2534 return err; 2535} 2536 2537static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2538 int port, u16 vid) 2539{ 2540 struct mv88e6xxx_vtu_entry vlan; 2541 int i, err; 2542 2543 if (!vid) 2544 return 0; 2545 2546 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2547 if (err) 2548 return err; 2549 2550 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2551 * tell switchdev that this VLAN is likely handled in software. 2552 */ 2553 if (!vlan.valid || 2554 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2555 return -EOPNOTSUPP; 2556 2557 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2558 2559 /* keep the VLAN unless all ports are excluded */ 2560 vlan.valid = false; 2561 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2562 if (vlan.member[i] != 2563 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2564 vlan.valid = true; 2565 break; 2566 } 2567 } 2568 2569 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2570 if (err) 2571 return err; 2572 2573 if (!vlan.valid) { 2574 err = mv88e6xxx_mst_put(chip, vlan.sid); 2575 if (err) 2576 return err; 2577 } 2578 2579 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2580} 2581 2582static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2583 const struct switchdev_obj_port_vlan *vlan) 2584{ 2585 struct mv88e6xxx_chip *chip = ds->priv; 2586 struct mv88e6xxx_port *p = &chip->ports[port]; 2587 int err = 0; 2588 u16 pvid; 2589 2590 if (!mv88e6xxx_max_vid(chip)) 2591 return -EOPNOTSUPP; 2592 2593 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2594 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2595 * switchdev workqueue to ensure that all FDB entries are deleted 2596 * before we remove the VLAN. 2597 */ 2598 dsa_flush_workqueue(); 2599 2600 mv88e6xxx_reg_lock(chip); 2601 2602 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2603 if (err) 2604 goto unlock; 2605 2606 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2607 if (err) 2608 goto unlock; 2609 2610 if (vlan->vid == pvid) { 2611 p->bridge_pvid.valid = false; 2612 2613 err = mv88e6xxx_port_commit_pvid(chip, port); 2614 if (err) 2615 goto unlock; 2616 } 2617 2618unlock: 2619 mv88e6xxx_reg_unlock(chip); 2620 2621 return err; 2622} 2623 2624static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2625{ 2626 struct mv88e6xxx_chip *chip = ds->priv; 2627 struct mv88e6xxx_vtu_entry vlan; 2628 int err; 2629 2630 mv88e6xxx_reg_lock(chip); 2631 2632 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2633 if (err) 2634 goto unlock; 2635 2636 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2637 2638unlock: 2639 mv88e6xxx_reg_unlock(chip); 2640 2641 return err; 2642} 2643 2644static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2645 struct dsa_bridge bridge, 2646 const struct switchdev_vlan_msti *msti) 2647{ 2648 struct mv88e6xxx_chip *chip = ds->priv; 2649 struct mv88e6xxx_vtu_entry vlan; 2650 u8 old_sid, new_sid; 2651 int err; 2652 2653 if (!mv88e6xxx_has_stu(chip)) 2654 return -EOPNOTSUPP; 2655 2656 mv88e6xxx_reg_lock(chip); 2657 2658 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2659 if (err) 2660 goto unlock; 2661 2662 if (!vlan.valid) { 2663 err = -EINVAL; 2664 goto unlock; 2665 } 2666 2667 old_sid = vlan.sid; 2668 2669 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2670 if (err) 2671 goto unlock; 2672 2673 if (new_sid != old_sid) { 2674 vlan.sid = new_sid; 2675 2676 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2677 if (err) { 2678 mv88e6xxx_mst_put(chip, new_sid); 2679 goto unlock; 2680 } 2681 } 2682 2683 err = mv88e6xxx_mst_put(chip, old_sid); 2684 2685unlock: 2686 mv88e6xxx_reg_unlock(chip); 2687 return err; 2688} 2689 2690static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2691 const unsigned char *addr, u16 vid, 2692 struct dsa_db db) 2693{ 2694 struct mv88e6xxx_chip *chip = ds->priv; 2695 int err; 2696 2697 mv88e6xxx_reg_lock(chip); 2698 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2699 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2700 mv88e6xxx_reg_unlock(chip); 2701 2702 return err; 2703} 2704 2705static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2706 const unsigned char *addr, u16 vid, 2707 struct dsa_db db) 2708{ 2709 struct mv88e6xxx_chip *chip = ds->priv; 2710 int err; 2711 2712 mv88e6xxx_reg_lock(chip); 2713 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2714 mv88e6xxx_reg_unlock(chip); 2715 2716 return err; 2717} 2718 2719static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2720 u16 fid, u16 vid, int port, 2721 dsa_fdb_dump_cb_t *cb, void *data) 2722{ 2723 struct mv88e6xxx_atu_entry addr; 2724 bool is_static; 2725 int err; 2726 2727 addr.state = 0; 2728 eth_broadcast_addr(addr.mac); 2729 2730 do { 2731 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2732 if (err) 2733 return err; 2734 2735 if (!addr.state) 2736 break; 2737 2738 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2739 continue; 2740 2741 if (!is_unicast_ether_addr(addr.mac)) 2742 continue; 2743 2744 is_static = (addr.state == 2745 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2746 err = cb(addr.mac, vid, is_static, data); 2747 if (err) 2748 return err; 2749 } while (!is_broadcast_ether_addr(addr.mac)); 2750 2751 return err; 2752} 2753 2754struct mv88e6xxx_port_db_dump_vlan_ctx { 2755 int port; 2756 dsa_fdb_dump_cb_t *cb; 2757 void *data; 2758}; 2759 2760static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2761 const struct mv88e6xxx_vtu_entry *entry, 2762 void *_data) 2763{ 2764 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2765 2766 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2767 ctx->port, ctx->cb, ctx->data); 2768} 2769 2770static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2771 dsa_fdb_dump_cb_t *cb, void *data) 2772{ 2773 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2774 .port = port, 2775 .cb = cb, 2776 .data = data, 2777 }; 2778 u16 fid; 2779 int err; 2780 2781 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2782 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2783 if (err) 2784 return err; 2785 2786 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2787 if (err) 2788 return err; 2789 2790 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2791} 2792 2793static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2794 dsa_fdb_dump_cb_t *cb, void *data) 2795{ 2796 struct mv88e6xxx_chip *chip = ds->priv; 2797 int err; 2798 2799 mv88e6xxx_reg_lock(chip); 2800 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2801 mv88e6xxx_reg_unlock(chip); 2802 2803 return err; 2804} 2805 2806static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2807 struct dsa_bridge bridge) 2808{ 2809 struct dsa_switch *ds = chip->ds; 2810 struct dsa_switch_tree *dst = ds->dst; 2811 struct dsa_port *dp; 2812 int err; 2813 2814 list_for_each_entry(dp, &dst->ports, list) { 2815 if (dsa_port_offloads_bridge(dp, &bridge)) { 2816 if (dp->ds == ds) { 2817 /* This is a local bridge group member, 2818 * remap its Port VLAN Map. 2819 */ 2820 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2821 if (err) 2822 return err; 2823 } else { 2824 /* This is an external bridge group member, 2825 * remap its cross-chip Port VLAN Table entry. 2826 */ 2827 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2828 dp->index); 2829 if (err) 2830 return err; 2831 } 2832 } 2833 } 2834 2835 return 0; 2836} 2837 2838/* Treat the software bridge as a virtual single-port switch behind the 2839 * CPU and map in the PVT. First dst->last_switch elements are taken by 2840 * physical switches, so start from beyond that range. 2841 */ 2842static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2843 unsigned int bridge_num) 2844{ 2845 u8 dev = bridge_num + ds->dst->last_switch; 2846 struct mv88e6xxx_chip *chip = ds->priv; 2847 2848 return mv88e6xxx_pvt_map(chip, dev, 0); 2849} 2850 2851static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2852 struct dsa_bridge bridge, 2853 bool *tx_fwd_offload, 2854 struct netlink_ext_ack *extack) 2855{ 2856 struct mv88e6xxx_chip *chip = ds->priv; 2857 int err; 2858 2859 mv88e6xxx_reg_lock(chip); 2860 2861 err = mv88e6xxx_bridge_map(chip, bridge); 2862 if (err) 2863 goto unlock; 2864 2865 err = mv88e6xxx_port_set_map_da(chip, port, true); 2866 if (err) 2867 goto unlock; 2868 2869 err = mv88e6xxx_port_commit_pvid(chip, port); 2870 if (err) 2871 goto unlock; 2872 2873 if (mv88e6xxx_has_pvt(chip)) { 2874 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2875 if (err) 2876 goto unlock; 2877 2878 *tx_fwd_offload = true; 2879 } 2880 2881unlock: 2882 mv88e6xxx_reg_unlock(chip); 2883 2884 return err; 2885} 2886 2887static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2888 struct dsa_bridge bridge) 2889{ 2890 struct mv88e6xxx_chip *chip = ds->priv; 2891 int err; 2892 2893 mv88e6xxx_reg_lock(chip); 2894 2895 if (bridge.tx_fwd_offload && 2896 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2897 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2898 2899 if (mv88e6xxx_bridge_map(chip, bridge) || 2900 mv88e6xxx_port_vlan_map(chip, port)) 2901 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2902 2903 err = mv88e6xxx_port_set_map_da(chip, port, false); 2904 if (err) 2905 dev_err(ds->dev, 2906 "port %d failed to restore map-DA: %pe\n", 2907 port, ERR_PTR(err)); 2908 2909 err = mv88e6xxx_port_commit_pvid(chip, port); 2910 if (err) 2911 dev_err(ds->dev, 2912 "port %d failed to restore standalone pvid: %pe\n", 2913 port, ERR_PTR(err)); 2914 2915 mv88e6xxx_reg_unlock(chip); 2916} 2917 2918static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2919 int tree_index, int sw_index, 2920 int port, struct dsa_bridge bridge, 2921 struct netlink_ext_ack *extack) 2922{ 2923 struct mv88e6xxx_chip *chip = ds->priv; 2924 int err; 2925 2926 if (tree_index != ds->dst->index) 2927 return 0; 2928 2929 mv88e6xxx_reg_lock(chip); 2930 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2931 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2932 mv88e6xxx_reg_unlock(chip); 2933 2934 return err; 2935} 2936 2937static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2938 int tree_index, int sw_index, 2939 int port, struct dsa_bridge bridge) 2940{ 2941 struct mv88e6xxx_chip *chip = ds->priv; 2942 2943 if (tree_index != ds->dst->index) 2944 return; 2945 2946 mv88e6xxx_reg_lock(chip); 2947 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2948 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2949 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2950 mv88e6xxx_reg_unlock(chip); 2951} 2952 2953static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2954{ 2955 if (chip->info->ops->reset) 2956 return chip->info->ops->reset(chip); 2957 2958 return 0; 2959} 2960 2961static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2962{ 2963 struct gpio_desc *gpiod = chip->reset; 2964 2965 /* If there is a GPIO connected to the reset pin, toggle it */ 2966 if (gpiod) { 2967 /* If the switch has just been reset and not yet completed 2968 * loading EEPROM, the reset may interrupt the I2C transaction 2969 * mid-byte, causing the first EEPROM read after the reset 2970 * from the wrong location resulting in the switch booting 2971 * to wrong mode and inoperable. 2972 */ 2973 if (chip->info->ops->get_eeprom) 2974 mv88e6xxx_g2_eeprom_wait(chip); 2975 2976 gpiod_set_value_cansleep(gpiod, 1); 2977 usleep_range(10000, 20000); 2978 gpiod_set_value_cansleep(gpiod, 0); 2979 usleep_range(10000, 20000); 2980 2981 if (chip->info->ops->get_eeprom) 2982 mv88e6xxx_g2_eeprom_wait(chip); 2983 } 2984} 2985 2986static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2987{ 2988 int i, err; 2989 2990 /* Set all ports to the Disabled state */ 2991 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2992 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2993 if (err) 2994 return err; 2995 } 2996 2997 /* Wait for transmit queues to drain, 2998 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2999 */ 3000 usleep_range(2000, 4000); 3001 3002 return 0; 3003} 3004 3005static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3006{ 3007 int err; 3008 3009 err = mv88e6xxx_disable_ports(chip); 3010 if (err) 3011 return err; 3012 3013 mv88e6xxx_hardware_reset(chip); 3014 3015 return mv88e6xxx_software_reset(chip); 3016} 3017 3018static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3019 enum mv88e6xxx_frame_mode frame, 3020 enum mv88e6xxx_egress_mode egress, u16 etype) 3021{ 3022 int err; 3023 3024 if (!chip->info->ops->port_set_frame_mode) 3025 return -EOPNOTSUPP; 3026 3027 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3028 if (err) 3029 return err; 3030 3031 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3032 if (err) 3033 return err; 3034 3035 if (chip->info->ops->port_set_ether_type) 3036 return chip->info->ops->port_set_ether_type(chip, port, etype); 3037 3038 return 0; 3039} 3040 3041static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3042{ 3043 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3044 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3045 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3046} 3047 3048static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3049{ 3050 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3051 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3052 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3053} 3054 3055static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3056{ 3057 return mv88e6xxx_set_port_mode(chip, port, 3058 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3059 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3060 ETH_P_EDSA); 3061} 3062 3063static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3064{ 3065 if (dsa_is_dsa_port(chip->ds, port)) 3066 return mv88e6xxx_set_port_mode_dsa(chip, port); 3067 3068 if (dsa_is_user_port(chip->ds, port)) 3069 return mv88e6xxx_set_port_mode_normal(chip, port); 3070 3071 /* Setup CPU port mode depending on its supported tag format */ 3072 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3073 return mv88e6xxx_set_port_mode_dsa(chip, port); 3074 3075 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3076 return mv88e6xxx_set_port_mode_edsa(chip, port); 3077 3078 return -EINVAL; 3079} 3080 3081static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3082{ 3083 bool message = dsa_is_dsa_port(chip->ds, port); 3084 3085 return mv88e6xxx_port_set_message_port(chip, port, message); 3086} 3087 3088static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3089{ 3090 int err; 3091 3092 if (chip->info->ops->port_set_ucast_flood) { 3093 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3094 if (err) 3095 return err; 3096 } 3097 if (chip->info->ops->port_set_mcast_flood) { 3098 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3099 if (err) 3100 return err; 3101 } 3102 3103 return 0; 3104} 3105 3106static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3107 enum mv88e6xxx_egress_direction direction, 3108 int port) 3109{ 3110 int err; 3111 3112 if (!chip->info->ops->set_egress_port) 3113 return -EOPNOTSUPP; 3114 3115 err = chip->info->ops->set_egress_port(chip, direction, port); 3116 if (err) 3117 return err; 3118 3119 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3120 chip->ingress_dest_port = port; 3121 else 3122 chip->egress_dest_port = port; 3123 3124 return 0; 3125} 3126 3127static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3128{ 3129 struct dsa_switch *ds = chip->ds; 3130 int upstream_port; 3131 int err; 3132 3133 upstream_port = dsa_upstream_port(ds, port); 3134 if (chip->info->ops->port_set_upstream_port) { 3135 err = chip->info->ops->port_set_upstream_port(chip, port, 3136 upstream_port); 3137 if (err) 3138 return err; 3139 } 3140 3141 if (port == upstream_port) { 3142 if (chip->info->ops->set_cpu_port) { 3143 err = chip->info->ops->set_cpu_port(chip, 3144 upstream_port); 3145 if (err) 3146 return err; 3147 } 3148 3149 err = mv88e6xxx_set_egress_port(chip, 3150 MV88E6XXX_EGRESS_DIR_INGRESS, 3151 upstream_port); 3152 if (err && err != -EOPNOTSUPP) 3153 return err; 3154 3155 err = mv88e6xxx_set_egress_port(chip, 3156 MV88E6XXX_EGRESS_DIR_EGRESS, 3157 upstream_port); 3158 if (err && err != -EOPNOTSUPP) 3159 return err; 3160 } 3161 3162 return 0; 3163} 3164 3165static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3166{ 3167 struct device_node *phy_handle = NULL; 3168 struct dsa_switch *ds = chip->ds; 3169 struct dsa_port *dp; 3170 int tx_amp; 3171 int err; 3172 u16 reg; 3173 3174 chip->ports[port].chip = chip; 3175 chip->ports[port].port = port; 3176 3177 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3178 SPEED_UNFORCED, DUPLEX_UNFORCED, 3179 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3180 if (err) 3181 return err; 3182 3183 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3184 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3185 * tunneling, determine priority by looking at 802.1p and IP 3186 * priority fields (IP prio has precedence), and set STP state 3187 * to Forwarding. 3188 * 3189 * If this is the CPU link, use DSA or EDSA tagging depending 3190 * on which tagging mode was configured. 3191 * 3192 * If this is a link to another switch, use DSA tagging mode. 3193 * 3194 * If this is the upstream port for this switch, enable 3195 * forwarding of unknown unicasts and multicasts. 3196 */ 3197 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3198 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3199 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3200 * by a USER port to the CPU port to allow snooping. 3201 */ 3202 if (dsa_is_user_port(ds, port)) 3203 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3204 3205 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3206 if (err) 3207 return err; 3208 3209 err = mv88e6xxx_setup_port_mode(chip, port); 3210 if (err) 3211 return err; 3212 3213 err = mv88e6xxx_setup_egress_floods(chip, port); 3214 if (err) 3215 return err; 3216 3217 /* Port Control 2: don't force a good FCS, set the MTU size to 3218 * 10222 bytes, disable 802.1q tags checking, don't discard 3219 * tagged or untagged frames on this port, skip destination 3220 * address lookup on user ports, disable ARP mirroring and don't 3221 * send a copy of all transmitted/received frames on this port 3222 * to the CPU. 3223 */ 3224 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3225 if (err) 3226 return err; 3227 3228 err = mv88e6xxx_setup_upstream_port(chip, port); 3229 if (err) 3230 return err; 3231 3232 /* On chips that support it, set all downstream DSA ports' 3233 * VLAN policy to TRAP. In combination with loading 3234 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3235 * provides a better isolation barrier between standalone 3236 * ports, as the ATU is bypassed on any intermediate switches 3237 * between the incoming port and the CPU. 3238 */ 3239 if (dsa_is_downstream_port(ds, port) && 3240 chip->info->ops->port_set_policy) { 3241 err = chip->info->ops->port_set_policy(chip, port, 3242 MV88E6XXX_POLICY_MAPPING_VTU, 3243 MV88E6XXX_POLICY_ACTION_TRAP); 3244 if (err) 3245 return err; 3246 } 3247 3248 /* User ports start out in standalone mode and 802.1Q is 3249 * therefore disabled. On DSA ports, all valid VIDs are always 3250 * loaded in the VTU - therefore, enable 802.1Q in order to take 3251 * advantage of VLAN policy on chips that supports it. 3252 */ 3253 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3254 dsa_is_user_port(ds, port) ? 3255 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3256 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3257 if (err) 3258 return err; 3259 3260 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3261 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3262 * the first free FID. This will be used as the private PVID for 3263 * unbridged ports. Shared (DSA and CPU) ports must also be 3264 * members of this VID, in order to trap all frames assigned to 3265 * it to the CPU. 3266 */ 3267 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3268 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3269 false); 3270 if (err) 3271 return err; 3272 3273 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3274 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3275 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3276 * as the private PVID on ports under a VLAN-unaware bridge. 3277 * Shared (DSA and CPU) ports must also be members of it, to translate 3278 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3279 * relying on their port default FID. 3280 */ 3281 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3282 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3283 false); 3284 if (err) 3285 return err; 3286 3287 if (chip->info->ops->port_set_jumbo_size) { 3288 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3289 if (err) 3290 return err; 3291 } 3292 3293 /* Port Association Vector: disable automatic address learning 3294 * on all user ports since they start out in standalone 3295 * mode. When joining a bridge, learning will be configured to 3296 * match the bridge port settings. Enable learning on all 3297 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3298 * learning process. 3299 * 3300 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3301 * and RefreshLocked. I.e. setup standard automatic learning. 3302 */ 3303 if (dsa_is_user_port(ds, port)) 3304 reg = 0; 3305 else 3306 reg = 1 << port; 3307 3308 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3309 reg); 3310 if (err) 3311 return err; 3312 3313 /* Egress rate control 2: disable egress rate control. */ 3314 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3315 0x0000); 3316 if (err) 3317 return err; 3318 3319 if (chip->info->ops->port_pause_limit) { 3320 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3321 if (err) 3322 return err; 3323 } 3324 3325 if (chip->info->ops->port_disable_learn_limit) { 3326 err = chip->info->ops->port_disable_learn_limit(chip, port); 3327 if (err) 3328 return err; 3329 } 3330 3331 if (chip->info->ops->port_disable_pri_override) { 3332 err = chip->info->ops->port_disable_pri_override(chip, port); 3333 if (err) 3334 return err; 3335 } 3336 3337 if (chip->info->ops->port_tag_remap) { 3338 err = chip->info->ops->port_tag_remap(chip, port); 3339 if (err) 3340 return err; 3341 } 3342 3343 if (chip->info->ops->port_egress_rate_limiting) { 3344 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3345 if (err) 3346 return err; 3347 } 3348 3349 if (chip->info->ops->port_setup_message_port) { 3350 err = chip->info->ops->port_setup_message_port(chip, port); 3351 if (err) 3352 return err; 3353 } 3354 3355 if (chip->info->ops->serdes_set_tx_amplitude) { 3356 dp = dsa_to_port(ds, port); 3357 if (dp) 3358 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3359 3360 if (phy_handle && !of_property_read_u32(phy_handle, 3361 "tx-p2p-microvolt", 3362 &tx_amp)) 3363 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3364 port, tx_amp); 3365 if (phy_handle) { 3366 of_node_put(phy_handle); 3367 if (err) 3368 return err; 3369 } 3370 } 3371 3372 /* Port based VLAN map: give each port the same default address 3373 * database, and allow bidirectional communication between the 3374 * CPU and DSA port(s), and the other ports. 3375 */ 3376 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3377 if (err) 3378 return err; 3379 3380 err = mv88e6xxx_port_vlan_map(chip, port); 3381 if (err) 3382 return err; 3383 3384 /* Default VLAN ID and priority: don't set a default VLAN 3385 * ID, and set the default packet priority to zero. 3386 */ 3387 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3388} 3389 3390static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3391{ 3392 struct mv88e6xxx_chip *chip = ds->priv; 3393 3394 if (chip->info->ops->port_set_jumbo_size) 3395 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3396 else if (chip->info->ops->set_max_frame_size) 3397 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3398 return ETH_DATA_LEN; 3399} 3400 3401static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3402{ 3403 struct mv88e6xxx_chip *chip = ds->priv; 3404 int ret = 0; 3405 3406 /* For families where we don't know how to alter the MTU, 3407 * just accept any value up to ETH_DATA_LEN 3408 */ 3409 if (!chip->info->ops->port_set_jumbo_size && 3410 !chip->info->ops->set_max_frame_size) { 3411 if (new_mtu > ETH_DATA_LEN) 3412 return -EINVAL; 3413 3414 return 0; 3415 } 3416 3417 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3418 new_mtu += EDSA_HLEN; 3419 3420 mv88e6xxx_reg_lock(chip); 3421 if (chip->info->ops->port_set_jumbo_size) 3422 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3423 else if (chip->info->ops->set_max_frame_size) 3424 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3425 mv88e6xxx_reg_unlock(chip); 3426 3427 return ret; 3428} 3429 3430static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3431 unsigned int ageing_time) 3432{ 3433 struct mv88e6xxx_chip *chip = ds->priv; 3434 int err; 3435 3436 mv88e6xxx_reg_lock(chip); 3437 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3438 mv88e6xxx_reg_unlock(chip); 3439 3440 return err; 3441} 3442 3443static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3444{ 3445 int err; 3446 3447 /* Initialize the statistics unit */ 3448 if (chip->info->ops->stats_set_histogram) { 3449 err = chip->info->ops->stats_set_histogram(chip); 3450 if (err) 3451 return err; 3452 } 3453 3454 return mv88e6xxx_g1_stats_clear(chip); 3455} 3456 3457/* Check if the errata has already been applied. */ 3458static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3459{ 3460 int port; 3461 int err; 3462 u16 val; 3463 3464 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3465 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3466 if (err) { 3467 dev_err(chip->dev, 3468 "Error reading hidden register: %d\n", err); 3469 return false; 3470 } 3471 if (val != 0x01c0) 3472 return false; 3473 } 3474 3475 return true; 3476} 3477 3478/* The 6390 copper ports have an errata which require poking magic 3479 * values into undocumented hidden registers and then performing a 3480 * software reset. 3481 */ 3482static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3483{ 3484 int port; 3485 int err; 3486 3487 if (mv88e6390_setup_errata_applied(chip)) 3488 return 0; 3489 3490 /* Set the ports into blocking mode */ 3491 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3492 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3493 if (err) 3494 return err; 3495 } 3496 3497 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3498 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3499 if (err) 3500 return err; 3501 } 3502 3503 return mv88e6xxx_software_reset(chip); 3504} 3505 3506/* prod_id for switch families which do not have a PHY model number */ 3507static const u16 family_prod_id_table[] = { 3508 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3509 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3510 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3511}; 3512 3513static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3514{ 3515 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3516 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3517 u16 prod_id; 3518 u16 val; 3519 int err; 3520 3521 if (!chip->info->ops->phy_read) 3522 return -EOPNOTSUPP; 3523 3524 mv88e6xxx_reg_lock(chip); 3525 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3526 mv88e6xxx_reg_unlock(chip); 3527 3528 /* Some internal PHYs don't have a model number. */ 3529 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3530 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3531 prod_id = family_prod_id_table[chip->info->family]; 3532 if (prod_id) 3533 val |= prod_id >> 4; 3534 } 3535 3536 return err ? err : val; 3537} 3538 3539static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3540 int reg) 3541{ 3542 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3543 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3544 u16 val; 3545 int err; 3546 3547 if (!chip->info->ops->phy_read_c45) 3548 return 0xffff; 3549 3550 mv88e6xxx_reg_lock(chip); 3551 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3552 mv88e6xxx_reg_unlock(chip); 3553 3554 return err ? err : val; 3555} 3556 3557static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3558{ 3559 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3560 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3561 int err; 3562 3563 if (!chip->info->ops->phy_write) 3564 return -EOPNOTSUPP; 3565 3566 mv88e6xxx_reg_lock(chip); 3567 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3568 mv88e6xxx_reg_unlock(chip); 3569 3570 return err; 3571} 3572 3573static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3574 int reg, u16 val) 3575{ 3576 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3577 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3578 int err; 3579 3580 if (!chip->info->ops->phy_write_c45) 3581 return -EOPNOTSUPP; 3582 3583 mv88e6xxx_reg_lock(chip); 3584 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3585 mv88e6xxx_reg_unlock(chip); 3586 3587 return err; 3588} 3589 3590static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3591 struct device_node *np, 3592 bool external) 3593{ 3594 static int index; 3595 struct mv88e6xxx_mdio_bus *mdio_bus; 3596 struct mii_bus *bus; 3597 int err; 3598 3599 if (external) { 3600 mv88e6xxx_reg_lock(chip); 3601 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3602 mv88e6xxx_reg_unlock(chip); 3603 3604 if (err) 3605 return err; 3606 } 3607 3608 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3609 if (!bus) 3610 return -ENOMEM; 3611 3612 mdio_bus = bus->priv; 3613 mdio_bus->bus = bus; 3614 mdio_bus->chip = chip; 3615 INIT_LIST_HEAD(&mdio_bus->list); 3616 mdio_bus->external = external; 3617 3618 if (np) { 3619 bus->name = np->full_name; 3620 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3621 } else { 3622 bus->name = "mv88e6xxx SMI"; 3623 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3624 } 3625 3626 bus->read = mv88e6xxx_mdio_read; 3627 bus->write = mv88e6xxx_mdio_write; 3628 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3629 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3630 bus->parent = chip->dev; 3631 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3632 mv88e6xxx_num_ports(chip) - 1, 3633 chip->info->phy_base_addr); 3634 3635 if (!external) { 3636 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3637 if (err) 3638 goto out; 3639 } 3640 3641 err = of_mdiobus_register(bus, np); 3642 if (err) { 3643 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3644 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3645 goto out; 3646 } 3647 3648 if (external) 3649 list_add_tail(&mdio_bus->list, &chip->mdios); 3650 else 3651 list_add(&mdio_bus->list, &chip->mdios); 3652 3653 return 0; 3654 3655out: 3656 mdiobus_free(bus); 3657 return err; 3658} 3659 3660static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3661 3662{ 3663 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3664 struct mii_bus *bus; 3665 3666 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3667 bus = mdio_bus->bus; 3668 3669 if (!mdio_bus->external) 3670 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3671 3672 mdiobus_unregister(bus); 3673 mdiobus_free(bus); 3674 } 3675} 3676 3677static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3678{ 3679 struct device_node *np = chip->dev->of_node; 3680 struct device_node *child; 3681 int err; 3682 3683 /* Always register one mdio bus for the internal/default mdio 3684 * bus. This maybe represented in the device tree, but is 3685 * optional. 3686 */ 3687 child = of_get_child_by_name(np, "mdio"); 3688 err = mv88e6xxx_mdio_register(chip, child, false); 3689 of_node_put(child); 3690 if (err) 3691 return err; 3692 3693 /* Walk the device tree, and see if there are any other nodes 3694 * which say they are compatible with the external mdio 3695 * bus. 3696 */ 3697 for_each_available_child_of_node(np, child) { 3698 if (of_device_is_compatible( 3699 child, "marvell,mv88e6xxx-mdio-external")) { 3700 err = mv88e6xxx_mdio_register(chip, child, true); 3701 if (err) { 3702 mv88e6xxx_mdios_unregister(chip); 3703 of_node_put(child); 3704 return err; 3705 } 3706 } 3707 } 3708 3709 return 0; 3710} 3711 3712static void mv88e6xxx_teardown(struct dsa_switch *ds) 3713{ 3714 struct mv88e6xxx_chip *chip = ds->priv; 3715 3716 mv88e6xxx_teardown_devlink_params(ds); 3717 dsa_devlink_resources_unregister(ds); 3718 mv88e6xxx_teardown_devlink_regions_global(ds); 3719 mv88e6xxx_mdios_unregister(chip); 3720} 3721 3722static int mv88e6xxx_setup(struct dsa_switch *ds) 3723{ 3724 struct mv88e6xxx_chip *chip = ds->priv; 3725 u8 cmode; 3726 int err; 3727 int i; 3728 3729 err = mv88e6xxx_mdios_register(chip); 3730 if (err) 3731 return err; 3732 3733 chip->ds = ds; 3734 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3735 3736 /* Since virtual bridges are mapped in the PVT, the number we support 3737 * depends on the physical switch topology. We need to let DSA figure 3738 * that out and therefore we cannot set this at dsa_register_switch() 3739 * time. 3740 */ 3741 if (mv88e6xxx_has_pvt(chip)) 3742 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3743 ds->dst->last_switch - 1; 3744 3745 mv88e6xxx_reg_lock(chip); 3746 3747 if (chip->info->ops->setup_errata) { 3748 err = chip->info->ops->setup_errata(chip); 3749 if (err) 3750 goto unlock; 3751 } 3752 3753 /* Cache the cmode of each port. */ 3754 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3755 if (chip->info->ops->port_get_cmode) { 3756 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3757 if (err) 3758 goto unlock; 3759 3760 chip->ports[i].cmode = cmode; 3761 } 3762 } 3763 3764 err = mv88e6xxx_vtu_setup(chip); 3765 if (err) 3766 goto unlock; 3767 3768 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3769 * VTU, thereby also flushing the STU). 3770 */ 3771 err = mv88e6xxx_stu_setup(chip); 3772 if (err) 3773 goto unlock; 3774 3775 /* Setup Switch Port Registers */ 3776 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3777 if (dsa_is_unused_port(ds, i)) 3778 continue; 3779 3780 /* Prevent the use of an invalid port. */ 3781 if (mv88e6xxx_is_invalid_port(chip, i)) { 3782 dev_err(chip->dev, "port %d is invalid\n", i); 3783 err = -EINVAL; 3784 goto unlock; 3785 } 3786 3787 err = mv88e6xxx_setup_port(chip, i); 3788 if (err) 3789 goto unlock; 3790 } 3791 3792 err = mv88e6xxx_irl_setup(chip); 3793 if (err) 3794 goto unlock; 3795 3796 err = mv88e6xxx_mac_setup(chip); 3797 if (err) 3798 goto unlock; 3799 3800 err = mv88e6xxx_phy_setup(chip); 3801 if (err) 3802 goto unlock; 3803 3804 err = mv88e6xxx_pvt_setup(chip); 3805 if (err) 3806 goto unlock; 3807 3808 err = mv88e6xxx_atu_setup(chip); 3809 if (err) 3810 goto unlock; 3811 3812 err = mv88e6xxx_broadcast_setup(chip, 0); 3813 if (err) 3814 goto unlock; 3815 3816 err = mv88e6xxx_pot_setup(chip); 3817 if (err) 3818 goto unlock; 3819 3820 err = mv88e6xxx_rmu_setup(chip); 3821 if (err) 3822 goto unlock; 3823 3824 err = mv88e6xxx_rsvd2cpu_setup(chip); 3825 if (err) 3826 goto unlock; 3827 3828 err = mv88e6xxx_trunk_setup(chip); 3829 if (err) 3830 goto unlock; 3831 3832 err = mv88e6xxx_devmap_setup(chip); 3833 if (err) 3834 goto unlock; 3835 3836 err = mv88e6xxx_pri_setup(chip); 3837 if (err) 3838 goto unlock; 3839 3840 /* Setup PTP Hardware Clock and timestamping */ 3841 if (chip->info->ptp_support) { 3842 err = mv88e6xxx_ptp_setup(chip); 3843 if (err) 3844 goto unlock; 3845 3846 err = mv88e6xxx_hwtstamp_setup(chip); 3847 if (err) 3848 goto unlock; 3849 } 3850 3851 err = mv88e6xxx_stats_setup(chip); 3852 if (err) 3853 goto unlock; 3854 3855unlock: 3856 mv88e6xxx_reg_unlock(chip); 3857 3858 if (err) 3859 goto out_mdios; 3860 3861 /* Have to be called without holding the register lock, since 3862 * they take the devlink lock, and we later take the locks in 3863 * the reverse order when getting/setting parameters or 3864 * resource occupancy. 3865 */ 3866 err = mv88e6xxx_setup_devlink_resources(ds); 3867 if (err) 3868 goto out_mdios; 3869 3870 err = mv88e6xxx_setup_devlink_params(ds); 3871 if (err) 3872 goto out_resources; 3873 3874 err = mv88e6xxx_setup_devlink_regions_global(ds); 3875 if (err) 3876 goto out_params; 3877 3878 return 0; 3879 3880out_params: 3881 mv88e6xxx_teardown_devlink_params(ds); 3882out_resources: 3883 dsa_devlink_resources_unregister(ds); 3884out_mdios: 3885 mv88e6xxx_mdios_unregister(chip); 3886 3887 return err; 3888} 3889 3890static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3891{ 3892 struct mv88e6xxx_chip *chip = ds->priv; 3893 int err; 3894 3895 if (chip->info->ops->pcs_ops && 3896 chip->info->ops->pcs_ops->pcs_init) { 3897 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 3898 if (err) 3899 return err; 3900 } 3901 3902 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3903} 3904 3905static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3906{ 3907 struct mv88e6xxx_chip *chip = ds->priv; 3908 3909 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3910 3911 if (chip->info->ops->pcs_ops && 3912 chip->info->ops->pcs_ops->pcs_teardown) 3913 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 3914} 3915 3916static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3917{ 3918 struct mv88e6xxx_chip *chip = ds->priv; 3919 3920 return chip->eeprom_len; 3921} 3922 3923static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3924 struct ethtool_eeprom *eeprom, u8 *data) 3925{ 3926 struct mv88e6xxx_chip *chip = ds->priv; 3927 int err; 3928 3929 if (!chip->info->ops->get_eeprom) 3930 return -EOPNOTSUPP; 3931 3932 mv88e6xxx_reg_lock(chip); 3933 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3934 mv88e6xxx_reg_unlock(chip); 3935 3936 if (err) 3937 return err; 3938 3939 eeprom->magic = 0xc3ec4951; 3940 3941 return 0; 3942} 3943 3944static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3945 struct ethtool_eeprom *eeprom, u8 *data) 3946{ 3947 struct mv88e6xxx_chip *chip = ds->priv; 3948 int err; 3949 3950 if (!chip->info->ops->set_eeprom) 3951 return -EOPNOTSUPP; 3952 3953 if (eeprom->magic != 0xc3ec4951) 3954 return -EINVAL; 3955 3956 mv88e6xxx_reg_lock(chip); 3957 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3958 mv88e6xxx_reg_unlock(chip); 3959 3960 return err; 3961} 3962 3963static const struct mv88e6xxx_ops mv88e6085_ops = { 3964 /* MV88E6XXX_FAMILY_6097 */ 3965 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3966 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3967 .irl_init_all = mv88e6352_g2_irl_init_all, 3968 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3969 .phy_read = mv88e6185_phy_ppu_read, 3970 .phy_write = mv88e6185_phy_ppu_write, 3971 .port_set_link = mv88e6xxx_port_set_link, 3972 .port_sync_link = mv88e6xxx_port_sync_link, 3973 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3974 .port_tag_remap = mv88e6095_port_tag_remap, 3975 .port_set_policy = mv88e6352_port_set_policy, 3976 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3977 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3978 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3979 .port_set_ether_type = mv88e6351_port_set_ether_type, 3980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3981 .port_pause_limit = mv88e6097_port_pause_limit, 3982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3984 .port_get_cmode = mv88e6185_port_get_cmode, 3985 .port_setup_message_port = mv88e6xxx_setup_message_port, 3986 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3987 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3988 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3989 .stats_get_strings = mv88e6095_stats_get_strings, 3990 .stats_get_stats = mv88e6095_stats_get_stats, 3991 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3992 .set_egress_port = mv88e6095_g1_set_egress_port, 3993 .watchdog_ops = &mv88e6097_watchdog_ops, 3994 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3995 .pot_clear = mv88e6xxx_g2_pot_clear, 3996 .ppu_enable = mv88e6185_g1_ppu_enable, 3997 .ppu_disable = mv88e6185_g1_ppu_disable, 3998 .reset = mv88e6185_g1_reset, 3999 .rmu_disable = mv88e6085_g1_rmu_disable, 4000 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4001 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4002 .stu_getnext = mv88e6352_g1_stu_getnext, 4003 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4004 .phylink_get_caps = mv88e6185_phylink_get_caps, 4005 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4006}; 4007 4008static const struct mv88e6xxx_ops mv88e6095_ops = { 4009 /* MV88E6XXX_FAMILY_6095 */ 4010 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4011 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4012 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4013 .phy_read = mv88e6185_phy_ppu_read, 4014 .phy_write = mv88e6185_phy_ppu_write, 4015 .port_set_link = mv88e6xxx_port_set_link, 4016 .port_sync_link = mv88e6185_port_sync_link, 4017 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4018 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4019 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4020 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4021 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4022 .port_get_cmode = mv88e6185_port_get_cmode, 4023 .port_setup_message_port = mv88e6xxx_setup_message_port, 4024 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4025 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4026 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4027 .stats_get_strings = mv88e6095_stats_get_strings, 4028 .stats_get_stats = mv88e6095_stats_get_stats, 4029 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4030 .ppu_enable = mv88e6185_g1_ppu_enable, 4031 .ppu_disable = mv88e6185_g1_ppu_disable, 4032 .reset = mv88e6185_g1_reset, 4033 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4034 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4035 .phylink_get_caps = mv88e6095_phylink_get_caps, 4036 .pcs_ops = &mv88e6185_pcs_ops, 4037 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4038}; 4039 4040static const struct mv88e6xxx_ops mv88e6097_ops = { 4041 /* MV88E6XXX_FAMILY_6097 */ 4042 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4043 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4044 .irl_init_all = mv88e6352_g2_irl_init_all, 4045 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4046 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4047 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4048 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4049 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4050 .port_set_link = mv88e6xxx_port_set_link, 4051 .port_sync_link = mv88e6185_port_sync_link, 4052 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4053 .port_tag_remap = mv88e6095_port_tag_remap, 4054 .port_set_policy = mv88e6352_port_set_policy, 4055 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4056 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4057 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4058 .port_set_ether_type = mv88e6351_port_set_ether_type, 4059 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4060 .port_pause_limit = mv88e6097_port_pause_limit, 4061 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4062 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4063 .port_get_cmode = mv88e6185_port_get_cmode, 4064 .port_setup_message_port = mv88e6xxx_setup_message_port, 4065 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4066 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4067 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4068 .stats_get_strings = mv88e6095_stats_get_strings, 4069 .stats_get_stats = mv88e6095_stats_get_stats, 4070 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4071 .set_egress_port = mv88e6095_g1_set_egress_port, 4072 .watchdog_ops = &mv88e6097_watchdog_ops, 4073 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4074 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4075 .pot_clear = mv88e6xxx_g2_pot_clear, 4076 .reset = mv88e6352_g1_reset, 4077 .rmu_disable = mv88e6085_g1_rmu_disable, 4078 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4079 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4080 .phylink_get_caps = mv88e6095_phylink_get_caps, 4081 .pcs_ops = &mv88e6185_pcs_ops, 4082 .stu_getnext = mv88e6352_g1_stu_getnext, 4083 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4084 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4085}; 4086 4087static const struct mv88e6xxx_ops mv88e6123_ops = { 4088 /* MV88E6XXX_FAMILY_6165 */ 4089 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4090 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4091 .irl_init_all = mv88e6352_g2_irl_init_all, 4092 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4093 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4094 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4095 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4096 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4097 .port_set_link = mv88e6xxx_port_set_link, 4098 .port_sync_link = mv88e6xxx_port_sync_link, 4099 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4100 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4101 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4102 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4103 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4104 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4105 .port_get_cmode = mv88e6185_port_get_cmode, 4106 .port_setup_message_port = mv88e6xxx_setup_message_port, 4107 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4108 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4109 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4110 .stats_get_strings = mv88e6095_stats_get_strings, 4111 .stats_get_stats = mv88e6095_stats_get_stats, 4112 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4113 .set_egress_port = mv88e6095_g1_set_egress_port, 4114 .watchdog_ops = &mv88e6097_watchdog_ops, 4115 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4116 .pot_clear = mv88e6xxx_g2_pot_clear, 4117 .reset = mv88e6352_g1_reset, 4118 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4119 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4120 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4121 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4122 .stu_getnext = mv88e6352_g1_stu_getnext, 4123 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4124 .phylink_get_caps = mv88e6185_phylink_get_caps, 4125 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4126}; 4127 4128static const struct mv88e6xxx_ops mv88e6131_ops = { 4129 /* MV88E6XXX_FAMILY_6185 */ 4130 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4131 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4132 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4133 .phy_read = mv88e6185_phy_ppu_read, 4134 .phy_write = mv88e6185_phy_ppu_write, 4135 .port_set_link = mv88e6xxx_port_set_link, 4136 .port_sync_link = mv88e6xxx_port_sync_link, 4137 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4138 .port_tag_remap = mv88e6095_port_tag_remap, 4139 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4140 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4141 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4142 .port_set_ether_type = mv88e6351_port_set_ether_type, 4143 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4144 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4145 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4146 .port_pause_limit = mv88e6097_port_pause_limit, 4147 .port_set_pause = mv88e6185_port_set_pause, 4148 .port_get_cmode = mv88e6185_port_get_cmode, 4149 .port_setup_message_port = mv88e6xxx_setup_message_port, 4150 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4151 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4152 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4153 .stats_get_strings = mv88e6095_stats_get_strings, 4154 .stats_get_stats = mv88e6095_stats_get_stats, 4155 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4156 .set_egress_port = mv88e6095_g1_set_egress_port, 4157 .watchdog_ops = &mv88e6097_watchdog_ops, 4158 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4159 .ppu_enable = mv88e6185_g1_ppu_enable, 4160 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4161 .ppu_disable = mv88e6185_g1_ppu_disable, 4162 .reset = mv88e6185_g1_reset, 4163 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4164 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4165 .phylink_get_caps = mv88e6185_phylink_get_caps, 4166}; 4167 4168static const struct mv88e6xxx_ops mv88e6141_ops = { 4169 /* MV88E6XXX_FAMILY_6341 */ 4170 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4171 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4172 .irl_init_all = mv88e6352_g2_irl_init_all, 4173 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4174 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4175 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4176 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4177 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4178 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4179 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4180 .port_set_link = mv88e6xxx_port_set_link, 4181 .port_sync_link = mv88e6xxx_port_sync_link, 4182 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4183 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4184 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4185 .port_tag_remap = mv88e6095_port_tag_remap, 4186 .port_set_policy = mv88e6352_port_set_policy, 4187 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4188 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4189 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4190 .port_set_ether_type = mv88e6351_port_set_ether_type, 4191 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4192 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4193 .port_pause_limit = mv88e6097_port_pause_limit, 4194 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4196 .port_get_cmode = mv88e6352_port_get_cmode, 4197 .port_set_cmode = mv88e6341_port_set_cmode, 4198 .port_setup_message_port = mv88e6xxx_setup_message_port, 4199 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4200 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4201 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4202 .stats_get_strings = mv88e6320_stats_get_strings, 4203 .stats_get_stats = mv88e6390_stats_get_stats, 4204 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4205 .set_egress_port = mv88e6390_g1_set_egress_port, 4206 .watchdog_ops = &mv88e6390_watchdog_ops, 4207 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4208 .pot_clear = mv88e6xxx_g2_pot_clear, 4209 .reset = mv88e6352_g1_reset, 4210 .rmu_disable = mv88e6390_g1_rmu_disable, 4211 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4212 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4213 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4214 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4215 .stu_getnext = mv88e6352_g1_stu_getnext, 4216 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4217 .serdes_get_lane = mv88e6341_serdes_get_lane, 4218 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4219 .gpio_ops = &mv88e6352_gpio_ops, 4220 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4221 .serdes_get_strings = mv88e6390_serdes_get_strings, 4222 .serdes_get_stats = mv88e6390_serdes_get_stats, 4223 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4224 .serdes_get_regs = mv88e6390_serdes_get_regs, 4225 .phylink_get_caps = mv88e6341_phylink_get_caps, 4226 .pcs_ops = &mv88e6390_pcs_ops, 4227}; 4228 4229static const struct mv88e6xxx_ops mv88e6161_ops = { 4230 /* MV88E6XXX_FAMILY_6165 */ 4231 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4232 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4233 .irl_init_all = mv88e6352_g2_irl_init_all, 4234 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4235 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4236 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4237 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4238 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4239 .port_set_link = mv88e6xxx_port_set_link, 4240 .port_sync_link = mv88e6xxx_port_sync_link, 4241 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4242 .port_tag_remap = mv88e6095_port_tag_remap, 4243 .port_set_policy = mv88e6352_port_set_policy, 4244 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4245 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4246 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4247 .port_set_ether_type = mv88e6351_port_set_ether_type, 4248 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4249 .port_pause_limit = mv88e6097_port_pause_limit, 4250 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4251 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4252 .port_get_cmode = mv88e6185_port_get_cmode, 4253 .port_setup_message_port = mv88e6xxx_setup_message_port, 4254 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4255 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4256 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4257 .stats_get_strings = mv88e6095_stats_get_strings, 4258 .stats_get_stats = mv88e6095_stats_get_stats, 4259 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4260 .set_egress_port = mv88e6095_g1_set_egress_port, 4261 .watchdog_ops = &mv88e6097_watchdog_ops, 4262 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4263 .pot_clear = mv88e6xxx_g2_pot_clear, 4264 .reset = mv88e6352_g1_reset, 4265 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4266 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4267 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4268 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4269 .stu_getnext = mv88e6352_g1_stu_getnext, 4270 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4271 .avb_ops = &mv88e6165_avb_ops, 4272 .ptp_ops = &mv88e6165_ptp_ops, 4273 .phylink_get_caps = mv88e6185_phylink_get_caps, 4274 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4275}; 4276 4277static const struct mv88e6xxx_ops mv88e6165_ops = { 4278 /* MV88E6XXX_FAMILY_6165 */ 4279 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4280 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4281 .irl_init_all = mv88e6352_g2_irl_init_all, 4282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4283 .phy_read = mv88e6165_phy_read, 4284 .phy_write = mv88e6165_phy_write, 4285 .port_set_link = mv88e6xxx_port_set_link, 4286 .port_sync_link = mv88e6xxx_port_sync_link, 4287 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4288 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4289 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4290 .port_get_cmode = mv88e6185_port_get_cmode, 4291 .port_setup_message_port = mv88e6xxx_setup_message_port, 4292 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4293 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4294 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4295 .stats_get_strings = mv88e6095_stats_get_strings, 4296 .stats_get_stats = mv88e6095_stats_get_stats, 4297 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4298 .set_egress_port = mv88e6095_g1_set_egress_port, 4299 .watchdog_ops = &mv88e6097_watchdog_ops, 4300 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4301 .pot_clear = mv88e6xxx_g2_pot_clear, 4302 .reset = mv88e6352_g1_reset, 4303 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4304 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4305 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4306 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4307 .stu_getnext = mv88e6352_g1_stu_getnext, 4308 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4309 .avb_ops = &mv88e6165_avb_ops, 4310 .ptp_ops = &mv88e6165_ptp_ops, 4311 .phylink_get_caps = mv88e6185_phylink_get_caps, 4312}; 4313 4314static const struct mv88e6xxx_ops mv88e6171_ops = { 4315 /* MV88E6XXX_FAMILY_6351 */ 4316 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4317 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4318 .irl_init_all = mv88e6352_g2_irl_init_all, 4319 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4320 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4321 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4322 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4323 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4324 .port_set_link = mv88e6xxx_port_set_link, 4325 .port_sync_link = mv88e6xxx_port_sync_link, 4326 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4327 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4328 .port_tag_remap = mv88e6095_port_tag_remap, 4329 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4330 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4331 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4332 .port_set_ether_type = mv88e6351_port_set_ether_type, 4333 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4334 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4335 .port_pause_limit = mv88e6097_port_pause_limit, 4336 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4337 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4338 .port_get_cmode = mv88e6352_port_get_cmode, 4339 .port_setup_message_port = mv88e6xxx_setup_message_port, 4340 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4341 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4342 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4343 .stats_get_strings = mv88e6095_stats_get_strings, 4344 .stats_get_stats = mv88e6095_stats_get_stats, 4345 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4346 .set_egress_port = mv88e6095_g1_set_egress_port, 4347 .watchdog_ops = &mv88e6097_watchdog_ops, 4348 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4349 .pot_clear = mv88e6xxx_g2_pot_clear, 4350 .reset = mv88e6352_g1_reset, 4351 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4352 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4353 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4354 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4355 .stu_getnext = mv88e6352_g1_stu_getnext, 4356 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4357 .phylink_get_caps = mv88e6351_phylink_get_caps, 4358}; 4359 4360static const struct mv88e6xxx_ops mv88e6172_ops = { 4361 /* MV88E6XXX_FAMILY_6352 */ 4362 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4363 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4364 .irl_init_all = mv88e6352_g2_irl_init_all, 4365 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4366 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4367 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4368 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4369 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4370 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4371 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4372 .port_set_link = mv88e6xxx_port_set_link, 4373 .port_sync_link = mv88e6xxx_port_sync_link, 4374 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4375 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4376 .port_tag_remap = mv88e6095_port_tag_remap, 4377 .port_set_policy = mv88e6352_port_set_policy, 4378 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4379 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4380 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4381 .port_set_ether_type = mv88e6351_port_set_ether_type, 4382 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4383 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4384 .port_pause_limit = mv88e6097_port_pause_limit, 4385 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4386 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4387 .port_get_cmode = mv88e6352_port_get_cmode, 4388 .port_setup_message_port = mv88e6xxx_setup_message_port, 4389 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4390 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4391 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4392 .stats_get_strings = mv88e6095_stats_get_strings, 4393 .stats_get_stats = mv88e6095_stats_get_stats, 4394 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4395 .set_egress_port = mv88e6095_g1_set_egress_port, 4396 .watchdog_ops = &mv88e6097_watchdog_ops, 4397 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4398 .pot_clear = mv88e6xxx_g2_pot_clear, 4399 .reset = mv88e6352_g1_reset, 4400 .rmu_disable = mv88e6352_g1_rmu_disable, 4401 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4402 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4403 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4404 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4405 .stu_getnext = mv88e6352_g1_stu_getnext, 4406 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4407 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4408 .serdes_get_regs = mv88e6352_serdes_get_regs, 4409 .gpio_ops = &mv88e6352_gpio_ops, 4410 .phylink_get_caps = mv88e6352_phylink_get_caps, 4411 .pcs_ops = &mv88e6352_pcs_ops, 4412}; 4413 4414static const struct mv88e6xxx_ops mv88e6175_ops = { 4415 /* MV88E6XXX_FAMILY_6351 */ 4416 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4417 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4418 .irl_init_all = mv88e6352_g2_irl_init_all, 4419 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4420 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4421 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4422 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4423 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4424 .port_set_link = mv88e6xxx_port_set_link, 4425 .port_sync_link = mv88e6xxx_port_sync_link, 4426 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4427 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4428 .port_tag_remap = mv88e6095_port_tag_remap, 4429 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4430 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4431 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4432 .port_set_ether_type = mv88e6351_port_set_ether_type, 4433 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4434 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4435 .port_pause_limit = mv88e6097_port_pause_limit, 4436 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4437 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4438 .port_get_cmode = mv88e6352_port_get_cmode, 4439 .port_setup_message_port = mv88e6xxx_setup_message_port, 4440 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4441 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4442 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4443 .stats_get_strings = mv88e6095_stats_get_strings, 4444 .stats_get_stats = mv88e6095_stats_get_stats, 4445 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4446 .set_egress_port = mv88e6095_g1_set_egress_port, 4447 .watchdog_ops = &mv88e6097_watchdog_ops, 4448 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4449 .pot_clear = mv88e6xxx_g2_pot_clear, 4450 .reset = mv88e6352_g1_reset, 4451 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4452 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4453 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4454 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4455 .stu_getnext = mv88e6352_g1_stu_getnext, 4456 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4457 .phylink_get_caps = mv88e6351_phylink_get_caps, 4458}; 4459 4460static const struct mv88e6xxx_ops mv88e6176_ops = { 4461 /* MV88E6XXX_FAMILY_6352 */ 4462 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4463 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4464 .irl_init_all = mv88e6352_g2_irl_init_all, 4465 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4466 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4468 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4469 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4470 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4471 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4472 .port_set_link = mv88e6xxx_port_set_link, 4473 .port_sync_link = mv88e6xxx_port_sync_link, 4474 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4475 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4476 .port_tag_remap = mv88e6095_port_tag_remap, 4477 .port_set_policy = mv88e6352_port_set_policy, 4478 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4479 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4480 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4481 .port_set_ether_type = mv88e6351_port_set_ether_type, 4482 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4483 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4484 .port_pause_limit = mv88e6097_port_pause_limit, 4485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4487 .port_get_cmode = mv88e6352_port_get_cmode, 4488 .port_setup_message_port = mv88e6xxx_setup_message_port, 4489 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4491 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4492 .stats_get_strings = mv88e6095_stats_get_strings, 4493 .stats_get_stats = mv88e6095_stats_get_stats, 4494 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4495 .set_egress_port = mv88e6095_g1_set_egress_port, 4496 .watchdog_ops = &mv88e6097_watchdog_ops, 4497 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4498 .pot_clear = mv88e6xxx_g2_pot_clear, 4499 .reset = mv88e6352_g1_reset, 4500 .rmu_disable = mv88e6352_g1_rmu_disable, 4501 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4502 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4503 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4504 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4505 .stu_getnext = mv88e6352_g1_stu_getnext, 4506 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4507 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4508 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4509 .serdes_get_regs = mv88e6352_serdes_get_regs, 4510 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4511 .gpio_ops = &mv88e6352_gpio_ops, 4512 .phylink_get_caps = mv88e6352_phylink_get_caps, 4513 .pcs_ops = &mv88e6352_pcs_ops, 4514}; 4515 4516static const struct mv88e6xxx_ops mv88e6185_ops = { 4517 /* MV88E6XXX_FAMILY_6185 */ 4518 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4519 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4520 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4521 .phy_read = mv88e6185_phy_ppu_read, 4522 .phy_write = mv88e6185_phy_ppu_write, 4523 .port_set_link = mv88e6xxx_port_set_link, 4524 .port_sync_link = mv88e6185_port_sync_link, 4525 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4526 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4527 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4528 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4529 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4530 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4531 .port_set_pause = mv88e6185_port_set_pause, 4532 .port_get_cmode = mv88e6185_port_get_cmode, 4533 .port_setup_message_port = mv88e6xxx_setup_message_port, 4534 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4535 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4536 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4537 .stats_get_strings = mv88e6095_stats_get_strings, 4538 .stats_get_stats = mv88e6095_stats_get_stats, 4539 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4540 .set_egress_port = mv88e6095_g1_set_egress_port, 4541 .watchdog_ops = &mv88e6097_watchdog_ops, 4542 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4543 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4544 .ppu_enable = mv88e6185_g1_ppu_enable, 4545 .ppu_disable = mv88e6185_g1_ppu_disable, 4546 .reset = mv88e6185_g1_reset, 4547 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4548 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4549 .phylink_get_caps = mv88e6185_phylink_get_caps, 4550 .pcs_ops = &mv88e6185_pcs_ops, 4551 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4552}; 4553 4554static const struct mv88e6xxx_ops mv88e6190_ops = { 4555 /* MV88E6XXX_FAMILY_6390 */ 4556 .setup_errata = mv88e6390_setup_errata, 4557 .irl_init_all = mv88e6390_g2_irl_init_all, 4558 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4559 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4560 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4561 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4562 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4563 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4564 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4565 .port_set_link = mv88e6xxx_port_set_link, 4566 .port_sync_link = mv88e6xxx_port_sync_link, 4567 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4568 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4569 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4570 .port_tag_remap = mv88e6390_port_tag_remap, 4571 .port_set_policy = mv88e6352_port_set_policy, 4572 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4573 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4574 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4575 .port_set_ether_type = mv88e6351_port_set_ether_type, 4576 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4577 .port_pause_limit = mv88e6390_port_pause_limit, 4578 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4579 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4580 .port_get_cmode = mv88e6352_port_get_cmode, 4581 .port_set_cmode = mv88e6390_port_set_cmode, 4582 .port_setup_message_port = mv88e6xxx_setup_message_port, 4583 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4584 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4585 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4586 .stats_get_strings = mv88e6320_stats_get_strings, 4587 .stats_get_stats = mv88e6390_stats_get_stats, 4588 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4589 .set_egress_port = mv88e6390_g1_set_egress_port, 4590 .watchdog_ops = &mv88e6390_watchdog_ops, 4591 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4592 .pot_clear = mv88e6xxx_g2_pot_clear, 4593 .reset = mv88e6352_g1_reset, 4594 .rmu_disable = mv88e6390_g1_rmu_disable, 4595 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4596 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4597 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4598 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4599 .stu_getnext = mv88e6390_g1_stu_getnext, 4600 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4601 .serdes_get_lane = mv88e6390_serdes_get_lane, 4602 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4603 .serdes_get_strings = mv88e6390_serdes_get_strings, 4604 .serdes_get_stats = mv88e6390_serdes_get_stats, 4605 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4606 .serdes_get_regs = mv88e6390_serdes_get_regs, 4607 .gpio_ops = &mv88e6352_gpio_ops, 4608 .phylink_get_caps = mv88e6390_phylink_get_caps, 4609 .pcs_ops = &mv88e6390_pcs_ops, 4610}; 4611 4612static const struct mv88e6xxx_ops mv88e6190x_ops = { 4613 /* MV88E6XXX_FAMILY_6390 */ 4614 .setup_errata = mv88e6390_setup_errata, 4615 .irl_init_all = mv88e6390_g2_irl_init_all, 4616 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4617 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4619 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4620 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4621 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4622 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4623 .port_set_link = mv88e6xxx_port_set_link, 4624 .port_sync_link = mv88e6xxx_port_sync_link, 4625 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4626 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4627 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4628 .port_tag_remap = mv88e6390_port_tag_remap, 4629 .port_set_policy = mv88e6352_port_set_policy, 4630 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4633 .port_set_ether_type = mv88e6351_port_set_ether_type, 4634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4635 .port_pause_limit = mv88e6390_port_pause_limit, 4636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4638 .port_get_cmode = mv88e6352_port_get_cmode, 4639 .port_set_cmode = mv88e6390x_port_set_cmode, 4640 .port_setup_message_port = mv88e6xxx_setup_message_port, 4641 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4642 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4643 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4644 .stats_get_strings = mv88e6320_stats_get_strings, 4645 .stats_get_stats = mv88e6390_stats_get_stats, 4646 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4647 .set_egress_port = mv88e6390_g1_set_egress_port, 4648 .watchdog_ops = &mv88e6390_watchdog_ops, 4649 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4650 .pot_clear = mv88e6xxx_g2_pot_clear, 4651 .reset = mv88e6352_g1_reset, 4652 .rmu_disable = mv88e6390_g1_rmu_disable, 4653 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4654 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4655 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4656 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4657 .stu_getnext = mv88e6390_g1_stu_getnext, 4658 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4659 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4660 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4661 .serdes_get_strings = mv88e6390_serdes_get_strings, 4662 .serdes_get_stats = mv88e6390_serdes_get_stats, 4663 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4664 .serdes_get_regs = mv88e6390_serdes_get_regs, 4665 .gpio_ops = &mv88e6352_gpio_ops, 4666 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4667 .pcs_ops = &mv88e6390_pcs_ops, 4668}; 4669 4670static const struct mv88e6xxx_ops mv88e6191_ops = { 4671 /* MV88E6XXX_FAMILY_6390 */ 4672 .setup_errata = mv88e6390_setup_errata, 4673 .irl_init_all = mv88e6390_g2_irl_init_all, 4674 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4675 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4676 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4677 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4678 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4679 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4680 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4681 .port_set_link = mv88e6xxx_port_set_link, 4682 .port_sync_link = mv88e6xxx_port_sync_link, 4683 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4684 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4685 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4686 .port_tag_remap = mv88e6390_port_tag_remap, 4687 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4688 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4689 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4690 .port_set_ether_type = mv88e6351_port_set_ether_type, 4691 .port_pause_limit = mv88e6390_port_pause_limit, 4692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4694 .port_get_cmode = mv88e6352_port_get_cmode, 4695 .port_set_cmode = mv88e6390_port_set_cmode, 4696 .port_setup_message_port = mv88e6xxx_setup_message_port, 4697 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4698 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4699 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4700 .stats_get_strings = mv88e6320_stats_get_strings, 4701 .stats_get_stats = mv88e6390_stats_get_stats, 4702 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4703 .set_egress_port = mv88e6390_g1_set_egress_port, 4704 .watchdog_ops = &mv88e6390_watchdog_ops, 4705 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4706 .pot_clear = mv88e6xxx_g2_pot_clear, 4707 .reset = mv88e6352_g1_reset, 4708 .rmu_disable = mv88e6390_g1_rmu_disable, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4713 .stu_getnext = mv88e6390_g1_stu_getnext, 4714 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4715 .serdes_get_lane = mv88e6390_serdes_get_lane, 4716 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4717 .serdes_get_strings = mv88e6390_serdes_get_strings, 4718 .serdes_get_stats = mv88e6390_serdes_get_stats, 4719 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4720 .serdes_get_regs = mv88e6390_serdes_get_regs, 4721 .avb_ops = &mv88e6390_avb_ops, 4722 .ptp_ops = &mv88e6352_ptp_ops, 4723 .phylink_get_caps = mv88e6390_phylink_get_caps, 4724 .pcs_ops = &mv88e6390_pcs_ops, 4725}; 4726 4727static const struct mv88e6xxx_ops mv88e6240_ops = { 4728 /* MV88E6XXX_FAMILY_6352 */ 4729 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4730 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4731 .irl_init_all = mv88e6352_g2_irl_init_all, 4732 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4733 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4734 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4735 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4736 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4737 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4738 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4739 .port_set_link = mv88e6xxx_port_set_link, 4740 .port_sync_link = mv88e6xxx_port_sync_link, 4741 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4742 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4743 .port_tag_remap = mv88e6095_port_tag_remap, 4744 .port_set_policy = mv88e6352_port_set_policy, 4745 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4746 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4747 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4748 .port_set_ether_type = mv88e6351_port_set_ether_type, 4749 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4750 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4751 .port_pause_limit = mv88e6097_port_pause_limit, 4752 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4753 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4754 .port_get_cmode = mv88e6352_port_get_cmode, 4755 .port_setup_message_port = mv88e6xxx_setup_message_port, 4756 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4757 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4758 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4759 .stats_get_strings = mv88e6095_stats_get_strings, 4760 .stats_get_stats = mv88e6095_stats_get_stats, 4761 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4762 .set_egress_port = mv88e6095_g1_set_egress_port, 4763 .watchdog_ops = &mv88e6097_watchdog_ops, 4764 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4765 .pot_clear = mv88e6xxx_g2_pot_clear, 4766 .reset = mv88e6352_g1_reset, 4767 .rmu_disable = mv88e6352_g1_rmu_disable, 4768 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4769 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4770 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4771 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4772 .stu_getnext = mv88e6352_g1_stu_getnext, 4773 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4774 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4775 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4776 .serdes_get_regs = mv88e6352_serdes_get_regs, 4777 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4778 .gpio_ops = &mv88e6352_gpio_ops, 4779 .avb_ops = &mv88e6352_avb_ops, 4780 .ptp_ops = &mv88e6352_ptp_ops, 4781 .phylink_get_caps = mv88e6352_phylink_get_caps, 4782 .pcs_ops = &mv88e6352_pcs_ops, 4783}; 4784 4785static const struct mv88e6xxx_ops mv88e6250_ops = { 4786 /* MV88E6XXX_FAMILY_6250 */ 4787 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4788 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4789 .irl_init_all = mv88e6352_g2_irl_init_all, 4790 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4791 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4792 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4793 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4794 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4795 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4796 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4797 .port_set_link = mv88e6xxx_port_set_link, 4798 .port_sync_link = mv88e6xxx_port_sync_link, 4799 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4800 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4801 .port_tag_remap = mv88e6095_port_tag_remap, 4802 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4803 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4804 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4805 .port_set_ether_type = mv88e6351_port_set_ether_type, 4806 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4807 .port_pause_limit = mv88e6097_port_pause_limit, 4808 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4809 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4810 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4811 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4812 .stats_get_strings = mv88e6250_stats_get_strings, 4813 .stats_get_stats = mv88e6250_stats_get_stats, 4814 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4815 .set_egress_port = mv88e6095_g1_set_egress_port, 4816 .watchdog_ops = &mv88e6250_watchdog_ops, 4817 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4818 .pot_clear = mv88e6xxx_g2_pot_clear, 4819 .reset = mv88e6250_g1_reset, 4820 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4821 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4822 .avb_ops = &mv88e6352_avb_ops, 4823 .ptp_ops = &mv88e6250_ptp_ops, 4824 .phylink_get_caps = mv88e6250_phylink_get_caps, 4825 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4826}; 4827 4828static const struct mv88e6xxx_ops mv88e6290_ops = { 4829 /* MV88E6XXX_FAMILY_6390 */ 4830 .setup_errata = mv88e6390_setup_errata, 4831 .irl_init_all = mv88e6390_g2_irl_init_all, 4832 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4833 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4834 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4835 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4836 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4837 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4838 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4839 .port_set_link = mv88e6xxx_port_set_link, 4840 .port_sync_link = mv88e6xxx_port_sync_link, 4841 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4842 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4843 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4844 .port_tag_remap = mv88e6390_port_tag_remap, 4845 .port_set_policy = mv88e6352_port_set_policy, 4846 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4847 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4848 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4849 .port_set_ether_type = mv88e6351_port_set_ether_type, 4850 .port_pause_limit = mv88e6390_port_pause_limit, 4851 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4852 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4853 .port_get_cmode = mv88e6352_port_get_cmode, 4854 .port_set_cmode = mv88e6390_port_set_cmode, 4855 .port_setup_message_port = mv88e6xxx_setup_message_port, 4856 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4857 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4858 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4859 .stats_get_strings = mv88e6320_stats_get_strings, 4860 .stats_get_stats = mv88e6390_stats_get_stats, 4861 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4862 .set_egress_port = mv88e6390_g1_set_egress_port, 4863 .watchdog_ops = &mv88e6390_watchdog_ops, 4864 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4865 .pot_clear = mv88e6xxx_g2_pot_clear, 4866 .reset = mv88e6352_g1_reset, 4867 .rmu_disable = mv88e6390_g1_rmu_disable, 4868 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4869 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4870 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4871 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4872 .stu_getnext = mv88e6390_g1_stu_getnext, 4873 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4874 .serdes_get_lane = mv88e6390_serdes_get_lane, 4875 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4876 .serdes_get_strings = mv88e6390_serdes_get_strings, 4877 .serdes_get_stats = mv88e6390_serdes_get_stats, 4878 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4879 .serdes_get_regs = mv88e6390_serdes_get_regs, 4880 .gpio_ops = &mv88e6352_gpio_ops, 4881 .avb_ops = &mv88e6390_avb_ops, 4882 .ptp_ops = &mv88e6390_ptp_ops, 4883 .phylink_get_caps = mv88e6390_phylink_get_caps, 4884 .pcs_ops = &mv88e6390_pcs_ops, 4885}; 4886 4887static const struct mv88e6xxx_ops mv88e6320_ops = { 4888 /* MV88E6XXX_FAMILY_6320 */ 4889 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4890 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4891 .irl_init_all = mv88e6352_g2_irl_init_all, 4892 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4893 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4895 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4896 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4897 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4898 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4899 .port_set_link = mv88e6xxx_port_set_link, 4900 .port_sync_link = mv88e6xxx_port_sync_link, 4901 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4902 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4903 .port_tag_remap = mv88e6095_port_tag_remap, 4904 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4905 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4906 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4907 .port_set_ether_type = mv88e6351_port_set_ether_type, 4908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4909 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4910 .port_pause_limit = mv88e6097_port_pause_limit, 4911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4913 .port_get_cmode = mv88e6352_port_get_cmode, 4914 .port_setup_message_port = mv88e6xxx_setup_message_port, 4915 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4916 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4917 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4918 .stats_get_strings = mv88e6320_stats_get_strings, 4919 .stats_get_stats = mv88e6320_stats_get_stats, 4920 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4921 .set_egress_port = mv88e6095_g1_set_egress_port, 4922 .watchdog_ops = &mv88e6390_watchdog_ops, 4923 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4924 .pot_clear = mv88e6xxx_g2_pot_clear, 4925 .reset = mv88e6352_g1_reset, 4926 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4927 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4928 .gpio_ops = &mv88e6352_gpio_ops, 4929 .avb_ops = &mv88e6352_avb_ops, 4930 .ptp_ops = &mv88e6352_ptp_ops, 4931 .phylink_get_caps = mv88e6185_phylink_get_caps, 4932}; 4933 4934static const struct mv88e6xxx_ops mv88e6321_ops = { 4935 /* MV88E6XXX_FAMILY_6320 */ 4936 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4937 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4938 .irl_init_all = mv88e6352_g2_irl_init_all, 4939 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4940 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4941 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4942 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4943 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4944 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4945 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4946 .port_set_link = mv88e6xxx_port_set_link, 4947 .port_sync_link = mv88e6xxx_port_sync_link, 4948 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4949 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4950 .port_tag_remap = mv88e6095_port_tag_remap, 4951 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4952 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4953 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4954 .port_set_ether_type = mv88e6351_port_set_ether_type, 4955 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4956 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4957 .port_pause_limit = mv88e6097_port_pause_limit, 4958 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4959 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4960 .port_get_cmode = mv88e6352_port_get_cmode, 4961 .port_setup_message_port = mv88e6xxx_setup_message_port, 4962 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4963 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4964 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4965 .stats_get_strings = mv88e6320_stats_get_strings, 4966 .stats_get_stats = mv88e6320_stats_get_stats, 4967 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4968 .set_egress_port = mv88e6095_g1_set_egress_port, 4969 .watchdog_ops = &mv88e6390_watchdog_ops, 4970 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4971 .reset = mv88e6352_g1_reset, 4972 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4973 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4974 .gpio_ops = &mv88e6352_gpio_ops, 4975 .avb_ops = &mv88e6352_avb_ops, 4976 .ptp_ops = &mv88e6352_ptp_ops, 4977 .phylink_get_caps = mv88e6185_phylink_get_caps, 4978}; 4979 4980static const struct mv88e6xxx_ops mv88e6341_ops = { 4981 /* MV88E6XXX_FAMILY_6341 */ 4982 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4983 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4984 .irl_init_all = mv88e6352_g2_irl_init_all, 4985 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4986 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4987 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4988 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4989 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4990 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4991 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4992 .port_set_link = mv88e6xxx_port_set_link, 4993 .port_sync_link = mv88e6xxx_port_sync_link, 4994 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4995 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4996 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4997 .port_tag_remap = mv88e6095_port_tag_remap, 4998 .port_set_policy = mv88e6352_port_set_policy, 4999 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5000 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5001 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5002 .port_set_ether_type = mv88e6351_port_set_ether_type, 5003 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5004 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5005 .port_pause_limit = mv88e6097_port_pause_limit, 5006 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5007 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5008 .port_get_cmode = mv88e6352_port_get_cmode, 5009 .port_set_cmode = mv88e6341_port_set_cmode, 5010 .port_setup_message_port = mv88e6xxx_setup_message_port, 5011 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5012 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5013 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5014 .stats_get_strings = mv88e6320_stats_get_strings, 5015 .stats_get_stats = mv88e6390_stats_get_stats, 5016 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5017 .set_egress_port = mv88e6390_g1_set_egress_port, 5018 .watchdog_ops = &mv88e6390_watchdog_ops, 5019 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5020 .pot_clear = mv88e6xxx_g2_pot_clear, 5021 .reset = mv88e6352_g1_reset, 5022 .rmu_disable = mv88e6390_g1_rmu_disable, 5023 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5024 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5025 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5026 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5027 .stu_getnext = mv88e6352_g1_stu_getnext, 5028 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5029 .serdes_get_lane = mv88e6341_serdes_get_lane, 5030 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5031 .gpio_ops = &mv88e6352_gpio_ops, 5032 .avb_ops = &mv88e6390_avb_ops, 5033 .ptp_ops = &mv88e6352_ptp_ops, 5034 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5035 .serdes_get_strings = mv88e6390_serdes_get_strings, 5036 .serdes_get_stats = mv88e6390_serdes_get_stats, 5037 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5038 .serdes_get_regs = mv88e6390_serdes_get_regs, 5039 .phylink_get_caps = mv88e6341_phylink_get_caps, 5040 .pcs_ops = &mv88e6390_pcs_ops, 5041}; 5042 5043static const struct mv88e6xxx_ops mv88e6350_ops = { 5044 /* MV88E6XXX_FAMILY_6351 */ 5045 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5046 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5047 .irl_init_all = mv88e6352_g2_irl_init_all, 5048 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5049 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5050 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5051 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5052 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5053 .port_set_link = mv88e6xxx_port_set_link, 5054 .port_sync_link = mv88e6xxx_port_sync_link, 5055 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5056 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5057 .port_tag_remap = mv88e6095_port_tag_remap, 5058 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5059 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5060 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5061 .port_set_ether_type = mv88e6351_port_set_ether_type, 5062 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5063 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5064 .port_pause_limit = mv88e6097_port_pause_limit, 5065 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5066 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5067 .port_get_cmode = mv88e6352_port_get_cmode, 5068 .port_setup_message_port = mv88e6xxx_setup_message_port, 5069 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5070 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5071 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5072 .stats_get_strings = mv88e6095_stats_get_strings, 5073 .stats_get_stats = mv88e6095_stats_get_stats, 5074 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5075 .set_egress_port = mv88e6095_g1_set_egress_port, 5076 .watchdog_ops = &mv88e6097_watchdog_ops, 5077 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5078 .pot_clear = mv88e6xxx_g2_pot_clear, 5079 .reset = mv88e6352_g1_reset, 5080 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5081 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5082 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5083 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5084 .stu_getnext = mv88e6352_g1_stu_getnext, 5085 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5086 .phylink_get_caps = mv88e6351_phylink_get_caps, 5087}; 5088 5089static const struct mv88e6xxx_ops mv88e6351_ops = { 5090 /* MV88E6XXX_FAMILY_6351 */ 5091 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5092 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5093 .irl_init_all = mv88e6352_g2_irl_init_all, 5094 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5095 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5096 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5097 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5098 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5099 .port_set_link = mv88e6xxx_port_set_link, 5100 .port_sync_link = mv88e6xxx_port_sync_link, 5101 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5102 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5103 .port_tag_remap = mv88e6095_port_tag_remap, 5104 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5105 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5106 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5107 .port_set_ether_type = mv88e6351_port_set_ether_type, 5108 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5109 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5110 .port_pause_limit = mv88e6097_port_pause_limit, 5111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5113 .port_get_cmode = mv88e6352_port_get_cmode, 5114 .port_setup_message_port = mv88e6xxx_setup_message_port, 5115 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5116 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5117 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5118 .stats_get_strings = mv88e6095_stats_get_strings, 5119 .stats_get_stats = mv88e6095_stats_get_stats, 5120 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5121 .set_egress_port = mv88e6095_g1_set_egress_port, 5122 .watchdog_ops = &mv88e6097_watchdog_ops, 5123 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5124 .pot_clear = mv88e6xxx_g2_pot_clear, 5125 .reset = mv88e6352_g1_reset, 5126 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5127 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5128 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5129 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5130 .stu_getnext = mv88e6352_g1_stu_getnext, 5131 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5132 .avb_ops = &mv88e6352_avb_ops, 5133 .ptp_ops = &mv88e6352_ptp_ops, 5134 .phylink_get_caps = mv88e6351_phylink_get_caps, 5135}; 5136 5137static const struct mv88e6xxx_ops mv88e6352_ops = { 5138 /* MV88E6XXX_FAMILY_6352 */ 5139 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5140 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5141 .irl_init_all = mv88e6352_g2_irl_init_all, 5142 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5143 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5145 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5146 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5147 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5148 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5149 .port_set_link = mv88e6xxx_port_set_link, 5150 .port_sync_link = mv88e6xxx_port_sync_link, 5151 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5152 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5153 .port_tag_remap = mv88e6095_port_tag_remap, 5154 .port_set_policy = mv88e6352_port_set_policy, 5155 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5156 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5157 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5158 .port_set_ether_type = mv88e6351_port_set_ether_type, 5159 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5160 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5161 .port_pause_limit = mv88e6097_port_pause_limit, 5162 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5163 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5164 .port_get_cmode = mv88e6352_port_get_cmode, 5165 .port_setup_message_port = mv88e6xxx_setup_message_port, 5166 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5167 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5168 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5169 .stats_get_strings = mv88e6095_stats_get_strings, 5170 .stats_get_stats = mv88e6095_stats_get_stats, 5171 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5172 .set_egress_port = mv88e6095_g1_set_egress_port, 5173 .watchdog_ops = &mv88e6097_watchdog_ops, 5174 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5175 .pot_clear = mv88e6xxx_g2_pot_clear, 5176 .reset = mv88e6352_g1_reset, 5177 .rmu_disable = mv88e6352_g1_rmu_disable, 5178 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5179 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5180 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5181 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5182 .stu_getnext = mv88e6352_g1_stu_getnext, 5183 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5184 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5185 .gpio_ops = &mv88e6352_gpio_ops, 5186 .avb_ops = &mv88e6352_avb_ops, 5187 .ptp_ops = &mv88e6352_ptp_ops, 5188 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5189 .serdes_get_strings = mv88e6352_serdes_get_strings, 5190 .serdes_get_stats = mv88e6352_serdes_get_stats, 5191 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5192 .serdes_get_regs = mv88e6352_serdes_get_regs, 5193 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5194 .phylink_get_caps = mv88e6352_phylink_get_caps, 5195 .pcs_ops = &mv88e6352_pcs_ops, 5196}; 5197 5198static const struct mv88e6xxx_ops mv88e6390_ops = { 5199 /* MV88E6XXX_FAMILY_6390 */ 5200 .setup_errata = mv88e6390_setup_errata, 5201 .irl_init_all = mv88e6390_g2_irl_init_all, 5202 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5203 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5204 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5205 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5206 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5207 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5208 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5209 .port_set_link = mv88e6xxx_port_set_link, 5210 .port_sync_link = mv88e6xxx_port_sync_link, 5211 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5212 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5213 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5214 .port_tag_remap = mv88e6390_port_tag_remap, 5215 .port_set_policy = mv88e6352_port_set_policy, 5216 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5217 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5218 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5219 .port_set_ether_type = mv88e6351_port_set_ether_type, 5220 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5221 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5222 .port_pause_limit = mv88e6390_port_pause_limit, 5223 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5224 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5225 .port_get_cmode = mv88e6352_port_get_cmode, 5226 .port_set_cmode = mv88e6390_port_set_cmode, 5227 .port_setup_message_port = mv88e6xxx_setup_message_port, 5228 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5229 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5230 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5231 .stats_get_strings = mv88e6320_stats_get_strings, 5232 .stats_get_stats = mv88e6390_stats_get_stats, 5233 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5234 .set_egress_port = mv88e6390_g1_set_egress_port, 5235 .watchdog_ops = &mv88e6390_watchdog_ops, 5236 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5237 .pot_clear = mv88e6xxx_g2_pot_clear, 5238 .reset = mv88e6352_g1_reset, 5239 .rmu_disable = mv88e6390_g1_rmu_disable, 5240 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5241 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5242 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5243 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5244 .stu_getnext = mv88e6390_g1_stu_getnext, 5245 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5246 .serdes_get_lane = mv88e6390_serdes_get_lane, 5247 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5248 .gpio_ops = &mv88e6352_gpio_ops, 5249 .avb_ops = &mv88e6390_avb_ops, 5250 .ptp_ops = &mv88e6390_ptp_ops, 5251 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5252 .serdes_get_strings = mv88e6390_serdes_get_strings, 5253 .serdes_get_stats = mv88e6390_serdes_get_stats, 5254 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5255 .serdes_get_regs = mv88e6390_serdes_get_regs, 5256 .phylink_get_caps = mv88e6390_phylink_get_caps, 5257 .pcs_ops = &mv88e6390_pcs_ops, 5258}; 5259 5260static const struct mv88e6xxx_ops mv88e6390x_ops = { 5261 /* MV88E6XXX_FAMILY_6390 */ 5262 .setup_errata = mv88e6390_setup_errata, 5263 .irl_init_all = mv88e6390_g2_irl_init_all, 5264 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5265 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5266 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5267 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5268 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5269 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5270 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5271 .port_set_link = mv88e6xxx_port_set_link, 5272 .port_sync_link = mv88e6xxx_port_sync_link, 5273 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5274 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5275 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5276 .port_tag_remap = mv88e6390_port_tag_remap, 5277 .port_set_policy = mv88e6352_port_set_policy, 5278 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5279 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5280 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5281 .port_set_ether_type = mv88e6351_port_set_ether_type, 5282 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5283 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5284 .port_pause_limit = mv88e6390_port_pause_limit, 5285 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5286 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5287 .port_get_cmode = mv88e6352_port_get_cmode, 5288 .port_set_cmode = mv88e6390x_port_set_cmode, 5289 .port_setup_message_port = mv88e6xxx_setup_message_port, 5290 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5291 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5292 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5293 .stats_get_strings = mv88e6320_stats_get_strings, 5294 .stats_get_stats = mv88e6390_stats_get_stats, 5295 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5296 .set_egress_port = mv88e6390_g1_set_egress_port, 5297 .watchdog_ops = &mv88e6390_watchdog_ops, 5298 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5299 .pot_clear = mv88e6xxx_g2_pot_clear, 5300 .reset = mv88e6352_g1_reset, 5301 .rmu_disable = mv88e6390_g1_rmu_disable, 5302 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5303 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5304 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5305 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5306 .stu_getnext = mv88e6390_g1_stu_getnext, 5307 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5308 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5309 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5310 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5311 .serdes_get_strings = mv88e6390_serdes_get_strings, 5312 .serdes_get_stats = mv88e6390_serdes_get_stats, 5313 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5314 .serdes_get_regs = mv88e6390_serdes_get_regs, 5315 .gpio_ops = &mv88e6352_gpio_ops, 5316 .avb_ops = &mv88e6390_avb_ops, 5317 .ptp_ops = &mv88e6390_ptp_ops, 5318 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5319 .pcs_ops = &mv88e6390_pcs_ops, 5320}; 5321 5322static const struct mv88e6xxx_ops mv88e6393x_ops = { 5323 /* MV88E6XXX_FAMILY_6393 */ 5324 .irl_init_all = mv88e6390_g2_irl_init_all, 5325 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5326 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5327 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5328 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5329 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5330 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5331 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5332 .port_set_link = mv88e6xxx_port_set_link, 5333 .port_sync_link = mv88e6xxx_port_sync_link, 5334 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5335 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5336 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5337 .port_tag_remap = mv88e6390_port_tag_remap, 5338 .port_set_policy = mv88e6393x_port_set_policy, 5339 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5340 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5341 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5342 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5343 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5344 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5345 .port_pause_limit = mv88e6390_port_pause_limit, 5346 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5347 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5348 .port_get_cmode = mv88e6352_port_get_cmode, 5349 .port_set_cmode = mv88e6393x_port_set_cmode, 5350 .port_setup_message_port = mv88e6xxx_setup_message_port, 5351 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5352 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5353 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5354 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5355 .stats_get_strings = mv88e6320_stats_get_strings, 5356 .stats_get_stats = mv88e6390_stats_get_stats, 5357 /* .set_cpu_port is missing because this family does not support a global 5358 * CPU port, only per port CPU port which is set via 5359 * .port_set_upstream_port method. 5360 */ 5361 .set_egress_port = mv88e6393x_set_egress_port, 5362 .watchdog_ops = &mv88e6393x_watchdog_ops, 5363 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5364 .pot_clear = mv88e6xxx_g2_pot_clear, 5365 .reset = mv88e6352_g1_reset, 5366 .rmu_disable = mv88e6390_g1_rmu_disable, 5367 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5368 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5369 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5370 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5371 .stu_getnext = mv88e6390_g1_stu_getnext, 5372 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5373 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5374 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5375 /* TODO: serdes stats */ 5376 .gpio_ops = &mv88e6352_gpio_ops, 5377 .avb_ops = &mv88e6390_avb_ops, 5378 .ptp_ops = &mv88e6352_ptp_ops, 5379 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5380 .pcs_ops = &mv88e6393x_pcs_ops, 5381}; 5382 5383static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5384 [MV88E6020] = { 5385 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5386 .family = MV88E6XXX_FAMILY_6250, 5387 .name = "Marvell 88E6020", 5388 .num_databases = 64, 5389 .num_ports = 4, 5390 .num_internal_phys = 2, 5391 .max_vid = 4095, 5392 .port_base_addr = 0x8, 5393 .phy_base_addr = 0x0, 5394 .global1_addr = 0xf, 5395 .global2_addr = 0x7, 5396 .age_time_coeff = 15000, 5397 .g1_irqs = 9, 5398 .g2_irqs = 5, 5399 .atu_move_port_mask = 0xf, 5400 .dual_chip = true, 5401 .ops = &mv88e6250_ops, 5402 }, 5403 5404 [MV88E6071] = { 5405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5406 .family = MV88E6XXX_FAMILY_6250, 5407 .name = "Marvell 88E6071", 5408 .num_databases = 64, 5409 .num_ports = 7, 5410 .num_internal_phys = 5, 5411 .max_vid = 4095, 5412 .port_base_addr = 0x08, 5413 .phy_base_addr = 0x00, 5414 .global1_addr = 0x0f, 5415 .global2_addr = 0x07, 5416 .age_time_coeff = 15000, 5417 .g1_irqs = 9, 5418 .g2_irqs = 5, 5419 .atu_move_port_mask = 0xf, 5420 .dual_chip = true, 5421 .ops = &mv88e6250_ops, 5422 }, 5423 5424 [MV88E6085] = { 5425 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5426 .family = MV88E6XXX_FAMILY_6097, 5427 .name = "Marvell 88E6085", 5428 .num_databases = 4096, 5429 .num_macs = 8192, 5430 .num_ports = 10, 5431 .num_internal_phys = 5, 5432 .max_vid = 4095, 5433 .max_sid = 63, 5434 .port_base_addr = 0x10, 5435 .phy_base_addr = 0x0, 5436 .global1_addr = 0x1b, 5437 .global2_addr = 0x1c, 5438 .age_time_coeff = 15000, 5439 .g1_irqs = 8, 5440 .g2_irqs = 10, 5441 .atu_move_port_mask = 0xf, 5442 .pvt = true, 5443 .multi_chip = true, 5444 .ops = &mv88e6085_ops, 5445 }, 5446 5447 [MV88E6095] = { 5448 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5449 .family = MV88E6XXX_FAMILY_6095, 5450 .name = "Marvell 88E6095/88E6095F", 5451 .num_databases = 256, 5452 .num_macs = 8192, 5453 .num_ports = 11, 5454 .num_internal_phys = 0, 5455 .max_vid = 4095, 5456 .port_base_addr = 0x10, 5457 .phy_base_addr = 0x0, 5458 .global1_addr = 0x1b, 5459 .global2_addr = 0x1c, 5460 .age_time_coeff = 15000, 5461 .g1_irqs = 8, 5462 .atu_move_port_mask = 0xf, 5463 .multi_chip = true, 5464 .ops = &mv88e6095_ops, 5465 }, 5466 5467 [MV88E6097] = { 5468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5469 .family = MV88E6XXX_FAMILY_6097, 5470 .name = "Marvell 88E6097/88E6097F", 5471 .num_databases = 4096, 5472 .num_macs = 8192, 5473 .num_ports = 11, 5474 .num_internal_phys = 8, 5475 .max_vid = 4095, 5476 .max_sid = 63, 5477 .port_base_addr = 0x10, 5478 .phy_base_addr = 0x0, 5479 .global1_addr = 0x1b, 5480 .global2_addr = 0x1c, 5481 .age_time_coeff = 15000, 5482 .g1_irqs = 8, 5483 .g2_irqs = 10, 5484 .atu_move_port_mask = 0xf, 5485 .pvt = true, 5486 .multi_chip = true, 5487 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5488 .ops = &mv88e6097_ops, 5489 }, 5490 5491 [MV88E6123] = { 5492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5493 .family = MV88E6XXX_FAMILY_6165, 5494 .name = "Marvell 88E6123", 5495 .num_databases = 4096, 5496 .num_macs = 1024, 5497 .num_ports = 3, 5498 .num_internal_phys = 5, 5499 .max_vid = 4095, 5500 .max_sid = 63, 5501 .port_base_addr = 0x10, 5502 .phy_base_addr = 0x0, 5503 .global1_addr = 0x1b, 5504 .global2_addr = 0x1c, 5505 .age_time_coeff = 15000, 5506 .g1_irqs = 9, 5507 .g2_irqs = 10, 5508 .atu_move_port_mask = 0xf, 5509 .pvt = true, 5510 .multi_chip = true, 5511 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5512 .ops = &mv88e6123_ops, 5513 }, 5514 5515 [MV88E6131] = { 5516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5517 .family = MV88E6XXX_FAMILY_6185, 5518 .name = "Marvell 88E6131", 5519 .num_databases = 256, 5520 .num_macs = 8192, 5521 .num_ports = 8, 5522 .num_internal_phys = 0, 5523 .max_vid = 4095, 5524 .port_base_addr = 0x10, 5525 .phy_base_addr = 0x0, 5526 .global1_addr = 0x1b, 5527 .global2_addr = 0x1c, 5528 .age_time_coeff = 15000, 5529 .g1_irqs = 9, 5530 .atu_move_port_mask = 0xf, 5531 .multi_chip = true, 5532 .ops = &mv88e6131_ops, 5533 }, 5534 5535 [MV88E6141] = { 5536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5537 .family = MV88E6XXX_FAMILY_6341, 5538 .name = "Marvell 88E6141", 5539 .num_databases = 4096, 5540 .num_macs = 2048, 5541 .num_ports = 6, 5542 .num_internal_phys = 5, 5543 .num_gpio = 11, 5544 .max_vid = 4095, 5545 .max_sid = 63, 5546 .port_base_addr = 0x10, 5547 .phy_base_addr = 0x10, 5548 .global1_addr = 0x1b, 5549 .global2_addr = 0x1c, 5550 .age_time_coeff = 3750, 5551 .atu_move_port_mask = 0x1f, 5552 .g1_irqs = 9, 5553 .g2_irqs = 10, 5554 .pvt = true, 5555 .multi_chip = true, 5556 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5557 .ops = &mv88e6141_ops, 5558 }, 5559 5560 [MV88E6161] = { 5561 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5562 .family = MV88E6XXX_FAMILY_6165, 5563 .name = "Marvell 88E6161", 5564 .num_databases = 4096, 5565 .num_macs = 1024, 5566 .num_ports = 6, 5567 .num_internal_phys = 5, 5568 .max_vid = 4095, 5569 .max_sid = 63, 5570 .port_base_addr = 0x10, 5571 .phy_base_addr = 0x0, 5572 .global1_addr = 0x1b, 5573 .global2_addr = 0x1c, 5574 .age_time_coeff = 15000, 5575 .g1_irqs = 9, 5576 .g2_irqs = 10, 5577 .atu_move_port_mask = 0xf, 5578 .pvt = true, 5579 .multi_chip = true, 5580 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5581 .ptp_support = true, 5582 .ops = &mv88e6161_ops, 5583 }, 5584 5585 [MV88E6165] = { 5586 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5587 .family = MV88E6XXX_FAMILY_6165, 5588 .name = "Marvell 88E6165", 5589 .num_databases = 4096, 5590 .num_macs = 8192, 5591 .num_ports = 6, 5592 .num_internal_phys = 0, 5593 .max_vid = 4095, 5594 .max_sid = 63, 5595 .port_base_addr = 0x10, 5596 .phy_base_addr = 0x0, 5597 .global1_addr = 0x1b, 5598 .global2_addr = 0x1c, 5599 .age_time_coeff = 15000, 5600 .g1_irqs = 9, 5601 .g2_irqs = 10, 5602 .atu_move_port_mask = 0xf, 5603 .pvt = true, 5604 .multi_chip = true, 5605 .ptp_support = true, 5606 .ops = &mv88e6165_ops, 5607 }, 5608 5609 [MV88E6171] = { 5610 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5611 .family = MV88E6XXX_FAMILY_6351, 5612 .name = "Marvell 88E6171", 5613 .num_databases = 4096, 5614 .num_macs = 8192, 5615 .num_ports = 7, 5616 .num_internal_phys = 5, 5617 .max_vid = 4095, 5618 .max_sid = 63, 5619 .port_base_addr = 0x10, 5620 .phy_base_addr = 0x0, 5621 .global1_addr = 0x1b, 5622 .global2_addr = 0x1c, 5623 .age_time_coeff = 15000, 5624 .g1_irqs = 9, 5625 .g2_irqs = 10, 5626 .atu_move_port_mask = 0xf, 5627 .pvt = true, 5628 .multi_chip = true, 5629 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5630 .ops = &mv88e6171_ops, 5631 }, 5632 5633 [MV88E6172] = { 5634 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5635 .family = MV88E6XXX_FAMILY_6352, 5636 .name = "Marvell 88E6172", 5637 .num_databases = 4096, 5638 .num_macs = 8192, 5639 .num_ports = 7, 5640 .num_internal_phys = 5, 5641 .num_gpio = 15, 5642 .max_vid = 4095, 5643 .max_sid = 63, 5644 .port_base_addr = 0x10, 5645 .phy_base_addr = 0x0, 5646 .global1_addr = 0x1b, 5647 .global2_addr = 0x1c, 5648 .age_time_coeff = 15000, 5649 .g1_irqs = 9, 5650 .g2_irqs = 10, 5651 .atu_move_port_mask = 0xf, 5652 .pvt = true, 5653 .multi_chip = true, 5654 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5655 .ops = &mv88e6172_ops, 5656 }, 5657 5658 [MV88E6175] = { 5659 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5660 .family = MV88E6XXX_FAMILY_6351, 5661 .name = "Marvell 88E6175", 5662 .num_databases = 4096, 5663 .num_macs = 8192, 5664 .num_ports = 7, 5665 .num_internal_phys = 5, 5666 .max_vid = 4095, 5667 .max_sid = 63, 5668 .port_base_addr = 0x10, 5669 .phy_base_addr = 0x0, 5670 .global1_addr = 0x1b, 5671 .global2_addr = 0x1c, 5672 .age_time_coeff = 15000, 5673 .g1_irqs = 9, 5674 .g2_irqs = 10, 5675 .atu_move_port_mask = 0xf, 5676 .pvt = true, 5677 .multi_chip = true, 5678 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5679 .ops = &mv88e6175_ops, 5680 }, 5681 5682 [MV88E6176] = { 5683 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5684 .family = MV88E6XXX_FAMILY_6352, 5685 .name = "Marvell 88E6176", 5686 .num_databases = 4096, 5687 .num_macs = 8192, 5688 .num_ports = 7, 5689 .num_internal_phys = 5, 5690 .num_gpio = 15, 5691 .max_vid = 4095, 5692 .max_sid = 63, 5693 .port_base_addr = 0x10, 5694 .phy_base_addr = 0x0, 5695 .global1_addr = 0x1b, 5696 .global2_addr = 0x1c, 5697 .age_time_coeff = 15000, 5698 .g1_irqs = 9, 5699 .g2_irqs = 10, 5700 .atu_move_port_mask = 0xf, 5701 .pvt = true, 5702 .multi_chip = true, 5703 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5704 .ops = &mv88e6176_ops, 5705 }, 5706 5707 [MV88E6185] = { 5708 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5709 .family = MV88E6XXX_FAMILY_6185, 5710 .name = "Marvell 88E6185", 5711 .num_databases = 256, 5712 .num_macs = 8192, 5713 .num_ports = 10, 5714 .num_internal_phys = 0, 5715 .max_vid = 4095, 5716 .port_base_addr = 0x10, 5717 .phy_base_addr = 0x0, 5718 .global1_addr = 0x1b, 5719 .global2_addr = 0x1c, 5720 .age_time_coeff = 15000, 5721 .g1_irqs = 8, 5722 .atu_move_port_mask = 0xf, 5723 .multi_chip = true, 5724 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5725 .ops = &mv88e6185_ops, 5726 }, 5727 5728 [MV88E6190] = { 5729 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5730 .family = MV88E6XXX_FAMILY_6390, 5731 .name = "Marvell 88E6190", 5732 .num_databases = 4096, 5733 .num_macs = 16384, 5734 .num_ports = 11, /* 10 + Z80 */ 5735 .num_internal_phys = 9, 5736 .num_gpio = 16, 5737 .max_vid = 8191, 5738 .max_sid = 63, 5739 .port_base_addr = 0x0, 5740 .phy_base_addr = 0x0, 5741 .global1_addr = 0x1b, 5742 .global2_addr = 0x1c, 5743 .age_time_coeff = 3750, 5744 .g1_irqs = 9, 5745 .g2_irqs = 14, 5746 .pvt = true, 5747 .multi_chip = true, 5748 .atu_move_port_mask = 0x1f, 5749 .ops = &mv88e6190_ops, 5750 }, 5751 5752 [MV88E6190X] = { 5753 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5754 .family = MV88E6XXX_FAMILY_6390, 5755 .name = "Marvell 88E6190X", 5756 .num_databases = 4096, 5757 .num_macs = 16384, 5758 .num_ports = 11, /* 10 + Z80 */ 5759 .num_internal_phys = 9, 5760 .num_gpio = 16, 5761 .max_vid = 8191, 5762 .max_sid = 63, 5763 .port_base_addr = 0x0, 5764 .phy_base_addr = 0x0, 5765 .global1_addr = 0x1b, 5766 .global2_addr = 0x1c, 5767 .age_time_coeff = 3750, 5768 .g1_irqs = 9, 5769 .g2_irqs = 14, 5770 .atu_move_port_mask = 0x1f, 5771 .pvt = true, 5772 .multi_chip = true, 5773 .ops = &mv88e6190x_ops, 5774 }, 5775 5776 [MV88E6191] = { 5777 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5778 .family = MV88E6XXX_FAMILY_6390, 5779 .name = "Marvell 88E6191", 5780 .num_databases = 4096, 5781 .num_macs = 16384, 5782 .num_ports = 11, /* 10 + Z80 */ 5783 .num_internal_phys = 9, 5784 .max_vid = 8191, 5785 .max_sid = 63, 5786 .port_base_addr = 0x0, 5787 .phy_base_addr = 0x0, 5788 .global1_addr = 0x1b, 5789 .global2_addr = 0x1c, 5790 .age_time_coeff = 3750, 5791 .g1_irqs = 9, 5792 .g2_irqs = 14, 5793 .atu_move_port_mask = 0x1f, 5794 .pvt = true, 5795 .multi_chip = true, 5796 .ptp_support = true, 5797 .ops = &mv88e6191_ops, 5798 }, 5799 5800 [MV88E6191X] = { 5801 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5802 .family = MV88E6XXX_FAMILY_6393, 5803 .name = "Marvell 88E6191X", 5804 .num_databases = 4096, 5805 .num_ports = 11, /* 10 + Z80 */ 5806 .num_internal_phys = 8, 5807 .internal_phys_offset = 1, 5808 .max_vid = 8191, 5809 .max_sid = 63, 5810 .port_base_addr = 0x0, 5811 .phy_base_addr = 0x0, 5812 .global1_addr = 0x1b, 5813 .global2_addr = 0x1c, 5814 .age_time_coeff = 3750, 5815 .g1_irqs = 10, 5816 .g2_irqs = 14, 5817 .atu_move_port_mask = 0x1f, 5818 .pvt = true, 5819 .multi_chip = true, 5820 .ptp_support = true, 5821 .ops = &mv88e6393x_ops, 5822 }, 5823 5824 [MV88E6193X] = { 5825 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5826 .family = MV88E6XXX_FAMILY_6393, 5827 .name = "Marvell 88E6193X", 5828 .num_databases = 4096, 5829 .num_ports = 11, /* 10 + Z80 */ 5830 .num_internal_phys = 8, 5831 .internal_phys_offset = 1, 5832 .max_vid = 8191, 5833 .max_sid = 63, 5834 .port_base_addr = 0x0, 5835 .phy_base_addr = 0x0, 5836 .global1_addr = 0x1b, 5837 .global2_addr = 0x1c, 5838 .age_time_coeff = 3750, 5839 .g1_irqs = 10, 5840 .g2_irqs = 14, 5841 .atu_move_port_mask = 0x1f, 5842 .pvt = true, 5843 .multi_chip = true, 5844 .ptp_support = true, 5845 .ops = &mv88e6393x_ops, 5846 }, 5847 5848 [MV88E6220] = { 5849 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5850 .family = MV88E6XXX_FAMILY_6250, 5851 .name = "Marvell 88E6220", 5852 .num_databases = 64, 5853 5854 /* Ports 2-4 are not routed to pins 5855 * => usable ports 0, 1, 5, 6 5856 */ 5857 .num_ports = 7, 5858 .num_internal_phys = 2, 5859 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5860 .max_vid = 4095, 5861 .port_base_addr = 0x08, 5862 .phy_base_addr = 0x00, 5863 .global1_addr = 0x0f, 5864 .global2_addr = 0x07, 5865 .age_time_coeff = 15000, 5866 .g1_irqs = 9, 5867 .g2_irqs = 10, 5868 .atu_move_port_mask = 0xf, 5869 .dual_chip = true, 5870 .ptp_support = true, 5871 .ops = &mv88e6250_ops, 5872 }, 5873 5874 [MV88E6240] = { 5875 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5876 .family = MV88E6XXX_FAMILY_6352, 5877 .name = "Marvell 88E6240", 5878 .num_databases = 4096, 5879 .num_macs = 8192, 5880 .num_ports = 7, 5881 .num_internal_phys = 5, 5882 .num_gpio = 15, 5883 .max_vid = 4095, 5884 .max_sid = 63, 5885 .port_base_addr = 0x10, 5886 .phy_base_addr = 0x0, 5887 .global1_addr = 0x1b, 5888 .global2_addr = 0x1c, 5889 .age_time_coeff = 15000, 5890 .g1_irqs = 9, 5891 .g2_irqs = 10, 5892 .atu_move_port_mask = 0xf, 5893 .pvt = true, 5894 .multi_chip = true, 5895 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5896 .ptp_support = true, 5897 .ops = &mv88e6240_ops, 5898 }, 5899 5900 [MV88E6250] = { 5901 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5902 .family = MV88E6XXX_FAMILY_6250, 5903 .name = "Marvell 88E6250", 5904 .num_databases = 64, 5905 .num_ports = 7, 5906 .num_internal_phys = 5, 5907 .max_vid = 4095, 5908 .port_base_addr = 0x08, 5909 .phy_base_addr = 0x00, 5910 .global1_addr = 0x0f, 5911 .global2_addr = 0x07, 5912 .age_time_coeff = 15000, 5913 .g1_irqs = 9, 5914 .g2_irqs = 10, 5915 .atu_move_port_mask = 0xf, 5916 .dual_chip = true, 5917 .ptp_support = true, 5918 .ops = &mv88e6250_ops, 5919 }, 5920 5921 [MV88E6290] = { 5922 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5923 .family = MV88E6XXX_FAMILY_6390, 5924 .name = "Marvell 88E6290", 5925 .num_databases = 4096, 5926 .num_ports = 11, /* 10 + Z80 */ 5927 .num_internal_phys = 9, 5928 .num_gpio = 16, 5929 .max_vid = 8191, 5930 .max_sid = 63, 5931 .port_base_addr = 0x0, 5932 .phy_base_addr = 0x0, 5933 .global1_addr = 0x1b, 5934 .global2_addr = 0x1c, 5935 .age_time_coeff = 3750, 5936 .g1_irqs = 9, 5937 .g2_irqs = 14, 5938 .atu_move_port_mask = 0x1f, 5939 .pvt = true, 5940 .multi_chip = true, 5941 .ptp_support = true, 5942 .ops = &mv88e6290_ops, 5943 }, 5944 5945 [MV88E6320] = { 5946 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5947 .family = MV88E6XXX_FAMILY_6320, 5948 .name = "Marvell 88E6320", 5949 .num_databases = 4096, 5950 .num_macs = 8192, 5951 .num_ports = 7, 5952 .num_internal_phys = 5, 5953 .num_gpio = 15, 5954 .max_vid = 4095, 5955 .port_base_addr = 0x10, 5956 .phy_base_addr = 0x0, 5957 .global1_addr = 0x1b, 5958 .global2_addr = 0x1c, 5959 .age_time_coeff = 15000, 5960 .g1_irqs = 8, 5961 .g2_irqs = 10, 5962 .atu_move_port_mask = 0xf, 5963 .pvt = true, 5964 .multi_chip = true, 5965 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5966 .ptp_support = true, 5967 .ops = &mv88e6320_ops, 5968 }, 5969 5970 [MV88E6321] = { 5971 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5972 .family = MV88E6XXX_FAMILY_6320, 5973 .name = "Marvell 88E6321", 5974 .num_databases = 4096, 5975 .num_macs = 8192, 5976 .num_ports = 7, 5977 .num_internal_phys = 5, 5978 .num_gpio = 15, 5979 .max_vid = 4095, 5980 .port_base_addr = 0x10, 5981 .phy_base_addr = 0x0, 5982 .global1_addr = 0x1b, 5983 .global2_addr = 0x1c, 5984 .age_time_coeff = 15000, 5985 .g1_irqs = 8, 5986 .g2_irqs = 10, 5987 .atu_move_port_mask = 0xf, 5988 .multi_chip = true, 5989 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5990 .ptp_support = true, 5991 .ops = &mv88e6321_ops, 5992 }, 5993 5994 [MV88E6341] = { 5995 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5996 .family = MV88E6XXX_FAMILY_6341, 5997 .name = "Marvell 88E6341", 5998 .num_databases = 4096, 5999 .num_macs = 2048, 6000 .num_internal_phys = 5, 6001 .num_ports = 6, 6002 .num_gpio = 11, 6003 .max_vid = 4095, 6004 .max_sid = 63, 6005 .port_base_addr = 0x10, 6006 .phy_base_addr = 0x10, 6007 .global1_addr = 0x1b, 6008 .global2_addr = 0x1c, 6009 .age_time_coeff = 3750, 6010 .atu_move_port_mask = 0x1f, 6011 .g1_irqs = 9, 6012 .g2_irqs = 10, 6013 .pvt = true, 6014 .multi_chip = true, 6015 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6016 .ptp_support = true, 6017 .ops = &mv88e6341_ops, 6018 }, 6019 6020 [MV88E6350] = { 6021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6022 .family = MV88E6XXX_FAMILY_6351, 6023 .name = "Marvell 88E6350", 6024 .num_databases = 4096, 6025 .num_macs = 8192, 6026 .num_ports = 7, 6027 .num_internal_phys = 5, 6028 .max_vid = 4095, 6029 .max_sid = 63, 6030 .port_base_addr = 0x10, 6031 .phy_base_addr = 0x0, 6032 .global1_addr = 0x1b, 6033 .global2_addr = 0x1c, 6034 .age_time_coeff = 15000, 6035 .g1_irqs = 9, 6036 .g2_irqs = 10, 6037 .atu_move_port_mask = 0xf, 6038 .pvt = true, 6039 .multi_chip = true, 6040 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6041 .ops = &mv88e6350_ops, 6042 }, 6043 6044 [MV88E6351] = { 6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6046 .family = MV88E6XXX_FAMILY_6351, 6047 .name = "Marvell 88E6351", 6048 .num_databases = 4096, 6049 .num_macs = 8192, 6050 .num_ports = 7, 6051 .num_internal_phys = 5, 6052 .max_vid = 4095, 6053 .max_sid = 63, 6054 .port_base_addr = 0x10, 6055 .phy_base_addr = 0x0, 6056 .global1_addr = 0x1b, 6057 .global2_addr = 0x1c, 6058 .age_time_coeff = 15000, 6059 .g1_irqs = 9, 6060 .g2_irqs = 10, 6061 .atu_move_port_mask = 0xf, 6062 .pvt = true, 6063 .multi_chip = true, 6064 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6065 .ops = &mv88e6351_ops, 6066 }, 6067 6068 [MV88E6352] = { 6069 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6070 .family = MV88E6XXX_FAMILY_6352, 6071 .name = "Marvell 88E6352", 6072 .num_databases = 4096, 6073 .num_macs = 8192, 6074 .num_ports = 7, 6075 .num_internal_phys = 5, 6076 .num_gpio = 15, 6077 .max_vid = 4095, 6078 .max_sid = 63, 6079 .port_base_addr = 0x10, 6080 .phy_base_addr = 0x0, 6081 .global1_addr = 0x1b, 6082 .global2_addr = 0x1c, 6083 .age_time_coeff = 15000, 6084 .g1_irqs = 9, 6085 .g2_irqs = 10, 6086 .atu_move_port_mask = 0xf, 6087 .pvt = true, 6088 .multi_chip = true, 6089 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6090 .ptp_support = true, 6091 .ops = &mv88e6352_ops, 6092 }, 6093 [MV88E6361] = { 6094 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6095 .family = MV88E6XXX_FAMILY_6393, 6096 .name = "Marvell 88E6361", 6097 .num_databases = 4096, 6098 .num_macs = 16384, 6099 .num_ports = 11, 6100 /* Ports 1, 2 and 8 are not routed */ 6101 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6102 .num_internal_phys = 5, 6103 .internal_phys_offset = 3, 6104 .max_vid = 4095, 6105 .max_sid = 63, 6106 .port_base_addr = 0x0, 6107 .phy_base_addr = 0x0, 6108 .global1_addr = 0x1b, 6109 .global2_addr = 0x1c, 6110 .age_time_coeff = 3750, 6111 .g1_irqs = 10, 6112 .g2_irqs = 14, 6113 .atu_move_port_mask = 0x1f, 6114 .pvt = true, 6115 .multi_chip = true, 6116 .ptp_support = true, 6117 .ops = &mv88e6393x_ops, 6118 }, 6119 [MV88E6390] = { 6120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6121 .family = MV88E6XXX_FAMILY_6390, 6122 .name = "Marvell 88E6390", 6123 .num_databases = 4096, 6124 .num_macs = 16384, 6125 .num_ports = 11, /* 10 + Z80 */ 6126 .num_internal_phys = 9, 6127 .num_gpio = 16, 6128 .max_vid = 8191, 6129 .max_sid = 63, 6130 .port_base_addr = 0x0, 6131 .phy_base_addr = 0x0, 6132 .global1_addr = 0x1b, 6133 .global2_addr = 0x1c, 6134 .age_time_coeff = 3750, 6135 .g1_irqs = 9, 6136 .g2_irqs = 14, 6137 .atu_move_port_mask = 0x1f, 6138 .pvt = true, 6139 .multi_chip = true, 6140 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6141 .ptp_support = true, 6142 .ops = &mv88e6390_ops, 6143 }, 6144 [MV88E6390X] = { 6145 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6146 .family = MV88E6XXX_FAMILY_6390, 6147 .name = "Marvell 88E6390X", 6148 .num_databases = 4096, 6149 .num_macs = 16384, 6150 .num_ports = 11, /* 10 + Z80 */ 6151 .num_internal_phys = 9, 6152 .num_gpio = 16, 6153 .max_vid = 8191, 6154 .max_sid = 63, 6155 .port_base_addr = 0x0, 6156 .phy_base_addr = 0x0, 6157 .global1_addr = 0x1b, 6158 .global2_addr = 0x1c, 6159 .age_time_coeff = 3750, 6160 .g1_irqs = 9, 6161 .g2_irqs = 14, 6162 .atu_move_port_mask = 0x1f, 6163 .pvt = true, 6164 .multi_chip = true, 6165 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6166 .ptp_support = true, 6167 .ops = &mv88e6390x_ops, 6168 }, 6169 6170 [MV88E6393X] = { 6171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6172 .family = MV88E6XXX_FAMILY_6393, 6173 .name = "Marvell 88E6393X", 6174 .num_databases = 4096, 6175 .num_ports = 11, /* 10 + Z80 */ 6176 .num_internal_phys = 8, 6177 .internal_phys_offset = 1, 6178 .max_vid = 8191, 6179 .max_sid = 63, 6180 .port_base_addr = 0x0, 6181 .phy_base_addr = 0x0, 6182 .global1_addr = 0x1b, 6183 .global2_addr = 0x1c, 6184 .age_time_coeff = 3750, 6185 .g1_irqs = 10, 6186 .g2_irqs = 14, 6187 .atu_move_port_mask = 0x1f, 6188 .pvt = true, 6189 .multi_chip = true, 6190 .ptp_support = true, 6191 .ops = &mv88e6393x_ops, 6192 }, 6193}; 6194 6195static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6196{ 6197 int i; 6198 6199 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6200 if (mv88e6xxx_table[i].prod_num == prod_num) 6201 return &mv88e6xxx_table[i]; 6202 6203 return NULL; 6204} 6205 6206static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6207{ 6208 const struct mv88e6xxx_info *info; 6209 unsigned int prod_num, rev; 6210 u16 id; 6211 int err; 6212 6213 mv88e6xxx_reg_lock(chip); 6214 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6215 mv88e6xxx_reg_unlock(chip); 6216 if (err) 6217 return err; 6218 6219 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6220 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6221 6222 info = mv88e6xxx_lookup_info(prod_num); 6223 if (!info) 6224 return -ENODEV; 6225 6226 /* Update the compatible info with the probed one */ 6227 chip->info = info; 6228 6229 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6230 chip->info->prod_num, chip->info->name, rev); 6231 6232 return 0; 6233} 6234 6235static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6236 struct mdio_device *mdiodev) 6237{ 6238 int err; 6239 6240 /* dual_chip takes precedence over single/multi-chip modes */ 6241 if (chip->info->dual_chip) 6242 return -EINVAL; 6243 6244 /* If the mdio addr is 16 indicating the first port address of a switch 6245 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6246 * configured in single chip addressing mode. Setup the smi access as 6247 * single chip addressing mode and attempt to detect the model of the 6248 * switch, if this fails the device is not configured in single chip 6249 * addressing mode. 6250 */ 6251 if (mdiodev->addr != 16) 6252 return -EINVAL; 6253 6254 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6255 if (err) 6256 return err; 6257 6258 return mv88e6xxx_detect(chip); 6259} 6260 6261static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6262{ 6263 struct mv88e6xxx_chip *chip; 6264 6265 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6266 if (!chip) 6267 return NULL; 6268 6269 chip->dev = dev; 6270 6271 mutex_init(&chip->reg_lock); 6272 INIT_LIST_HEAD(&chip->mdios); 6273 idr_init(&chip->policies); 6274 INIT_LIST_HEAD(&chip->msts); 6275 6276 return chip; 6277} 6278 6279static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6280 int port, 6281 enum dsa_tag_protocol m) 6282{ 6283 struct mv88e6xxx_chip *chip = ds->priv; 6284 6285 return chip->tag_protocol; 6286} 6287 6288static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6289 enum dsa_tag_protocol proto) 6290{ 6291 struct mv88e6xxx_chip *chip = ds->priv; 6292 enum dsa_tag_protocol old_protocol; 6293 struct dsa_port *cpu_dp; 6294 int err; 6295 6296 switch (proto) { 6297 case DSA_TAG_PROTO_EDSA: 6298 switch (chip->info->edsa_support) { 6299 case MV88E6XXX_EDSA_UNSUPPORTED: 6300 return -EPROTONOSUPPORT; 6301 case MV88E6XXX_EDSA_UNDOCUMENTED: 6302 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6303 fallthrough; 6304 case MV88E6XXX_EDSA_SUPPORTED: 6305 break; 6306 } 6307 break; 6308 case DSA_TAG_PROTO_DSA: 6309 break; 6310 default: 6311 return -EPROTONOSUPPORT; 6312 } 6313 6314 old_protocol = chip->tag_protocol; 6315 chip->tag_protocol = proto; 6316 6317 mv88e6xxx_reg_lock(chip); 6318 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6319 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6320 if (err) { 6321 mv88e6xxx_reg_unlock(chip); 6322 goto unwind; 6323 } 6324 } 6325 mv88e6xxx_reg_unlock(chip); 6326 6327 return 0; 6328 6329unwind: 6330 chip->tag_protocol = old_protocol; 6331 6332 mv88e6xxx_reg_lock(chip); 6333 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6334 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6335 mv88e6xxx_reg_unlock(chip); 6336 6337 return err; 6338} 6339 6340static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6341 const struct switchdev_obj_port_mdb *mdb, 6342 struct dsa_db db) 6343{ 6344 struct mv88e6xxx_chip *chip = ds->priv; 6345 int err; 6346 6347 mv88e6xxx_reg_lock(chip); 6348 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6349 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6350 mv88e6xxx_reg_unlock(chip); 6351 6352 return err; 6353} 6354 6355static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6356 const struct switchdev_obj_port_mdb *mdb, 6357 struct dsa_db db) 6358{ 6359 struct mv88e6xxx_chip *chip = ds->priv; 6360 int err; 6361 6362 mv88e6xxx_reg_lock(chip); 6363 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6364 mv88e6xxx_reg_unlock(chip); 6365 6366 return err; 6367} 6368 6369static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6370 struct dsa_mall_mirror_tc_entry *mirror, 6371 bool ingress, 6372 struct netlink_ext_ack *extack) 6373{ 6374 enum mv88e6xxx_egress_direction direction = ingress ? 6375 MV88E6XXX_EGRESS_DIR_INGRESS : 6376 MV88E6XXX_EGRESS_DIR_EGRESS; 6377 struct mv88e6xxx_chip *chip = ds->priv; 6378 bool other_mirrors = false; 6379 int i; 6380 int err; 6381 6382 mutex_lock(&chip->reg_lock); 6383 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6384 mirror->to_local_port) { 6385 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6386 other_mirrors |= ingress ? 6387 chip->ports[i].mirror_ingress : 6388 chip->ports[i].mirror_egress; 6389 6390 /* Can't change egress port when other mirror is active */ 6391 if (other_mirrors) { 6392 err = -EBUSY; 6393 goto out; 6394 } 6395 6396 err = mv88e6xxx_set_egress_port(chip, direction, 6397 mirror->to_local_port); 6398 if (err) 6399 goto out; 6400 } 6401 6402 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6403out: 6404 mutex_unlock(&chip->reg_lock); 6405 6406 return err; 6407} 6408 6409static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6410 struct dsa_mall_mirror_tc_entry *mirror) 6411{ 6412 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6413 MV88E6XXX_EGRESS_DIR_INGRESS : 6414 MV88E6XXX_EGRESS_DIR_EGRESS; 6415 struct mv88e6xxx_chip *chip = ds->priv; 6416 bool other_mirrors = false; 6417 int i; 6418 6419 mutex_lock(&chip->reg_lock); 6420 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6421 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6422 6423 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6424 other_mirrors |= mirror->ingress ? 6425 chip->ports[i].mirror_ingress : 6426 chip->ports[i].mirror_egress; 6427 6428 /* Reset egress port when no other mirror is active */ 6429 if (!other_mirrors) { 6430 if (mv88e6xxx_set_egress_port(chip, direction, 6431 dsa_upstream_port(ds, port))) 6432 dev_err(ds->dev, "failed to set egress port\n"); 6433 } 6434 6435 mutex_unlock(&chip->reg_lock); 6436} 6437 6438static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6439 struct switchdev_brport_flags flags, 6440 struct netlink_ext_ack *extack) 6441{ 6442 struct mv88e6xxx_chip *chip = ds->priv; 6443 const struct mv88e6xxx_ops *ops; 6444 6445 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6446 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6447 return -EINVAL; 6448 6449 ops = chip->info->ops; 6450 6451 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6452 return -EINVAL; 6453 6454 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6455 return -EINVAL; 6456 6457 return 0; 6458} 6459 6460static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6461 struct switchdev_brport_flags flags, 6462 struct netlink_ext_ack *extack) 6463{ 6464 struct mv88e6xxx_chip *chip = ds->priv; 6465 int err = 0; 6466 6467 mv88e6xxx_reg_lock(chip); 6468 6469 if (flags.mask & BR_LEARNING) { 6470 bool learning = !!(flags.val & BR_LEARNING); 6471 u16 pav = learning ? (1 << port) : 0; 6472 6473 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6474 if (err) 6475 goto out; 6476 } 6477 6478 if (flags.mask & BR_FLOOD) { 6479 bool unicast = !!(flags.val & BR_FLOOD); 6480 6481 err = chip->info->ops->port_set_ucast_flood(chip, port, 6482 unicast); 6483 if (err) 6484 goto out; 6485 } 6486 6487 if (flags.mask & BR_MCAST_FLOOD) { 6488 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6489 6490 err = chip->info->ops->port_set_mcast_flood(chip, port, 6491 multicast); 6492 if (err) 6493 goto out; 6494 } 6495 6496 if (flags.mask & BR_BCAST_FLOOD) { 6497 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6498 6499 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6500 if (err) 6501 goto out; 6502 } 6503 6504 if (flags.mask & BR_PORT_MAB) { 6505 bool mab = !!(flags.val & BR_PORT_MAB); 6506 6507 mv88e6xxx_port_set_mab(chip, port, mab); 6508 } 6509 6510 if (flags.mask & BR_PORT_LOCKED) { 6511 bool locked = !!(flags.val & BR_PORT_LOCKED); 6512 6513 err = mv88e6xxx_port_set_lock(chip, port, locked); 6514 if (err) 6515 goto out; 6516 } 6517out: 6518 mv88e6xxx_reg_unlock(chip); 6519 6520 return err; 6521} 6522 6523static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6524 struct dsa_lag lag, 6525 struct netdev_lag_upper_info *info, 6526 struct netlink_ext_ack *extack) 6527{ 6528 struct mv88e6xxx_chip *chip = ds->priv; 6529 struct dsa_port *dp; 6530 int members = 0; 6531 6532 if (!mv88e6xxx_has_lag(chip)) { 6533 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6534 return false; 6535 } 6536 6537 if (!lag.id) 6538 return false; 6539 6540 dsa_lag_foreach_port(dp, ds->dst, &lag) 6541 /* Includes the port joining the LAG */ 6542 members++; 6543 6544 if (members > 8) { 6545 NL_SET_ERR_MSG_MOD(extack, 6546 "Cannot offload more than 8 LAG ports"); 6547 return false; 6548 } 6549 6550 /* We could potentially relax this to include active 6551 * backup in the future. 6552 */ 6553 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6554 NL_SET_ERR_MSG_MOD(extack, 6555 "Can only offload LAG using hash TX type"); 6556 return false; 6557 } 6558 6559 /* Ideally we would also validate that the hash type matches 6560 * the hardware. Alas, this is always set to unknown on team 6561 * interfaces. 6562 */ 6563 return true; 6564} 6565 6566static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6567{ 6568 struct mv88e6xxx_chip *chip = ds->priv; 6569 struct dsa_port *dp; 6570 u16 map = 0; 6571 int id; 6572 6573 /* DSA LAG IDs are one-based, hardware is zero-based */ 6574 id = lag.id - 1; 6575 6576 /* Build the map of all ports to distribute flows destined for 6577 * this LAG. This can be either a local user port, or a DSA 6578 * port if the LAG port is on a remote chip. 6579 */ 6580 dsa_lag_foreach_port(dp, ds->dst, &lag) 6581 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6582 6583 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6584} 6585 6586static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6587 /* Row number corresponds to the number of active members in a 6588 * LAG. Each column states which of the eight hash buckets are 6589 * mapped to the column:th port in the LAG. 6590 * 6591 * Example: In a LAG with three active ports, the second port 6592 * ([2][1]) would be selected for traffic mapped to buckets 6593 * 3,4,5 (0x38). 6594 */ 6595 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6596 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6597 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6598 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6599 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6600 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6601 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6602 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6603}; 6604 6605static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6606 int num_tx, int nth) 6607{ 6608 u8 active = 0; 6609 int i; 6610 6611 num_tx = num_tx <= 8 ? num_tx : 8; 6612 if (nth < num_tx) 6613 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6614 6615 for (i = 0; i < 8; i++) { 6616 if (BIT(i) & active) 6617 mask[i] |= BIT(port); 6618 } 6619} 6620 6621static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6622{ 6623 struct mv88e6xxx_chip *chip = ds->priv; 6624 unsigned int id, num_tx; 6625 struct dsa_port *dp; 6626 struct dsa_lag *lag; 6627 int i, err, nth; 6628 u16 mask[8]; 6629 u16 ivec; 6630 6631 /* Assume no port is a member of any LAG. */ 6632 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6633 6634 /* Disable all masks for ports that _are_ members of a LAG. */ 6635 dsa_switch_for_each_port(dp, ds) { 6636 if (!dp->lag) 6637 continue; 6638 6639 ivec &= ~BIT(dp->index); 6640 } 6641 6642 for (i = 0; i < 8; i++) 6643 mask[i] = ivec; 6644 6645 /* Enable the correct subset of masks for all LAG ports that 6646 * are in the Tx set. 6647 */ 6648 dsa_lags_foreach_id(id, ds->dst) { 6649 lag = dsa_lag_by_id(ds->dst, id); 6650 if (!lag) 6651 continue; 6652 6653 num_tx = 0; 6654 dsa_lag_foreach_port(dp, ds->dst, lag) { 6655 if (dp->lag_tx_enabled) 6656 num_tx++; 6657 } 6658 6659 if (!num_tx) 6660 continue; 6661 6662 nth = 0; 6663 dsa_lag_foreach_port(dp, ds->dst, lag) { 6664 if (!dp->lag_tx_enabled) 6665 continue; 6666 6667 if (dp->ds == ds) 6668 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6669 num_tx, nth); 6670 6671 nth++; 6672 } 6673 } 6674 6675 for (i = 0; i < 8; i++) { 6676 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6677 if (err) 6678 return err; 6679 } 6680 6681 return 0; 6682} 6683 6684static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6685 struct dsa_lag lag) 6686{ 6687 int err; 6688 6689 err = mv88e6xxx_lag_sync_masks(ds); 6690 6691 if (!err) 6692 err = mv88e6xxx_lag_sync_map(ds, lag); 6693 6694 return err; 6695} 6696 6697static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6698{ 6699 struct mv88e6xxx_chip *chip = ds->priv; 6700 int err; 6701 6702 mv88e6xxx_reg_lock(chip); 6703 err = mv88e6xxx_lag_sync_masks(ds); 6704 mv88e6xxx_reg_unlock(chip); 6705 return err; 6706} 6707 6708static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6709 struct dsa_lag lag, 6710 struct netdev_lag_upper_info *info, 6711 struct netlink_ext_ack *extack) 6712{ 6713 struct mv88e6xxx_chip *chip = ds->priv; 6714 int err, id; 6715 6716 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6717 return -EOPNOTSUPP; 6718 6719 /* DSA LAG IDs are one-based */ 6720 id = lag.id - 1; 6721 6722 mv88e6xxx_reg_lock(chip); 6723 6724 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6725 if (err) 6726 goto err_unlock; 6727 6728 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6729 if (err) 6730 goto err_clear_trunk; 6731 6732 mv88e6xxx_reg_unlock(chip); 6733 return 0; 6734 6735err_clear_trunk: 6736 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6737err_unlock: 6738 mv88e6xxx_reg_unlock(chip); 6739 return err; 6740} 6741 6742static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6743 struct dsa_lag lag) 6744{ 6745 struct mv88e6xxx_chip *chip = ds->priv; 6746 int err_sync, err_trunk; 6747 6748 mv88e6xxx_reg_lock(chip); 6749 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6750 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6751 mv88e6xxx_reg_unlock(chip); 6752 return err_sync ? : err_trunk; 6753} 6754 6755static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6756 int port) 6757{ 6758 struct mv88e6xxx_chip *chip = ds->priv; 6759 int err; 6760 6761 mv88e6xxx_reg_lock(chip); 6762 err = mv88e6xxx_lag_sync_masks(ds); 6763 mv88e6xxx_reg_unlock(chip); 6764 return err; 6765} 6766 6767static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6768 int port, struct dsa_lag lag, 6769 struct netdev_lag_upper_info *info, 6770 struct netlink_ext_ack *extack) 6771{ 6772 struct mv88e6xxx_chip *chip = ds->priv; 6773 int err; 6774 6775 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6776 return -EOPNOTSUPP; 6777 6778 mv88e6xxx_reg_lock(chip); 6779 6780 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6781 if (err) 6782 goto unlock; 6783 6784 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6785 6786unlock: 6787 mv88e6xxx_reg_unlock(chip); 6788 return err; 6789} 6790 6791static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6792 int port, struct dsa_lag lag) 6793{ 6794 struct mv88e6xxx_chip *chip = ds->priv; 6795 int err_sync, err_pvt; 6796 6797 mv88e6xxx_reg_lock(chip); 6798 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6799 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6800 mv88e6xxx_reg_unlock(chip); 6801 return err_sync ? : err_pvt; 6802} 6803 6804static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6805 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6806 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6807 .setup = mv88e6xxx_setup, 6808 .teardown = mv88e6xxx_teardown, 6809 .port_setup = mv88e6xxx_port_setup, 6810 .port_teardown = mv88e6xxx_port_teardown, 6811 .phylink_get_caps = mv88e6xxx_get_caps, 6812 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, 6813 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 6814 .phylink_mac_config = mv88e6xxx_mac_config, 6815 .phylink_mac_finish = mv88e6xxx_mac_finish, 6816 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6817 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6818 .get_strings = mv88e6xxx_get_strings, 6819 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6820 .get_sset_count = mv88e6xxx_get_sset_count, 6821 .port_max_mtu = mv88e6xxx_get_max_mtu, 6822 .port_change_mtu = mv88e6xxx_change_mtu, 6823 .get_mac_eee = mv88e6xxx_get_mac_eee, 6824 .set_mac_eee = mv88e6xxx_set_mac_eee, 6825 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6826 .get_eeprom = mv88e6xxx_get_eeprom, 6827 .set_eeprom = mv88e6xxx_set_eeprom, 6828 .get_regs_len = mv88e6xxx_get_regs_len, 6829 .get_regs = mv88e6xxx_get_regs, 6830 .get_rxnfc = mv88e6xxx_get_rxnfc, 6831 .set_rxnfc = mv88e6xxx_set_rxnfc, 6832 .set_ageing_time = mv88e6xxx_set_ageing_time, 6833 .port_bridge_join = mv88e6xxx_port_bridge_join, 6834 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6835 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6836 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6837 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6838 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6839 .port_fast_age = mv88e6xxx_port_fast_age, 6840 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6841 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6842 .port_vlan_add = mv88e6xxx_port_vlan_add, 6843 .port_vlan_del = mv88e6xxx_port_vlan_del, 6844 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6845 .port_fdb_add = mv88e6xxx_port_fdb_add, 6846 .port_fdb_del = mv88e6xxx_port_fdb_del, 6847 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6848 .port_mdb_add = mv88e6xxx_port_mdb_add, 6849 .port_mdb_del = mv88e6xxx_port_mdb_del, 6850 .port_mirror_add = mv88e6xxx_port_mirror_add, 6851 .port_mirror_del = mv88e6xxx_port_mirror_del, 6852 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6853 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6854 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6855 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6856 .port_txtstamp = mv88e6xxx_port_txtstamp, 6857 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6858 .get_ts_info = mv88e6xxx_get_ts_info, 6859 .devlink_param_get = mv88e6xxx_devlink_param_get, 6860 .devlink_param_set = mv88e6xxx_devlink_param_set, 6861 .devlink_info_get = mv88e6xxx_devlink_info_get, 6862 .port_lag_change = mv88e6xxx_port_lag_change, 6863 .port_lag_join = mv88e6xxx_port_lag_join, 6864 .port_lag_leave = mv88e6xxx_port_lag_leave, 6865 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6866 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6867 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6868}; 6869 6870static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6871{ 6872 struct device *dev = chip->dev; 6873 struct dsa_switch *ds; 6874 6875 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6876 if (!ds) 6877 return -ENOMEM; 6878 6879 ds->dev = dev; 6880 ds->num_ports = mv88e6xxx_num_ports(chip); 6881 ds->priv = chip; 6882 ds->dev = dev; 6883 ds->ops = &mv88e6xxx_switch_ops; 6884 ds->ageing_time_min = chip->info->age_time_coeff; 6885 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6886 6887 /* Some chips support up to 32, but that requires enabling the 6888 * 5-bit port mode, which we do not support. 640k^W16 ought to 6889 * be enough for anyone. 6890 */ 6891 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6892 6893 dev_set_drvdata(dev, ds); 6894 6895 return dsa_register_switch(ds); 6896} 6897 6898static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6899{ 6900 dsa_unregister_switch(chip->ds); 6901} 6902 6903static const void *pdata_device_get_match_data(struct device *dev) 6904{ 6905 const struct of_device_id *matches = dev->driver->of_match_table; 6906 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6907 6908 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6909 matches++) { 6910 if (!strcmp(pdata->compatible, matches->compatible)) 6911 return matches->data; 6912 } 6913 return NULL; 6914} 6915 6916/* There is no suspend to RAM support at DSA level yet, the switch configuration 6917 * would be lost after a power cycle so prevent it to be suspended. 6918 */ 6919static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6920{ 6921 return -EOPNOTSUPP; 6922} 6923 6924static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6925{ 6926 return 0; 6927} 6928 6929static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6930 6931static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6932{ 6933 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6934 const struct mv88e6xxx_info *compat_info = NULL; 6935 struct device *dev = &mdiodev->dev; 6936 struct device_node *np = dev->of_node; 6937 struct mv88e6xxx_chip *chip; 6938 int port; 6939 int err; 6940 6941 if (!np && !pdata) 6942 return -EINVAL; 6943 6944 if (np) 6945 compat_info = of_device_get_match_data(dev); 6946 6947 if (pdata) { 6948 compat_info = pdata_device_get_match_data(dev); 6949 6950 if (!pdata->netdev) 6951 return -EINVAL; 6952 6953 for (port = 0; port < DSA_MAX_PORTS; port++) { 6954 if (!(pdata->enabled_ports & (1 << port))) 6955 continue; 6956 if (strcmp(pdata->cd.port_names[port], "cpu")) 6957 continue; 6958 pdata->cd.netdev[port] = &pdata->netdev->dev; 6959 break; 6960 } 6961 } 6962 6963 if (!compat_info) 6964 return -EINVAL; 6965 6966 chip = mv88e6xxx_alloc_chip(dev); 6967 if (!chip) { 6968 err = -ENOMEM; 6969 goto out; 6970 } 6971 6972 chip->info = compat_info; 6973 6974 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6975 if (IS_ERR(chip->reset)) { 6976 err = PTR_ERR(chip->reset); 6977 goto out; 6978 } 6979 if (chip->reset) 6980 usleep_range(10000, 20000); 6981 6982 /* Detect if the device is configured in single chip addressing mode, 6983 * otherwise continue with address specific smi init/detection. 6984 */ 6985 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 6986 if (err) { 6987 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6988 if (err) 6989 goto out; 6990 6991 err = mv88e6xxx_detect(chip); 6992 if (err) 6993 goto out; 6994 } 6995 6996 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6997 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6998 else 6999 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7000 7001 mv88e6xxx_phy_init(chip); 7002 7003 if (chip->info->ops->get_eeprom) { 7004 if (np) 7005 of_property_read_u32(np, "eeprom-length", 7006 &chip->eeprom_len); 7007 else 7008 chip->eeprom_len = pdata->eeprom_len; 7009 } 7010 7011 mv88e6xxx_reg_lock(chip); 7012 err = mv88e6xxx_switch_reset(chip); 7013 mv88e6xxx_reg_unlock(chip); 7014 if (err) 7015 goto out; 7016 7017 if (np) { 7018 chip->irq = of_irq_get(np, 0); 7019 if (chip->irq == -EPROBE_DEFER) { 7020 err = chip->irq; 7021 goto out; 7022 } 7023 } 7024 7025 if (pdata) 7026 chip->irq = pdata->irq; 7027 7028 /* Has to be performed before the MDIO bus is created, because 7029 * the PHYs will link their interrupts to these interrupt 7030 * controllers 7031 */ 7032 mv88e6xxx_reg_lock(chip); 7033 if (chip->irq > 0) 7034 err = mv88e6xxx_g1_irq_setup(chip); 7035 else 7036 err = mv88e6xxx_irq_poll_setup(chip); 7037 mv88e6xxx_reg_unlock(chip); 7038 7039 if (err) 7040 goto out; 7041 7042 if (chip->info->g2_irqs > 0) { 7043 err = mv88e6xxx_g2_irq_setup(chip); 7044 if (err) 7045 goto out_g1_irq; 7046 } 7047 7048 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7049 if (err) 7050 goto out_g2_irq; 7051 7052 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7053 if (err) 7054 goto out_g1_atu_prob_irq; 7055 7056 err = mv88e6xxx_register_switch(chip); 7057 if (err) 7058 goto out_g1_vtu_prob_irq; 7059 7060 return 0; 7061 7062out_g1_vtu_prob_irq: 7063 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7064out_g1_atu_prob_irq: 7065 mv88e6xxx_g1_atu_prob_irq_free(chip); 7066out_g2_irq: 7067 if (chip->info->g2_irqs > 0) 7068 mv88e6xxx_g2_irq_free(chip); 7069out_g1_irq: 7070 if (chip->irq > 0) 7071 mv88e6xxx_g1_irq_free(chip); 7072 else 7073 mv88e6xxx_irq_poll_free(chip); 7074out: 7075 if (pdata) 7076 dev_put(pdata->netdev); 7077 7078 return err; 7079} 7080 7081static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7082{ 7083 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7084 struct mv88e6xxx_chip *chip; 7085 7086 if (!ds) 7087 return; 7088 7089 chip = ds->priv; 7090 7091 if (chip->info->ptp_support) { 7092 mv88e6xxx_hwtstamp_free(chip); 7093 mv88e6xxx_ptp_free(chip); 7094 } 7095 7096 mv88e6xxx_phy_destroy(chip); 7097 mv88e6xxx_unregister_switch(chip); 7098 7099 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7100 mv88e6xxx_g1_atu_prob_irq_free(chip); 7101 7102 if (chip->info->g2_irqs > 0) 7103 mv88e6xxx_g2_irq_free(chip); 7104 7105 if (chip->irq > 0) 7106 mv88e6xxx_g1_irq_free(chip); 7107 else 7108 mv88e6xxx_irq_poll_free(chip); 7109} 7110 7111static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7112{ 7113 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7114 7115 if (!ds) 7116 return; 7117 7118 dsa_switch_shutdown(ds); 7119 7120 dev_set_drvdata(&mdiodev->dev, NULL); 7121} 7122 7123static const struct of_device_id mv88e6xxx_of_match[] = { 7124 { 7125 .compatible = "marvell,mv88e6085", 7126 .data = &mv88e6xxx_table[MV88E6085], 7127 }, 7128 { 7129 .compatible = "marvell,mv88e6190", 7130 .data = &mv88e6xxx_table[MV88E6190], 7131 }, 7132 { 7133 .compatible = "marvell,mv88e6250", 7134 .data = &mv88e6xxx_table[MV88E6250], 7135 }, 7136 { /* sentinel */ }, 7137}; 7138 7139MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7140 7141static struct mdio_driver mv88e6xxx_driver = { 7142 .probe = mv88e6xxx_probe, 7143 .remove = mv88e6xxx_remove, 7144 .shutdown = mv88e6xxx_shutdown, 7145 .mdiodrv.driver = { 7146 .name = "mv88e6085", 7147 .of_match_table = mv88e6xxx_of_match, 7148 .pm = &mv88e6xxx_pm_ops, 7149 }, 7150}; 7151 7152mdio_module_driver(mv88e6xxx_driver); 7153 7154MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7155MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7156MODULE_LICENSE("GPL"); 7157