1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6#include <linux/etherdevice.h> 7#include <linux/if_bridge.h> 8#include <linux/iopoll.h> 9#include <linux/mdio.h> 10#include <linux/mfd/syscon.h> 11#include <linux/module.h> 12#include <linux/netdevice.h> 13#include <linux/of_irq.h> 14#include <linux/of_mdio.h> 15#include <linux/of_net.h> 16#include <linux/of_platform.h> 17#include <linux/phylink.h> 18#include <linux/regmap.h> 19#include <linux/regulator/consumer.h> 20#include <linux/reset.h> 21#include <linux/gpio/consumer.h> 22#include <linux/gpio/driver.h> 23#include <net/dsa.h> 24 25#include "mt7530.h" 26 27static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28{ 29 return container_of(pcs, struct mt753x_pcs, pcs); 30} 31 32/* String, offset, and register size in bytes if different from 4 bytes */ 33static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75}; 76 77/* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82static int 83core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84{ 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111} 112 113static int 114core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116{ 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142} 143 144static void 145mt7530_mutex_lock(struct mt7530_priv *priv) 146{ 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149} 150 151static void 152mt7530_mutex_unlock(struct mt7530_priv *priv) 153{ 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156} 157 158static void 159core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160{ 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166} 167 168static void 169core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170{ 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181} 182 183static void 184core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185{ 186 core_rmw(priv, reg, 0, val); 187} 188 189static void 190core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191{ 192 core_rmw(priv, reg, val, 0); 193} 194 195static int 196mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197{ 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207} 208 209static u32 210mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211{ 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224} 225 226static void 227mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228{ 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234} 235 236static u32 237_mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238{ 239 return mt7530_mii_read(p->priv, p->reg); 240} 241 242static u32 243_mt7530_read(struct mt7530_dummy_poll *p) 244{ 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254} 255 256static u32 257mt7530_read(struct mt7530_priv *priv, u32 reg) 258{ 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263} 264 265static void 266mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268{ 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274} 275 276static void 277mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278{ 279 mt7530_rmw(priv, reg, val, val); 280} 281 282static void 283mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284{ 285 mt7530_rmw(priv, reg, val, 0); 286} 287 288static int 289mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290{ 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318} 319 320static void 321mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322{ 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344} 345 346static void 347mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350{ 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374} 375 376/* Set up switch core clock for MT7530 */ 377static void mt7530_pll_setup(struct mt7530_priv *priv) 378{ 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400} 401 402/* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405static struct dsa_port * 406mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407{ 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414} 415 416/* Setup port 6 interface mode and TRGMII TX circuit */ 417static int 418mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 419{ 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, trgint, xtal; 422 423 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 424 425 if (xtal == HWTRAP_XTAL_20MHZ) { 426 dev_err(priv->dev, 427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 428 __func__); 429 return -EINVAL; 430 } 431 432 switch (interface) { 433 case PHY_INTERFACE_MODE_RGMII: 434 trgint = 0; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (xtal == HWTRAP_XTAL_25MHZ) 439 ssc_delta = 0x57; 440 else 441 ssc_delta = 0x87; 442 if (priv->id == ID_MT7621) { 443 /* PLL frequency: 125MHz: 1.0GBit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0640; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x0a00; 448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 449 if (xtal == HWTRAP_XTAL_40MHZ) 450 ncpo1 = 0x0c80; 451 if (xtal == HWTRAP_XTAL_25MHZ) 452 ncpo1 = 0x1400; 453 } 454 break; 455 default: 456 dev_err(priv->dev, "xMII interface %d not supported\n", 457 interface); 458 return -EINVAL; 459 } 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Disable the MT7530 TRGMII clocks */ 466 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP4, 474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 475 RG_SYSPLL_BIAS_LPF_EN); 476 core_write(priv, CORE_PLL_GROUP2, 477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 478 RG_SYSPLL_POSDIV(1)); 479 core_write(priv, CORE_PLL_GROUP7, 480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 482 483 /* Enable the MT7530 TRGMII clocks */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 485 } 486 487 return 0; 488} 489 490static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 491{ 492 u32 val; 493 494 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 495 496 return (val & PAD_DUAL_SGMII_EN) != 0; 497} 498 499static int 500mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 501{ 502 return 0; 503} 504 505static void 506mt7531_pll_setup(struct mt7530_priv *priv) 507{ 508 u32 top_sig; 509 u32 hwstrap; 510 u32 xtal; 511 u32 val; 512 513 if (mt7531_dual_sgmii_supported(priv)) 514 return; 515 516 val = mt7530_read(priv, MT7531_CREV); 517 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 518 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 519 if ((val & CHIP_REV_M) > 0) 520 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 521 HWTRAP_XTAL_FSEL_25MHZ; 522 else 523 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 524 525 /* Step 1 : Disable MT7531 COREPLL */ 526 val = mt7530_read(priv, MT7531_PLLGP_EN); 527 val &= ~EN_COREPLL; 528 mt7530_write(priv, MT7531_PLLGP_EN, val); 529 530 /* Step 2: switch to XTAL output */ 531 val = mt7530_read(priv, MT7531_PLLGP_EN); 532 val |= SW_CLKSW; 533 mt7530_write(priv, MT7531_PLLGP_EN, val); 534 535 val = mt7530_read(priv, MT7531_PLLGP_CR0); 536 val &= ~RG_COREPLL_EN; 537 mt7530_write(priv, MT7531_PLLGP_CR0, val); 538 539 /* Step 3: disable PLLGP and enable program PLLGP */ 540 val = mt7530_read(priv, MT7531_PLLGP_EN); 541 val |= SW_PLLGP; 542 mt7530_write(priv, MT7531_PLLGP_EN, val); 543 544 /* Step 4: program COREPLL output frequency to 500MHz */ 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_POSDIV_M; 547 val |= 2 << RG_COREPLL_POSDIV_S; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 usleep_range(25, 35); 550 551 switch (xtal) { 552 case HWTRAP_XTAL_FSEL_25MHZ: 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val &= ~RG_COREPLL_SDM_PCW_M; 555 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 556 mt7530_write(priv, MT7531_PLLGP_CR0, val); 557 break; 558 case HWTRAP_XTAL_FSEL_40MHZ: 559 val = mt7530_read(priv, MT7531_PLLGP_CR0); 560 val &= ~RG_COREPLL_SDM_PCW_M; 561 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 break; 564 } 565 566 /* Set feedback divide ratio update signal to high */ 567 val = mt7530_read(priv, MT7531_PLLGP_CR0); 568 val |= RG_COREPLL_SDM_PCW_CHG; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 /* Wait for at least 16 XTAL clocks */ 571 usleep_range(10, 20); 572 573 /* Step 5: set feedback divide ratio update signal to low */ 574 val = mt7530_read(priv, MT7531_PLLGP_CR0); 575 val &= ~RG_COREPLL_SDM_PCW_CHG; 576 mt7530_write(priv, MT7531_PLLGP_CR0, val); 577 578 /* Enable 325M clock for SGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 580 581 /* Enable 250SSC clock for RGMII */ 582 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 583 584 /* Step 6: Enable MT7531 PLL */ 585 val = mt7530_read(priv, MT7531_PLLGP_CR0); 586 val |= RG_COREPLL_EN; 587 mt7530_write(priv, MT7531_PLLGP_CR0, val); 588 589 val = mt7530_read(priv, MT7531_PLLGP_EN); 590 val |= EN_COREPLL; 591 mt7530_write(priv, MT7531_PLLGP_EN, val); 592 usleep_range(25, 35); 593} 594 595static void 596mt7530_mib_reset(struct dsa_switch *ds) 597{ 598 struct mt7530_priv *priv = ds->priv; 599 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 602} 603 604static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 605{ 606 return mdiobus_read_nested(priv->bus, port, regnum); 607} 608 609static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 610 u16 val) 611{ 612 return mdiobus_write_nested(priv->bus, port, regnum, val); 613} 614 615static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 616 int devad, int regnum) 617{ 618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 619} 620 621static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 622 int regnum, u16 val) 623{ 624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 625} 626 627static int 628mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 629 int regnum) 630{ 631 struct mt7530_dummy_poll p; 632 u32 reg, val; 633 int ret; 634 635 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 636 637 mt7530_mutex_lock(priv); 638 639 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 640 !(val & MT7531_PHY_ACS_ST), 20, 100000); 641 if (ret < 0) { 642 dev_err(priv->dev, "poll timeout\n"); 643 goto out; 644 } 645 646 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 647 MT7531_MDIO_DEV_ADDR(devad) | regnum; 648 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 649 650 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 651 !(val & MT7531_PHY_ACS_ST), 20, 100000); 652 if (ret < 0) { 653 dev_err(priv->dev, "poll timeout\n"); 654 goto out; 655 } 656 657 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 658 MT7531_MDIO_DEV_ADDR(devad); 659 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 660 661 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 ret = val & MT7531_MDIO_RW_DATA_MASK; 669out: 670 mt7530_mutex_unlock(priv); 671 672 return ret; 673} 674 675static int 676mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 677 int regnum, u16 data) 678{ 679 struct mt7530_dummy_poll p; 680 u32 val, reg; 681 int ret; 682 683 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 684 685 mt7530_mutex_lock(priv); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | regnum; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 706 MT7531_MDIO_DEV_ADDR(devad) | data; 707 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 708 709 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 710 !(val & MT7531_PHY_ACS_ST), 20, 100000); 711 if (ret < 0) { 712 dev_err(priv->dev, "poll timeout\n"); 713 goto out; 714 } 715 716out: 717 mt7530_mutex_unlock(priv); 718 719 return ret; 720} 721 722static int 723mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 724{ 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 val; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 734 !(val & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum); 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 746 !(val & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 ret = val & MT7531_MDIO_RW_DATA_MASK; 753out: 754 mt7530_mutex_unlock(priv); 755 756 return ret; 757} 758 759static int 760mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 761 u16 data) 762{ 763 struct mt7530_dummy_poll p; 764 int ret; 765 u32 reg; 766 767 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 768 769 mt7530_mutex_lock(priv); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 779 MT7531_MDIO_REG_ADDR(regnum) | data; 780 781 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 782 783 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 784 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 785 if (ret < 0) { 786 dev_err(priv->dev, "poll timeout\n"); 787 goto out; 788 } 789 790out: 791 mt7530_mutex_unlock(priv); 792 793 return ret; 794} 795 796static int 797mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 798{ 799 struct mt7530_priv *priv = bus->priv; 800 801 return priv->info->phy_read_c22(priv, port, regnum); 802} 803 804static int 805mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 806{ 807 struct mt7530_priv *priv = bus->priv; 808 809 return priv->info->phy_read_c45(priv, port, devad, regnum); 810} 811 812static int 813mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 814{ 815 struct mt7530_priv *priv = bus->priv; 816 817 return priv->info->phy_write_c22(priv, port, regnum, val); 818} 819 820static int 821mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 822 u16 val) 823{ 824 struct mt7530_priv *priv = bus->priv; 825 826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 827} 828 829static void 830mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 831 uint8_t *data) 832{ 833 int i; 834 835 if (stringset != ETH_SS_STATS) 836 return; 837 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 840 ETH_GSTRING_LEN); 841} 842 843static void 844mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 845 uint64_t *data) 846{ 847 struct mt7530_priv *priv = ds->priv; 848 const struct mt7530_mib_desc *mib; 849 u32 reg, i; 850 u64 hi; 851 852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 853 mib = &mt7530_mib[i]; 854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 855 856 data[i] = mt7530_read(priv, reg); 857 if (mib->size == 2) { 858 hi = mt7530_read(priv, reg + 4); 859 data[i] |= hi << 32; 860 } 861 } 862} 863 864static int 865mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 866{ 867 if (sset != ETH_SS_STATS) 868 return 0; 869 870 return ARRAY_SIZE(mt7530_mib); 871} 872 873static int 874mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 875{ 876 struct mt7530_priv *priv = ds->priv; 877 unsigned int secs = msecs / 1000; 878 unsigned int tmp_age_count; 879 unsigned int error = -1; 880 unsigned int age_count; 881 unsigned int age_unit; 882 883 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 884 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 885 return -ERANGE; 886 887 /* iterate through all possible age_count to find the closest pair */ 888 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 890 891 if (tmp_age_unit <= AGE_UNIT_MAX) { 892 unsigned int tmp_error = secs - 893 (tmp_age_count + 1) * (tmp_age_unit + 1); 894 895 /* found a closer pair */ 896 if (error > tmp_error) { 897 error = tmp_error; 898 age_count = tmp_age_count; 899 age_unit = tmp_age_unit; 900 } 901 902 /* found the exact match, so break the loop */ 903 if (!error) 904 break; 905 } 906 } 907 908 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 909 910 return 0; 911} 912 913static const char *p5_intf_modes(unsigned int p5_interface) 914{ 915 switch (p5_interface) { 916 case P5_DISABLED: 917 return "DISABLED"; 918 case P5_INTF_SEL_PHY_P0: 919 return "PHY P0"; 920 case P5_INTF_SEL_PHY_P4: 921 return "PHY P4"; 922 case P5_INTF_SEL_GMAC5: 923 return "GMAC5"; 924 case P5_INTF_SEL_GMAC5_SGMII: 925 return "GMAC5_SGMII"; 926 default: 927 return "unknown"; 928 } 929} 930 931static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 932{ 933 struct mt7530_priv *priv = ds->priv; 934 u8 tx_delay = 0; 935 int val; 936 937 mutex_lock(&priv->reg_mutex); 938 939 val = mt7530_read(priv, MT7530_MHWTRAP); 940 941 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 942 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 943 944 switch (priv->p5_intf_sel) { 945 case P5_INTF_SEL_PHY_P0: 946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 947 val |= MHWTRAP_PHY0_SEL; 948 fallthrough; 949 case P5_INTF_SEL_PHY_P4: 950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 951 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 952 953 /* Setup the MAC by default for the cpu port */ 954 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 955 break; 956 case P5_INTF_SEL_GMAC5: 957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 958 val &= ~MHWTRAP_P5_DIS; 959 break; 960 case P5_DISABLED: 961 interface = PHY_INTERFACE_MODE_NA; 962 break; 963 default: 964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 965 priv->p5_intf_sel); 966 goto unlock_exit; 967 } 968 969 /* Setup RGMII settings */ 970 if (phy_interface_mode_is_rgmii(interface)) { 971 val |= MHWTRAP_P5_RGMII_MODE; 972 973 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 974 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 975 976 /* Don't set delay in DSA mode */ 977 if (!dsa_is_dsa_port(priv->ds, 5) && 978 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 979 interface == PHY_INTERFACE_MODE_RGMII_ID)) 980 tx_delay = 4; /* n * 0.5 ns */ 981 982 /* P5 RGMII TX Clock Control: delay x */ 983 mt7530_write(priv, MT7530_P5RGMIITXCR, 984 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 985 986 /* reduce P5 RGMII Tx driving, 8mA */ 987 mt7530_write(priv, MT7530_IO_DRV_CR, 988 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 989 } 990 991 mt7530_write(priv, MT7530_MHWTRAP, val); 992 993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 995 996 priv->p5_interface = interface; 997 998unlock_exit: 999 mutex_unlock(&priv->reg_mutex); 1000} 1001 1002/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std 1003 * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA 1004 * must only be propagated to C-VLAN and MAC Bridge components. That means 1005 * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports, 1006 * these frames are supposed to be processed by the CPU (software). So we make 1007 * the switch only forward them to the CPU port. And if received from a CPU 1008 * port, forward to a single port. The software is responsible of making the 1009 * switch conform to the latter by setting a single port as destination port on 1010 * the special tag. 1011 * 1012 * This switch intellectual property cannot conform to this part of the standard 1013 * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC 1014 * DAs, it also includes :22-FF which the scope of propagation is not supposed 1015 * to be restricted for these MAC DAs. 1016 */ 1017static void 1018mt753x_trap_frames(struct mt7530_priv *priv) 1019{ 1020 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1021 * VLAN-untagged. 1022 */ 1023 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK | 1024 MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | 1025 MT753X_BPDU_PORT_FW_MASK, 1026 MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1027 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1028 MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1029 MT753X_BPDU_CPU_ONLY); 1030 1031 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1032 * them VLAN-untagged. 1033 */ 1034 mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK | 1035 MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK | 1036 MT753X_R01_PORT_FW_MASK, 1037 MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1038 MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1039 MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1040 MT753X_BPDU_CPU_ONLY); 1041 1042 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1043 * them VLAN-untagged. 1044 */ 1045 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK | 1046 MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK | 1047 MT753X_R03_PORT_FW_MASK, 1048 MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1049 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1050 MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1051 MT753X_BPDU_CPU_ONLY); 1052} 1053 1054static int 1055mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1056{ 1057 struct mt7530_priv *priv = ds->priv; 1058 int ret; 1059 1060 /* Setup max capability of CPU port at first */ 1061 if (priv->info->cpu_port_config) { 1062 ret = priv->info->cpu_port_config(ds, port); 1063 if (ret) 1064 return ret; 1065 } 1066 1067 /* Enable Mediatek header mode on the cpu port */ 1068 mt7530_write(priv, MT7530_PVC_P(port), 1069 PORT_SPEC_TAG); 1070 1071 /* Enable flooding on the CPU port */ 1072 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1073 UNU_FFP(BIT(port))); 1074 1075 /* Set CPU port number */ 1076 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 1077 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1078 1079 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1080 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1081 * is affine to the inbound user port. 1082 */ 1083 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1084 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1085 1086 /* CPU port gets connected to all user ports of 1087 * the switch. 1088 */ 1089 mt7530_write(priv, MT7530_PCR_P(port), 1090 PCR_MATRIX(dsa_user_ports(priv->ds))); 1091 1092 /* Set to fallback mode for independent VLAN learning */ 1093 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1094 MT7530_PORT_FALLBACK_MODE); 1095 1096 return 0; 1097} 1098 1099static int 1100mt7530_port_enable(struct dsa_switch *ds, int port, 1101 struct phy_device *phy) 1102{ 1103 struct dsa_port *dp = dsa_to_port(ds, port); 1104 struct mt7530_priv *priv = ds->priv; 1105 1106 mutex_lock(&priv->reg_mutex); 1107 1108 /* Allow the user port gets connected to the cpu port and also 1109 * restore the port matrix if the port is the member of a certain 1110 * bridge. 1111 */ 1112 if (dsa_port_is_user(dp)) { 1113 struct dsa_port *cpu_dp = dp->cpu_dp; 1114 1115 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1116 } 1117 priv->ports[port].enable = true; 1118 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1119 priv->ports[port].pm); 1120 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1121 1122 mutex_unlock(&priv->reg_mutex); 1123 1124 return 0; 1125} 1126 1127static void 1128mt7530_port_disable(struct dsa_switch *ds, int port) 1129{ 1130 struct mt7530_priv *priv = ds->priv; 1131 1132 mutex_lock(&priv->reg_mutex); 1133 1134 /* Clear up all port matrix which could be restored in the next 1135 * enablement for the port. 1136 */ 1137 priv->ports[port].enable = false; 1138 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1139 PCR_MATRIX_CLR); 1140 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1141 1142 mutex_unlock(&priv->reg_mutex); 1143} 1144 1145static int 1146mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1147{ 1148 struct mt7530_priv *priv = ds->priv; 1149 int length; 1150 u32 val; 1151 1152 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1153 * largest MTU of the slave ports. Because the switch only has a global 1154 * RX length register, only allowing CPU port here is enough. 1155 */ 1156 if (!dsa_is_cpu_port(ds, port)) 1157 return 0; 1158 1159 mt7530_mutex_lock(priv); 1160 1161 val = mt7530_mii_read(priv, MT7530_GMACCR); 1162 val &= ~MAX_RX_PKT_LEN_MASK; 1163 1164 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1165 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1166 if (length <= 1522) { 1167 val |= MAX_RX_PKT_LEN_1522; 1168 } else if (length <= 1536) { 1169 val |= MAX_RX_PKT_LEN_1536; 1170 } else if (length <= 1552) { 1171 val |= MAX_RX_PKT_LEN_1552; 1172 } else { 1173 val &= ~MAX_RX_JUMBO_MASK; 1174 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1175 val |= MAX_RX_PKT_LEN_JUMBO; 1176 } 1177 1178 mt7530_mii_write(priv, MT7530_GMACCR, val); 1179 1180 mt7530_mutex_unlock(priv); 1181 1182 return 0; 1183} 1184 1185static int 1186mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1187{ 1188 return MT7530_MAX_MTU; 1189} 1190 1191static void 1192mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1193{ 1194 struct mt7530_priv *priv = ds->priv; 1195 u32 stp_state; 1196 1197 switch (state) { 1198 case BR_STATE_DISABLED: 1199 stp_state = MT7530_STP_DISABLED; 1200 break; 1201 case BR_STATE_BLOCKING: 1202 stp_state = MT7530_STP_BLOCKING; 1203 break; 1204 case BR_STATE_LISTENING: 1205 stp_state = MT7530_STP_LISTENING; 1206 break; 1207 case BR_STATE_LEARNING: 1208 stp_state = MT7530_STP_LEARNING; 1209 break; 1210 case BR_STATE_FORWARDING: 1211 default: 1212 stp_state = MT7530_STP_FORWARDING; 1213 break; 1214 } 1215 1216 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1217 FID_PST(FID_BRIDGED, stp_state)); 1218} 1219 1220static int 1221mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1222 struct switchdev_brport_flags flags, 1223 struct netlink_ext_ack *extack) 1224{ 1225 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1226 BR_BCAST_FLOOD)) 1227 return -EINVAL; 1228 1229 return 0; 1230} 1231 1232static int 1233mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1234 struct switchdev_brport_flags flags, 1235 struct netlink_ext_ack *extack) 1236{ 1237 struct mt7530_priv *priv = ds->priv; 1238 1239 if (flags.mask & BR_LEARNING) 1240 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1241 flags.val & BR_LEARNING ? 0 : SA_DIS); 1242 1243 if (flags.mask & BR_FLOOD) 1244 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1245 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1246 1247 if (flags.mask & BR_MCAST_FLOOD) 1248 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1249 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1250 1251 if (flags.mask & BR_BCAST_FLOOD) 1252 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1253 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1254 1255 return 0; 1256} 1257 1258static int 1259mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1260 struct dsa_bridge bridge, bool *tx_fwd_offload, 1261 struct netlink_ext_ack *extack) 1262{ 1263 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1264 struct dsa_port *cpu_dp = dp->cpu_dp; 1265 u32 port_bitmap = BIT(cpu_dp->index); 1266 struct mt7530_priv *priv = ds->priv; 1267 1268 mutex_lock(&priv->reg_mutex); 1269 1270 dsa_switch_for_each_user_port(other_dp, ds) { 1271 int other_port = other_dp->index; 1272 1273 if (dp == other_dp) 1274 continue; 1275 1276 /* Add this port to the port matrix of the other ports in the 1277 * same bridge. If the port is disabled, port matrix is kept 1278 * and not being setup until the port becomes enabled. 1279 */ 1280 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1281 continue; 1282 1283 if (priv->ports[other_port].enable) 1284 mt7530_set(priv, MT7530_PCR_P(other_port), 1285 PCR_MATRIX(BIT(port))); 1286 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1287 1288 port_bitmap |= BIT(other_port); 1289 } 1290 1291 /* Add the all other ports to this port matrix. */ 1292 if (priv->ports[port].enable) 1293 mt7530_rmw(priv, MT7530_PCR_P(port), 1294 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1295 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1296 1297 /* Set to fallback mode for independent VLAN learning */ 1298 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1299 MT7530_PORT_FALLBACK_MODE); 1300 1301 mutex_unlock(&priv->reg_mutex); 1302 1303 return 0; 1304} 1305 1306static void 1307mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1308{ 1309 struct mt7530_priv *priv = ds->priv; 1310 bool all_user_ports_removed = true; 1311 int i; 1312 1313 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1314 * bridge. Don't set standalone ports to fallback mode. 1315 */ 1316 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1317 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1318 MT7530_PORT_FALLBACK_MODE); 1319 1320 mt7530_rmw(priv, MT7530_PVC_P(port), 1321 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1322 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1323 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1324 MT7530_VLAN_ACC_ALL); 1325 1326 /* Set PVID to 0 */ 1327 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1328 G0_PORT_VID_DEF); 1329 1330 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1331 if (dsa_is_user_port(ds, i) && 1332 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1333 all_user_ports_removed = false; 1334 break; 1335 } 1336 } 1337 1338 /* CPU port also does the same thing until all user ports belonging to 1339 * the CPU port get out of VLAN filtering mode. 1340 */ 1341 if (all_user_ports_removed) { 1342 struct dsa_port *dp = dsa_to_port(ds, port); 1343 struct dsa_port *cpu_dp = dp->cpu_dp; 1344 1345 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1346 PCR_MATRIX(dsa_user_ports(priv->ds))); 1347 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1348 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1349 } 1350} 1351 1352static void 1353mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1354{ 1355 struct mt7530_priv *priv = ds->priv; 1356 1357 /* Trapped into security mode allows packet forwarding through VLAN 1358 * table lookup. 1359 */ 1360 if (dsa_is_user_port(ds, port)) { 1361 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1362 MT7530_PORT_SECURITY_MODE); 1363 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1364 G0_PORT_VID(priv->ports[port].pvid)); 1365 1366 /* Only accept tagged frames if PVID is not set */ 1367 if (!priv->ports[port].pvid) 1368 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1369 MT7530_VLAN_ACC_TAGGED); 1370 1371 /* Set the port as a user port which is to be able to recognize 1372 * VID from incoming packets before fetching entry within the 1373 * VLAN table. 1374 */ 1375 mt7530_rmw(priv, MT7530_PVC_P(port), 1376 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1377 VLAN_ATTR(MT7530_VLAN_USER) | 1378 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1379 } else { 1380 /* Also set CPU ports to the "user" VLAN port attribute, to 1381 * allow VLAN classification, but keep the EG_TAG attribute as 1382 * "consistent" (i.o.w. don't change its value) for packets 1383 * received by the switch from the CPU, so that tagged packets 1384 * are forwarded to user ports as tagged, and untagged as 1385 * untagged. 1386 */ 1387 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1388 VLAN_ATTR(MT7530_VLAN_USER)); 1389 } 1390} 1391 1392static void 1393mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1394 struct dsa_bridge bridge) 1395{ 1396 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1397 struct dsa_port *cpu_dp = dp->cpu_dp; 1398 struct mt7530_priv *priv = ds->priv; 1399 1400 mutex_lock(&priv->reg_mutex); 1401 1402 dsa_switch_for_each_user_port(other_dp, ds) { 1403 int other_port = other_dp->index; 1404 1405 if (dp == other_dp) 1406 continue; 1407 1408 /* Remove this port from the port matrix of the other ports 1409 * in the same bridge. If the port is disabled, port matrix 1410 * is kept and not being setup until the port becomes enabled. 1411 */ 1412 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1413 continue; 1414 1415 if (priv->ports[other_port].enable) 1416 mt7530_clear(priv, MT7530_PCR_P(other_port), 1417 PCR_MATRIX(BIT(port))); 1418 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1419 } 1420 1421 /* Set the cpu port to be the only one in the port matrix of 1422 * this port. 1423 */ 1424 if (priv->ports[port].enable) 1425 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1426 PCR_MATRIX(BIT(cpu_dp->index))); 1427 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1428 1429 /* When a port is removed from the bridge, the port would be set up 1430 * back to the default as is at initial boot which is a VLAN-unaware 1431 * port. 1432 */ 1433 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1434 MT7530_PORT_MATRIX_MODE); 1435 1436 mutex_unlock(&priv->reg_mutex); 1437} 1438 1439static int 1440mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1441 const unsigned char *addr, u16 vid, 1442 struct dsa_db db) 1443{ 1444 struct mt7530_priv *priv = ds->priv; 1445 int ret; 1446 u8 port_mask = BIT(port); 1447 1448 mutex_lock(&priv->reg_mutex); 1449 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1450 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1451 mutex_unlock(&priv->reg_mutex); 1452 1453 return ret; 1454} 1455 1456static int 1457mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1458 const unsigned char *addr, u16 vid, 1459 struct dsa_db db) 1460{ 1461 struct mt7530_priv *priv = ds->priv; 1462 int ret; 1463 u8 port_mask = BIT(port); 1464 1465 mutex_lock(&priv->reg_mutex); 1466 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1467 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1468 mutex_unlock(&priv->reg_mutex); 1469 1470 return ret; 1471} 1472 1473static int 1474mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1475 dsa_fdb_dump_cb_t *cb, void *data) 1476{ 1477 struct mt7530_priv *priv = ds->priv; 1478 struct mt7530_fdb _fdb = { 0 }; 1479 int cnt = MT7530_NUM_FDB_RECORDS; 1480 int ret = 0; 1481 u32 rsp = 0; 1482 1483 mutex_lock(&priv->reg_mutex); 1484 1485 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1486 if (ret < 0) 1487 goto err; 1488 1489 do { 1490 if (rsp & ATC_SRCH_HIT) { 1491 mt7530_fdb_read(priv, &_fdb); 1492 if (_fdb.port_mask & BIT(port)) { 1493 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1494 data); 1495 if (ret < 0) 1496 break; 1497 } 1498 } 1499 } while (--cnt && 1500 !(rsp & ATC_SRCH_END) && 1501 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1502err: 1503 mutex_unlock(&priv->reg_mutex); 1504 1505 return 0; 1506} 1507 1508static int 1509mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1510 const struct switchdev_obj_port_mdb *mdb, 1511 struct dsa_db db) 1512{ 1513 struct mt7530_priv *priv = ds->priv; 1514 const u8 *addr = mdb->addr; 1515 u16 vid = mdb->vid; 1516 u8 port_mask = 0; 1517 int ret; 1518 1519 mutex_lock(&priv->reg_mutex); 1520 1521 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1522 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1523 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1524 & PORT_MAP_MASK; 1525 1526 port_mask |= BIT(port); 1527 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1528 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1529 1530 mutex_unlock(&priv->reg_mutex); 1531 1532 return ret; 1533} 1534 1535static int 1536mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1537 const struct switchdev_obj_port_mdb *mdb, 1538 struct dsa_db db) 1539{ 1540 struct mt7530_priv *priv = ds->priv; 1541 const u8 *addr = mdb->addr; 1542 u16 vid = mdb->vid; 1543 u8 port_mask = 0; 1544 int ret; 1545 1546 mutex_lock(&priv->reg_mutex); 1547 1548 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1549 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1550 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1551 & PORT_MAP_MASK; 1552 1553 port_mask &= ~BIT(port); 1554 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1555 port_mask ? STATIC_ENT : STATIC_EMP); 1556 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1557 1558 mutex_unlock(&priv->reg_mutex); 1559 1560 return ret; 1561} 1562 1563static int 1564mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1565{ 1566 struct mt7530_dummy_poll p; 1567 u32 val; 1568 int ret; 1569 1570 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1571 mt7530_write(priv, MT7530_VTCR, val); 1572 1573 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1574 ret = readx_poll_timeout(_mt7530_read, &p, val, 1575 !(val & VTCR_BUSY), 20, 20000); 1576 if (ret < 0) { 1577 dev_err(priv->dev, "poll timeout\n"); 1578 return ret; 1579 } 1580 1581 val = mt7530_read(priv, MT7530_VTCR); 1582 if (val & VTCR_INVALID) { 1583 dev_err(priv->dev, "read VTCR invalid\n"); 1584 return -EINVAL; 1585 } 1586 1587 return 0; 1588} 1589 1590static int 1591mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1592 struct netlink_ext_ack *extack) 1593{ 1594 struct dsa_port *dp = dsa_to_port(ds, port); 1595 struct dsa_port *cpu_dp = dp->cpu_dp; 1596 1597 if (vlan_filtering) { 1598 /* The port is being kept as VLAN-unaware port when bridge is 1599 * set up with vlan_filtering not being set, Otherwise, the 1600 * port and the corresponding CPU port is required the setup 1601 * for becoming a VLAN-aware port. 1602 */ 1603 mt7530_port_set_vlan_aware(ds, port); 1604 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1605 } else { 1606 mt7530_port_set_vlan_unaware(ds, port); 1607 } 1608 1609 return 0; 1610} 1611 1612static void 1613mt7530_hw_vlan_add(struct mt7530_priv *priv, 1614 struct mt7530_hw_vlan_entry *entry) 1615{ 1616 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1617 u8 new_members; 1618 u32 val; 1619 1620 new_members = entry->old_members | BIT(entry->port); 1621 1622 /* Validate the entry with independent learning, create egress tag per 1623 * VLAN and joining the port as one of the port members. 1624 */ 1625 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1626 VLAN_VALID; 1627 mt7530_write(priv, MT7530_VAWD1, val); 1628 1629 /* Decide whether adding tag or not for those outgoing packets from the 1630 * port inside the VLAN. 1631 * CPU port is always taken as a tagged port for serving more than one 1632 * VLANs across and also being applied with egress type stack mode for 1633 * that VLAN tags would be appended after hardware special tag used as 1634 * DSA tag. 1635 */ 1636 if (dsa_port_is_cpu(dp)) 1637 val = MT7530_VLAN_EGRESS_STACK; 1638 else if (entry->untagged) 1639 val = MT7530_VLAN_EGRESS_UNTAG; 1640 else 1641 val = MT7530_VLAN_EGRESS_TAG; 1642 mt7530_rmw(priv, MT7530_VAWD2, 1643 ETAG_CTRL_P_MASK(entry->port), 1644 ETAG_CTRL_P(entry->port, val)); 1645} 1646 1647static void 1648mt7530_hw_vlan_del(struct mt7530_priv *priv, 1649 struct mt7530_hw_vlan_entry *entry) 1650{ 1651 u8 new_members; 1652 u32 val; 1653 1654 new_members = entry->old_members & ~BIT(entry->port); 1655 1656 val = mt7530_read(priv, MT7530_VAWD1); 1657 if (!(val & VLAN_VALID)) { 1658 dev_err(priv->dev, 1659 "Cannot be deleted due to invalid entry\n"); 1660 return; 1661 } 1662 1663 if (new_members) { 1664 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1665 VLAN_VALID; 1666 mt7530_write(priv, MT7530_VAWD1, val); 1667 } else { 1668 mt7530_write(priv, MT7530_VAWD1, 0); 1669 mt7530_write(priv, MT7530_VAWD2, 0); 1670 } 1671} 1672 1673static void 1674mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1675 struct mt7530_hw_vlan_entry *entry, 1676 mt7530_vlan_op vlan_op) 1677{ 1678 u32 val; 1679 1680 /* Fetch entry */ 1681 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1682 1683 val = mt7530_read(priv, MT7530_VAWD1); 1684 1685 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1686 1687 /* Manipulate entry */ 1688 vlan_op(priv, entry); 1689 1690 /* Flush result to hardware */ 1691 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1692} 1693 1694static int 1695mt7530_setup_vlan0(struct mt7530_priv *priv) 1696{ 1697 u32 val; 1698 1699 /* Validate the entry with independent learning, keep the original 1700 * ingress tag attribute. 1701 */ 1702 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1703 VLAN_VALID; 1704 mt7530_write(priv, MT7530_VAWD1, val); 1705 1706 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1707} 1708 1709static int 1710mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1711 const struct switchdev_obj_port_vlan *vlan, 1712 struct netlink_ext_ack *extack) 1713{ 1714 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1715 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1716 struct mt7530_hw_vlan_entry new_entry; 1717 struct mt7530_priv *priv = ds->priv; 1718 1719 mutex_lock(&priv->reg_mutex); 1720 1721 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1722 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1723 1724 if (pvid) { 1725 priv->ports[port].pvid = vlan->vid; 1726 1727 /* Accept all frames if PVID is set */ 1728 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1729 MT7530_VLAN_ACC_ALL); 1730 1731 /* Only configure PVID if VLAN filtering is enabled */ 1732 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1733 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1734 G0_PORT_VID_MASK, 1735 G0_PORT_VID(vlan->vid)); 1736 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1737 /* This VLAN is overwritten without PVID, so unset it */ 1738 priv->ports[port].pvid = G0_PORT_VID_DEF; 1739 1740 /* Only accept tagged frames if the port is VLAN-aware */ 1741 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1742 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1743 MT7530_VLAN_ACC_TAGGED); 1744 1745 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1746 G0_PORT_VID_DEF); 1747 } 1748 1749 mutex_unlock(&priv->reg_mutex); 1750 1751 return 0; 1752} 1753 1754static int 1755mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1756 const struct switchdev_obj_port_vlan *vlan) 1757{ 1758 struct mt7530_hw_vlan_entry target_entry; 1759 struct mt7530_priv *priv = ds->priv; 1760 1761 mutex_lock(&priv->reg_mutex); 1762 1763 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1764 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1765 mt7530_hw_vlan_del); 1766 1767 /* PVID is being restored to the default whenever the PVID port 1768 * is being removed from the VLAN. 1769 */ 1770 if (priv->ports[port].pvid == vlan->vid) { 1771 priv->ports[port].pvid = G0_PORT_VID_DEF; 1772 1773 /* Only accept tagged frames if the port is VLAN-aware */ 1774 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1775 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1776 MT7530_VLAN_ACC_TAGGED); 1777 1778 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1779 G0_PORT_VID_DEF); 1780 } 1781 1782 1783 mutex_unlock(&priv->reg_mutex); 1784 1785 return 0; 1786} 1787 1788static int mt753x_mirror_port_get(unsigned int id, u32 val) 1789{ 1790 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1791 MIRROR_PORT(val); 1792} 1793 1794static int mt753x_mirror_port_set(unsigned int id, u32 val) 1795{ 1796 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1797 MIRROR_PORT(val); 1798} 1799 1800static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1801 struct dsa_mall_mirror_tc_entry *mirror, 1802 bool ingress, struct netlink_ext_ack *extack) 1803{ 1804 struct mt7530_priv *priv = ds->priv; 1805 int monitor_port; 1806 u32 val; 1807 1808 /* Check for existent entry */ 1809 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1810 return -EEXIST; 1811 1812 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1813 1814 /* MT7530 only supports one monitor port */ 1815 monitor_port = mt753x_mirror_port_get(priv->id, val); 1816 if (val & MT753X_MIRROR_EN(priv->id) && 1817 monitor_port != mirror->to_local_port) 1818 return -EEXIST; 1819 1820 val |= MT753X_MIRROR_EN(priv->id); 1821 val &= ~MT753X_MIRROR_MASK(priv->id); 1822 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1823 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1824 1825 val = mt7530_read(priv, MT7530_PCR_P(port)); 1826 if (ingress) { 1827 val |= PORT_RX_MIR; 1828 priv->mirror_rx |= BIT(port); 1829 } else { 1830 val |= PORT_TX_MIR; 1831 priv->mirror_tx |= BIT(port); 1832 } 1833 mt7530_write(priv, MT7530_PCR_P(port), val); 1834 1835 return 0; 1836} 1837 1838static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1839 struct dsa_mall_mirror_tc_entry *mirror) 1840{ 1841 struct mt7530_priv *priv = ds->priv; 1842 u32 val; 1843 1844 val = mt7530_read(priv, MT7530_PCR_P(port)); 1845 if (mirror->ingress) { 1846 val &= ~PORT_RX_MIR; 1847 priv->mirror_rx &= ~BIT(port); 1848 } else { 1849 val &= ~PORT_TX_MIR; 1850 priv->mirror_tx &= ~BIT(port); 1851 } 1852 mt7530_write(priv, MT7530_PCR_P(port), val); 1853 1854 if (!priv->mirror_rx && !priv->mirror_tx) { 1855 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1856 val &= ~MT753X_MIRROR_EN(priv->id); 1857 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1858 } 1859} 1860 1861static enum dsa_tag_protocol 1862mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1863 enum dsa_tag_protocol mp) 1864{ 1865 return DSA_TAG_PROTO_MTK; 1866} 1867 1868#ifdef CONFIG_GPIOLIB 1869static inline u32 1870mt7530_gpio_to_bit(unsigned int offset) 1871{ 1872 /* Map GPIO offset to register bit 1873 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1874 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1875 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1876 * [14:12] port 3 LED 0..2 as GPIO 9..11 1877 * [18:16] port 4 LED 0..2 as GPIO 12..14 1878 */ 1879 return BIT(offset + offset / 3); 1880} 1881 1882static int 1883mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1884{ 1885 struct mt7530_priv *priv = gpiochip_get_data(gc); 1886 u32 bit = mt7530_gpio_to_bit(offset); 1887 1888 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1889} 1890 1891static void 1892mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1893{ 1894 struct mt7530_priv *priv = gpiochip_get_data(gc); 1895 u32 bit = mt7530_gpio_to_bit(offset); 1896 1897 if (value) 1898 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1899 else 1900 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1901} 1902 1903static int 1904mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1905{ 1906 struct mt7530_priv *priv = gpiochip_get_data(gc); 1907 u32 bit = mt7530_gpio_to_bit(offset); 1908 1909 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1910 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1911} 1912 1913static int 1914mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1915{ 1916 struct mt7530_priv *priv = gpiochip_get_data(gc); 1917 u32 bit = mt7530_gpio_to_bit(offset); 1918 1919 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1920 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1921 1922 return 0; 1923} 1924 1925static int 1926mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1927{ 1928 struct mt7530_priv *priv = gpiochip_get_data(gc); 1929 u32 bit = mt7530_gpio_to_bit(offset); 1930 1931 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1932 1933 if (value) 1934 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1935 else 1936 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1937 1938 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1939 1940 return 0; 1941} 1942 1943static int 1944mt7530_setup_gpio(struct mt7530_priv *priv) 1945{ 1946 struct device *dev = priv->dev; 1947 struct gpio_chip *gc; 1948 1949 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1950 if (!gc) 1951 return -ENOMEM; 1952 1953 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1954 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1955 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1956 1957 gc->label = "mt7530"; 1958 gc->parent = dev; 1959 gc->owner = THIS_MODULE; 1960 gc->get_direction = mt7530_gpio_get_direction; 1961 gc->direction_input = mt7530_gpio_direction_input; 1962 gc->direction_output = mt7530_gpio_direction_output; 1963 gc->get = mt7530_gpio_get; 1964 gc->set = mt7530_gpio_set; 1965 gc->base = -1; 1966 gc->ngpio = 15; 1967 gc->can_sleep = true; 1968 1969 return devm_gpiochip_add_data(dev, gc, priv); 1970} 1971#endif /* CONFIG_GPIOLIB */ 1972 1973static irqreturn_t 1974mt7530_irq_thread_fn(int irq, void *dev_id) 1975{ 1976 struct mt7530_priv *priv = dev_id; 1977 bool handled = false; 1978 u32 val; 1979 int p; 1980 1981 mt7530_mutex_lock(priv); 1982 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1983 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1984 mt7530_mutex_unlock(priv); 1985 1986 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1987 if (BIT(p) & val) { 1988 unsigned int irq; 1989 1990 irq = irq_find_mapping(priv->irq_domain, p); 1991 handle_nested_irq(irq); 1992 handled = true; 1993 } 1994 } 1995 1996 return IRQ_RETVAL(handled); 1997} 1998 1999static void 2000mt7530_irq_mask(struct irq_data *d) 2001{ 2002 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2003 2004 priv->irq_enable &= ~BIT(d->hwirq); 2005} 2006 2007static void 2008mt7530_irq_unmask(struct irq_data *d) 2009{ 2010 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2011 2012 priv->irq_enable |= BIT(d->hwirq); 2013} 2014 2015static void 2016mt7530_irq_bus_lock(struct irq_data *d) 2017{ 2018 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2019 2020 mt7530_mutex_lock(priv); 2021} 2022 2023static void 2024mt7530_irq_bus_sync_unlock(struct irq_data *d) 2025{ 2026 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2027 2028 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2029 mt7530_mutex_unlock(priv); 2030} 2031 2032static struct irq_chip mt7530_irq_chip = { 2033 .name = KBUILD_MODNAME, 2034 .irq_mask = mt7530_irq_mask, 2035 .irq_unmask = mt7530_irq_unmask, 2036 .irq_bus_lock = mt7530_irq_bus_lock, 2037 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 2038}; 2039 2040static int 2041mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2042 irq_hw_number_t hwirq) 2043{ 2044 irq_set_chip_data(irq, domain->host_data); 2045 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2046 irq_set_nested_thread(irq, true); 2047 irq_set_noprobe(irq); 2048 2049 return 0; 2050} 2051 2052static const struct irq_domain_ops mt7530_irq_domain_ops = { 2053 .map = mt7530_irq_map, 2054 .xlate = irq_domain_xlate_onecell, 2055}; 2056 2057static void 2058mt7988_irq_mask(struct irq_data *d) 2059{ 2060 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2061 2062 priv->irq_enable &= ~BIT(d->hwirq); 2063 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2064} 2065 2066static void 2067mt7988_irq_unmask(struct irq_data *d) 2068{ 2069 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2070 2071 priv->irq_enable |= BIT(d->hwirq); 2072 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2073} 2074 2075static struct irq_chip mt7988_irq_chip = { 2076 .name = KBUILD_MODNAME, 2077 .irq_mask = mt7988_irq_mask, 2078 .irq_unmask = mt7988_irq_unmask, 2079}; 2080 2081static int 2082mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2083 irq_hw_number_t hwirq) 2084{ 2085 irq_set_chip_data(irq, domain->host_data); 2086 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2087 irq_set_nested_thread(irq, true); 2088 irq_set_noprobe(irq); 2089 2090 return 0; 2091} 2092 2093static const struct irq_domain_ops mt7988_irq_domain_ops = { 2094 .map = mt7988_irq_map, 2095 .xlate = irq_domain_xlate_onecell, 2096}; 2097 2098static void 2099mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2100{ 2101 struct dsa_switch *ds = priv->ds; 2102 int p; 2103 2104 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2105 if (BIT(p) & ds->phys_mii_mask) { 2106 unsigned int irq; 2107 2108 irq = irq_create_mapping(priv->irq_domain, p); 2109 ds->slave_mii_bus->irq[p] = irq; 2110 } 2111 } 2112} 2113 2114static int 2115mt7530_setup_irq(struct mt7530_priv *priv) 2116{ 2117 struct device *dev = priv->dev; 2118 struct device_node *np = dev->of_node; 2119 int ret; 2120 2121 if (!of_property_read_bool(np, "interrupt-controller")) { 2122 dev_info(dev, "no interrupt support\n"); 2123 return 0; 2124 } 2125 2126 priv->irq = of_irq_get(np, 0); 2127 if (priv->irq <= 0) { 2128 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2129 return priv->irq ? : -EINVAL; 2130 } 2131 2132 if (priv->id == ID_MT7988) 2133 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2134 &mt7988_irq_domain_ops, 2135 priv); 2136 else 2137 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2138 &mt7530_irq_domain_ops, 2139 priv); 2140 2141 if (!priv->irq_domain) { 2142 dev_err(dev, "failed to create IRQ domain\n"); 2143 return -ENOMEM; 2144 } 2145 2146 /* This register must be set for MT7530 to properly fire interrupts */ 2147 if (priv->id != ID_MT7531) 2148 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2149 2150 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2151 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2152 if (ret) { 2153 irq_domain_remove(priv->irq_domain); 2154 dev_err(dev, "failed to request IRQ: %d\n", ret); 2155 return ret; 2156 } 2157 2158 return 0; 2159} 2160 2161static void 2162mt7530_free_mdio_irq(struct mt7530_priv *priv) 2163{ 2164 int p; 2165 2166 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2167 if (BIT(p) & priv->ds->phys_mii_mask) { 2168 unsigned int irq; 2169 2170 irq = irq_find_mapping(priv->irq_domain, p); 2171 irq_dispose_mapping(irq); 2172 } 2173 } 2174} 2175 2176static void 2177mt7530_free_irq_common(struct mt7530_priv *priv) 2178{ 2179 free_irq(priv->irq, priv); 2180 irq_domain_remove(priv->irq_domain); 2181} 2182 2183static void 2184mt7530_free_irq(struct mt7530_priv *priv) 2185{ 2186 mt7530_free_mdio_irq(priv); 2187 mt7530_free_irq_common(priv); 2188} 2189 2190static int 2191mt7530_setup_mdio(struct mt7530_priv *priv) 2192{ 2193 struct dsa_switch *ds = priv->ds; 2194 struct device *dev = priv->dev; 2195 struct mii_bus *bus; 2196 static int idx; 2197 int ret; 2198 2199 bus = devm_mdiobus_alloc(dev); 2200 if (!bus) 2201 return -ENOMEM; 2202 2203 ds->slave_mii_bus = bus; 2204 bus->priv = priv; 2205 bus->name = KBUILD_MODNAME "-mii"; 2206 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2207 bus->read = mt753x_phy_read_c22; 2208 bus->write = mt753x_phy_write_c22; 2209 bus->read_c45 = mt753x_phy_read_c45; 2210 bus->write_c45 = mt753x_phy_write_c45; 2211 bus->parent = dev; 2212 bus->phy_mask = ~ds->phys_mii_mask; 2213 2214 if (priv->irq) 2215 mt7530_setup_mdio_irq(priv); 2216 2217 ret = devm_mdiobus_register(dev, bus); 2218 if (ret) { 2219 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2220 if (priv->irq) 2221 mt7530_free_mdio_irq(priv); 2222 } 2223 2224 return ret; 2225} 2226 2227static int 2228mt7530_setup(struct dsa_switch *ds) 2229{ 2230 struct mt7530_priv *priv = ds->priv; 2231 struct device_node *dn = NULL; 2232 struct device_node *phy_node; 2233 struct device_node *mac_np; 2234 struct mt7530_dummy_poll p; 2235 phy_interface_t interface; 2236 struct dsa_port *cpu_dp; 2237 u32 id, val; 2238 int ret, i; 2239 2240 /* The parent node of master netdev which holds the common system 2241 * controller also is the container for two GMACs nodes representing 2242 * as two netdev instances. 2243 */ 2244 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2245 dn = cpu_dp->master->dev.of_node->parent; 2246 /* It doesn't matter which CPU port is found first, 2247 * their masters should share the same parent OF node 2248 */ 2249 break; 2250 } 2251 2252 if (!dn) { 2253 dev_err(ds->dev, "parent OF node of DSA master not found"); 2254 return -EINVAL; 2255 } 2256 2257 ds->assisted_learning_on_cpu_port = true; 2258 ds->mtu_enforcement_ingress = true; 2259 2260 if (priv->id == ID_MT7530) { 2261 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2262 ret = regulator_enable(priv->core_pwr); 2263 if (ret < 0) { 2264 dev_err(priv->dev, 2265 "Failed to enable core power: %d\n", ret); 2266 return ret; 2267 } 2268 2269 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2270 ret = regulator_enable(priv->io_pwr); 2271 if (ret < 0) { 2272 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2273 ret); 2274 return ret; 2275 } 2276 } 2277 2278 /* Reset whole chip through gpio pin or memory-mapped registers for 2279 * different type of hardware 2280 */ 2281 if (priv->mcm) { 2282 reset_control_assert(priv->rstc); 2283 usleep_range(5000, 5100); 2284 reset_control_deassert(priv->rstc); 2285 } else { 2286 gpiod_set_value_cansleep(priv->reset, 0); 2287 usleep_range(5000, 5100); 2288 gpiod_set_value_cansleep(priv->reset, 1); 2289 } 2290 2291 /* Waiting for MT7530 got to stable */ 2292 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2293 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2294 20, 1000000); 2295 if (ret < 0) { 2296 dev_err(priv->dev, "reset timeout\n"); 2297 return ret; 2298 } 2299 2300 id = mt7530_read(priv, MT7530_CREV); 2301 id >>= CHIP_NAME_SHIFT; 2302 if (id != MT7530_ID) { 2303 dev_err(priv->dev, "chip %x can't be supported\n", id); 2304 return -ENODEV; 2305 } 2306 2307 /* Reset the switch through internal reset */ 2308 mt7530_write(priv, MT7530_SYS_CTRL, 2309 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2310 SYS_CTRL_REG_RST); 2311 2312 mt7530_pll_setup(priv); 2313 2314 /* Lower Tx driving for TRGMII path */ 2315 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2316 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2317 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2318 2319 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2320 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2321 RD_TAP_MASK, RD_TAP(16)); 2322 2323 /* Enable port 6 */ 2324 val = mt7530_read(priv, MT7530_MHWTRAP); 2325 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2326 val |= MHWTRAP_MANUAL; 2327 mt7530_write(priv, MT7530_MHWTRAP, val); 2328 2329 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2330 2331 mt753x_trap_frames(priv); 2332 2333 /* Enable and reset MIB counters */ 2334 mt7530_mib_reset(ds); 2335 2336 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2337 /* Disable forwarding by default on all ports */ 2338 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2339 PCR_MATRIX_CLR); 2340 2341 /* Disable learning by default on all ports */ 2342 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2343 2344 if (dsa_is_cpu_port(ds, i)) { 2345 ret = mt753x_cpu_port_enable(ds, i); 2346 if (ret) 2347 return ret; 2348 } else { 2349 mt7530_port_disable(ds, i); 2350 2351 /* Set default PVID to 0 on all user ports */ 2352 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2353 G0_PORT_VID_DEF); 2354 } 2355 /* Enable consistent egress tag */ 2356 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2357 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2358 } 2359 2360 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2361 ret = mt7530_setup_vlan0(priv); 2362 if (ret) 2363 return ret; 2364 2365 /* Setup port 5 */ 2366 priv->p5_intf_sel = P5_DISABLED; 2367 interface = PHY_INTERFACE_MODE_NA; 2368 2369 if (!dsa_is_unused_port(ds, 5)) { 2370 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2371 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2372 if (ret && ret != -ENODEV) 2373 return ret; 2374 } else { 2375 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2376 for_each_child_of_node(dn, mac_np) { 2377 if (!of_device_is_compatible(mac_np, 2378 "mediatek,eth-mac")) 2379 continue; 2380 2381 ret = of_property_read_u32(mac_np, "reg", &id); 2382 if (ret < 0 || id != 1) 2383 continue; 2384 2385 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2386 if (!phy_node) 2387 continue; 2388 2389 if (phy_node->parent == priv->dev->of_node->parent) { 2390 ret = of_get_phy_mode(mac_np, &interface); 2391 if (ret && ret != -ENODEV) { 2392 of_node_put(mac_np); 2393 of_node_put(phy_node); 2394 return ret; 2395 } 2396 id = of_mdio_parse_addr(ds->dev, phy_node); 2397 if (id == 0) 2398 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2399 if (id == 4) 2400 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2401 } 2402 of_node_put(mac_np); 2403 of_node_put(phy_node); 2404 break; 2405 } 2406 } 2407 2408#ifdef CONFIG_GPIOLIB 2409 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2410 ret = mt7530_setup_gpio(priv); 2411 if (ret) 2412 return ret; 2413 } 2414#endif /* CONFIG_GPIOLIB */ 2415 2416 mt7530_setup_port5(ds, interface); 2417 2418 /* Flush the FDB table */ 2419 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2420 if (ret < 0) 2421 return ret; 2422 2423 return 0; 2424} 2425 2426static int 2427mt7531_setup_common(struct dsa_switch *ds) 2428{ 2429 struct mt7530_priv *priv = ds->priv; 2430 int ret, i; 2431 2432 mt753x_trap_frames(priv); 2433 2434 /* Enable and reset MIB counters */ 2435 mt7530_mib_reset(ds); 2436 2437 /* Disable flooding on all ports */ 2438 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2439 UNU_FFP_MASK); 2440 2441 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2442 /* Disable forwarding by default on all ports */ 2443 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2444 PCR_MATRIX_CLR); 2445 2446 /* Disable learning by default on all ports */ 2447 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2448 2449 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2450 2451 if (dsa_is_cpu_port(ds, i)) { 2452 ret = mt753x_cpu_port_enable(ds, i); 2453 if (ret) 2454 return ret; 2455 } else { 2456 mt7530_port_disable(ds, i); 2457 2458 /* Set default PVID to 0 on all user ports */ 2459 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2460 G0_PORT_VID_DEF); 2461 } 2462 2463 /* Enable consistent egress tag */ 2464 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2465 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2466 } 2467 2468 /* Flush the FDB table */ 2469 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2470 if (ret < 0) 2471 return ret; 2472 2473 return 0; 2474} 2475 2476static int 2477mt7531_setup(struct dsa_switch *ds) 2478{ 2479 struct mt7530_priv *priv = ds->priv; 2480 struct mt7530_dummy_poll p; 2481 u32 val, id; 2482 int ret, i; 2483 2484 /* Reset whole chip through gpio pin or memory-mapped registers for 2485 * different type of hardware 2486 */ 2487 if (priv->mcm) { 2488 reset_control_assert(priv->rstc); 2489 usleep_range(5000, 5100); 2490 reset_control_deassert(priv->rstc); 2491 } else { 2492 gpiod_set_value_cansleep(priv->reset, 0); 2493 usleep_range(5000, 5100); 2494 gpiod_set_value_cansleep(priv->reset, 1); 2495 } 2496 2497 /* Waiting for MT7530 got to stable */ 2498 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2499 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2500 20, 1000000); 2501 if (ret < 0) { 2502 dev_err(priv->dev, "reset timeout\n"); 2503 return ret; 2504 } 2505 2506 id = mt7530_read(priv, MT7531_CREV); 2507 id >>= CHIP_NAME_SHIFT; 2508 2509 if (id != MT7531_ID) { 2510 dev_err(priv->dev, "chip %x can't be supported\n", id); 2511 return -ENODEV; 2512 } 2513 2514 /* all MACs must be forced link-down before sw reset */ 2515 for (i = 0; i < MT7530_NUM_PORTS; i++) 2516 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2517 2518 /* Reset the switch through internal reset */ 2519 mt7530_write(priv, MT7530_SYS_CTRL, 2520 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2521 SYS_CTRL_REG_RST); 2522 2523 mt7531_pll_setup(priv); 2524 2525 if (mt7531_dual_sgmii_supported(priv)) { 2526 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2527 2528 /* Let ds->slave_mii_bus be able to access external phy. */ 2529 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2530 MT7531_EXT_P_MDC_11); 2531 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2532 MT7531_EXT_P_MDIO_12); 2533 } else { 2534 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2535 } 2536 dev_dbg(ds->dev, "P5 support %s interface\n", 2537 p5_intf_modes(priv->p5_intf_sel)); 2538 2539 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2540 MT7531_GPIO0_INTERRUPT); 2541 2542 /* Let phylink decide the interface later. */ 2543 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2544 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2545 2546 /* Enable PHY core PLL, since phy_device has not yet been created 2547 * provided for phy_[read,write]_mmd_indirect is called, we provide 2548 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2549 * function. 2550 */ 2551 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2552 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2553 val |= MT7531_PHY_PLL_BYPASS_MODE; 2554 val &= ~MT7531_PHY_PLL_OFF; 2555 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2556 CORE_PLL_GROUP4, val); 2557 2558 mt7531_setup_common(ds); 2559 2560 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2561 ret = mt7530_setup_vlan0(priv); 2562 if (ret) 2563 return ret; 2564 2565 ds->assisted_learning_on_cpu_port = true; 2566 ds->mtu_enforcement_ingress = true; 2567 2568 return 0; 2569} 2570 2571static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2572 struct phylink_config *config) 2573{ 2574 switch (port) { 2575 case 0 ... 4: /* Internal phy */ 2576 __set_bit(PHY_INTERFACE_MODE_GMII, 2577 config->supported_interfaces); 2578 break; 2579 2580 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2581 phy_interface_set_rgmii(config->supported_interfaces); 2582 __set_bit(PHY_INTERFACE_MODE_MII, 2583 config->supported_interfaces); 2584 __set_bit(PHY_INTERFACE_MODE_GMII, 2585 config->supported_interfaces); 2586 break; 2587 2588 case 6: /* 1st cpu port */ 2589 __set_bit(PHY_INTERFACE_MODE_RGMII, 2590 config->supported_interfaces); 2591 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2592 config->supported_interfaces); 2593 break; 2594 } 2595} 2596 2597static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2598{ 2599 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2600} 2601 2602static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2603 struct phylink_config *config) 2604{ 2605 struct mt7530_priv *priv = ds->priv; 2606 2607 switch (port) { 2608 case 0 ... 4: /* Internal phy */ 2609 __set_bit(PHY_INTERFACE_MODE_GMII, 2610 config->supported_interfaces); 2611 break; 2612 2613 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2614 if (mt7531_is_rgmii_port(priv, port)) { 2615 phy_interface_set_rgmii(config->supported_interfaces); 2616 break; 2617 } 2618 fallthrough; 2619 2620 case 6: /* 1st cpu port supports sgmii/8023z only */ 2621 __set_bit(PHY_INTERFACE_MODE_SGMII, 2622 config->supported_interfaces); 2623 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2624 config->supported_interfaces); 2625 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2626 config->supported_interfaces); 2627 2628 config->mac_capabilities |= MAC_2500FD; 2629 break; 2630 } 2631} 2632 2633static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2634 struct phylink_config *config) 2635{ 2636 phy_interface_zero(config->supported_interfaces); 2637 2638 switch (port) { 2639 case 0 ... 4: /* Internal phy */ 2640 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2641 config->supported_interfaces); 2642 break; 2643 2644 case 6: 2645 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2646 config->supported_interfaces); 2647 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2648 MAC_10000FD; 2649 } 2650} 2651 2652static int 2653mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2654{ 2655 struct mt7530_priv *priv = ds->priv; 2656 2657 return priv->info->pad_setup(ds, state->interface); 2658} 2659 2660static int 2661mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2662 phy_interface_t interface) 2663{ 2664 struct mt7530_priv *priv = ds->priv; 2665 2666 /* Only need to setup port5. */ 2667 if (port != 5) 2668 return 0; 2669 2670 mt7530_setup_port5(priv->ds, interface); 2671 2672 return 0; 2673} 2674 2675static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2676 phy_interface_t interface, 2677 struct phy_device *phydev) 2678{ 2679 u32 val; 2680 2681 if (!mt7531_is_rgmii_port(priv, port)) { 2682 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2683 port); 2684 return -EINVAL; 2685 } 2686 2687 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2688 val |= GP_CLK_EN; 2689 val &= ~GP_MODE_MASK; 2690 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2691 val &= ~CLK_SKEW_IN_MASK; 2692 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2693 val &= ~CLK_SKEW_OUT_MASK; 2694 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2695 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2696 2697 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2698 if (!phydev || phy_driver_is_genphy(phydev)) { 2699 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2700 switch (interface) { 2701 case PHY_INTERFACE_MODE_RGMII: 2702 val |= TXCLK_NO_REVERSE; 2703 val |= RXCLK_NO_DELAY; 2704 break; 2705 case PHY_INTERFACE_MODE_RGMII_RXID: 2706 val |= TXCLK_NO_REVERSE; 2707 break; 2708 case PHY_INTERFACE_MODE_RGMII_TXID: 2709 val |= RXCLK_NO_DELAY; 2710 break; 2711 case PHY_INTERFACE_MODE_RGMII_ID: 2712 break; 2713 default: 2714 return -EINVAL; 2715 } 2716 } 2717 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2718 2719 return 0; 2720} 2721 2722static bool mt753x_is_mac_port(u32 port) 2723{ 2724 return (port == 5 || port == 6); 2725} 2726 2727static int 2728mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2729 phy_interface_t interface) 2730{ 2731 if (dsa_is_cpu_port(ds, port) && 2732 interface == PHY_INTERFACE_MODE_INTERNAL) 2733 return 0; 2734 2735 return -EINVAL; 2736} 2737 2738static int 2739mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2740 phy_interface_t interface) 2741{ 2742 struct mt7530_priv *priv = ds->priv; 2743 struct phy_device *phydev; 2744 struct dsa_port *dp; 2745 2746 if (!mt753x_is_mac_port(port)) { 2747 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2748 return -EINVAL; 2749 } 2750 2751 switch (interface) { 2752 case PHY_INTERFACE_MODE_RGMII: 2753 case PHY_INTERFACE_MODE_RGMII_ID: 2754 case PHY_INTERFACE_MODE_RGMII_RXID: 2755 case PHY_INTERFACE_MODE_RGMII_TXID: 2756 dp = dsa_to_port(ds, port); 2757 phydev = dp->slave->phydev; 2758 return mt7531_rgmii_setup(priv, port, interface, phydev); 2759 case PHY_INTERFACE_MODE_SGMII: 2760 case PHY_INTERFACE_MODE_NA: 2761 case PHY_INTERFACE_MODE_1000BASEX: 2762 case PHY_INTERFACE_MODE_2500BASEX: 2763 /* handled in SGMII PCS driver */ 2764 return 0; 2765 default: 2766 return -EINVAL; 2767 } 2768 2769 return -EINVAL; 2770} 2771 2772static int 2773mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2774 const struct phylink_link_state *state) 2775{ 2776 struct mt7530_priv *priv = ds->priv; 2777 2778 return priv->info->mac_port_config(ds, port, mode, state->interface); 2779} 2780 2781static struct phylink_pcs * 2782mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2783 phy_interface_t interface) 2784{ 2785 struct mt7530_priv *priv = ds->priv; 2786 2787 switch (interface) { 2788 case PHY_INTERFACE_MODE_TRGMII: 2789 return &priv->pcs[port].pcs; 2790 case PHY_INTERFACE_MODE_SGMII: 2791 case PHY_INTERFACE_MODE_1000BASEX: 2792 case PHY_INTERFACE_MODE_2500BASEX: 2793 return priv->ports[port].sgmii_pcs; 2794 default: 2795 return NULL; 2796 } 2797} 2798 2799static void 2800mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2801 const struct phylink_link_state *state) 2802{ 2803 struct mt7530_priv *priv = ds->priv; 2804 u32 mcr_cur, mcr_new; 2805 2806 switch (port) { 2807 case 0 ... 4: /* Internal phy */ 2808 if (state->interface != PHY_INTERFACE_MODE_GMII && 2809 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2810 goto unsupported; 2811 break; 2812 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2813 if (priv->p5_interface == state->interface) 2814 break; 2815 2816 if (mt753x_mac_config(ds, port, mode, state) < 0) 2817 goto unsupported; 2818 2819 if (priv->p5_intf_sel != P5_DISABLED) 2820 priv->p5_interface = state->interface; 2821 break; 2822 case 6: /* 1st cpu port */ 2823 if (priv->p6_interface == state->interface) 2824 break; 2825 2826 mt753x_pad_setup(ds, state); 2827 2828 if (mt753x_mac_config(ds, port, mode, state) < 0) 2829 goto unsupported; 2830 2831 priv->p6_interface = state->interface; 2832 break; 2833 default: 2834unsupported: 2835 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2836 __func__, phy_modes(state->interface), port); 2837 return; 2838 } 2839 2840 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2841 mcr_new = mcr_cur; 2842 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2843 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2844 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2845 2846 /* Are we connected to external phy */ 2847 if (port == 5 && dsa_is_user_port(ds, 5)) 2848 mcr_new |= PMCR_EXT_PHY; 2849 2850 if (mcr_new != mcr_cur) 2851 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2852} 2853 2854static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2855 unsigned int mode, 2856 phy_interface_t interface) 2857{ 2858 struct mt7530_priv *priv = ds->priv; 2859 2860 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2861} 2862 2863static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2864 unsigned int mode, 2865 phy_interface_t interface, 2866 int speed, int duplex) 2867{ 2868 if (pcs->ops->pcs_link_up) 2869 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2870} 2871 2872static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2873 unsigned int mode, 2874 phy_interface_t interface, 2875 struct phy_device *phydev, 2876 int speed, int duplex, 2877 bool tx_pause, bool rx_pause) 2878{ 2879 struct mt7530_priv *priv = ds->priv; 2880 u32 mcr; 2881 2882 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2883 2884 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2885 * variants. 2886 */ 2887 if (interface == PHY_INTERFACE_MODE_TRGMII || 2888 (phy_interface_mode_is_8023z(interface))) { 2889 speed = SPEED_1000; 2890 duplex = DUPLEX_FULL; 2891 } 2892 2893 switch (speed) { 2894 case SPEED_1000: 2895 mcr |= PMCR_FORCE_SPEED_1000; 2896 break; 2897 case SPEED_100: 2898 mcr |= PMCR_FORCE_SPEED_100; 2899 break; 2900 } 2901 if (duplex == DUPLEX_FULL) { 2902 mcr |= PMCR_FORCE_FDX; 2903 if (tx_pause) 2904 mcr |= PMCR_TX_FC_EN; 2905 if (rx_pause) 2906 mcr |= PMCR_RX_FC_EN; 2907 } 2908 2909 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2910 switch (speed) { 2911 case SPEED_1000: 2912 mcr |= PMCR_FORCE_EEE1G; 2913 break; 2914 case SPEED_100: 2915 mcr |= PMCR_FORCE_EEE100; 2916 break; 2917 } 2918 } 2919 2920 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2921} 2922 2923static int 2924mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2925{ 2926 struct mt7530_priv *priv = ds->priv; 2927 phy_interface_t interface; 2928 int speed; 2929 int ret; 2930 2931 switch (port) { 2932 case 5: 2933 if (mt7531_is_rgmii_port(priv, port)) 2934 interface = PHY_INTERFACE_MODE_RGMII; 2935 else 2936 interface = PHY_INTERFACE_MODE_2500BASEX; 2937 2938 priv->p5_interface = interface; 2939 break; 2940 case 6: 2941 interface = PHY_INTERFACE_MODE_2500BASEX; 2942 2943 priv->p6_interface = interface; 2944 break; 2945 default: 2946 return -EINVAL; 2947 } 2948 2949 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2950 speed = SPEED_2500; 2951 else 2952 speed = SPEED_1000; 2953 2954 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2955 if (ret) 2956 return ret; 2957 mt7530_write(priv, MT7530_PMCR_P(port), 2958 PMCR_CPU_PORT_SETTING(priv->id)); 2959 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2960 interface, speed, DUPLEX_FULL); 2961 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2962 speed, DUPLEX_FULL, true, true); 2963 2964 return 0; 2965} 2966 2967static int 2968mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2969{ 2970 struct mt7530_priv *priv = ds->priv; 2971 2972 mt7530_write(priv, MT7530_PMCR_P(port), 2973 PMCR_CPU_PORT_SETTING(priv->id)); 2974 2975 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2976 PHY_INTERFACE_MODE_INTERNAL, NULL, 2977 SPEED_10000, DUPLEX_FULL, true, true); 2978 2979 return 0; 2980} 2981 2982static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2983 struct phylink_config *config) 2984{ 2985 struct mt7530_priv *priv = ds->priv; 2986 2987 /* This switch only supports full-duplex at 1Gbps */ 2988 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2989 MAC_10 | MAC_100 | MAC_1000FD; 2990 2991 priv->info->mac_port_get_caps(ds, port, config); 2992} 2993 2994static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2995 unsigned long *supported, 2996 const struct phylink_link_state *state) 2997{ 2998 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2999 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3000 phy_interface_mode_is_8023z(state->interface)) 3001 phylink_clear(supported, Autoneg); 3002 3003 return 0; 3004} 3005 3006static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 3007 struct phylink_link_state *state) 3008{ 3009 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3010 int port = pcs_to_mt753x_pcs(pcs)->port; 3011 u32 pmsr; 3012 3013 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3014 3015 state->link = (pmsr & PMSR_LINK); 3016 state->an_complete = state->link; 3017 state->duplex = !!(pmsr & PMSR_DPX); 3018 3019 switch (pmsr & PMSR_SPEED_MASK) { 3020 case PMSR_SPEED_10: 3021 state->speed = SPEED_10; 3022 break; 3023 case PMSR_SPEED_100: 3024 state->speed = SPEED_100; 3025 break; 3026 case PMSR_SPEED_1000: 3027 state->speed = SPEED_1000; 3028 break; 3029 default: 3030 state->speed = SPEED_UNKNOWN; 3031 break; 3032 } 3033 3034 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3035 if (pmsr & PMSR_RX_FC) 3036 state->pause |= MLO_PAUSE_RX; 3037 if (pmsr & PMSR_TX_FC) 3038 state->pause |= MLO_PAUSE_TX; 3039} 3040 3041static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3042 phy_interface_t interface, 3043 const unsigned long *advertising, 3044 bool permit_pause_to_mac) 3045{ 3046 return 0; 3047} 3048 3049static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3050{ 3051} 3052 3053static const struct phylink_pcs_ops mt7530_pcs_ops = { 3054 .pcs_validate = mt753x_pcs_validate, 3055 .pcs_get_state = mt7530_pcs_get_state, 3056 .pcs_config = mt753x_pcs_config, 3057 .pcs_an_restart = mt7530_pcs_an_restart, 3058}; 3059 3060static int 3061mt753x_setup(struct dsa_switch *ds) 3062{ 3063 struct mt7530_priv *priv = ds->priv; 3064 int i, ret; 3065 3066 /* Initialise the PCS devices */ 3067 for (i = 0; i < priv->ds->num_ports; i++) { 3068 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3069 priv->pcs[i].pcs.neg_mode = true; 3070 priv->pcs[i].priv = priv; 3071 priv->pcs[i].port = i; 3072 } 3073 3074 ret = priv->info->sw_setup(ds); 3075 if (ret) 3076 return ret; 3077 3078 ret = mt7530_setup_irq(priv); 3079 if (ret) 3080 return ret; 3081 3082 ret = mt7530_setup_mdio(priv); 3083 if (ret && priv->irq) 3084 mt7530_free_irq_common(priv); 3085 3086 if (priv->create_sgmii) { 3087 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); 3088 if (ret && priv->irq) 3089 mt7530_free_irq(priv); 3090 } 3091 3092 return ret; 3093} 3094 3095static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3096 struct ethtool_eee *e) 3097{ 3098 struct mt7530_priv *priv = ds->priv; 3099 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3100 3101 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3102 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3103 3104 return 0; 3105} 3106 3107static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3108 struct ethtool_eee *e) 3109{ 3110 struct mt7530_priv *priv = ds->priv; 3111 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3112 3113 if (e->tx_lpi_timer > 0xFFF) 3114 return -EINVAL; 3115 3116 set = SET_LPI_THRESH(e->tx_lpi_timer); 3117 if (!e->tx_lpi_enabled) 3118 /* Force LPI Mode without a delay */ 3119 set |= LPI_MODE_EN; 3120 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3121 3122 return 0; 3123} 3124 3125static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3126{ 3127 return 0; 3128} 3129 3130static int mt7988_setup(struct dsa_switch *ds) 3131{ 3132 struct mt7530_priv *priv = ds->priv; 3133 3134 /* Reset the switch */ 3135 reset_control_assert(priv->rstc); 3136 usleep_range(20, 50); 3137 reset_control_deassert(priv->rstc); 3138 usleep_range(20, 50); 3139 3140 /* Reset the switch PHYs */ 3141 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3142 3143 return mt7531_setup_common(ds); 3144} 3145 3146const struct dsa_switch_ops mt7530_switch_ops = { 3147 .get_tag_protocol = mtk_get_tag_protocol, 3148 .setup = mt753x_setup, 3149 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3150 .get_strings = mt7530_get_strings, 3151 .get_ethtool_stats = mt7530_get_ethtool_stats, 3152 .get_sset_count = mt7530_get_sset_count, 3153 .set_ageing_time = mt7530_set_ageing_time, 3154 .port_enable = mt7530_port_enable, 3155 .port_disable = mt7530_port_disable, 3156 .port_change_mtu = mt7530_port_change_mtu, 3157 .port_max_mtu = mt7530_port_max_mtu, 3158 .port_stp_state_set = mt7530_stp_state_set, 3159 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3160 .port_bridge_flags = mt7530_port_bridge_flags, 3161 .port_bridge_join = mt7530_port_bridge_join, 3162 .port_bridge_leave = mt7530_port_bridge_leave, 3163 .port_fdb_add = mt7530_port_fdb_add, 3164 .port_fdb_del = mt7530_port_fdb_del, 3165 .port_fdb_dump = mt7530_port_fdb_dump, 3166 .port_mdb_add = mt7530_port_mdb_add, 3167 .port_mdb_del = mt7530_port_mdb_del, 3168 .port_vlan_filtering = mt7530_port_vlan_filtering, 3169 .port_vlan_add = mt7530_port_vlan_add, 3170 .port_vlan_del = mt7530_port_vlan_del, 3171 .port_mirror_add = mt753x_port_mirror_add, 3172 .port_mirror_del = mt753x_port_mirror_del, 3173 .phylink_get_caps = mt753x_phylink_get_caps, 3174 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3175 .phylink_mac_config = mt753x_phylink_mac_config, 3176 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3177 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3178 .get_mac_eee = mt753x_get_mac_eee, 3179 .set_mac_eee = mt753x_set_mac_eee, 3180}; 3181EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3182 3183const struct mt753x_info mt753x_table[] = { 3184 [ID_MT7621] = { 3185 .id = ID_MT7621, 3186 .pcs_ops = &mt7530_pcs_ops, 3187 .sw_setup = mt7530_setup, 3188 .phy_read_c22 = mt7530_phy_read_c22, 3189 .phy_write_c22 = mt7530_phy_write_c22, 3190 .phy_read_c45 = mt7530_phy_read_c45, 3191 .phy_write_c45 = mt7530_phy_write_c45, 3192 .pad_setup = mt7530_pad_clk_setup, 3193 .mac_port_get_caps = mt7530_mac_port_get_caps, 3194 .mac_port_config = mt7530_mac_config, 3195 }, 3196 [ID_MT7530] = { 3197 .id = ID_MT7530, 3198 .pcs_ops = &mt7530_pcs_ops, 3199 .sw_setup = mt7530_setup, 3200 .phy_read_c22 = mt7530_phy_read_c22, 3201 .phy_write_c22 = mt7530_phy_write_c22, 3202 .phy_read_c45 = mt7530_phy_read_c45, 3203 .phy_write_c45 = mt7530_phy_write_c45, 3204 .pad_setup = mt7530_pad_clk_setup, 3205 .mac_port_get_caps = mt7530_mac_port_get_caps, 3206 .mac_port_config = mt7530_mac_config, 3207 }, 3208 [ID_MT7531] = { 3209 .id = ID_MT7531, 3210 .pcs_ops = &mt7530_pcs_ops, 3211 .sw_setup = mt7531_setup, 3212 .phy_read_c22 = mt7531_ind_c22_phy_read, 3213 .phy_write_c22 = mt7531_ind_c22_phy_write, 3214 .phy_read_c45 = mt7531_ind_c45_phy_read, 3215 .phy_write_c45 = mt7531_ind_c45_phy_write, 3216 .pad_setup = mt7531_pad_setup, 3217 .cpu_port_config = mt7531_cpu_port_config, 3218 .mac_port_get_caps = mt7531_mac_port_get_caps, 3219 .mac_port_config = mt7531_mac_config, 3220 }, 3221 [ID_MT7988] = { 3222 .id = ID_MT7988, 3223 .pcs_ops = &mt7530_pcs_ops, 3224 .sw_setup = mt7988_setup, 3225 .phy_read_c22 = mt7531_ind_c22_phy_read, 3226 .phy_write_c22 = mt7531_ind_c22_phy_write, 3227 .phy_read_c45 = mt7531_ind_c45_phy_read, 3228 .phy_write_c45 = mt7531_ind_c45_phy_write, 3229 .pad_setup = mt7988_pad_setup, 3230 .cpu_port_config = mt7988_cpu_port_config, 3231 .mac_port_get_caps = mt7988_mac_port_get_caps, 3232 .mac_port_config = mt7988_mac_config, 3233 }, 3234}; 3235EXPORT_SYMBOL_GPL(mt753x_table); 3236 3237int 3238mt7530_probe_common(struct mt7530_priv *priv) 3239{ 3240 struct device *dev = priv->dev; 3241 3242 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3243 if (!priv->ds) 3244 return -ENOMEM; 3245 3246 priv->ds->dev = dev; 3247 priv->ds->num_ports = MT7530_NUM_PORTS; 3248 3249 /* Get the hardware identifier from the devicetree node. 3250 * We will need it for some of the clock and regulator setup. 3251 */ 3252 priv->info = of_device_get_match_data(dev); 3253 if (!priv->info) 3254 return -EINVAL; 3255 3256 /* Sanity check if these required device operations are filled 3257 * properly. 3258 */ 3259 if (!priv->info->sw_setup || !priv->info->pad_setup || 3260 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3261 !priv->info->mac_port_get_caps || 3262 !priv->info->mac_port_config) 3263 return -EINVAL; 3264 3265 priv->id = priv->info->id; 3266 priv->dev = dev; 3267 priv->ds->priv = priv; 3268 priv->ds->ops = &mt7530_switch_ops; 3269 mutex_init(&priv->reg_mutex); 3270 dev_set_drvdata(dev, priv); 3271 3272 return 0; 3273} 3274EXPORT_SYMBOL_GPL(mt7530_probe_common); 3275 3276void 3277mt7530_remove_common(struct mt7530_priv *priv) 3278{ 3279 if (priv->irq) 3280 mt7530_free_irq(priv); 3281 3282 dsa_unregister_switch(priv->ds); 3283 3284 mutex_destroy(&priv->reg_mutex); 3285} 3286EXPORT_SYMBOL_GPL(mt7530_remove_common); 3287 3288MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3289MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3290MODULE_LICENSE("GPL"); 3291