1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * at91_can.c - CAN network driver for AT91 SoC CAN controller 4 * 5 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 6 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 7 */ 8 9#include <linux/clk.h> 10#include <linux/errno.h> 11#include <linux/ethtool.h> 12#include <linux/if_arp.h> 13#include <linux/interrupt.h> 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/netdevice.h> 17#include <linux/of.h> 18#include <linux/platform_device.h> 19#include <linux/rtnetlink.h> 20#include <linux/skbuff.h> 21#include <linux/spinlock.h> 22#include <linux/string.h> 23#include <linux/types.h> 24 25#include <linux/can/dev.h> 26#include <linux/can/error.h> 27 28#define AT91_MB_MASK(i) ((1 << (i)) - 1) 29 30/* Common registers */ 31enum at91_reg { 32 AT91_MR = 0x000, 33 AT91_IER = 0x004, 34 AT91_IDR = 0x008, 35 AT91_IMR = 0x00C, 36 AT91_SR = 0x010, 37 AT91_BR = 0x014, 38 AT91_TIM = 0x018, 39 AT91_TIMESTP = 0x01C, 40 AT91_ECR = 0x020, 41 AT91_TCR = 0x024, 42 AT91_ACR = 0x028, 43}; 44 45/* Mailbox registers (0 <= i <= 15) */ 46#define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20))) 47#define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20))) 48#define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20))) 49#define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20))) 50#define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20))) 51#define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20))) 52#define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20))) 53#define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20))) 54 55/* Register bits */ 56#define AT91_MR_CANEN BIT(0) 57#define AT91_MR_LPM BIT(1) 58#define AT91_MR_ABM BIT(2) 59#define AT91_MR_OVL BIT(3) 60#define AT91_MR_TEOF BIT(4) 61#define AT91_MR_TTM BIT(5) 62#define AT91_MR_TIMFRZ BIT(6) 63#define AT91_MR_DRPT BIT(7) 64 65#define AT91_SR_RBSY BIT(29) 66 67#define AT91_MMR_PRIO_SHIFT (16) 68 69#define AT91_MID_MIDE BIT(29) 70 71#define AT91_MSR_MRTR BIT(20) 72#define AT91_MSR_MABT BIT(22) 73#define AT91_MSR_MRDY BIT(23) 74#define AT91_MSR_MMI BIT(24) 75 76#define AT91_MCR_MRTR BIT(20) 77#define AT91_MCR_MTCR BIT(23) 78 79/* Mailbox Modes */ 80enum at91_mb_mode { 81 AT91_MB_MODE_DISABLED = 0, 82 AT91_MB_MODE_RX = 1, 83 AT91_MB_MODE_RX_OVRWR = 2, 84 AT91_MB_MODE_TX = 3, 85 AT91_MB_MODE_CONSUMER = 4, 86 AT91_MB_MODE_PRODUCER = 5, 87}; 88 89/* Interrupt mask bits */ 90#define AT91_IRQ_ERRA BIT(16) 91#define AT91_IRQ_WARN BIT(17) 92#define AT91_IRQ_ERRP BIT(18) 93#define AT91_IRQ_BOFF BIT(19) 94#define AT91_IRQ_SLEEP BIT(20) 95#define AT91_IRQ_WAKEUP BIT(21) 96#define AT91_IRQ_TOVF BIT(22) 97#define AT91_IRQ_TSTP BIT(23) 98#define AT91_IRQ_CERR BIT(24) 99#define AT91_IRQ_SERR BIT(25) 100#define AT91_IRQ_AERR BIT(26) 101#define AT91_IRQ_FERR BIT(27) 102#define AT91_IRQ_BERR BIT(28) 103 104#define AT91_IRQ_ERR_ALL (0x1fff0000) 105#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 106 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 107#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 108 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 109 110#define AT91_IRQ_ALL (0x1fffffff) 111 112enum at91_devtype { 113 AT91_DEVTYPE_SAM9263, 114 AT91_DEVTYPE_SAM9X5, 115}; 116 117struct at91_devtype_data { 118 unsigned int rx_first; 119 unsigned int rx_split; 120 unsigned int rx_last; 121 unsigned int tx_shift; 122 enum at91_devtype type; 123}; 124 125struct at91_priv { 126 struct can_priv can; /* must be the first member! */ 127 struct napi_struct napi; 128 129 void __iomem *reg_base; 130 131 u32 reg_sr; 132 unsigned int tx_next; 133 unsigned int tx_echo; 134 unsigned int rx_next; 135 struct at91_devtype_data devtype_data; 136 137 struct clk *clk; 138 struct at91_can_data *pdata; 139 140 canid_t mb0_id; 141}; 142 143static const struct at91_devtype_data at91_at91sam9263_data = { 144 .rx_first = 1, 145 .rx_split = 8, 146 .rx_last = 11, 147 .tx_shift = 2, 148 .type = AT91_DEVTYPE_SAM9263, 149}; 150 151static const struct at91_devtype_data at91_at91sam9x5_data = { 152 .rx_first = 0, 153 .rx_split = 4, 154 .rx_last = 5, 155 .tx_shift = 1, 156 .type = AT91_DEVTYPE_SAM9X5, 157}; 158 159static const struct can_bittiming_const at91_bittiming_const = { 160 .name = KBUILD_MODNAME, 161 .tseg1_min = 4, 162 .tseg1_max = 16, 163 .tseg2_min = 2, 164 .tseg2_max = 8, 165 .sjw_max = 4, 166 .brp_min = 2, 167 .brp_max = 128, 168 .brp_inc = 1, 169}; 170 171#define AT91_IS(_model) \ 172static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \ 173{ \ 174 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 175} 176 177AT91_IS(9263); 178AT91_IS(9X5); 179 180static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 181{ 182 return priv->devtype_data.rx_first; 183} 184 185static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 186{ 187 return priv->devtype_data.rx_last; 188} 189 190static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 191{ 192 return priv->devtype_data.rx_split; 193} 194 195static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 196{ 197 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 198} 199 200static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 201{ 202 return get_mb_rx_split(priv) - 1; 203} 204 205static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 206{ 207 return AT91_MB_MASK(get_mb_rx_split(priv)) & 208 ~AT91_MB_MASK(get_mb_rx_first(priv)); 209} 210 211static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 212{ 213 return priv->devtype_data.tx_shift; 214} 215 216static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 217{ 218 return 1 << get_mb_tx_shift(priv); 219} 220 221static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 222{ 223 return get_mb_rx_last(priv) + 1; 224} 225 226static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 227{ 228 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 229} 230 231static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 232{ 233 return get_mb_tx_shift(priv); 234} 235 236static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 237{ 238 return 0xf << get_mb_tx_shift(priv); 239} 240 241static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 242{ 243 return AT91_MB_MASK(get_mb_tx_shift(priv)); 244} 245 246static inline unsigned int get_next_mask(const struct at91_priv *priv) 247{ 248 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 249} 250 251static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 252{ 253 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 254 ~AT91_MB_MASK(get_mb_rx_first(priv)); 255} 256 257static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 258{ 259 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 260 ~AT91_MB_MASK(get_mb_tx_first(priv)); 261} 262 263static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 264{ 265 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 266} 267 268static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 269{ 270 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 271} 272 273static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 274{ 275 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 276} 277 278static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 279{ 280 return readl_relaxed(priv->reg_base + reg); 281} 282 283static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 284 u32 value) 285{ 286 writel_relaxed(value, priv->reg_base + reg); 287} 288 289static inline void set_mb_mode_prio(const struct at91_priv *priv, 290 unsigned int mb, enum at91_mb_mode mode, 291 int prio) 292{ 293 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 294} 295 296static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 297 enum at91_mb_mode mode) 298{ 299 set_mb_mode_prio(priv, mb, mode, 0); 300} 301 302static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 303{ 304 u32 reg_mid; 305 306 if (can_id & CAN_EFF_FLAG) 307 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 308 else 309 reg_mid = (can_id & CAN_SFF_MASK) << 18; 310 311 return reg_mid; 312} 313 314static void at91_setup_mailboxes(struct net_device *dev) 315{ 316 struct at91_priv *priv = netdev_priv(dev); 317 unsigned int i; 318 u32 reg_mid; 319 320 /* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 321 * mailbox is disabled. The next 11 mailboxes are used as a 322 * reception FIFO. The last mailbox is configured with 323 * overwrite option. The overwrite flag indicates a FIFO 324 * overflow. 325 */ 326 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 327 for (i = 0; i < get_mb_rx_first(priv); i++) { 328 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 329 at91_write(priv, AT91_MID(i), reg_mid); 330 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 331 } 332 333 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 334 set_mb_mode(priv, i, AT91_MB_MODE_RX); 335 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 336 337 /* reset acceptance mask and id register */ 338 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 339 at91_write(priv, AT91_MAM(i), 0x0); 340 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 341 } 342 343 /* The last 4 mailboxes are used for transmitting. */ 344 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 345 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 346 347 /* Reset tx and rx helper pointers */ 348 priv->tx_next = priv->tx_echo = 0; 349 priv->rx_next = get_mb_rx_first(priv); 350} 351 352static int at91_set_bittiming(struct net_device *dev) 353{ 354 const struct at91_priv *priv = netdev_priv(dev); 355 const struct can_bittiming *bt = &priv->can.bittiming; 356 u32 reg_br; 357 358 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 359 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 360 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 361 ((bt->phase_seg2 - 1) << 0); 362 363 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 364 365 at91_write(priv, AT91_BR, reg_br); 366 367 return 0; 368} 369 370static int at91_get_berr_counter(const struct net_device *dev, 371 struct can_berr_counter *bec) 372{ 373 const struct at91_priv *priv = netdev_priv(dev); 374 u32 reg_ecr = at91_read(priv, AT91_ECR); 375 376 bec->rxerr = reg_ecr & 0xff; 377 bec->txerr = reg_ecr >> 16; 378 379 return 0; 380} 381 382static void at91_chip_start(struct net_device *dev) 383{ 384 struct at91_priv *priv = netdev_priv(dev); 385 u32 reg_mr, reg_ier; 386 387 /* disable interrupts */ 388 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 389 390 /* disable chip */ 391 reg_mr = at91_read(priv, AT91_MR); 392 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 393 394 at91_set_bittiming(dev); 395 at91_setup_mailboxes(dev); 396 397 /* enable chip */ 398 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 399 reg_mr = AT91_MR_CANEN | AT91_MR_ABM; 400 else 401 reg_mr = AT91_MR_CANEN; 402 at91_write(priv, AT91_MR, reg_mr); 403 404 priv->can.state = CAN_STATE_ERROR_ACTIVE; 405 406 /* Enable interrupts */ 407 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 408 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 409 at91_write(priv, AT91_IER, reg_ier); 410} 411 412static void at91_chip_stop(struct net_device *dev, enum can_state state) 413{ 414 struct at91_priv *priv = netdev_priv(dev); 415 u32 reg_mr; 416 417 /* disable interrupts */ 418 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 419 420 reg_mr = at91_read(priv, AT91_MR); 421 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 422 423 priv->can.state = state; 424} 425 426/* theory of operation: 427 * 428 * According to the datasheet priority 0 is the highest priority, 15 429 * is the lowest. If two mailboxes have the same priority level the 430 * message of the mailbox with the lowest number is sent first. 431 * 432 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 433 * the next mailbox with prio 0, and so on, until all mailboxes are 434 * used. Then we start from the beginning with mailbox 435 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 436 * prio 1. When we reach the last mailbox with prio 15, we have to 437 * stop sending, waiting for all messages to be delivered, then start 438 * again with mailbox AT91_MB_TX_FIRST prio 0. 439 * 440 * We use the priv->tx_next as counter for the next transmission 441 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 442 * encode the mailbox number, the upper 4 bits the mailbox priority: 443 * 444 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 445 * (mb - get_mb_tx_first(priv)); 446 * 447 */ 448static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 449{ 450 struct at91_priv *priv = netdev_priv(dev); 451 struct can_frame *cf = (struct can_frame *)skb->data; 452 unsigned int mb, prio; 453 u32 reg_mid, reg_mcr; 454 455 if (can_dev_dropped_skb(dev, skb)) 456 return NETDEV_TX_OK; 457 458 mb = get_tx_next_mb(priv); 459 prio = get_tx_next_prio(priv); 460 461 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 462 netif_stop_queue(dev); 463 464 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 465 return NETDEV_TX_BUSY; 466 } 467 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 468 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 469 (cf->len << 16) | AT91_MCR_MTCR; 470 471 /* disable MB while writing ID (see datasheet) */ 472 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 473 at91_write(priv, AT91_MID(mb), reg_mid); 474 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 475 476 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 477 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 478 479 /* This triggers transmission */ 480 at91_write(priv, AT91_MCR(mb), reg_mcr); 481 482 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 483 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv), 0); 484 485 /* we have to stop the queue and deliver all messages in case 486 * of a prio+mb counter wrap around. This is the case if 487 * tx_next buffer prio and mailbox equals 0. 488 * 489 * also stop the queue if next buffer is still in use 490 * (== not ready) 491 */ 492 priv->tx_next++; 493 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 494 AT91_MSR_MRDY) || 495 (priv->tx_next & get_next_mask(priv)) == 0) 496 netif_stop_queue(dev); 497 498 /* Enable interrupt for this mailbox */ 499 at91_write(priv, AT91_IER, 1 << mb); 500 501 return NETDEV_TX_OK; 502} 503 504/** 505 * at91_activate_rx_low - activate lower rx mailboxes 506 * @priv: a91 context 507 * 508 * Reenables the lower mailboxes for reception of new CAN messages 509 */ 510static inline void at91_activate_rx_low(const struct at91_priv *priv) 511{ 512 u32 mask = get_mb_rx_low_mask(priv); 513 514 at91_write(priv, AT91_TCR, mask); 515} 516 517/** 518 * at91_activate_rx_mb - reactive single rx mailbox 519 * @priv: a91 context 520 * @mb: mailbox to reactivate 521 * 522 * Reenables given mailbox for reception of new CAN messages 523 */ 524static inline void at91_activate_rx_mb(const struct at91_priv *priv, 525 unsigned int mb) 526{ 527 u32 mask = 1 << mb; 528 529 at91_write(priv, AT91_TCR, mask); 530} 531 532/** 533 * at91_rx_overflow_err - send error frame due to rx overflow 534 * @dev: net device 535 */ 536static void at91_rx_overflow_err(struct net_device *dev) 537{ 538 struct net_device_stats *stats = &dev->stats; 539 struct sk_buff *skb; 540 struct can_frame *cf; 541 542 netdev_dbg(dev, "RX buffer overflow\n"); 543 stats->rx_over_errors++; 544 stats->rx_errors++; 545 546 skb = alloc_can_err_skb(dev, &cf); 547 if (unlikely(!skb)) 548 return; 549 550 cf->can_id |= CAN_ERR_CRTL; 551 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 552 553 netif_receive_skb(skb); 554} 555 556/** 557 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 558 * @dev: net device 559 * @mb: mailbox number to read from 560 * @cf: can frame where to store message 561 * 562 * Reads a CAN message from the given mailbox and stores data into 563 * given can frame. "mb" and "cf" must be valid. 564 */ 565static void at91_read_mb(struct net_device *dev, unsigned int mb, 566 struct can_frame *cf) 567{ 568 const struct at91_priv *priv = netdev_priv(dev); 569 u32 reg_msr, reg_mid; 570 571 reg_mid = at91_read(priv, AT91_MID(mb)); 572 if (reg_mid & AT91_MID_MIDE) 573 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 574 else 575 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 576 577 reg_msr = at91_read(priv, AT91_MSR(mb)); 578 cf->len = can_cc_dlc2len((reg_msr >> 16) & 0xf); 579 580 if (reg_msr & AT91_MSR_MRTR) { 581 cf->can_id |= CAN_RTR_FLAG; 582 } else { 583 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 584 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 585 } 586 587 /* allow RX of extended frames */ 588 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 589 590 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 591 at91_rx_overflow_err(dev); 592} 593 594/** 595 * at91_read_msg - read CAN message from mailbox 596 * @dev: net device 597 * @mb: mail box to read from 598 * 599 * Reads a CAN message from given mailbox, and put into linux network 600 * RX queue, does all housekeeping chores (stats, ...) 601 */ 602static void at91_read_msg(struct net_device *dev, unsigned int mb) 603{ 604 struct net_device_stats *stats = &dev->stats; 605 struct can_frame *cf; 606 struct sk_buff *skb; 607 608 skb = alloc_can_skb(dev, &cf); 609 if (unlikely(!skb)) { 610 stats->rx_dropped++; 611 return; 612 } 613 614 at91_read_mb(dev, mb, cf); 615 616 stats->rx_packets++; 617 if (!(cf->can_id & CAN_RTR_FLAG)) 618 stats->rx_bytes += cf->len; 619 620 netif_receive_skb(skb); 621} 622 623/** 624 * at91_poll_rx - read multiple CAN messages from mailboxes 625 * @dev: net device 626 * @quota: max number of pkgs we're allowed to receive 627 * 628 * Theory of Operation: 629 * 630 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 631 * on the chip are reserved for RX. We split them into 2 groups. The 632 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 633 * 634 * Like it or not, but the chip always saves a received CAN message 635 * into the first free mailbox it finds (starting with the 636 * lowest). This makes it very difficult to read the messages in the 637 * right order from the chip. This is how we work around that problem: 638 * 639 * The first message goes into mb nr. 1 and issues an interrupt. All 640 * rx ints are disabled in the interrupt handler and a napi poll is 641 * scheduled. We read the mailbox, but do _not_ re-enable the mb (to 642 * receive another message). 643 * 644 * lower mbxs upper 645 * ____^______ __^__ 646 * / \ / \ 647 * +-+-+-+-+-+-+-+-++-+-+-+-+ 648 * | |x|x|x|x|x|x|x|| | | | | 649 * +-+-+-+-+-+-+-+-++-+-+-+-+ 650 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 651 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 652 * ^ 653 * | 654 * \ 655 * unused, due to chip bug 656 * 657 * The variable priv->rx_next points to the next mailbox to read a 658 * message from. As long we're in the lower mailboxes we just read the 659 * mailbox but not re-enable it. 660 * 661 * With completion of the last of the lower mailboxes, we re-enable the 662 * whole first group, but continue to look for filled mailboxes in the 663 * upper mailboxes. Imagine the second group like overflow mailboxes, 664 * which takes CAN messages if the lower goup is full. While in the 665 * upper group we re-enable the mailbox right after reading it. Giving 666 * the chip more room to store messages. 667 * 668 * After finishing we look again in the lower group if we've still 669 * quota. 670 * 671 */ 672static int at91_poll_rx(struct net_device *dev, int quota) 673{ 674 struct at91_priv *priv = netdev_priv(dev); 675 u32 reg_sr = at91_read(priv, AT91_SR); 676 const unsigned long *addr = (unsigned long *)®_sr; 677 unsigned int mb; 678 int received = 0; 679 680 if (priv->rx_next > get_mb_rx_low_last(priv) && 681 reg_sr & get_mb_rx_low_mask(priv)) 682 netdev_info(dev, 683 "order of incoming frames cannot be guaranteed\n"); 684 685 again: 686 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 687 mb < get_mb_tx_first(priv) && quota > 0; 688 reg_sr = at91_read(priv, AT91_SR), 689 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 690 at91_read_msg(dev, mb); 691 692 /* reactivate mailboxes */ 693 if (mb == get_mb_rx_low_last(priv)) 694 /* all lower mailboxed, if just finished it */ 695 at91_activate_rx_low(priv); 696 else if (mb > get_mb_rx_low_last(priv)) 697 /* only the mailbox we read */ 698 at91_activate_rx_mb(priv, mb); 699 700 received++; 701 quota--; 702 } 703 704 /* upper group completed, look again in lower */ 705 if (priv->rx_next > get_mb_rx_low_last(priv) && 706 mb > get_mb_rx_last(priv)) { 707 priv->rx_next = get_mb_rx_first(priv); 708 if (quota > 0) 709 goto again; 710 } 711 712 return received; 713} 714 715static void at91_poll_err_frame(struct net_device *dev, 716 struct can_frame *cf, u32 reg_sr) 717{ 718 struct at91_priv *priv = netdev_priv(dev); 719 720 /* CRC error */ 721 if (reg_sr & AT91_IRQ_CERR) { 722 netdev_dbg(dev, "CERR irq\n"); 723 dev->stats.rx_errors++; 724 priv->can.can_stats.bus_error++; 725 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 726 } 727 728 /* Stuffing Error */ 729 if (reg_sr & AT91_IRQ_SERR) { 730 netdev_dbg(dev, "SERR irq\n"); 731 dev->stats.rx_errors++; 732 priv->can.can_stats.bus_error++; 733 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 734 cf->data[2] |= CAN_ERR_PROT_STUFF; 735 } 736 737 /* Acknowledgement Error */ 738 if (reg_sr & AT91_IRQ_AERR) { 739 netdev_dbg(dev, "AERR irq\n"); 740 dev->stats.tx_errors++; 741 cf->can_id |= CAN_ERR_ACK; 742 } 743 744 /* Form error */ 745 if (reg_sr & AT91_IRQ_FERR) { 746 netdev_dbg(dev, "FERR irq\n"); 747 dev->stats.rx_errors++; 748 priv->can.can_stats.bus_error++; 749 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 750 cf->data[2] |= CAN_ERR_PROT_FORM; 751 } 752 753 /* Bit Error */ 754 if (reg_sr & AT91_IRQ_BERR) { 755 netdev_dbg(dev, "BERR irq\n"); 756 dev->stats.tx_errors++; 757 priv->can.can_stats.bus_error++; 758 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 759 cf->data[2] |= CAN_ERR_PROT_BIT; 760 } 761} 762 763static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 764{ 765 struct sk_buff *skb; 766 struct can_frame *cf; 767 768 if (quota == 0) 769 return 0; 770 771 skb = alloc_can_err_skb(dev, &cf); 772 if (unlikely(!skb)) 773 return 0; 774 775 at91_poll_err_frame(dev, cf, reg_sr); 776 777 netif_receive_skb(skb); 778 779 return 1; 780} 781 782static int at91_poll(struct napi_struct *napi, int quota) 783{ 784 struct net_device *dev = napi->dev; 785 const struct at91_priv *priv = netdev_priv(dev); 786 u32 reg_sr = at91_read(priv, AT91_SR); 787 int work_done = 0; 788 789 if (reg_sr & get_irq_mb_rx(priv)) 790 work_done += at91_poll_rx(dev, quota - work_done); 791 792 /* The error bits are clear on read, 793 * so use saved value from irq handler. 794 */ 795 reg_sr |= priv->reg_sr; 796 if (reg_sr & AT91_IRQ_ERR_FRAME) 797 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 798 799 if (work_done < quota) { 800 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 801 u32 reg_ier = AT91_IRQ_ERR_FRAME; 802 803 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 804 805 napi_complete_done(napi, work_done); 806 at91_write(priv, AT91_IER, reg_ier); 807 } 808 809 return work_done; 810} 811 812/* theory of operation: 813 * 814 * priv->tx_echo holds the number of the oldest can_frame put for 815 * transmission into the hardware, but not yet ACKed by the CAN tx 816 * complete IRQ. 817 * 818 * We iterate from priv->tx_echo to priv->tx_next and check if the 819 * packet has been transmitted, echo it back to the CAN framework. If 820 * we discover a not yet transmitted package, stop looking for more. 821 * 822 */ 823static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 824{ 825 struct at91_priv *priv = netdev_priv(dev); 826 u32 reg_msr; 827 unsigned int mb; 828 829 /* masking of reg_sr not needed, already done by at91_irq */ 830 831 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 832 mb = get_tx_echo_mb(priv); 833 834 /* no event in mailbox? */ 835 if (!(reg_sr & (1 << mb))) 836 break; 837 838 /* Disable irq for this TX mailbox */ 839 at91_write(priv, AT91_IDR, 1 << mb); 840 841 /* only echo if mailbox signals us a transfer 842 * complete (MSR_MRDY). Otherwise it's a tansfer 843 * abort. "can_bus_off()" takes care about the skbs 844 * parked in the echo queue. 845 */ 846 reg_msr = at91_read(priv, AT91_MSR(mb)); 847 if (likely(reg_msr & AT91_MSR_MRDY && 848 ~reg_msr & AT91_MSR_MABT)) { 849 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 850 dev->stats.tx_bytes += 851 can_get_echo_skb(dev, 852 mb - get_mb_tx_first(priv), 853 NULL); 854 dev->stats.tx_packets++; 855 } 856 } 857 858 /* restart queue if we don't have a wrap around but restart if 859 * we get a TX int for the last can frame directly before a 860 * wrap around. 861 */ 862 if ((priv->tx_next & get_next_mask(priv)) != 0 || 863 (priv->tx_echo & get_next_mask(priv)) == 0) 864 netif_wake_queue(dev); 865} 866 867static void at91_irq_err_state(struct net_device *dev, 868 struct can_frame *cf, enum can_state new_state) 869{ 870 struct at91_priv *priv = netdev_priv(dev); 871 u32 reg_idr = 0, reg_ier = 0; 872 struct can_berr_counter bec; 873 874 at91_get_berr_counter(dev, &bec); 875 876 switch (priv->can.state) { 877 case CAN_STATE_ERROR_ACTIVE: 878 /* from: ERROR_ACTIVE 879 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 880 * => : there was a warning int 881 */ 882 if (new_state >= CAN_STATE_ERROR_WARNING && 883 new_state <= CAN_STATE_BUS_OFF) { 884 netdev_dbg(dev, "Error Warning IRQ\n"); 885 priv->can.can_stats.error_warning++; 886 887 cf->can_id |= CAN_ERR_CRTL; 888 cf->data[1] = (bec.txerr > bec.rxerr) ? 889 CAN_ERR_CRTL_TX_WARNING : 890 CAN_ERR_CRTL_RX_WARNING; 891 } 892 fallthrough; 893 case CAN_STATE_ERROR_WARNING: 894 /* from: ERROR_ACTIVE, ERROR_WARNING 895 * to : ERROR_PASSIVE, BUS_OFF 896 * => : error passive int 897 */ 898 if (new_state >= CAN_STATE_ERROR_PASSIVE && 899 new_state <= CAN_STATE_BUS_OFF) { 900 netdev_dbg(dev, "Error Passive IRQ\n"); 901 priv->can.can_stats.error_passive++; 902 903 cf->can_id |= CAN_ERR_CRTL; 904 cf->data[1] = (bec.txerr > bec.rxerr) ? 905 CAN_ERR_CRTL_TX_PASSIVE : 906 CAN_ERR_CRTL_RX_PASSIVE; 907 } 908 break; 909 case CAN_STATE_BUS_OFF: 910 /* from: BUS_OFF 911 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 912 */ 913 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 914 cf->can_id |= CAN_ERR_RESTARTED; 915 916 netdev_dbg(dev, "restarted\n"); 917 priv->can.can_stats.restarts++; 918 919 netif_carrier_on(dev); 920 netif_wake_queue(dev); 921 } 922 break; 923 default: 924 break; 925 } 926 927 /* process state changes depending on the new state */ 928 switch (new_state) { 929 case CAN_STATE_ERROR_ACTIVE: 930 /* actually we want to enable AT91_IRQ_WARN here, but 931 * it screws up the system under certain 932 * circumstances. so just enable AT91_IRQ_ERRP, thus 933 * the "fallthrough" 934 */ 935 netdev_dbg(dev, "Error Active\n"); 936 cf->can_id |= CAN_ERR_PROT; 937 cf->data[2] = CAN_ERR_PROT_ACTIVE; 938 fallthrough; 939 case CAN_STATE_ERROR_WARNING: 940 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 941 reg_ier = AT91_IRQ_ERRP; 942 break; 943 case CAN_STATE_ERROR_PASSIVE: 944 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 945 reg_ier = AT91_IRQ_BOFF; 946 break; 947 case CAN_STATE_BUS_OFF: 948 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 949 AT91_IRQ_WARN | AT91_IRQ_BOFF; 950 reg_ier = 0; 951 952 cf->can_id |= CAN_ERR_BUSOFF; 953 954 netdev_dbg(dev, "bus-off\n"); 955 netif_carrier_off(dev); 956 priv->can.can_stats.bus_off++; 957 958 /* turn off chip, if restart is disabled */ 959 if (!priv->can.restart_ms) { 960 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 961 return; 962 } 963 break; 964 default: 965 break; 966 } 967 968 at91_write(priv, AT91_IDR, reg_idr); 969 at91_write(priv, AT91_IER, reg_ier); 970} 971 972static int at91_get_state_by_bec(const struct net_device *dev, 973 enum can_state *state) 974{ 975 struct can_berr_counter bec; 976 int err; 977 978 err = at91_get_berr_counter(dev, &bec); 979 if (err) 980 return err; 981 982 if (bec.txerr < 96 && bec.rxerr < 96) 983 *state = CAN_STATE_ERROR_ACTIVE; 984 else if (bec.txerr < 128 && bec.rxerr < 128) 985 *state = CAN_STATE_ERROR_WARNING; 986 else if (bec.txerr < 256 && bec.rxerr < 256) 987 *state = CAN_STATE_ERROR_PASSIVE; 988 else 989 *state = CAN_STATE_BUS_OFF; 990 991 return 0; 992} 993 994static void at91_irq_err(struct net_device *dev) 995{ 996 struct at91_priv *priv = netdev_priv(dev); 997 struct sk_buff *skb; 998 struct can_frame *cf; 999 enum can_state new_state; 1000 u32 reg_sr; 1001 int err; 1002 1003 if (at91_is_sam9263(priv)) { 1004 reg_sr = at91_read(priv, AT91_SR); 1005 1006 /* we need to look at the unmasked reg_sr */ 1007 if (unlikely(reg_sr & AT91_IRQ_BOFF)) { 1008 new_state = CAN_STATE_BUS_OFF; 1009 } else if (unlikely(reg_sr & AT91_IRQ_ERRP)) { 1010 new_state = CAN_STATE_ERROR_PASSIVE; 1011 } else if (unlikely(reg_sr & AT91_IRQ_WARN)) { 1012 new_state = CAN_STATE_ERROR_WARNING; 1013 } else if (likely(reg_sr & AT91_IRQ_ERRA)) { 1014 new_state = CAN_STATE_ERROR_ACTIVE; 1015 } else { 1016 netdev_err(dev, "BUG! hardware in undefined state\n"); 1017 return; 1018 } 1019 } else { 1020 err = at91_get_state_by_bec(dev, &new_state); 1021 if (err) 1022 return; 1023 } 1024 1025 /* state hasn't changed */ 1026 if (likely(new_state == priv->can.state)) 1027 return; 1028 1029 skb = alloc_can_err_skb(dev, &cf); 1030 if (unlikely(!skb)) 1031 return; 1032 1033 at91_irq_err_state(dev, cf, new_state); 1034 1035 netif_rx(skb); 1036 1037 priv->can.state = new_state; 1038} 1039 1040/* interrupt handler 1041 */ 1042static irqreturn_t at91_irq(int irq, void *dev_id) 1043{ 1044 struct net_device *dev = dev_id; 1045 struct at91_priv *priv = netdev_priv(dev); 1046 irqreturn_t handled = IRQ_NONE; 1047 u32 reg_sr, reg_imr; 1048 1049 reg_sr = at91_read(priv, AT91_SR); 1050 reg_imr = at91_read(priv, AT91_IMR); 1051 1052 /* Ignore masked interrupts */ 1053 reg_sr &= reg_imr; 1054 if (!reg_sr) 1055 goto exit; 1056 1057 handled = IRQ_HANDLED; 1058 1059 /* Receive or error interrupt? -> napi */ 1060 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1061 /* The error bits are clear on read, 1062 * save for later use. 1063 */ 1064 priv->reg_sr = reg_sr; 1065 at91_write(priv, AT91_IDR, 1066 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1067 napi_schedule(&priv->napi); 1068 } 1069 1070 /* Transmission complete interrupt */ 1071 if (reg_sr & get_irq_mb_tx(priv)) 1072 at91_irq_tx(dev, reg_sr); 1073 1074 at91_irq_err(dev); 1075 1076 exit: 1077 return handled; 1078} 1079 1080static int at91_open(struct net_device *dev) 1081{ 1082 struct at91_priv *priv = netdev_priv(dev); 1083 int err; 1084 1085 err = clk_prepare_enable(priv->clk); 1086 if (err) 1087 return err; 1088 1089 /* check or determine and set bittime */ 1090 err = open_candev(dev); 1091 if (err) 1092 goto out; 1093 1094 /* register interrupt handler */ 1095 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1096 dev->name, dev)) { 1097 err = -EAGAIN; 1098 goto out_close; 1099 } 1100 1101 /* start chip and queuing */ 1102 at91_chip_start(dev); 1103 napi_enable(&priv->napi); 1104 netif_start_queue(dev); 1105 1106 return 0; 1107 1108 out_close: 1109 close_candev(dev); 1110 out: 1111 clk_disable_unprepare(priv->clk); 1112 1113 return err; 1114} 1115 1116/* stop CAN bus activity 1117 */ 1118static int at91_close(struct net_device *dev) 1119{ 1120 struct at91_priv *priv = netdev_priv(dev); 1121 1122 netif_stop_queue(dev); 1123 napi_disable(&priv->napi); 1124 at91_chip_stop(dev, CAN_STATE_STOPPED); 1125 1126 free_irq(dev->irq, dev); 1127 clk_disable_unprepare(priv->clk); 1128 1129 close_candev(dev); 1130 1131 return 0; 1132} 1133 1134static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1135{ 1136 switch (mode) { 1137 case CAN_MODE_START: 1138 at91_chip_start(dev); 1139 netif_wake_queue(dev); 1140 break; 1141 1142 default: 1143 return -EOPNOTSUPP; 1144 } 1145 1146 return 0; 1147} 1148 1149static const struct net_device_ops at91_netdev_ops = { 1150 .ndo_open = at91_open, 1151 .ndo_stop = at91_close, 1152 .ndo_start_xmit = at91_start_xmit, 1153 .ndo_change_mtu = can_change_mtu, 1154}; 1155 1156static const struct ethtool_ops at91_ethtool_ops = { 1157 .get_ts_info = ethtool_op_get_ts_info, 1158}; 1159 1160static ssize_t mb0_id_show(struct device *dev, 1161 struct device_attribute *attr, char *buf) 1162{ 1163 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1164 1165 if (priv->mb0_id & CAN_EFF_FLAG) 1166 return sysfs_emit(buf, "0x%08x\n", priv->mb0_id); 1167 else 1168 return sysfs_emit(buf, "0x%03x\n", priv->mb0_id); 1169} 1170 1171static ssize_t mb0_id_store(struct device *dev, 1172 struct device_attribute *attr, 1173 const char *buf, size_t count) 1174{ 1175 struct net_device *ndev = to_net_dev(dev); 1176 struct at91_priv *priv = netdev_priv(ndev); 1177 unsigned long can_id; 1178 ssize_t ret; 1179 int err; 1180 1181 rtnl_lock(); 1182 1183 if (ndev->flags & IFF_UP) { 1184 ret = -EBUSY; 1185 goto out; 1186 } 1187 1188 err = kstrtoul(buf, 0, &can_id); 1189 if (err) { 1190 ret = err; 1191 goto out; 1192 } 1193 1194 if (can_id & CAN_EFF_FLAG) 1195 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1196 else 1197 can_id &= CAN_SFF_MASK; 1198 1199 priv->mb0_id = can_id; 1200 ret = count; 1201 1202 out: 1203 rtnl_unlock(); 1204 return ret; 1205} 1206 1207static DEVICE_ATTR_RW(mb0_id); 1208 1209static struct attribute *at91_sysfs_attrs[] = { 1210 &dev_attr_mb0_id.attr, 1211 NULL, 1212}; 1213 1214static const struct attribute_group at91_sysfs_attr_group = { 1215 .attrs = at91_sysfs_attrs, 1216}; 1217 1218#if defined(CONFIG_OF) 1219static const struct of_device_id at91_can_dt_ids[] = { 1220 { 1221 .compatible = "atmel,at91sam9x5-can", 1222 .data = &at91_at91sam9x5_data, 1223 }, { 1224 .compatible = "atmel,at91sam9263-can", 1225 .data = &at91_at91sam9263_data, 1226 }, { 1227 /* sentinel */ 1228 } 1229}; 1230MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1231#endif 1232 1233static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1234{ 1235 if (pdev->dev.of_node) { 1236 const struct of_device_id *match; 1237 1238 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1239 if (!match) { 1240 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1241 return NULL; 1242 } 1243 return (const struct at91_devtype_data *)match->data; 1244 } 1245 return (const struct at91_devtype_data *) 1246 platform_get_device_id(pdev)->driver_data; 1247} 1248 1249static int at91_can_probe(struct platform_device *pdev) 1250{ 1251 const struct at91_devtype_data *devtype_data; 1252 struct net_device *dev; 1253 struct at91_priv *priv; 1254 struct resource *res; 1255 struct clk *clk; 1256 void __iomem *addr; 1257 int err, irq; 1258 1259 devtype_data = at91_can_get_driver_data(pdev); 1260 if (!devtype_data) { 1261 dev_err(&pdev->dev, "no driver data\n"); 1262 err = -ENODEV; 1263 goto exit; 1264 } 1265 1266 clk = clk_get(&pdev->dev, "can_clk"); 1267 if (IS_ERR(clk)) { 1268 dev_err(&pdev->dev, "no clock defined\n"); 1269 err = -ENODEV; 1270 goto exit; 1271 } 1272 1273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1274 irq = platform_get_irq(pdev, 0); 1275 if (!res || irq <= 0) { 1276 err = -ENODEV; 1277 goto exit_put; 1278 } 1279 1280 if (!request_mem_region(res->start, 1281 resource_size(res), 1282 pdev->name)) { 1283 err = -EBUSY; 1284 goto exit_put; 1285 } 1286 1287 addr = ioremap(res->start, resource_size(res)); 1288 if (!addr) { 1289 err = -ENOMEM; 1290 goto exit_release; 1291 } 1292 1293 dev = alloc_candev(sizeof(struct at91_priv), 1294 1 << devtype_data->tx_shift); 1295 if (!dev) { 1296 err = -ENOMEM; 1297 goto exit_iounmap; 1298 } 1299 1300 dev->netdev_ops = &at91_netdev_ops; 1301 dev->ethtool_ops = &at91_ethtool_ops; 1302 dev->irq = irq; 1303 dev->flags |= IFF_ECHO; 1304 1305 priv = netdev_priv(dev); 1306 priv->can.clock.freq = clk_get_rate(clk); 1307 priv->can.bittiming_const = &at91_bittiming_const; 1308 priv->can.do_set_mode = at91_set_mode; 1309 priv->can.do_get_berr_counter = at91_get_berr_counter; 1310 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1311 CAN_CTRLMODE_LISTENONLY; 1312 priv->reg_base = addr; 1313 priv->devtype_data = *devtype_data; 1314 priv->clk = clk; 1315 priv->pdata = dev_get_platdata(&pdev->dev); 1316 priv->mb0_id = 0x7ff; 1317 1318 netif_napi_add_weight(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1319 1320 if (at91_is_sam9263(priv)) 1321 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1322 1323 platform_set_drvdata(pdev, dev); 1324 SET_NETDEV_DEV(dev, &pdev->dev); 1325 1326 err = register_candev(dev); 1327 if (err) { 1328 dev_err(&pdev->dev, "registering netdev failed\n"); 1329 goto exit_free; 1330 } 1331 1332 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1333 priv->reg_base, dev->irq); 1334 1335 return 0; 1336 1337 exit_free: 1338 free_candev(dev); 1339 exit_iounmap: 1340 iounmap(addr); 1341 exit_release: 1342 release_mem_region(res->start, resource_size(res)); 1343 exit_put: 1344 clk_put(clk); 1345 exit: 1346 return err; 1347} 1348 1349static void at91_can_remove(struct platform_device *pdev) 1350{ 1351 struct net_device *dev = platform_get_drvdata(pdev); 1352 struct at91_priv *priv = netdev_priv(dev); 1353 struct resource *res; 1354 1355 unregister_netdev(dev); 1356 1357 iounmap(priv->reg_base); 1358 1359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1360 release_mem_region(res->start, resource_size(res)); 1361 1362 clk_put(priv->clk); 1363 1364 free_candev(dev); 1365} 1366 1367static const struct platform_device_id at91_can_id_table[] = { 1368 { 1369 .name = "at91sam9x5_can", 1370 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1371 }, { 1372 .name = "at91_can", 1373 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1374 }, { 1375 /* sentinel */ 1376 } 1377}; 1378MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1379 1380static struct platform_driver at91_can_driver = { 1381 .probe = at91_can_probe, 1382 .remove_new = at91_can_remove, 1383 .driver = { 1384 .name = KBUILD_MODNAME, 1385 .of_match_table = of_match_ptr(at91_can_dt_ids), 1386 }, 1387 .id_table = at91_can_id_table, 1388}; 1389 1390module_platform_driver(at91_can_driver); 1391 1392MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1393MODULE_LICENSE("GPL v2"); 1394MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1395