1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Arasan Secure Digital Host Controller Interface. 4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 5 * Copyright (c) 2012 Wind River Systems, Inc. 6 * Copyright (C) 2013 Pengutronix e.K. 7 * Copyright (C) 2013 Xilinx Inc. 8 * 9 * Based on sdhci-of-esdhc.c 10 * 11 * Copyright (c) 2007 Freescale Semiconductor, Inc. 12 * Copyright (c) 2009 MontaVista Software, Inc. 13 * 14 * Authors: Xiaobo Xie <X.Xie@freescale.com> 15 * Anton Vorontsov <avorontsov@ru.mvista.com> 16 */ 17 18#include <linux/clk-provider.h> 19#include <linux/mfd/syscon.h> 20#include <linux/module.h> 21#include <linux/of.h> 22#include <linux/platform_device.h> 23#include <linux/phy/phy.h> 24#include <linux/regmap.h> 25#include <linux/reset.h> 26#include <linux/firmware/xlnx-zynqmp.h> 27 28#include "cqhci.h" 29#include "sdhci-cqhci.h" 30#include "sdhci-pltfm.h" 31 32#define SDHCI_ARASAN_VENDOR_REGISTER 0x78 33 34#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 35#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF 36 37#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC 38#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F 39 40#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 41#define VENDOR_ENHANCED_STROBE BIT(0) 42 43#define PHY_CLK_TOO_SLOW_HZ 400000 44#define MIN_PHY_CLK_HZ 50000000 45 46#define SDHCI_ITAPDLY_CHGWIN 0x200 47#define SDHCI_ITAPDLY_ENABLE 0x100 48#define SDHCI_OTAPDLY_ENABLE 0x40 49 50#define PHY_CTRL_REG1 0x270 51#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0) 52#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1) 53#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1 54#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6) 55#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8) 56#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12) 57#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12 58#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16) 59#define PHY_CTRL_STRB_SEL_SHIFT 16 60#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24) 61 62#define PHY_CTRL_REG2 0x274 63#define PHY_CTRL_EN_DLL_MASK BIT(0) 64#define PHY_CTRL_DLL_RDY_MASK BIT(1) 65#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4) 66#define PHY_CTRL_FREQ_SEL_SHIFT 4 67#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16) 68#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17) 69#define FREQSEL_200M_170M 0x0 70#define FREQSEL_170M_140M 0x1 71#define FREQSEL_140M_110M 0x2 72#define FREQSEL_110M_80M 0x3 73#define FREQSEL_80M_50M 0x4 74#define FREQSEL_275M_250M 0x5 75#define FREQSEL_250M_225M 0x6 76#define FREQSEL_225M_200M 0x7 77#define PHY_DLL_TIMEOUT_MS 100 78 79/* Default settings for ZynqMP Clock Phases */ 80#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0} 81#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0} 82 83#define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0} 84#define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0} 85 86#define VERSAL_NET_EMMC_ICLK_PHASE {0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0} 87#define VERSAL_NET_EMMC_OCLK_PHASE {0, 113, 0, 0, 0, 0, 0, 0, 113, 79, 45} 88 89#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77 90 91/* 92 * On some SoCs the syscon area has a feature where the upper 16-bits of 93 * each 32-bit register act as a write mask for the lower 16-bits. This allows 94 * atomic updates of the register without locking. This macro is used on SoCs 95 * that have that feature. 96 */ 97#define HIWORD_UPDATE(val, mask, shift) \ 98 ((val) << (shift) | (mask) << ((shift) + 16)) 99 100/** 101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map 102 * 103 * @reg: Offset within the syscon of the register containing this field 104 * @width: Number of bits for this field 105 * @shift: Bit offset within @reg of this field (or -1 if not avail) 106 */ 107struct sdhci_arasan_soc_ctl_field { 108 u32 reg; 109 u16 width; 110 s16 shift; 111}; 112 113/** 114 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers 115 * 116 * @baseclkfreq: Where to find corecfg_baseclkfreq 117 * @clockmultiplier: Where to find corecfg_clockmultiplier 118 * @support64b: Where to find SUPPORT64B bit 119 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon 120 * 121 * It's up to the licensee of the Arsan IP block to make these available 122 * somewhere if needed. Presumably these will be scattered somewhere that's 123 * accessible via the syscon API. 124 */ 125struct sdhci_arasan_soc_ctl_map { 126 struct sdhci_arasan_soc_ctl_field baseclkfreq; 127 struct sdhci_arasan_soc_ctl_field clockmultiplier; 128 struct sdhci_arasan_soc_ctl_field support64b; 129 bool hiword_update; 130}; 131 132/** 133 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller 134 * 135 * @sdcardclk_ops: The output clock related operations 136 * @sampleclk_ops: The sample clock related operations 137 */ 138struct sdhci_arasan_clk_ops { 139 const struct clk_ops *sdcardclk_ops; 140 const struct clk_ops *sampleclk_ops; 141}; 142 143/** 144 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data. 145 * 146 * @sdcardclk_hw: Struct for the clock we might provide to a PHY. 147 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. 148 * @sampleclk_hw: Struct for the clock we might provide to a PHY. 149 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. 150 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes 151 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes 152 * @set_clk_delays: Function pointer for setting Clock Delays 153 * @clk_of_data: Platform specific runtime clock data storage pointer 154 */ 155struct sdhci_arasan_clk_data { 156 struct clk_hw sdcardclk_hw; 157 struct clk *sdcardclk; 158 struct clk_hw sampleclk_hw; 159 struct clk *sampleclk; 160 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; 161 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; 162 void (*set_clk_delays)(struct sdhci_host *host); 163 void *clk_of_data; 164}; 165 166/** 167 * struct sdhci_arasan_data - Arasan Controller Data 168 * 169 * @host: Pointer to the main SDHCI host structure. 170 * @clk_ahb: Pointer to the AHB clock 171 * @phy: Pointer to the generic phy 172 * @is_phy_on: True if the PHY is on; false if not. 173 * @internal_phy_reg: True if the PHY is within the Host controller. 174 * @has_cqe: True if controller has command queuing engine. 175 * @clk_data: Struct for the Arasan Controller Clock Data. 176 * @clk_ops: Struct for the Arasan Controller Clock Operations. 177 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. 178 * @soc_ctl_map: Map to get offsets into soc_ctl registers. 179 * @quirks: Arasan deviations from spec. 180 */ 181struct sdhci_arasan_data { 182 struct sdhci_host *host; 183 struct clk *clk_ahb; 184 struct phy *phy; 185 bool is_phy_on; 186 bool internal_phy_reg; 187 188 bool has_cqe; 189 struct sdhci_arasan_clk_data clk_data; 190 const struct sdhci_arasan_clk_ops *clk_ops; 191 192 struct regmap *soc_ctl_base; 193 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 194 unsigned int quirks; 195 196/* Controller does not have CD wired and will not function normally without */ 197#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) 198/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the 199 * internal clock even when the clock isn't stable */ 200#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) 201/* 202 * Some of the Arasan variations might not have timing requirements 203 * met at 25MHz for Default Speed mode, those controllers work at 204 * 19MHz instead 205 */ 206#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2) 207}; 208 209struct sdhci_arasan_of_data { 210 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 211 const struct sdhci_pltfm_data *pdata; 212 const struct sdhci_arasan_clk_ops *clk_ops; 213}; 214 215static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { 216 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, 217 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, 218 .hiword_update = true, 219}; 220 221static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { 222 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, 223 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 224 .hiword_update = false, 225}; 226 227static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { 228 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 }, 229 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, 230 .hiword_update = false, 231}; 232 233static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { 234 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, 235 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, 236 .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, 237 .hiword_update = false, 238}; 239 240static void sdhci_arasan_phy_set_delaychain(struct sdhci_host *host, bool enable) 241{ 242 u32 reg; 243 244 reg = readl(host->ioaddr + PHY_CTRL_REG2); 245 if (enable) 246 reg |= (PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK); 247 else 248 reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK); 249 250 writel(reg, host->ioaddr + PHY_CTRL_REG2); 251} 252 253static int sdhci_arasan_phy_set_dll(struct sdhci_host *host, bool enable) 254{ 255 u32 reg; 256 257 reg = readl(host->ioaddr + PHY_CTRL_REG2); 258 if (enable) 259 reg |= PHY_CTRL_EN_DLL_MASK; 260 else 261 reg &= ~PHY_CTRL_EN_DLL_MASK; 262 263 writel(reg, host->ioaddr + PHY_CTRL_REG2); 264 265 if (!enable) 266 return 0; 267 268 return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg, 269 (reg & PHY_CTRL_DLL_RDY_MASK), 10, 270 1000 * PHY_DLL_TIMEOUT_MS); 271} 272 273static void sdhci_arasan_phy_dll_set_freq(struct sdhci_host *host, int clock) 274{ 275 u32 reg, freq_sel, freq; 276 277 freq = DIV_ROUND_CLOSEST(clock, 1000000); 278 if (freq <= 200 && freq > 170) 279 freq_sel = FREQSEL_200M_170M; 280 else if (freq <= 170 && freq > 140) 281 freq_sel = FREQSEL_170M_140M; 282 else if (freq <= 140 && freq > 110) 283 freq_sel = FREQSEL_140M_110M; 284 else if (freq <= 110 && freq > 80) 285 freq_sel = FREQSEL_110M_80M; 286 else 287 freq_sel = FREQSEL_80M_50M; 288 289 reg = readl(host->ioaddr + PHY_CTRL_REG2); 290 reg &= ~PHY_CTRL_FREQ_SEL_MASK; 291 reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT); 292 writel(reg, host->ioaddr + PHY_CTRL_REG2); 293} 294 295/** 296 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers 297 * 298 * @host: The sdhci_host 299 * @fld: The field to write to 300 * @val: The value to write 301 * 302 * This function allows writing to fields in sdhci_arasan_soc_ctl_map. 303 * Note that if a field is specified as not available (shift < 0) then 304 * this function will silently return an error code. It will be noisy 305 * and print errors for any other (unexpected) errors. 306 * 307 * Return: 0 on success and error value on error 308 */ 309static int sdhci_arasan_syscon_write(struct sdhci_host *host, 310 const struct sdhci_arasan_soc_ctl_field *fld, 311 u32 val) 312{ 313 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 314 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 315 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; 316 u32 reg = fld->reg; 317 u16 width = fld->width; 318 s16 shift = fld->shift; 319 int ret; 320 321 /* 322 * Silently return errors for shift < 0 so caller doesn't have 323 * to check for fields which are optional. For fields that 324 * are required then caller needs to do something special 325 * anyway. 326 */ 327 if (shift < 0) 328 return -EINVAL; 329 330 if (sdhci_arasan->soc_ctl_map->hiword_update) 331 ret = regmap_write(soc_ctl_base, reg, 332 HIWORD_UPDATE(val, GENMASK(width, 0), 333 shift)); 334 else 335 ret = regmap_update_bits(soc_ctl_base, reg, 336 GENMASK(shift + width, shift), 337 val << shift); 338 339 /* Yell about (unexpected) regmap errors */ 340 if (ret) 341 pr_warn("%s: Regmap write fail: %d\n", 342 mmc_hostname(host->mmc), ret); 343 344 return ret; 345} 346 347static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) 348{ 349 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 350 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 351 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 352 bool ctrl_phy = false; 353 354 if (!IS_ERR(sdhci_arasan->phy)) { 355 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { 356 /* 357 * If PHY off, set clock to max speed and power PHY on. 358 * 359 * Although PHY docs apparently suggest power cycling 360 * when changing the clock the PHY doesn't like to be 361 * powered on while at low speeds like those used in ID 362 * mode. Even worse is powering the PHY on while the 363 * clock is off. 364 * 365 * To workaround the PHY limitations, the best we can 366 * do is to power it on at a faster speed and then slam 367 * through low speeds without power cycling. 368 */ 369 sdhci_set_clock(host, host->max_clk); 370 if (phy_power_on(sdhci_arasan->phy)) { 371 pr_err("%s: Cannot power on phy.\n", 372 mmc_hostname(host->mmc)); 373 return; 374 } 375 376 sdhci_arasan->is_phy_on = true; 377 378 /* 379 * We'll now fall through to the below case with 380 * ctrl_phy = false (so we won't turn off/on). The 381 * sdhci_set_clock() will set the real clock. 382 */ 383 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { 384 /* 385 * At higher clock speeds the PHY is fine being power 386 * cycled and docs say you _should_ power cycle when 387 * changing clock speeds. 388 */ 389 ctrl_phy = true; 390 } 391 } 392 393 if (ctrl_phy && sdhci_arasan->is_phy_on) { 394 phy_power_off(sdhci_arasan->phy); 395 sdhci_arasan->is_phy_on = false; 396 } 397 398 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { 399 /* 400 * Some of the Arasan variations might not have timing 401 * requirements met at 25MHz for Default Speed mode, 402 * those controllers work at 19MHz instead. 403 */ 404 if (clock == DEFAULT_SPEED_MAX_DTR) 405 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25; 406 } 407 408 /* Set the Input and Output Clock Phase Delays */ 409 if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ) 410 clk_data->set_clk_delays(host); 411 412 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) { 413 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 414 sdhci_arasan_phy_set_dll(host, 0); 415 sdhci_arasan_phy_set_delaychain(host, 0); 416 sdhci_arasan_phy_dll_set_freq(host, clock); 417 } else if (sdhci_arasan->internal_phy_reg) { 418 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 419 sdhci_arasan_phy_set_delaychain(host, 1); 420 } 421 422 sdhci_set_clock(host, clock); 423 424 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) 425 sdhci_arasan_phy_set_dll(host, 1); 426 427 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) 428 /* 429 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE 430 * after enabling the clock even though the clock is not 431 * stable. Trying to use a clock without waiting here results 432 * in EILSEQ while detecting some older/slower cards. The 433 * chosen delay is the maximum delay from sdhci_set_clock. 434 */ 435 msleep(20); 436 437 if (ctrl_phy) { 438 if (phy_power_on(sdhci_arasan->phy)) { 439 pr_err("%s: Cannot power on phy.\n", 440 mmc_hostname(host->mmc)); 441 return; 442 } 443 444 sdhci_arasan->is_phy_on = true; 445 } 446} 447 448static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, 449 struct mmc_ios *ios) 450{ 451 u32 vendor; 452 struct sdhci_host *host = mmc_priv(mmc); 453 454 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); 455 if (ios->enhanced_strobe) 456 vendor |= VENDOR_ENHANCED_STROBE; 457 else 458 vendor &= ~VENDOR_ENHANCED_STROBE; 459 460 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); 461} 462 463static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 464{ 465 u8 ctrl; 466 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 467 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 468 469 sdhci_and_cqhci_reset(host, mask); 470 471 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { 472 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 473 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 474 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 475 } 476} 477 478static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, 479 struct mmc_ios *ios) 480{ 481 switch (ios->signal_voltage) { 482 case MMC_SIGNAL_VOLTAGE_180: 483 /* 484 * Plese don't switch to 1V8 as arasan,5.1 doesn't 485 * actually refer to this setting to indicate the 486 * signal voltage and the state machine will be broken 487 * actually if we force to enable 1V8. That's something 488 * like broken quirk but we could work around here. 489 */ 490 return 0; 491 case MMC_SIGNAL_VOLTAGE_330: 492 case MMC_SIGNAL_VOLTAGE_120: 493 /* We don't support 3V3 and 1V2 */ 494 break; 495 } 496 497 return -EINVAL; 498} 499 500static const struct sdhci_ops sdhci_arasan_ops = { 501 .set_clock = sdhci_arasan_set_clock, 502 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 503 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 504 .set_bus_width = sdhci_set_bus_width, 505 .reset = sdhci_arasan_reset, 506 .set_uhs_signaling = sdhci_set_uhs_signaling, 507 .set_power = sdhci_set_power_and_bus_voltage, 508}; 509 510static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask) 511{ 512 int cmd_error = 0; 513 int data_error = 0; 514 515 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 516 return intmask; 517 518 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 519 520 return 0; 521} 522 523static void sdhci_arasan_dumpregs(struct mmc_host *mmc) 524{ 525 sdhci_dumpregs(mmc_priv(mmc)); 526} 527 528static void sdhci_arasan_cqe_enable(struct mmc_host *mmc) 529{ 530 struct sdhci_host *host = mmc_priv(mmc); 531 u32 reg; 532 533 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 534 while (reg & SDHCI_DATA_AVAILABLE) { 535 sdhci_readl(host, SDHCI_BUFFER); 536 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 537 } 538 539 sdhci_cqe_enable(mmc); 540} 541 542static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = { 543 .enable = sdhci_arasan_cqe_enable, 544 .disable = sdhci_cqe_disable, 545 .dumpregs = sdhci_arasan_dumpregs, 546}; 547 548static const struct sdhci_ops sdhci_arasan_cqe_ops = { 549 .set_clock = sdhci_arasan_set_clock, 550 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 551 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 552 .set_bus_width = sdhci_set_bus_width, 553 .reset = sdhci_arasan_reset, 554 .set_uhs_signaling = sdhci_set_uhs_signaling, 555 .set_power = sdhci_set_power_and_bus_voltage, 556 .irq = sdhci_arasan_cqhci_irq, 557}; 558 559static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { 560 .ops = &sdhci_arasan_cqe_ops, 561 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 562 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 563 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 564}; 565 566#ifdef CONFIG_PM_SLEEP 567/** 568 * sdhci_arasan_suspend - Suspend method for the driver 569 * @dev: Address of the device structure 570 * 571 * Put the device in a low power state. 572 * 573 * Return: 0 on success and error value on error 574 */ 575static int sdhci_arasan_suspend(struct device *dev) 576{ 577 struct sdhci_host *host = dev_get_drvdata(dev); 578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 579 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 580 int ret; 581 582 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 583 mmc_retune_needed(host->mmc); 584 585 if (sdhci_arasan->has_cqe) { 586 ret = cqhci_suspend(host->mmc); 587 if (ret) 588 return ret; 589 } 590 591 ret = sdhci_suspend_host(host); 592 if (ret) 593 return ret; 594 595 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { 596 ret = phy_power_off(sdhci_arasan->phy); 597 if (ret) { 598 dev_err(dev, "Cannot power off phy.\n"); 599 if (sdhci_resume_host(host)) 600 dev_err(dev, "Cannot resume host.\n"); 601 602 return ret; 603 } 604 sdhci_arasan->is_phy_on = false; 605 } 606 607 clk_disable(pltfm_host->clk); 608 clk_disable(sdhci_arasan->clk_ahb); 609 610 return 0; 611} 612 613/** 614 * sdhci_arasan_resume - Resume method for the driver 615 * @dev: Address of the device structure 616 * 617 * Resume operation after suspend 618 * 619 * Return: 0 on success and error value on error 620 */ 621static int sdhci_arasan_resume(struct device *dev) 622{ 623 struct sdhci_host *host = dev_get_drvdata(dev); 624 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 625 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 626 int ret; 627 628 ret = clk_enable(sdhci_arasan->clk_ahb); 629 if (ret) { 630 dev_err(dev, "Cannot enable AHB clock.\n"); 631 return ret; 632 } 633 634 ret = clk_enable(pltfm_host->clk); 635 if (ret) { 636 dev_err(dev, "Cannot enable SD clock.\n"); 637 return ret; 638 } 639 640 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { 641 ret = phy_power_on(sdhci_arasan->phy); 642 if (ret) { 643 dev_err(dev, "Cannot power on phy.\n"); 644 return ret; 645 } 646 sdhci_arasan->is_phy_on = true; 647 } 648 649 ret = sdhci_resume_host(host); 650 if (ret) { 651 dev_err(dev, "Cannot resume host.\n"); 652 return ret; 653 } 654 655 if (sdhci_arasan->has_cqe) 656 return cqhci_resume(host->mmc); 657 658 return 0; 659} 660#endif /* ! CONFIG_PM_SLEEP */ 661 662static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, 663 sdhci_arasan_resume); 664 665/** 666 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate 667 * 668 * @hw: Pointer to the hardware clock structure. 669 * @parent_rate: The parent rate (should be rate of clk_xin). 670 * 671 * Return the current actual rate of the SD card clock. This can be used 672 * to communicate with out PHY. 673 * 674 * Return: The card clock rate. 675 */ 676static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, 677 unsigned long parent_rate) 678{ 679 struct sdhci_arasan_clk_data *clk_data = 680 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 681 struct sdhci_arasan_data *sdhci_arasan = 682 container_of(clk_data, struct sdhci_arasan_data, clk_data); 683 struct sdhci_host *host = sdhci_arasan->host; 684 685 return host->mmc->actual_clock; 686} 687 688static const struct clk_ops arasan_sdcardclk_ops = { 689 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 690}; 691 692/** 693 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate 694 * 695 * @hw: Pointer to the hardware clock structure. 696 * @parent_rate: The parent rate (should be rate of clk_xin). 697 * 698 * Return the current actual rate of the sampling clock. This can be used 699 * to communicate with out PHY. 700 * 701 * Return: The sample clock rate. 702 */ 703static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, 704 unsigned long parent_rate) 705{ 706 struct sdhci_arasan_clk_data *clk_data = 707 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 708 struct sdhci_arasan_data *sdhci_arasan = 709 container_of(clk_data, struct sdhci_arasan_data, clk_data); 710 struct sdhci_host *host = sdhci_arasan->host; 711 712 return host->mmc->actual_clock; 713} 714 715static const struct clk_ops arasan_sampleclk_ops = { 716 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 717}; 718 719/** 720 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays 721 * 722 * @hw: Pointer to the hardware clock structure. 723 * @degrees: The clock phase shift between 0 - 359. 724 * 725 * Set the SD Output Clock Tap Delays for Output path 726 * 727 * Return: 0 on success and error value on error 728 */ 729static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) 730{ 731 struct sdhci_arasan_clk_data *clk_data = 732 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 733 struct sdhci_arasan_data *sdhci_arasan = 734 container_of(clk_data, struct sdhci_arasan_data, clk_data); 735 struct sdhci_host *host = sdhci_arasan->host; 736 const char *clk_name = clk_hw_get_name(hw); 737 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; 738 u8 tap_delay, tap_max = 0; 739 int ret; 740 741 /* This is applicable for SDHCI_SPEC_300 and above */ 742 if (host->version < SDHCI_SPEC_300) 743 return 0; 744 745 switch (host->timing) { 746 case MMC_TIMING_MMC_HS: 747 case MMC_TIMING_SD_HS: 748 case MMC_TIMING_UHS_SDR25: 749 case MMC_TIMING_UHS_DDR50: 750 case MMC_TIMING_MMC_DDR52: 751 /* For 50MHz clock, 30 Taps are available */ 752 tap_max = 30; 753 break; 754 case MMC_TIMING_UHS_SDR50: 755 /* For 100MHz clock, 15 Taps are available */ 756 tap_max = 15; 757 break; 758 case MMC_TIMING_UHS_SDR104: 759 case MMC_TIMING_MMC_HS200: 760 /* For 200MHz clock, 8 Taps are available */ 761 tap_max = 8; 762 break; 763 default: 764 break; 765 } 766 767 tap_delay = (degrees * tap_max) / 360; 768 769 /* Set the Clock Phase */ 770 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); 771 if (ret) 772 pr_err("Error setting Output Tap Delay\n"); 773 774 /* Release DLL Reset */ 775 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE); 776 777 return ret; 778} 779 780static const struct clk_ops zynqmp_sdcardclk_ops = { 781 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 782 .set_phase = sdhci_zynqmp_sdcardclk_set_phase, 783}; 784 785/** 786 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays 787 * 788 * @hw: Pointer to the hardware clock structure. 789 * @degrees: The clock phase shift between 0 - 359. 790 * 791 * Set the SD Input Clock Tap Delays for Input path 792 * 793 * Return: 0 on success and error value on error 794 */ 795static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) 796{ 797 struct sdhci_arasan_clk_data *clk_data = 798 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 799 struct sdhci_arasan_data *sdhci_arasan = 800 container_of(clk_data, struct sdhci_arasan_data, clk_data); 801 struct sdhci_host *host = sdhci_arasan->host; 802 const char *clk_name = clk_hw_get_name(hw); 803 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; 804 u8 tap_delay, tap_max = 0; 805 int ret; 806 807 /* This is applicable for SDHCI_SPEC_300 and above */ 808 if (host->version < SDHCI_SPEC_300) 809 return 0; 810 811 /* Assert DLL Reset */ 812 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT); 813 814 switch (host->timing) { 815 case MMC_TIMING_MMC_HS: 816 case MMC_TIMING_SD_HS: 817 case MMC_TIMING_UHS_SDR25: 818 case MMC_TIMING_UHS_DDR50: 819 case MMC_TIMING_MMC_DDR52: 820 /* For 50MHz clock, 120 Taps are available */ 821 tap_max = 120; 822 break; 823 case MMC_TIMING_UHS_SDR50: 824 /* For 100MHz clock, 60 Taps are available */ 825 tap_max = 60; 826 break; 827 case MMC_TIMING_UHS_SDR104: 828 case MMC_TIMING_MMC_HS200: 829 /* For 200MHz clock, 30 Taps are available */ 830 tap_max = 30; 831 break; 832 default: 833 break; 834 } 835 836 tap_delay = (degrees * tap_max) / 360; 837 838 /* Set the Clock Phase */ 839 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); 840 if (ret) 841 pr_err("Error setting Input Tap Delay\n"); 842 843 return ret; 844} 845 846static const struct clk_ops zynqmp_sampleclk_ops = { 847 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 848 .set_phase = sdhci_zynqmp_sampleclk_set_phase, 849}; 850 851/** 852 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays 853 * 854 * @hw: Pointer to the hardware clock structure. 855 * @degrees: The clock phase shift between 0 - 359. 856 * 857 * Set the SD Output Clock Tap Delays for Output path 858 * 859 * Return: 0 on success and error value on error 860 */ 861static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) 862{ 863 struct sdhci_arasan_clk_data *clk_data = 864 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 865 struct sdhci_arasan_data *sdhci_arasan = 866 container_of(clk_data, struct sdhci_arasan_data, clk_data); 867 struct sdhci_host *host = sdhci_arasan->host; 868 u8 tap_delay, tap_max = 0; 869 870 /* This is applicable for SDHCI_SPEC_300 and above */ 871 if (host->version < SDHCI_SPEC_300) 872 return 0; 873 874 switch (host->timing) { 875 case MMC_TIMING_MMC_HS: 876 case MMC_TIMING_SD_HS: 877 case MMC_TIMING_UHS_SDR25: 878 case MMC_TIMING_UHS_DDR50: 879 case MMC_TIMING_MMC_DDR52: 880 /* For 50MHz clock, 30 Taps are available */ 881 tap_max = 30; 882 break; 883 case MMC_TIMING_UHS_SDR50: 884 /* For 100MHz clock, 15 Taps are available */ 885 tap_max = 15; 886 break; 887 case MMC_TIMING_UHS_SDR104: 888 case MMC_TIMING_MMC_HS200: 889 /* For 200MHz clock, 8 Taps are available */ 890 tap_max = 8; 891 break; 892 default: 893 break; 894 } 895 896 tap_delay = (degrees * tap_max) / 360; 897 898 /* Set the Clock Phase */ 899 if (tap_delay) { 900 u32 regval; 901 902 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); 903 regval |= SDHCI_OTAPDLY_ENABLE; 904 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); 905 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK; 906 regval |= tap_delay; 907 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); 908 } 909 910 return 0; 911} 912 913static const struct clk_ops versal_sdcardclk_ops = { 914 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 915 .set_phase = sdhci_versal_sdcardclk_set_phase, 916}; 917 918/** 919 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays 920 * 921 * @hw: Pointer to the hardware clock structure. 922 * @degrees: The clock phase shift between 0 - 359. 923 * 924 * Set the SD Input Clock Tap Delays for Input path 925 * 926 * Return: 0 on success and error value on error 927 */ 928static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) 929{ 930 struct sdhci_arasan_clk_data *clk_data = 931 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 932 struct sdhci_arasan_data *sdhci_arasan = 933 container_of(clk_data, struct sdhci_arasan_data, clk_data); 934 struct sdhci_host *host = sdhci_arasan->host; 935 u8 tap_delay, tap_max = 0; 936 937 /* This is applicable for SDHCI_SPEC_300 and above */ 938 if (host->version < SDHCI_SPEC_300) 939 return 0; 940 941 switch (host->timing) { 942 case MMC_TIMING_MMC_HS: 943 case MMC_TIMING_SD_HS: 944 case MMC_TIMING_UHS_SDR25: 945 case MMC_TIMING_UHS_DDR50: 946 case MMC_TIMING_MMC_DDR52: 947 /* For 50MHz clock, 120 Taps are available */ 948 tap_max = 120; 949 break; 950 case MMC_TIMING_UHS_SDR50: 951 /* For 100MHz clock, 60 Taps are available */ 952 tap_max = 60; 953 break; 954 case MMC_TIMING_UHS_SDR104: 955 case MMC_TIMING_MMC_HS200: 956 /* For 200MHz clock, 30 Taps are available */ 957 tap_max = 30; 958 break; 959 default: 960 break; 961 } 962 963 tap_delay = (degrees * tap_max) / 360; 964 965 /* Set the Clock Phase */ 966 if (tap_delay) { 967 u32 regval; 968 969 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); 970 regval |= SDHCI_ITAPDLY_CHGWIN; 971 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 972 regval |= SDHCI_ITAPDLY_ENABLE; 973 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 974 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK; 975 regval |= tap_delay; 976 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 977 regval &= ~SDHCI_ITAPDLY_CHGWIN; 978 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 979 } 980 981 return 0; 982} 983 984static const struct clk_ops versal_sampleclk_ops = { 985 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 986 .set_phase = sdhci_versal_sampleclk_set_phase, 987}; 988 989static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct clk_hw *hw, int degrees) 990{ 991 struct sdhci_arasan_clk_data *clk_data = 992 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw); 993 struct sdhci_arasan_data *sdhci_arasan = 994 container_of(clk_data, struct sdhci_arasan_data, clk_data); 995 struct sdhci_host *host = sdhci_arasan->host; 996 u8 tap_delay, tap_max = 0; 997 998 switch (host->timing) { 999 case MMC_TIMING_MMC_HS: 1000 case MMC_TIMING_MMC_DDR52: 1001 tap_max = 16; 1002 break; 1003 case MMC_TIMING_MMC_HS200: 1004 case MMC_TIMING_MMC_HS400: 1005 /* For 200MHz clock, 32 Taps are available */ 1006 tap_max = 32; 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 tap_delay = (degrees * tap_max) / 360; 1013 1014 /* Set the Clock Phase */ 1015 if (tap_delay) { 1016 u32 regval; 1017 1018 regval = sdhci_readl(host, PHY_CTRL_REG1); 1019 regval |= PHY_CTRL_OTAPDLY_ENA_MASK; 1020 sdhci_writel(host, regval, PHY_CTRL_REG1); 1021 regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK; 1022 regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT; 1023 sdhci_writel(host, regval, PHY_CTRL_REG1); 1024 } 1025 1026 return 0; 1027} 1028 1029static const struct clk_ops versal_net_sdcardclk_ops = { 1030 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, 1031 .set_phase = sdhci_versal_net_emmc_sdcardclk_set_phase, 1032}; 1033 1034static int sdhci_versal_net_emmc_sampleclk_set_phase(struct clk_hw *hw, int degrees) 1035{ 1036 struct sdhci_arasan_clk_data *clk_data = 1037 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); 1038 struct sdhci_arasan_data *sdhci_arasan = 1039 container_of(clk_data, struct sdhci_arasan_data, clk_data); 1040 struct sdhci_host *host = sdhci_arasan->host; 1041 u8 tap_delay, tap_max = 0; 1042 u32 regval; 1043 1044 switch (host->timing) { 1045 case MMC_TIMING_MMC_HS: 1046 case MMC_TIMING_MMC_DDR52: 1047 tap_max = 32; 1048 break; 1049 case MMC_TIMING_MMC_HS400: 1050 /* Strobe select tap point for strb90 and strb180 */ 1051 regval = sdhci_readl(host, PHY_CTRL_REG1); 1052 regval &= ~PHY_CTRL_STRB_SEL_MASK; 1053 regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT; 1054 sdhci_writel(host, regval, PHY_CTRL_REG1); 1055 break; 1056 default: 1057 break; 1058 } 1059 1060 tap_delay = (degrees * tap_max) / 360; 1061 1062 /* Set the Clock Phase */ 1063 if (tap_delay) { 1064 regval = sdhci_readl(host, PHY_CTRL_REG1); 1065 regval |= PHY_CTRL_ITAP_CHG_WIN_MASK; 1066 sdhci_writel(host, regval, PHY_CTRL_REG1); 1067 regval |= PHY_CTRL_ITAPDLY_ENA_MASK; 1068 sdhci_writel(host, regval, PHY_CTRL_REG1); 1069 regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK; 1070 regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT; 1071 sdhci_writel(host, regval, PHY_CTRL_REG1); 1072 regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK; 1073 sdhci_writel(host, regval, PHY_CTRL_REG1); 1074 } 1075 1076 return 0; 1077} 1078 1079static const struct clk_ops versal_net_sampleclk_ops = { 1080 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, 1081 .set_phase = sdhci_versal_net_emmc_sampleclk_set_phase, 1082}; 1083 1084static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) 1085{ 1086 u16 clk; 1087 1088 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1089 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); 1090 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1091 1092 /* Issue DLL Reset */ 1093 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); 1094 1095 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1096 1097 sdhci_enable_clk(host, clk); 1098} 1099 1100static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode) 1101{ 1102 struct sdhci_host *host = mmc_priv(mmc); 1103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1104 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1105 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; 1106 const char *clk_name = clk_hw_get_name(hw); 1107 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : 1108 NODE_SD_1; 1109 int err; 1110 1111 /* ZynqMP SD controller does not perform auto tuning in DDR50 mode */ 1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 1113 return 0; 1114 1115 arasan_zynqmp_dll_reset(host, device_id); 1116 1117 err = sdhci_execute_tuning(mmc, opcode); 1118 if (err) 1119 return err; 1120 1121 arasan_zynqmp_dll_reset(host, device_id); 1122 1123 return 0; 1124} 1125 1126/** 1127 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier 1128 * 1129 * @host: The sdhci_host 1130 * @value: The value to write 1131 * 1132 * The corecfg_clockmultiplier is supposed to contain clock multiplier 1133 * value of programmable clock generator. 1134 * 1135 * NOTES: 1136 * - Many existing devices don't seem to do this and work fine. To keep 1137 * compatibility for old hardware where the device tree doesn't provide a 1138 * register map, this function is a noop if a soc_ctl_map hasn't been provided 1139 * for this platform. 1140 * - The value of corecfg_clockmultiplier should sync with that of corresponding 1141 * value reading from sdhci_capability_register. So this function is called 1142 * once at probe time and never called again. 1143 */ 1144static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, 1145 u32 value) 1146{ 1147 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1148 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1149 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 1150 sdhci_arasan->soc_ctl_map; 1151 1152 /* Having a map is optional */ 1153 if (!soc_ctl_map) 1154 return; 1155 1156 /* If we have a map, we expect to have a syscon */ 1157 if (!sdhci_arasan->soc_ctl_base) { 1158 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 1159 mmc_hostname(host->mmc)); 1160 return; 1161 } 1162 1163 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); 1164} 1165 1166/** 1167 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq 1168 * 1169 * @host: The sdhci_host 1170 * 1171 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This 1172 * function can be used to make that happen. 1173 * 1174 * NOTES: 1175 * - Many existing devices don't seem to do this and work fine. To keep 1176 * compatibility for old hardware where the device tree doesn't provide a 1177 * register map, this function is a noop if a soc_ctl_map hasn't been provided 1178 * for this platform. 1179 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider 1180 * to achieve lower clock rates. That means that this function is called once 1181 * at probe time and never called again. 1182 */ 1183static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) 1184{ 1185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1186 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1187 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = 1188 sdhci_arasan->soc_ctl_map; 1189 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); 1190 1191 /* Having a map is optional */ 1192 if (!soc_ctl_map) 1193 return; 1194 1195 /* If we have a map, we expect to have a syscon */ 1196 if (!sdhci_arasan->soc_ctl_base) { 1197 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 1198 mmc_hostname(host->mmc)); 1199 return; 1200 } 1201 1202 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); 1203} 1204 1205static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) 1206{ 1207 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1208 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1209 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 1210 1211 clk_set_phase(clk_data->sampleclk, 1212 clk_data->clk_phase_in[host->timing]); 1213 clk_set_phase(clk_data->sdcardclk, 1214 clk_data->clk_phase_out[host->timing]); 1215} 1216 1217static void arasan_dt_read_clk_phase(struct device *dev, 1218 struct sdhci_arasan_clk_data *clk_data, 1219 unsigned int timing, const char *prop) 1220{ 1221 struct device_node *np = dev->of_node; 1222 1223 u32 clk_phase[2] = {0}; 1224 int ret; 1225 1226 /* 1227 * Read Tap Delay values from DT, if the DT does not contain the 1228 * Tap Values then use the pre-defined values. 1229 */ 1230 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0], 1231 2, 0); 1232 if (ret < 0) { 1233 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", 1234 prop, clk_data->clk_phase_in[timing], 1235 clk_data->clk_phase_out[timing]); 1236 return; 1237 } 1238 1239 /* The values read are Input and Output Clock Delays in order */ 1240 clk_data->clk_phase_in[timing] = clk_phase[0]; 1241 clk_data->clk_phase_out[timing] = clk_phase[1]; 1242} 1243 1244/** 1245 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT 1246 * 1247 * @dev: Pointer to our struct device. 1248 * @clk_data: Pointer to the Clock Data structure 1249 * 1250 * Called at initialization to parse the values of Clock Delays. 1251 */ 1252static void arasan_dt_parse_clk_phases(struct device *dev, 1253 struct sdhci_arasan_clk_data *clk_data) 1254{ 1255 u32 mio_bank = 0; 1256 int i; 1257 1258 /* 1259 * This has been kept as a pointer and is assigned a function here. 1260 * So that different controller variants can assign their own handling 1261 * function. 1262 */ 1263 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; 1264 1265 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { 1266 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1267 ZYNQMP_ICLK_PHASE; 1268 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1269 ZYNQMP_OCLK_PHASE; 1270 1271 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); 1272 if (mio_bank == 2) { 1273 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; 1274 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90; 1275 } 1276 1277 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { 1278 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; 1279 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; 1280 } 1281 } 1282 1283 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { 1284 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1285 VERSAL_ICLK_PHASE; 1286 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1287 VERSAL_OCLK_PHASE; 1288 1289 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { 1290 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; 1291 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; 1292 } 1293 } 1294 if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) { 1295 u32 versal_net_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1296 VERSAL_NET_EMMC_ICLK_PHASE; 1297 u32 versal_net_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = 1298 VERSAL_NET_EMMC_OCLK_PHASE; 1299 1300 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { 1301 clk_data->clk_phase_in[i] = versal_net_iclk_phase[i]; 1302 clk_data->clk_phase_out[i] = versal_net_oclk_phase[i]; 1303 } 1304 } 1305 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY, 1306 "clk-phase-legacy"); 1307 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS, 1308 "clk-phase-mmc-hs"); 1309 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS, 1310 "clk-phase-sd-hs"); 1311 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12, 1312 "clk-phase-uhs-sdr12"); 1313 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25, 1314 "clk-phase-uhs-sdr25"); 1315 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50, 1316 "clk-phase-uhs-sdr50"); 1317 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104, 1318 "clk-phase-uhs-sdr104"); 1319 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, 1320 "clk-phase-uhs-ddr50"); 1321 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, 1322 "clk-phase-mmc-ddr52"); 1323 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200, 1324 "clk-phase-mmc-hs200"); 1325 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400, 1326 "clk-phase-mmc-hs400"); 1327} 1328 1329static const struct sdhci_pltfm_data sdhci_arasan_pdata = { 1330 .ops = &sdhci_arasan_ops, 1331 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1332 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1333 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1334 SDHCI_QUIRK2_STOP_WITH_TC, 1335}; 1336 1337static const struct sdhci_arasan_clk_ops arasan_clk_ops = { 1338 .sdcardclk_ops = &arasan_sdcardclk_ops, 1339 .sampleclk_ops = &arasan_sampleclk_ops, 1340}; 1341 1342static struct sdhci_arasan_of_data sdhci_arasan_generic_data = { 1343 .pdata = &sdhci_arasan_pdata, 1344 .clk_ops = &arasan_clk_ops, 1345}; 1346 1347static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = { 1348 .ops = &sdhci_arasan_cqe_ops, 1349 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1350 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1351 SDHCI_QUIRK_NO_LED | 1352 SDHCI_QUIRK_32BIT_DMA_ADDR | 1353 SDHCI_QUIRK_32BIT_DMA_SIZE | 1354 SDHCI_QUIRK_32BIT_ADMA_SIZE, 1355 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1356 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1357 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1358 SDHCI_QUIRK2_STOP_WITH_TC | 1359 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1360}; 1361 1362static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = { 1363 .ops = &sdhci_arasan_ops, 1364 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1365 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1366 SDHCI_QUIRK_NO_LED | 1367 SDHCI_QUIRK_32BIT_DMA_ADDR | 1368 SDHCI_QUIRK_32BIT_DMA_SIZE | 1369 SDHCI_QUIRK_32BIT_ADMA_SIZE, 1370 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1371 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1372 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1373 SDHCI_QUIRK2_STOP_WITH_TC | 1374 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1375}; 1376 1377static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = { 1378 .ops = &sdhci_arasan_ops, 1379 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1380 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1381 SDHCI_QUIRK_NO_LED | 1382 SDHCI_QUIRK_32BIT_DMA_ADDR | 1383 SDHCI_QUIRK_32BIT_DMA_SIZE | 1384 SDHCI_QUIRK_32BIT_ADMA_SIZE, 1385 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1386 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1387 SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1388 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1389}; 1390 1391static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = { 1392 .soc_ctl_map = &rk3399_soc_ctl_map, 1393 .pdata = &sdhci_arasan_cqe_pdata, 1394 .clk_ops = &arasan_clk_ops, 1395}; 1396 1397static struct sdhci_arasan_of_data intel_lgm_emmc_data = { 1398 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map, 1399 .pdata = &sdhci_arasan_cqe_pdata, 1400 .clk_ops = &arasan_clk_ops, 1401}; 1402 1403static struct sdhci_arasan_of_data intel_lgm_sdxc_data = { 1404 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map, 1405 .pdata = &sdhci_arasan_cqe_pdata, 1406 .clk_ops = &arasan_clk_ops, 1407}; 1408 1409static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = { 1410 .ops = &sdhci_arasan_ops, 1411 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1412 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1413 SDHCI_QUIRK2_STOP_WITH_TC, 1414}; 1415 1416static const struct sdhci_pltfm_data sdhci_arasan_versal_net_pdata = { 1417 .ops = &sdhci_arasan_ops, 1418 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1419 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | 1420 SDHCI_QUIRK2_STOP_WITH_TC | 1421 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, 1422}; 1423 1424static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = { 1425 .sdcardclk_ops = &zynqmp_sdcardclk_ops, 1426 .sampleclk_ops = &zynqmp_sampleclk_ops, 1427}; 1428 1429static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = { 1430 .pdata = &sdhci_arasan_zynqmp_pdata, 1431 .clk_ops = &zynqmp_clk_ops, 1432}; 1433 1434static const struct sdhci_arasan_clk_ops versal_clk_ops = { 1435 .sdcardclk_ops = &versal_sdcardclk_ops, 1436 .sampleclk_ops = &versal_sampleclk_ops, 1437}; 1438 1439static struct sdhci_arasan_of_data sdhci_arasan_versal_data = { 1440 .pdata = &sdhci_arasan_zynqmp_pdata, 1441 .clk_ops = &versal_clk_ops, 1442}; 1443 1444static const struct sdhci_arasan_clk_ops versal_net_clk_ops = { 1445 .sdcardclk_ops = &versal_net_sdcardclk_ops, 1446 .sampleclk_ops = &versal_net_sampleclk_ops, 1447}; 1448 1449static struct sdhci_arasan_of_data sdhci_arasan_versal_net_data = { 1450 .pdata = &sdhci_arasan_versal_net_pdata, 1451 .clk_ops = &versal_net_clk_ops, 1452}; 1453 1454static struct sdhci_arasan_of_data intel_keembay_emmc_data = { 1455 .soc_ctl_map = &intel_keembay_soc_ctl_map, 1456 .pdata = &sdhci_keembay_emmc_pdata, 1457 .clk_ops = &arasan_clk_ops, 1458}; 1459 1460static struct sdhci_arasan_of_data intel_keembay_sd_data = { 1461 .soc_ctl_map = &intel_keembay_soc_ctl_map, 1462 .pdata = &sdhci_keembay_sd_pdata, 1463 .clk_ops = &arasan_clk_ops, 1464}; 1465 1466static struct sdhci_arasan_of_data intel_keembay_sdio_data = { 1467 .soc_ctl_map = &intel_keembay_soc_ctl_map, 1468 .pdata = &sdhci_keembay_sdio_pdata, 1469 .clk_ops = &arasan_clk_ops, 1470}; 1471 1472static const struct of_device_id sdhci_arasan_of_match[] = { 1473 /* SoC-specific compatible strings w/ soc_ctl_map */ 1474 { 1475 .compatible = "rockchip,rk3399-sdhci-5.1", 1476 .data = &sdhci_arasan_rk3399_data, 1477 }, 1478 { 1479 .compatible = "intel,lgm-sdhci-5.1-emmc", 1480 .data = &intel_lgm_emmc_data, 1481 }, 1482 { 1483 .compatible = "intel,lgm-sdhci-5.1-sdxc", 1484 .data = &intel_lgm_sdxc_data, 1485 }, 1486 { 1487 .compatible = "intel,keembay-sdhci-5.1-emmc", 1488 .data = &intel_keembay_emmc_data, 1489 }, 1490 { 1491 .compatible = "intel,keembay-sdhci-5.1-sd", 1492 .data = &intel_keembay_sd_data, 1493 }, 1494 { 1495 .compatible = "intel,keembay-sdhci-5.1-sdio", 1496 .data = &intel_keembay_sdio_data, 1497 }, 1498 /* Generic compatible below here */ 1499 { 1500 .compatible = "arasan,sdhci-8.9a", 1501 .data = &sdhci_arasan_generic_data, 1502 }, 1503 { 1504 .compatible = "arasan,sdhci-5.1", 1505 .data = &sdhci_arasan_generic_data, 1506 }, 1507 { 1508 .compatible = "arasan,sdhci-4.9a", 1509 .data = &sdhci_arasan_generic_data, 1510 }, 1511 { 1512 .compatible = "xlnx,zynqmp-8.9a", 1513 .data = &sdhci_arasan_zynqmp_data, 1514 }, 1515 { 1516 .compatible = "xlnx,versal-8.9a", 1517 .data = &sdhci_arasan_versal_data, 1518 }, 1519 { 1520 .compatible = "xlnx,versal-net-emmc", 1521 .data = &sdhci_arasan_versal_net_data, 1522 }, 1523 { /* sentinel */ } 1524}; 1525MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); 1526 1527/** 1528 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use 1529 * 1530 * @sdhci_arasan: Our private data structure. 1531 * @clk_xin: Pointer to the functional clock 1532 * @dev: Pointer to our struct device. 1533 * 1534 * Some PHY devices need to know what the actual card clock is. In order for 1535 * them to find out, we'll provide a clock through the common clock framework 1536 * for them to query. 1537 * 1538 * Return: 0 on success and error value on error 1539 */ 1540static int 1541sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, 1542 struct clk *clk_xin, 1543 struct device *dev) 1544{ 1545 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 1546 struct device_node *np = dev->of_node; 1547 struct clk_init_data sdcardclk_init; 1548 const char *parent_clk_name; 1549 int ret; 1550 1551 ret = of_property_read_string_index(np, "clock-output-names", 0, 1552 &sdcardclk_init.name); 1553 if (ret) { 1554 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 1555 return ret; 1556 } 1557 1558 parent_clk_name = __clk_get_name(clk_xin); 1559 sdcardclk_init.parent_names = &parent_clk_name; 1560 sdcardclk_init.num_parents = 1; 1561 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; 1562 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; 1563 1564 clk_data->sdcardclk_hw.init = &sdcardclk_init; 1565 clk_data->sdcardclk = 1566 devm_clk_register(dev, &clk_data->sdcardclk_hw); 1567 if (IS_ERR(clk_data->sdcardclk)) 1568 return PTR_ERR(clk_data->sdcardclk); 1569 clk_data->sdcardclk_hw.init = NULL; 1570 1571 ret = of_clk_add_provider(np, of_clk_src_simple_get, 1572 clk_data->sdcardclk); 1573 if (ret) 1574 dev_err(dev, "Failed to add sdcard clock provider\n"); 1575 1576 return ret; 1577} 1578 1579/** 1580 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use 1581 * 1582 * @sdhci_arasan: Our private data structure. 1583 * @clk_xin: Pointer to the functional clock 1584 * @dev: Pointer to our struct device. 1585 * 1586 * Some PHY devices need to know what the actual card clock is. In order for 1587 * them to find out, we'll provide a clock through the common clock framework 1588 * for them to query. 1589 * 1590 * Return: 0 on success and error value on error 1591 */ 1592static int 1593sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, 1594 struct clk *clk_xin, 1595 struct device *dev) 1596{ 1597 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; 1598 struct device_node *np = dev->of_node; 1599 struct clk_init_data sampleclk_init; 1600 const char *parent_clk_name; 1601 int ret; 1602 1603 ret = of_property_read_string_index(np, "clock-output-names", 1, 1604 &sampleclk_init.name); 1605 if (ret) { 1606 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); 1607 return ret; 1608 } 1609 1610 parent_clk_name = __clk_get_name(clk_xin); 1611 sampleclk_init.parent_names = &parent_clk_name; 1612 sampleclk_init.num_parents = 1; 1613 sampleclk_init.flags = CLK_GET_RATE_NOCACHE; 1614 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; 1615 1616 clk_data->sampleclk_hw.init = &sampleclk_init; 1617 clk_data->sampleclk = 1618 devm_clk_register(dev, &clk_data->sampleclk_hw); 1619 if (IS_ERR(clk_data->sampleclk)) 1620 return PTR_ERR(clk_data->sampleclk); 1621 clk_data->sampleclk_hw.init = NULL; 1622 1623 ret = of_clk_add_provider(np, of_clk_src_simple_get, 1624 clk_data->sampleclk); 1625 if (ret) 1626 dev_err(dev, "Failed to add sample clock provider\n"); 1627 1628 return ret; 1629} 1630 1631/** 1632 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() 1633 * 1634 * @dev: Pointer to our struct device. 1635 * 1636 * Should be called any time we're exiting and sdhci_arasan_register_sdclk() 1637 * returned success. 1638 */ 1639static void sdhci_arasan_unregister_sdclk(struct device *dev) 1640{ 1641 struct device_node *np = dev->of_node; 1642 1643 if (!of_property_present(np, "#clock-cells")) 1644 return; 1645 1646 of_clk_del_provider(dev->of_node); 1647} 1648 1649/** 1650 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support) 1651 * @host: The sdhci_host 1652 * @value: The value to write 1653 * 1654 * This should be set based on the System Address Bus. 1655 * 0: the Core supports only 32-bit System Address Bus. 1656 * 1: the Core supports 64-bit System Address Bus. 1657 * 1658 * NOTE: 1659 * For Keem Bay, it is required to clear this bit. Its default value is 1'b1. 1660 * Keem Bay does not support 64-bit access. 1661 */ 1662static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value) 1663{ 1664 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1665 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1666 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; 1667 1668 /* Having a map is optional */ 1669 soc_ctl_map = sdhci_arasan->soc_ctl_map; 1670 if (!soc_ctl_map) 1671 return; 1672 1673 /* If we have a map, we expect to have a syscon */ 1674 if (!sdhci_arasan->soc_ctl_base) { 1675 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", 1676 mmc_hostname(host->mmc)); 1677 return; 1678 } 1679 1680 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); 1681} 1682 1683/** 1684 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use 1685 * 1686 * @sdhci_arasan: Our private data structure. 1687 * @clk_xin: Pointer to the functional clock 1688 * @dev: Pointer to our struct device. 1689 * 1690 * Some PHY devices need to know what the actual card clock is. In order for 1691 * them to find out, we'll provide a clock through the common clock framework 1692 * for them to query. 1693 * 1694 * Note: without seriously re-architecting SDHCI's clock code and testing on 1695 * all platforms, there's no way to create a totally beautiful clock here 1696 * with all clock ops implemented. Instead, we'll just create a clock that can 1697 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock 1698 * framework that we're doing things behind its back. This should be sufficient 1699 * to create nice clean device tree bindings and later (if needed) we can try 1700 * re-architecting SDHCI if we see some benefit to it. 1701 * 1702 * Return: 0 on success and error value on error 1703 */ 1704static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, 1705 struct clk *clk_xin, 1706 struct device *dev) 1707{ 1708 struct device_node *np = dev->of_node; 1709 u32 num_clks = 0; 1710 int ret; 1711 1712 /* Providing a clock to the PHY is optional; no error if missing */ 1713 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) 1714 return 0; 1715 1716 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev); 1717 if (ret) 1718 return ret; 1719 1720 if (num_clks) { 1721 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, 1722 dev); 1723 if (ret) { 1724 sdhci_arasan_unregister_sdclk(dev); 1725 return ret; 1726 } 1727 } 1728 1729 return 0; 1730} 1731 1732static int sdhci_zynqmp_set_dynamic_config(struct device *dev, 1733 struct sdhci_arasan_data *sdhci_arasan) 1734{ 1735 struct sdhci_host *host = sdhci_arasan->host; 1736 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; 1737 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1738 const char *clk_name = clk_hw_get_name(hw); 1739 u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; 1740 struct reset_control *rstc; 1741 int ret; 1742 1743 /* Obtain SDHC reset control */ 1744 rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 1745 if (IS_ERR(rstc)) { 1746 dev_err(dev, "Cannot get SDHC reset.\n"); 1747 return PTR_ERR(rstc); 1748 } 1749 1750 ret = reset_control_assert(rstc); 1751 if (ret) 1752 return ret; 1753 1754 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0); 1755 if (ret) 1756 return ret; 1757 1758 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL, 1759 !!(host->mmc->caps & MMC_CAP_NONREMOVABLE)); 1760 if (ret) 1761 return ret; 1762 1763 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); 1764 if (mhz > 100 && mhz <= 200) 1765 mhz = 200; 1766 else if (mhz > 50 && mhz <= 100) 1767 mhz = 100; 1768 else if (mhz > 25 && mhz <= 50) 1769 mhz = 50; 1770 else 1771 mhz = 25; 1772 1773 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz); 1774 if (ret) 1775 return ret; 1776 1777 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT, 1778 !!(host->mmc->caps & MMC_CAP_8_BIT_DATA)); 1779 if (ret) 1780 return ret; 1781 1782 ret = reset_control_deassert(rstc); 1783 if (ret) 1784 return ret; 1785 1786 usleep_range(1000, 1500); 1787 1788 return 0; 1789} 1790 1791static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 1792{ 1793 struct sdhci_host *host = sdhci_arasan->host; 1794 struct cqhci_host *cq_host; 1795 bool dma64; 1796 int ret; 1797 1798 if (!sdhci_arasan->has_cqe) 1799 return sdhci_add_host(host); 1800 1801 ret = sdhci_setup_host(host); 1802 if (ret) 1803 return ret; 1804 1805 cq_host = devm_kzalloc(host->mmc->parent, 1806 sizeof(*cq_host), GFP_KERNEL); 1807 if (!cq_host) { 1808 ret = -ENOMEM; 1809 goto cleanup; 1810 } 1811 1812 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 1813 cq_host->ops = &sdhci_arasan_cqhci_ops; 1814 1815 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1816 if (dma64) 1817 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1818 1819 ret = cqhci_init(cq_host, host->mmc, dma64); 1820 if (ret) 1821 goto cleanup; 1822 1823 ret = __sdhci_add_host(host); 1824 if (ret) 1825 goto cleanup; 1826 1827 return 0; 1828 1829cleanup: 1830 sdhci_cleanup_host(host); 1831 return ret; 1832} 1833 1834static int sdhci_arasan_probe(struct platform_device *pdev) 1835{ 1836 int ret; 1837 struct device_node *node; 1838 struct clk *clk_xin; 1839 struct clk *clk_dll; 1840 struct sdhci_host *host; 1841 struct sdhci_pltfm_host *pltfm_host; 1842 struct device *dev = &pdev->dev; 1843 struct device_node *np = dev->of_node; 1844 struct sdhci_arasan_data *sdhci_arasan; 1845 const struct sdhci_arasan_of_data *data; 1846 1847 data = of_device_get_match_data(dev); 1848 if (!data) 1849 return -EINVAL; 1850 1851 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); 1852 1853 if (IS_ERR(host)) 1854 return PTR_ERR(host); 1855 1856 pltfm_host = sdhci_priv(host); 1857 sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 1858 sdhci_arasan->host = host; 1859 1860 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; 1861 sdhci_arasan->clk_ops = data->clk_ops; 1862 1863 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); 1864 if (node) { 1865 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 1866 of_node_put(node); 1867 1868 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 1869 ret = dev_err_probe(dev, 1870 PTR_ERR(sdhci_arasan->soc_ctl_base), 1871 "Can't get syscon\n"); 1872 goto err_pltfm_free; 1873 } 1874 } 1875 1876 sdhci_get_of_property(pdev); 1877 1878 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); 1879 if (IS_ERR(sdhci_arasan->clk_ahb)) { 1880 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), 1881 "clk_ahb clock not found.\n"); 1882 goto err_pltfm_free; 1883 } 1884 1885 clk_xin = devm_clk_get(dev, "clk_xin"); 1886 if (IS_ERR(clk_xin)) { 1887 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); 1888 goto err_pltfm_free; 1889 } 1890 1891 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 1892 if (ret) { 1893 dev_err(dev, "Unable to enable AHB clock.\n"); 1894 goto err_pltfm_free; 1895 } 1896 1897 /* If clock-frequency property is set, use the provided value */ 1898 if (pltfm_host->clock && 1899 pltfm_host->clock != clk_get_rate(clk_xin)) { 1900 ret = clk_set_rate(clk_xin, pltfm_host->clock); 1901 if (ret) { 1902 dev_err(&pdev->dev, "Failed to set SD clock rate\n"); 1903 goto clk_dis_ahb; 1904 } 1905 } 1906 1907 ret = clk_prepare_enable(clk_xin); 1908 if (ret) { 1909 dev_err(dev, "Unable to enable SD clock.\n"); 1910 goto clk_dis_ahb; 1911 } 1912 1913 clk_dll = devm_clk_get_optional_enabled(dev, "gate"); 1914 if (IS_ERR(clk_dll)) { 1915 ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); 1916 goto clk_disable_all; 1917 } 1918 1919 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 1920 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; 1921 1922 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) 1923 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; 1924 1925 pltfm_host->clk = clk_xin; 1926 1927 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) 1928 sdhci_arasan_update_clockmultiplier(host, 0x0); 1929 1930 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || 1931 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || 1932 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { 1933 sdhci_arasan_update_clockmultiplier(host, 0x0); 1934 sdhci_arasan_update_support64b(host, 0x0); 1935 1936 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1937 } 1938 1939 sdhci_arasan_update_baseclkfreq(host); 1940 1941 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev); 1942 if (ret) 1943 goto clk_disable_all; 1944 1945 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { 1946 host->mmc_host_ops.execute_tuning = 1947 arasan_zynqmp_execute_tuning; 1948 1949 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; 1950 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 1951 } 1952 1953 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); 1954 1955 ret = mmc_of_parse(host->mmc); 1956 if (ret) { 1957 ret = dev_err_probe(dev, ret, "parsing dt failed.\n"); 1958 goto unreg_clk; 1959 } 1960 1961 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { 1962 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); 1963 if (!ret) { 1964 ret = sdhci_zynqmp_set_dynamic_config(dev, sdhci_arasan); 1965 if (ret) 1966 goto unreg_clk; 1967 } 1968 } 1969 1970 sdhci_arasan->phy = ERR_PTR(-ENODEV); 1971 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { 1972 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); 1973 if (IS_ERR(sdhci_arasan->phy)) { 1974 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), 1975 "No phy for arasan,sdhci-5.1.\n"); 1976 goto unreg_clk; 1977 } 1978 1979 ret = phy_init(sdhci_arasan->phy); 1980 if (ret < 0) { 1981 dev_err(dev, "phy_init err.\n"); 1982 goto unreg_clk; 1983 } 1984 1985 host->mmc_host_ops.hs400_enhanced_strobe = 1986 sdhci_arasan_hs400_enhanced_strobe; 1987 host->mmc_host_ops.start_signal_voltage_switch = 1988 sdhci_arasan_voltage_switch; 1989 sdhci_arasan->has_cqe = true; 1990 host->mmc->caps2 |= MMC_CAP2_CQE; 1991 1992 if (!of_property_read_bool(np, "disable-cqe-dcmd")) 1993 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 1994 } 1995 1996 if (of_device_is_compatible(np, "xlnx,versal-net-emmc")) 1997 sdhci_arasan->internal_phy_reg = true; 1998 1999 ret = sdhci_arasan_add_host(sdhci_arasan); 2000 if (ret) 2001 goto err_add_host; 2002 2003 return 0; 2004 2005err_add_host: 2006 if (!IS_ERR(sdhci_arasan->phy)) 2007 phy_exit(sdhci_arasan->phy); 2008unreg_clk: 2009 sdhci_arasan_unregister_sdclk(dev); 2010clk_disable_all: 2011 clk_disable_unprepare(clk_xin); 2012clk_dis_ahb: 2013 clk_disable_unprepare(sdhci_arasan->clk_ahb); 2014err_pltfm_free: 2015 sdhci_pltfm_free(pdev); 2016 return ret; 2017} 2018 2019static void sdhci_arasan_remove(struct platform_device *pdev) 2020{ 2021 struct sdhci_host *host = platform_get_drvdata(pdev); 2022 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2023 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); 2024 struct clk *clk_ahb = sdhci_arasan->clk_ahb; 2025 struct clk *clk_xin = pltfm_host->clk; 2026 2027 if (!IS_ERR(sdhci_arasan->phy)) { 2028 if (sdhci_arasan->is_phy_on) 2029 phy_power_off(sdhci_arasan->phy); 2030 phy_exit(sdhci_arasan->phy); 2031 } 2032 2033 sdhci_arasan_unregister_sdclk(&pdev->dev); 2034 2035 sdhci_pltfm_remove(pdev); 2036 2037 clk_disable_unprepare(clk_xin); 2038 clk_disable_unprepare(clk_ahb); 2039} 2040 2041static struct platform_driver sdhci_arasan_driver = { 2042 .driver = { 2043 .name = "sdhci-arasan", 2044 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2045 .of_match_table = sdhci_arasan_of_match, 2046 .pm = &sdhci_arasan_dev_pm_ops, 2047 }, 2048 .probe = sdhci_arasan_probe, 2049 .remove_new = sdhci_arasan_remove, 2050}; 2051 2052module_platform_driver(sdhci_arasan_driver); 2053 2054MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); 2055MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); 2056MODULE_LICENSE("GPL"); 2057