1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 4 * 5 * This is a driver for the SDHC controller found in Freescale MX2/MX3 6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 7 * Unlike the hardware found on MX1, this hardware just works and does 8 * not need all the quirks found in imxmmc.c, hence the separate driver. 9 * 10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 12 * 13 * derived from pxamci.c by Russell King 14 */ 15 16#include <linux/module.h> 17#include <linux/init.h> 18#include <linux/ioport.h> 19#include <linux/platform_device.h> 20#include <linux/highmem.h> 21#include <linux/interrupt.h> 22#include <linux/irq.h> 23#include <linux/blkdev.h> 24#include <linux/dma-mapping.h> 25#include <linux/mmc/host.h> 26#include <linux/mmc/card.h> 27#include <linux/delay.h> 28#include <linux/clk.h> 29#include <linux/io.h> 30#include <linux/regulator/consumer.h> 31#include <linux/dmaengine.h> 32#include <linux/types.h> 33#include <linux/of.h> 34#include <linux/of_dma.h> 35#include <linux/mmc/slot-gpio.h> 36 37#include <asm/dma.h> 38#include <asm/irq.h> 39#include <linux/platform_data/mmc-mxcmmc.h> 40 41#include <linux/dma/imx-dma.h> 42 43#define DRIVER_NAME "mxc-mmc" 44#define MXCMCI_TIMEOUT_MS 10000 45 46#define MMC_REG_STR_STP_CLK 0x00 47#define MMC_REG_STATUS 0x04 48#define MMC_REG_CLK_RATE 0x08 49#define MMC_REG_CMD_DAT_CONT 0x0C 50#define MMC_REG_RES_TO 0x10 51#define MMC_REG_READ_TO 0x14 52#define MMC_REG_BLK_LEN 0x18 53#define MMC_REG_NOB 0x1C 54#define MMC_REG_REV_NO 0x20 55#define MMC_REG_INT_CNTR 0x24 56#define MMC_REG_CMD 0x28 57#define MMC_REG_ARG 0x2C 58#define MMC_REG_RES_FIFO 0x34 59#define MMC_REG_BUFFER_ACCESS 0x38 60 61#define STR_STP_CLK_RESET (1 << 3) 62#define STR_STP_CLK_START_CLK (1 << 1) 63#define STR_STP_CLK_STOP_CLK (1 << 0) 64 65#define STATUS_CARD_INSERTION (1 << 31) 66#define STATUS_CARD_REMOVAL (1 << 30) 67#define STATUS_YBUF_EMPTY (1 << 29) 68#define STATUS_XBUF_EMPTY (1 << 28) 69#define STATUS_YBUF_FULL (1 << 27) 70#define STATUS_XBUF_FULL (1 << 26) 71#define STATUS_BUF_UND_RUN (1 << 25) 72#define STATUS_BUF_OVFL (1 << 24) 73#define STATUS_SDIO_INT_ACTIVE (1 << 14) 74#define STATUS_END_CMD_RESP (1 << 13) 75#define STATUS_WRITE_OP_DONE (1 << 12) 76#define STATUS_DATA_TRANS_DONE (1 << 11) 77#define STATUS_READ_OP_DONE (1 << 11) 78#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 79#define STATUS_CARD_BUS_CLK_RUN (1 << 8) 80#define STATUS_BUF_READ_RDY (1 << 7) 81#define STATUS_BUF_WRITE_RDY (1 << 6) 82#define STATUS_RESP_CRC_ERR (1 << 5) 83#define STATUS_CRC_READ_ERR (1 << 3) 84#define STATUS_CRC_WRITE_ERR (1 << 2) 85#define STATUS_TIME_OUT_RESP (1 << 1) 86#define STATUS_TIME_OUT_READ (1 << 0) 87#define STATUS_ERR_MASK 0x2f 88 89#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 90#define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 91#define CMD_DAT_CONT_START_READWAIT (1 << 10) 92#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 93#define CMD_DAT_CONT_INIT (1 << 7) 94#define CMD_DAT_CONT_WRITE (1 << 4) 95#define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 96#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 97#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 98#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 99 100#define INT_SDIO_INT_WKP_EN (1 << 18) 101#define INT_CARD_INSERTION_WKP_EN (1 << 17) 102#define INT_CARD_REMOVAL_WKP_EN (1 << 16) 103#define INT_CARD_INSERTION_EN (1 << 15) 104#define INT_CARD_REMOVAL_EN (1 << 14) 105#define INT_SDIO_IRQ_EN (1 << 13) 106#define INT_DAT0_EN (1 << 12) 107#define INT_BUF_READ_EN (1 << 4) 108#define INT_BUF_WRITE_EN (1 << 3) 109#define INT_END_CMD_RES_EN (1 << 2) 110#define INT_WRITE_OP_DONE_EN (1 << 1) 111#define INT_READ_OP_EN (1 << 0) 112 113enum mxcmci_type { 114 IMX21_MMC, 115 IMX31_MMC, 116 MPC512X_MMC, 117}; 118 119struct mxcmci_host { 120 struct mmc_host *mmc; 121 void __iomem *base; 122 dma_addr_t phys_base; 123 int detect_irq; 124 struct dma_chan *dma; 125 struct dma_async_tx_descriptor *desc; 126 int do_dma; 127 int default_irq_mask; 128 int use_sdio; 129 unsigned int power_mode; 130 struct imxmmc_platform_data *pdata; 131 132 struct mmc_request *req; 133 struct mmc_command *cmd; 134 struct mmc_data *data; 135 136 unsigned int datasize; 137 unsigned int dma_dir; 138 139 u16 rev_no; 140 unsigned int cmdat; 141 142 struct clk *clk_ipg; 143 struct clk *clk_per; 144 145 int clock; 146 147 struct work_struct datawork; 148 spinlock_t lock; 149 150 int burstlen; 151 int dmareq; 152 struct dma_slave_config dma_slave_config; 153 struct imx_dma_data dma_data; 154 155 struct timer_list watchdog; 156 enum mxcmci_type devtype; 157}; 158 159static const struct of_device_id mxcmci_of_match[] = { 160 { 161 .compatible = "fsl,imx21-mmc", 162 .data = (void *) IMX21_MMC, 163 }, { 164 .compatible = "fsl,imx31-mmc", 165 .data = (void *) IMX31_MMC, 166 }, { 167 .compatible = "fsl,mpc5121-sdhc", 168 .data = (void *) MPC512X_MMC, 169 }, { 170 /* sentinel */ 171 } 172}; 173MODULE_DEVICE_TABLE(of, mxcmci_of_match); 174 175static inline int is_imx31_mmc(struct mxcmci_host *host) 176{ 177 return host->devtype == IMX31_MMC; 178} 179 180static inline int is_mpc512x_mmc(struct mxcmci_host *host) 181{ 182 return host->devtype == MPC512X_MMC; 183} 184 185static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) 186{ 187 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 188 return ioread32be(host->base + reg); 189 else 190 return readl(host->base + reg); 191} 192 193static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) 194{ 195 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 196 iowrite32be(val, host->base + reg); 197 else 198 writel(val, host->base + reg); 199} 200 201static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) 202{ 203 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 204 return ioread32be(host->base + reg); 205 else 206 return readw(host->base + reg); 207} 208 209static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) 210{ 211 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 212 iowrite32be(val, host->base + reg); 213 else 214 writew(val, host->base + reg); 215} 216 217static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 218 219static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd) 220{ 221 if (!IS_ERR(host->mmc->supply.vmmc)) { 222 if (host->power_mode == MMC_POWER_UP) 223 mmc_regulator_set_ocr(host->mmc, 224 host->mmc->supply.vmmc, vdd); 225 else if (host->power_mode == MMC_POWER_OFF) 226 mmc_regulator_set_ocr(host->mmc, 227 host->mmc->supply.vmmc, 0); 228 } 229 230 if (host->pdata && host->pdata->setpower) 231 host->pdata->setpower(mmc_dev(host->mmc), vdd); 232} 233 234static inline int mxcmci_use_dma(struct mxcmci_host *host) 235{ 236 return host->do_dma; 237} 238 239static void mxcmci_softreset(struct mxcmci_host *host) 240{ 241 int i; 242 243 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 244 245 /* reset sequence */ 246 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK); 247 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 248 MMC_REG_STR_STP_CLK); 249 250 for (i = 0; i < 8; i++) 251 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 252 253 mxcmci_writew(host, 0xff, MMC_REG_RES_TO); 254} 255 256#if IS_ENABLED(CONFIG_PPC_MPC512x) 257static inline void buffer_swap32(u32 *buf, int len) 258{ 259 int i; 260 261 for (i = 0; i < ((len + 3) / 4); i++) { 262 *buf = swab32(*buf); 263 buf++; 264 } 265} 266 267static void mxcmci_swap_buffers(struct mmc_data *data) 268{ 269 struct scatterlist *sg; 270 int i; 271 272 for_each_sg(data->sg, sg, data->sg_len, i) 273 buffer_swap32(sg_virt(sg), sg->length); 274} 275#else 276static inline void mxcmci_swap_buffers(struct mmc_data *data) {} 277#endif 278 279static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 280{ 281 unsigned int nob = data->blocks; 282 unsigned int blksz = data->blksz; 283 unsigned int datasize = nob * blksz; 284 struct scatterlist *sg; 285 enum dma_transfer_direction slave_dirn; 286 int i, nents; 287 288 host->data = data; 289 data->bytes_xfered = 0; 290 291 mxcmci_writew(host, nob, MMC_REG_NOB); 292 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN); 293 host->datasize = datasize; 294 295 if (!mxcmci_use_dma(host)) 296 return 0; 297 298 for_each_sg(data->sg, sg, data->sg_len, i) { 299 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { 300 host->do_dma = 0; 301 return 0; 302 } 303 } 304 305 if (data->flags & MMC_DATA_READ) { 306 host->dma_dir = DMA_FROM_DEVICE; 307 slave_dirn = DMA_DEV_TO_MEM; 308 } else { 309 host->dma_dir = DMA_TO_DEVICE; 310 slave_dirn = DMA_MEM_TO_DEV; 311 312 mxcmci_swap_buffers(data); 313 } 314 315 nents = dma_map_sg(host->dma->device->dev, data->sg, 316 data->sg_len, host->dma_dir); 317 if (nents != data->sg_len) 318 return -EINVAL; 319 320 host->desc = dmaengine_prep_slave_sg(host->dma, 321 data->sg, data->sg_len, slave_dirn, 322 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 323 324 if (!host->desc) { 325 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 326 host->dma_dir); 327 host->do_dma = 0; 328 return 0; /* Fall back to PIO */ 329 } 330 wmb(); 331 332 dmaengine_submit(host->desc); 333 dma_async_issue_pending(host->dma); 334 335 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS)); 336 337 return 0; 338} 339 340static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat); 341static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); 342 343static void mxcmci_dma_callback(void *data) 344{ 345 struct mxcmci_host *host = data; 346 u32 stat; 347 348 del_timer(&host->watchdog); 349 350 stat = mxcmci_readl(host, MMC_REG_STATUS); 351 352 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 353 354 mxcmci_data_done(host, stat); 355} 356 357static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 358 unsigned int cmdat) 359{ 360 u32 int_cntr = host->default_irq_mask; 361 unsigned long flags; 362 363 WARN_ON(host->cmd != NULL); 364 host->cmd = cmd; 365 366 switch (mmc_resp_type(cmd)) { 367 case MMC_RSP_R1: /* short CRC, OPCODE */ 368 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 369 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 370 break; 371 case MMC_RSP_R2: /* long 136 bit + CRC */ 372 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 373 break; 374 case MMC_RSP_R3: /* short */ 375 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 376 break; 377 case MMC_RSP_NONE: 378 break; 379 default: 380 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 381 mmc_resp_type(cmd)); 382 cmd->error = -EINVAL; 383 return -EINVAL; 384 } 385 386 int_cntr = INT_END_CMD_RES_EN; 387 388 if (mxcmci_use_dma(host)) { 389 if (host->dma_dir == DMA_FROM_DEVICE) { 390 host->desc->callback = mxcmci_dma_callback; 391 host->desc->callback_param = host; 392 } else { 393 int_cntr |= INT_WRITE_OP_DONE_EN; 394 } 395 } 396 397 spin_lock_irqsave(&host->lock, flags); 398 if (host->use_sdio) 399 int_cntr |= INT_SDIO_IRQ_EN; 400 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 401 spin_unlock_irqrestore(&host->lock, flags); 402 403 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD); 404 mxcmci_writel(host, cmd->arg, MMC_REG_ARG); 405 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT); 406 407 return 0; 408} 409 410static void mxcmci_finish_request(struct mxcmci_host *host, 411 struct mmc_request *req) 412{ 413 u32 int_cntr = host->default_irq_mask; 414 unsigned long flags; 415 416 spin_lock_irqsave(&host->lock, flags); 417 if (host->use_sdio) 418 int_cntr |= INT_SDIO_IRQ_EN; 419 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 420 spin_unlock_irqrestore(&host->lock, flags); 421 422 host->req = NULL; 423 host->cmd = NULL; 424 host->data = NULL; 425 426 mmc_request_done(host->mmc, req); 427} 428 429static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 430{ 431 struct mmc_data *data = host->data; 432 int data_error; 433 434 if (mxcmci_use_dma(host)) { 435 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 436 host->dma_dir); 437 mxcmci_swap_buffers(data); 438 } 439 440 if (stat & STATUS_ERR_MASK) { 441 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 442 stat); 443 if (stat & STATUS_CRC_READ_ERR) { 444 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 445 data->error = -EILSEQ; 446 } else if (stat & STATUS_CRC_WRITE_ERR) { 447 u32 err_code = (stat >> 9) & 0x3; 448 if (err_code == 2) { /* No CRC response */ 449 dev_err(mmc_dev(host->mmc), 450 "%s: No CRC -ETIMEDOUT\n", __func__); 451 data->error = -ETIMEDOUT; 452 } else { 453 dev_err(mmc_dev(host->mmc), 454 "%s: -EILSEQ\n", __func__); 455 data->error = -EILSEQ; 456 } 457 } else if (stat & STATUS_TIME_OUT_READ) { 458 dev_err(mmc_dev(host->mmc), 459 "%s: read -ETIMEDOUT\n", __func__); 460 data->error = -ETIMEDOUT; 461 } else { 462 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 463 data->error = -EIO; 464 } 465 } else { 466 data->bytes_xfered = host->datasize; 467 } 468 469 data_error = data->error; 470 471 host->data = NULL; 472 473 return data_error; 474} 475 476static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 477{ 478 struct mmc_command *cmd = host->cmd; 479 int i; 480 u32 a, b, c; 481 482 if (!cmd) 483 return; 484 485 if (stat & STATUS_TIME_OUT_RESP) { 486 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 487 cmd->error = -ETIMEDOUT; 488 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 489 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 490 cmd->error = -EILSEQ; 491 } 492 493 if (cmd->flags & MMC_RSP_PRESENT) { 494 if (cmd->flags & MMC_RSP_136) { 495 for (i = 0; i < 4; i++) { 496 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 497 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 498 cmd->resp[i] = a << 16 | b; 499 } 500 } else { 501 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 502 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 503 c = mxcmci_readw(host, MMC_REG_RES_FIFO); 504 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 505 } 506 } 507} 508 509static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 510{ 511 u32 stat; 512 unsigned long timeout = jiffies + HZ; 513 514 do { 515 stat = mxcmci_readl(host, MMC_REG_STATUS); 516 if (stat & STATUS_ERR_MASK) 517 return stat; 518 if (time_after(jiffies, timeout)) { 519 mxcmci_softreset(host); 520 mxcmci_set_clk_rate(host, host->clock); 521 return STATUS_TIME_OUT_READ; 522 } 523 if (stat & mask) 524 return 0; 525 cpu_relax(); 526 } while (1); 527} 528 529static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 530{ 531 unsigned int stat; 532 u32 *buf = _buf; 533 534 while (bytes > 3) { 535 stat = mxcmci_poll_status(host, 536 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 537 if (stat) 538 return stat; 539 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 540 bytes -= 4; 541 } 542 543 if (bytes) { 544 u8 *b = (u8 *)buf; 545 u32 tmp; 546 547 stat = mxcmci_poll_status(host, 548 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 549 if (stat) 550 return stat; 551 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 552 memcpy(b, &tmp, bytes); 553 } 554 555 return 0; 556} 557 558static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 559{ 560 unsigned int stat; 561 u32 *buf = _buf; 562 563 while (bytes > 3) { 564 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 565 if (stat) 566 return stat; 567 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS); 568 bytes -= 4; 569 } 570 571 if (bytes) { 572 u8 *b = (u8 *)buf; 573 u32 tmp; 574 575 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 576 if (stat) 577 return stat; 578 579 memcpy(&tmp, b, bytes); 580 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS); 581 } 582 583 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 584} 585 586static int mxcmci_transfer_data(struct mxcmci_host *host) 587{ 588 struct mmc_data *data = host->req->data; 589 struct scatterlist *sg; 590 int stat, i; 591 592 host->data = data; 593 host->datasize = 0; 594 595 if (data->flags & MMC_DATA_READ) { 596 for_each_sg(data->sg, sg, data->sg_len, i) { 597 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 598 if (stat) 599 return stat; 600 host->datasize += sg->length; 601 } 602 } else { 603 for_each_sg(data->sg, sg, data->sg_len, i) { 604 stat = mxcmci_push(host, sg_virt(sg), sg->length); 605 if (stat) 606 return stat; 607 host->datasize += sg->length; 608 } 609 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 610 if (stat) 611 return stat; 612 } 613 return 0; 614} 615 616static void mxcmci_datawork(struct work_struct *work) 617{ 618 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 619 datawork); 620 int datastat = mxcmci_transfer_data(host); 621 622 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 623 MMC_REG_STATUS); 624 mxcmci_finish_data(host, datastat); 625 626 if (host->req->stop) { 627 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 628 mxcmci_finish_request(host, host->req); 629 return; 630 } 631 } else { 632 mxcmci_finish_request(host, host->req); 633 } 634} 635 636static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 637{ 638 struct mmc_request *req; 639 int data_error; 640 unsigned long flags; 641 642 spin_lock_irqsave(&host->lock, flags); 643 644 if (!host->data) { 645 spin_unlock_irqrestore(&host->lock, flags); 646 return; 647 } 648 649 if (!host->req) { 650 spin_unlock_irqrestore(&host->lock, flags); 651 return; 652 } 653 654 req = host->req; 655 if (!req->stop) 656 host->req = NULL; /* we will handle finish req below */ 657 658 data_error = mxcmci_finish_data(host, stat); 659 660 spin_unlock_irqrestore(&host->lock, flags); 661 662 if (data_error) 663 return; 664 665 mxcmci_read_response(host, stat); 666 host->cmd = NULL; 667 668 if (req->stop) { 669 if (mxcmci_start_cmd(host, req->stop, 0)) { 670 mxcmci_finish_request(host, req); 671 return; 672 } 673 } else { 674 mxcmci_finish_request(host, req); 675 } 676} 677 678static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 679{ 680 mxcmci_read_response(host, stat); 681 host->cmd = NULL; 682 683 if (!host->data && host->req) { 684 mxcmci_finish_request(host, host->req); 685 return; 686 } 687 688 /* For the DMA case the DMA engine handles the data transfer 689 * automatically. For non DMA we have to do it ourselves. 690 * Don't do it in interrupt context though. 691 */ 692 if (!mxcmci_use_dma(host) && host->data) 693 schedule_work(&host->datawork); 694 695} 696 697static irqreturn_t mxcmci_irq(int irq, void *devid) 698{ 699 struct mxcmci_host *host = devid; 700 bool sdio_irq; 701 u32 stat; 702 703 stat = mxcmci_readl(host, MMC_REG_STATUS); 704 mxcmci_writel(host, 705 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 706 STATUS_WRITE_OP_DONE), 707 MMC_REG_STATUS); 708 709 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 710 711 spin_lock(&host->lock); 712 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 713 spin_unlock(&host->lock); 714 715 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE))) 716 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS); 717 718 if (sdio_irq) { 719 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS); 720 mmc_signal_sdio_irq(host->mmc); 721 } 722 723 if (stat & STATUS_END_CMD_RESP) 724 mxcmci_cmd_done(host, stat); 725 726 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) { 727 del_timer(&host->watchdog); 728 mxcmci_data_done(host, stat); 729 } 730 731 if (host->default_irq_mask && 732 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 733 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 734 735 return IRQ_HANDLED; 736} 737 738static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 739{ 740 struct mxcmci_host *host = mmc_priv(mmc); 741 unsigned int cmdat = host->cmdat; 742 int error; 743 744 WARN_ON(host->req != NULL); 745 746 host->req = req; 747 host->cmdat &= ~CMD_DAT_CONT_INIT; 748 749 if (host->dma) 750 host->do_dma = 1; 751 752 if (req->data) { 753 error = mxcmci_setup_data(host, req->data); 754 if (error) { 755 req->cmd->error = error; 756 goto out; 757 } 758 759 760 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 761 762 if (req->data->flags & MMC_DATA_WRITE) 763 cmdat |= CMD_DAT_CONT_WRITE; 764 } 765 766 error = mxcmci_start_cmd(host, req->cmd, cmdat); 767 768out: 769 if (error) 770 mxcmci_finish_request(host, req); 771} 772 773static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 774{ 775 unsigned int divider; 776 int prescaler = 0; 777 unsigned int clk_in = clk_get_rate(host->clk_per); 778 779 while (prescaler <= 0x800) { 780 for (divider = 1; divider <= 0xF; divider++) { 781 int x; 782 783 x = (clk_in / (divider + 1)); 784 785 if (prescaler) 786 x /= (prescaler * 2); 787 788 if (x <= clk_ios) 789 break; 790 } 791 if (divider < 0x10) 792 break; 793 794 if (prescaler == 0) 795 prescaler = 1; 796 else 797 prescaler <<= 1; 798 } 799 800 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); 801 802 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 803 prescaler, divider, clk_in, clk_ios); 804} 805 806static int mxcmci_setup_dma(struct mmc_host *mmc) 807{ 808 struct mxcmci_host *host = mmc_priv(mmc); 809 struct dma_slave_config *config = &host->dma_slave_config; 810 811 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 812 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 813 config->dst_addr_width = 4; 814 config->src_addr_width = 4; 815 config->dst_maxburst = host->burstlen; 816 config->src_maxburst = host->burstlen; 817 config->device_fc = false; 818 819 return dmaengine_slave_config(host->dma, config); 820} 821 822static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 823{ 824 struct mxcmci_host *host = mmc_priv(mmc); 825 int burstlen, ret; 826 827 /* 828 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 829 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 830 */ 831 if (ios->bus_width == MMC_BUS_WIDTH_4) 832 burstlen = 16; 833 else 834 burstlen = 4; 835 836 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 837 host->burstlen = burstlen; 838 ret = mxcmci_setup_dma(mmc); 839 if (ret) { 840 dev_err(mmc_dev(host->mmc), 841 "failed to config DMA channel. Falling back to PIO\n"); 842 dma_release_channel(host->dma); 843 host->do_dma = 0; 844 host->dma = NULL; 845 } 846 } 847 848 if (ios->bus_width == MMC_BUS_WIDTH_4) 849 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 850 else 851 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 852 853 if (host->power_mode != ios->power_mode) { 854 host->power_mode = ios->power_mode; 855 mxcmci_set_power(host, ios->vdd); 856 857 if (ios->power_mode == MMC_POWER_ON) 858 host->cmdat |= CMD_DAT_CONT_INIT; 859 } 860 861 if (ios->clock) { 862 mxcmci_set_clk_rate(host, ios->clock); 863 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 864 } else { 865 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK); 866 } 867 868 host->clock = ios->clock; 869} 870 871static irqreturn_t mxcmci_detect_irq(int irq, void *data) 872{ 873 struct mmc_host *mmc = data; 874 875 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 876 877 mmc_detect_change(mmc, msecs_to_jiffies(250)); 878 return IRQ_HANDLED; 879} 880 881static int mxcmci_get_ro(struct mmc_host *mmc) 882{ 883 struct mxcmci_host *host = mmc_priv(mmc); 884 885 if (host->pdata && host->pdata->get_ro) 886 return !!host->pdata->get_ro(mmc_dev(mmc)); 887 /* 888 * If board doesn't support read only detection (no mmc_gpio 889 * context or gpio is invalid), then let the mmc core decide 890 * what to do. 891 */ 892 return mmc_gpio_get_ro(mmc); 893} 894 895static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 896{ 897 struct mxcmci_host *host = mmc_priv(mmc); 898 unsigned long flags; 899 u32 int_cntr; 900 901 spin_lock_irqsave(&host->lock, flags); 902 host->use_sdio = enable; 903 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR); 904 905 if (enable) 906 int_cntr |= INT_SDIO_IRQ_EN; 907 else 908 int_cntr &= ~INT_SDIO_IRQ_EN; 909 910 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 911 spin_unlock_irqrestore(&host->lock, flags); 912} 913 914static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 915{ 916 struct mxcmci_host *mxcmci = mmc_priv(host); 917 918 /* 919 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 920 * multi-block transfers when connected SDIO peripheral doesn't 921 * drive the BUSY line as required by the specs. 922 * One way to prevent this is to only allow 1-bit transfers. 923 */ 924 925 if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card)) 926 host->caps &= ~MMC_CAP_4_BIT_DATA; 927 else 928 host->caps |= MMC_CAP_4_BIT_DATA; 929} 930 931static bool filter(struct dma_chan *chan, void *param) 932{ 933 struct mxcmci_host *host = param; 934 935 if (!imx_dma_is_general_purpose(chan)) 936 return false; 937 938 chan->private = &host->dma_data; 939 940 return true; 941} 942 943static void mxcmci_watchdog(struct timer_list *t) 944{ 945 struct mxcmci_host *host = from_timer(host, t, watchdog); 946 struct mmc_request *req = host->req; 947 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS); 948 949 if (host->dma_dir == DMA_FROM_DEVICE) { 950 dmaengine_terminate_all(host->dma); 951 dev_err(mmc_dev(host->mmc), 952 "%s: read time out (status = 0x%08x)\n", 953 __func__, stat); 954 } else { 955 dev_err(mmc_dev(host->mmc), 956 "%s: write time out (status = 0x%08x)\n", 957 __func__, stat); 958 mxcmci_softreset(host); 959 } 960 961 /* Mark transfer as erroneus and inform the upper layers */ 962 963 if (host->data) 964 host->data->error = -ETIMEDOUT; 965 host->req = NULL; 966 host->cmd = NULL; 967 host->data = NULL; 968 mmc_request_done(host->mmc, req); 969} 970 971static const struct mmc_host_ops mxcmci_ops = { 972 .request = mxcmci_request, 973 .set_ios = mxcmci_set_ios, 974 .get_ro = mxcmci_get_ro, 975 .enable_sdio_irq = mxcmci_enable_sdio_irq, 976 .init_card = mxcmci_init_card, 977}; 978 979static int mxcmci_probe(struct platform_device *pdev) 980{ 981 struct mmc_host *mmc; 982 struct mxcmci_host *host; 983 struct resource *res; 984 int ret = 0, irq; 985 bool dat3_card_detect = false; 986 dma_cap_mask_t mask; 987 struct imxmmc_platform_data *pdata = pdev->dev.platform_data; 988 989 pr_info("i.MX/MPC512x SDHC driver\n"); 990 991 irq = platform_get_irq(pdev, 0); 992 if (irq < 0) 993 return irq; 994 995 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 996 if (!mmc) 997 return -ENOMEM; 998 999 host = mmc_priv(mmc); 1000 1001 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1002 if (IS_ERR(host->base)) { 1003 ret = PTR_ERR(host->base); 1004 goto out_free; 1005 } 1006 1007 host->phys_base = res->start; 1008 1009 ret = mmc_of_parse(mmc); 1010 if (ret) 1011 goto out_free; 1012 mmc->ops = &mxcmci_ops; 1013 1014 /* For devicetree parsing, the bus width is read from devicetree */ 1015 if (pdata) 1016 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1017 else 1018 mmc->caps |= MMC_CAP_SDIO_IRQ; 1019 1020 /* MMC core transfer sizes tunable parameters */ 1021 mmc->max_blk_size = 2048; 1022 mmc->max_blk_count = 65535; 1023 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1024 mmc->max_seg_size = mmc->max_req_size; 1025 1026 host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev); 1027 1028 /* adjust max_segs after devtype detection */ 1029 if (!is_mpc512x_mmc(host)) 1030 mmc->max_segs = 64; 1031 1032 host->mmc = mmc; 1033 host->pdata = pdata; 1034 spin_lock_init(&host->lock); 1035 1036 if (pdata) 1037 dat3_card_detect = pdata->dat3_card_detect; 1038 else if (mmc_card_is_removable(mmc) 1039 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) 1040 dat3_card_detect = true; 1041 1042 ret = mmc_regulator_get_supply(mmc); 1043 if (ret) 1044 goto out_free; 1045 1046 if (!mmc->ocr_avail) { 1047 if (pdata && pdata->ocr_avail) 1048 mmc->ocr_avail = pdata->ocr_avail; 1049 else 1050 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1051 } 1052 1053 if (dat3_card_detect) 1054 host->default_irq_mask = 1055 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 1056 else 1057 host->default_irq_mask = 0; 1058 1059 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1060 if (IS_ERR(host->clk_ipg)) { 1061 ret = PTR_ERR(host->clk_ipg); 1062 goto out_free; 1063 } 1064 1065 host->clk_per = devm_clk_get(&pdev->dev, "per"); 1066 if (IS_ERR(host->clk_per)) { 1067 ret = PTR_ERR(host->clk_per); 1068 goto out_free; 1069 } 1070 1071 ret = clk_prepare_enable(host->clk_per); 1072 if (ret) 1073 goto out_free; 1074 1075 ret = clk_prepare_enable(host->clk_ipg); 1076 if (ret) 1077 goto out_clk_per_put; 1078 1079 mxcmci_softreset(host); 1080 1081 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO); 1082 if (host->rev_no != 0x400) { 1083 ret = -ENODEV; 1084 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1085 host->rev_no); 1086 goto out_clk_put; 1087 } 1088 1089 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 1090 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 1091 1092 /* recommended in data sheet */ 1093 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO); 1094 1095 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR); 1096 1097 if (!host->pdata) { 1098 host->dma = dma_request_chan(&pdev->dev, "rx-tx"); 1099 if (IS_ERR(host->dma)) { 1100 if (PTR_ERR(host->dma) == -EPROBE_DEFER) { 1101 ret = -EPROBE_DEFER; 1102 goto out_clk_put; 1103 } 1104 1105 /* Ignore errors to fall back to PIO mode */ 1106 host->dma = NULL; 1107 } 1108 } else { 1109 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1110 if (res) { 1111 host->dmareq = res->start; 1112 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 1113 host->dma_data.priority = DMA_PRIO_LOW; 1114 host->dma_data.dma_request = host->dmareq; 1115 dma_cap_zero(mask); 1116 dma_cap_set(DMA_SLAVE, mask); 1117 host->dma = dma_request_channel(mask, filter, host); 1118 } 1119 } 1120 if (host->dma) 1121 mmc->max_seg_size = dma_get_max_seg_size( 1122 host->dma->device->dev); 1123 else 1124 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 1125 1126 INIT_WORK(&host->datawork, mxcmci_datawork); 1127 1128 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0, 1129 dev_name(&pdev->dev), host); 1130 if (ret) 1131 goto out_free_dma; 1132 1133 platform_set_drvdata(pdev, mmc); 1134 1135 if (host->pdata && host->pdata->init) { 1136 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 1137 host->mmc); 1138 if (ret) 1139 goto out_free_dma; 1140 } 1141 1142 timer_setup(&host->watchdog, mxcmci_watchdog, 0); 1143 1144 ret = mmc_add_host(mmc); 1145 if (ret) 1146 goto out_free_dma; 1147 1148 return 0; 1149 1150out_free_dma: 1151 if (host->dma) 1152 dma_release_channel(host->dma); 1153 1154out_clk_put: 1155 clk_disable_unprepare(host->clk_ipg); 1156out_clk_per_put: 1157 clk_disable_unprepare(host->clk_per); 1158 1159out_free: 1160 mmc_free_host(mmc); 1161 1162 return ret; 1163} 1164 1165static void mxcmci_remove(struct platform_device *pdev) 1166{ 1167 struct mmc_host *mmc = platform_get_drvdata(pdev); 1168 struct mxcmci_host *host = mmc_priv(mmc); 1169 1170 mmc_remove_host(mmc); 1171 1172 if (host->pdata && host->pdata->exit) 1173 host->pdata->exit(&pdev->dev, mmc); 1174 1175 if (host->dma) 1176 dma_release_channel(host->dma); 1177 1178 clk_disable_unprepare(host->clk_per); 1179 clk_disable_unprepare(host->clk_ipg); 1180 1181 mmc_free_host(mmc); 1182} 1183 1184static int mxcmci_suspend(struct device *dev) 1185{ 1186 struct mmc_host *mmc = dev_get_drvdata(dev); 1187 struct mxcmci_host *host = mmc_priv(mmc); 1188 1189 clk_disable_unprepare(host->clk_per); 1190 clk_disable_unprepare(host->clk_ipg); 1191 return 0; 1192} 1193 1194static int mxcmci_resume(struct device *dev) 1195{ 1196 struct mmc_host *mmc = dev_get_drvdata(dev); 1197 struct mxcmci_host *host = mmc_priv(mmc); 1198 int ret; 1199 1200 ret = clk_prepare_enable(host->clk_per); 1201 if (ret) 1202 return ret; 1203 1204 ret = clk_prepare_enable(host->clk_ipg); 1205 if (ret) 1206 clk_disable_unprepare(host->clk_per); 1207 1208 return ret; 1209} 1210 1211static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume); 1212 1213static struct platform_driver mxcmci_driver = { 1214 .probe = mxcmci_probe, 1215 .remove_new = mxcmci_remove, 1216 .driver = { 1217 .name = DRIVER_NAME, 1218 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1219 .pm = pm_sleep_ptr(&mxcmci_pm_ops), 1220 .of_match_table = mxcmci_of_match, 1221 } 1222}; 1223 1224module_platform_driver(mxcmci_driver); 1225 1226MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1227MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1228MODULE_LICENSE("GPL"); 1229MODULE_ALIAS("platform:mxc-mmc"); 1230