162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved. 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __MVSDIO_H 762306a36Sopenharmony_ci#define __MVSDIO_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/* 1062306a36Sopenharmony_ci * Clock rates 1162306a36Sopenharmony_ci */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#define MVSD_CLOCKRATE_MAX 50000000 1462306a36Sopenharmony_ci#define MVSD_BASE_DIV_MAX 0x7ff 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci/* 1862306a36Sopenharmony_ci * Register offsets 1962306a36Sopenharmony_ci */ 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define MVSD_SYS_ADDR_LOW 0x000 2262306a36Sopenharmony_ci#define MVSD_SYS_ADDR_HI 0x004 2362306a36Sopenharmony_ci#define MVSD_BLK_SIZE 0x008 2462306a36Sopenharmony_ci#define MVSD_BLK_COUNT 0x00c 2562306a36Sopenharmony_ci#define MVSD_ARG_LOW 0x010 2662306a36Sopenharmony_ci#define MVSD_ARG_HI 0x014 2762306a36Sopenharmony_ci#define MVSD_XFER_MODE 0x018 2862306a36Sopenharmony_ci#define MVSD_CMD 0x01c 2962306a36Sopenharmony_ci#define MVSD_RSP(i) (0x020 + ((i)<<2)) 3062306a36Sopenharmony_ci#define MVSD_RSP0 0x020 3162306a36Sopenharmony_ci#define MVSD_RSP1 0x024 3262306a36Sopenharmony_ci#define MVSD_RSP2 0x028 3362306a36Sopenharmony_ci#define MVSD_RSP3 0x02c 3462306a36Sopenharmony_ci#define MVSD_RSP4 0x030 3562306a36Sopenharmony_ci#define MVSD_RSP5 0x034 3662306a36Sopenharmony_ci#define MVSD_RSP6 0x038 3762306a36Sopenharmony_ci#define MVSD_RSP7 0x03c 3862306a36Sopenharmony_ci#define MVSD_FIFO 0x040 3962306a36Sopenharmony_ci#define MVSD_RSP_CRC7 0x044 4062306a36Sopenharmony_ci#define MVSD_HW_STATE 0x048 4162306a36Sopenharmony_ci#define MVSD_HOST_CTRL 0x050 4262306a36Sopenharmony_ci#define MVSD_BLK_GAP_CTRL 0x054 4362306a36Sopenharmony_ci#define MVSD_CLK_CTRL 0x058 4462306a36Sopenharmony_ci#define MVSD_SW_RESET 0x05c 4562306a36Sopenharmony_ci#define MVSD_NOR_INTR_STATUS 0x060 4662306a36Sopenharmony_ci#define MVSD_ERR_INTR_STATUS 0x064 4762306a36Sopenharmony_ci#define MVSD_NOR_STATUS_EN 0x068 4862306a36Sopenharmony_ci#define MVSD_ERR_STATUS_EN 0x06c 4962306a36Sopenharmony_ci#define MVSD_NOR_INTR_EN 0x070 5062306a36Sopenharmony_ci#define MVSD_ERR_INTR_EN 0x074 5162306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_STATUS 0x078 5262306a36Sopenharmony_ci#define MVSD_CURR_BYTE_LEFT 0x07c 5362306a36Sopenharmony_ci#define MVSD_CURR_BLK_LEFT 0x080 5462306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ARG_LOW 0x084 5562306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ARG_HI 0x088 5662306a36Sopenharmony_ci#define MVSD_AUTOCMD12_CMD 0x08c 5762306a36Sopenharmony_ci#define MVSD_AUTO_RSP(i) (0x090 + ((i)<<2)) 5862306a36Sopenharmony_ci#define MVSD_AUTO_RSP0 0x090 5962306a36Sopenharmony_ci#define MVSD_AUTO_RSP1 0x094 6062306a36Sopenharmony_ci#define MVSD_AUTO_RSP2 0x098 6162306a36Sopenharmony_ci#define MVSD_CLK_DIV 0x128 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci#define MVSD_WINDOW_CTRL(i) (0x108 + ((i) << 3)) 6462306a36Sopenharmony_ci#define MVSD_WINDOW_BASE(i) (0x10c + ((i) << 3)) 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ci/* 6862306a36Sopenharmony_ci * MVSD_CMD 6962306a36Sopenharmony_ci */ 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci#define MVSD_CMD_RSP_NONE (0 << 0) 7262306a36Sopenharmony_ci#define MVSD_CMD_RSP_136 (1 << 0) 7362306a36Sopenharmony_ci#define MVSD_CMD_RSP_48 (2 << 0) 7462306a36Sopenharmony_ci#define MVSD_CMD_RSP_48BUSY (3 << 0) 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_ci#define MVSD_CMD_CHECK_DATACRC16 (1 << 2) 7762306a36Sopenharmony_ci#define MVSD_CMD_CHECK_CMDCRC (1 << 3) 7862306a36Sopenharmony_ci#define MVSD_CMD_INDX_CHECK (1 << 4) 7962306a36Sopenharmony_ci#define MVSD_CMD_DATA_PRESENT (1 << 5) 8062306a36Sopenharmony_ci#define MVSD_UNEXPECTED_RESP (1 << 7) 8162306a36Sopenharmony_ci#define MVSD_CMD_INDEX(x) ((x) << 8) 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ci 8462306a36Sopenharmony_ci/* 8562306a36Sopenharmony_ci * MVSD_AUTOCMD12_CMD 8662306a36Sopenharmony_ci */ 8762306a36Sopenharmony_ci 8862306a36Sopenharmony_ci#define MVSD_AUTOCMD12_BUSY (1 << 0) 8962306a36Sopenharmony_ci#define MVSD_AUTOCMD12_INDX_CHECK (1 << 1) 9062306a36Sopenharmony_ci#define MVSD_AUTOCMD12_INDEX(x) ((x) << 8) 9162306a36Sopenharmony_ci 9262306a36Sopenharmony_ci/* 9362306a36Sopenharmony_ci * MVSD_XFER_MODE 9462306a36Sopenharmony_ci */ 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci#define MVSD_XFER_MODE_WR_DATA_START (1 << 0) 9762306a36Sopenharmony_ci#define MVSD_XFER_MODE_HW_WR_DATA_EN (1 << 1) 9862306a36Sopenharmony_ci#define MVSD_XFER_MODE_AUTO_CMD12 (1 << 2) 9962306a36Sopenharmony_ci#define MVSD_XFER_MODE_INT_CHK_EN (1 << 3) 10062306a36Sopenharmony_ci#define MVSD_XFER_MODE_TO_HOST (1 << 4) 10162306a36Sopenharmony_ci#define MVSD_XFER_MODE_STOP_CLK (1 << 5) 10262306a36Sopenharmony_ci#define MVSD_XFER_MODE_PIO (1 << 6) 10362306a36Sopenharmony_ci 10462306a36Sopenharmony_ci 10562306a36Sopenharmony_ci/* 10662306a36Sopenharmony_ci * MVSD_HOST_CTRL 10762306a36Sopenharmony_ci */ 10862306a36Sopenharmony_ci 10962306a36Sopenharmony_ci#define MVSD_HOST_CTRL_PUSH_PULL_EN (1 << 0) 11062306a36Sopenharmony_ci 11162306a36Sopenharmony_ci#define MVSD_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) 11262306a36Sopenharmony_ci#define MVSD_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) 11362306a36Sopenharmony_ci#define MVSD_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) 11462306a36Sopenharmony_ci#define MVSD_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) 11562306a36Sopenharmony_ci#define MVSD_HOST_CTRL_CARD_TYPE_MASK (3 << 1) 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_ci#define MVSD_HOST_CTRL_BIG_ENDIAN (1 << 3) 11862306a36Sopenharmony_ci#define MVSD_HOST_CTRL_LSB_FIRST (1 << 4) 11962306a36Sopenharmony_ci#define MVSD_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) 12062306a36Sopenharmony_ci#define MVSD_HOST_CTRL_HI_SPEED_EN (1 << 10) 12162306a36Sopenharmony_ci 12262306a36Sopenharmony_ci#define MVSD_HOST_CTRL_TMOUT_MAX 0xf 12362306a36Sopenharmony_ci#define MVSD_HOST_CTRL_TMOUT_MASK (0xf << 11) 12462306a36Sopenharmony_ci#define MVSD_HOST_CTRL_TMOUT(x) ((x) << 11) 12562306a36Sopenharmony_ci#define MVSD_HOST_CTRL_TMOUT_EN (1 << 15) 12662306a36Sopenharmony_ci 12762306a36Sopenharmony_ci 12862306a36Sopenharmony_ci/* 12962306a36Sopenharmony_ci * MVSD_SW_RESET 13062306a36Sopenharmony_ci */ 13162306a36Sopenharmony_ci 13262306a36Sopenharmony_ci#define MVSD_SW_RESET_NOW (1 << 8) 13362306a36Sopenharmony_ci 13462306a36Sopenharmony_ci 13562306a36Sopenharmony_ci/* 13662306a36Sopenharmony_ci * Normal interrupt status bits 13762306a36Sopenharmony_ci */ 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ci#define MVSD_NOR_CMD_DONE (1 << 0) 14062306a36Sopenharmony_ci#define MVSD_NOR_XFER_DONE (1 << 1) 14162306a36Sopenharmony_ci#define MVSD_NOR_BLK_GAP_EVT (1 << 2) 14262306a36Sopenharmony_ci#define MVSD_NOR_DMA_DONE (1 << 3) 14362306a36Sopenharmony_ci#define MVSD_NOR_TX_AVAIL (1 << 4) 14462306a36Sopenharmony_ci#define MVSD_NOR_RX_READY (1 << 5) 14562306a36Sopenharmony_ci#define MVSD_NOR_CARD_INT (1 << 8) 14662306a36Sopenharmony_ci#define MVSD_NOR_READ_WAIT_ON (1 << 9) 14762306a36Sopenharmony_ci#define MVSD_NOR_RX_FIFO_8W (1 << 10) 14862306a36Sopenharmony_ci#define MVSD_NOR_TX_FIFO_8W (1 << 11) 14962306a36Sopenharmony_ci#define MVSD_NOR_SUSPEND_ON (1 << 12) 15062306a36Sopenharmony_ci#define MVSD_NOR_AUTOCMD12_DONE (1 << 13) 15162306a36Sopenharmony_ci#define MVSD_NOR_UNEXP_RSP (1 << 14) 15262306a36Sopenharmony_ci#define MVSD_NOR_ERROR (1 << 15) 15362306a36Sopenharmony_ci 15462306a36Sopenharmony_ci 15562306a36Sopenharmony_ci/* 15662306a36Sopenharmony_ci * Error status bits 15762306a36Sopenharmony_ci */ 15862306a36Sopenharmony_ci 15962306a36Sopenharmony_ci#define MVSD_ERR_CMD_TIMEOUT (1 << 0) 16062306a36Sopenharmony_ci#define MVSD_ERR_CMD_CRC (1 << 1) 16162306a36Sopenharmony_ci#define MVSD_ERR_CMD_ENDBIT (1 << 2) 16262306a36Sopenharmony_ci#define MVSD_ERR_CMD_INDEX (1 << 3) 16362306a36Sopenharmony_ci#define MVSD_ERR_DATA_TIMEOUT (1 << 4) 16462306a36Sopenharmony_ci#define MVSD_ERR_DATA_CRC (1 << 5) 16562306a36Sopenharmony_ci#define MVSD_ERR_DATA_ENDBIT (1 << 6) 16662306a36Sopenharmony_ci#define MVSD_ERR_AUTOCMD12 (1 << 8) 16762306a36Sopenharmony_ci#define MVSD_ERR_CMD_STARTBIT (1 << 9) 16862306a36Sopenharmony_ci#define MVSD_ERR_XFER_SIZE (1 << 10) 16962306a36Sopenharmony_ci#define MVSD_ERR_RESP_T_BIT (1 << 11) 17062306a36Sopenharmony_ci#define MVSD_ERR_CRC_ENDBIT (1 << 12) 17162306a36Sopenharmony_ci#define MVSD_ERR_CRC_STARTBIT (1 << 13) 17262306a36Sopenharmony_ci#define MVSD_ERR_CRC_STATUS (1 << 14) 17362306a36Sopenharmony_ci 17462306a36Sopenharmony_ci 17562306a36Sopenharmony_ci/* 17662306a36Sopenharmony_ci * CMD12 error status bits 17762306a36Sopenharmony_ci */ 17862306a36Sopenharmony_ci 17962306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_NOTEXE (1 << 0) 18062306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_TIMEOUT (1 << 1) 18162306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_CRC (1 << 2) 18262306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_ENDBIT (1 << 3) 18362306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_INDEX (1 << 4) 18462306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) 18562306a36Sopenharmony_ci#define MVSD_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) 18662306a36Sopenharmony_ci 18762306a36Sopenharmony_ci#endif 188