1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Access SD/MMC cards through SPI master controllers 4 * 5 * (C) Copyright 2005, Intec Automation, 6 * Mike Lavender (mike@steroidmicros) 7 * (C) Copyright 2006-2007, David Brownell 8 * (C) Copyright 2007, Axis Communications, 9 * Hans-Peter Nilsson (hp@axis.com) 10 * (C) Copyright 2007, ATRON electronic GmbH, 11 * Jan Nikitenko <jan.nikitenko@gmail.com> 12 */ 13#include <linux/sched.h> 14#include <linux/delay.h> 15#include <linux/slab.h> 16#include <linux/module.h> 17#include <linux/bio.h> 18#include <linux/dma-direction.h> 19#include <linux/crc7.h> 20#include <linux/crc-itu-t.h> 21#include <linux/scatterlist.h> 22 23#include <linux/mmc/host.h> 24#include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ 25#include <linux/mmc/slot-gpio.h> 26 27#include <linux/spi/spi.h> 28#include <linux/spi/mmc_spi.h> 29 30#include <asm/unaligned.h> 31 32 33/* NOTES: 34 * 35 * - For now, we won't try to interoperate with a real mmc/sd/sdio 36 * controller, although some of them do have hardware support for 37 * SPI protocol. The main reason for such configs would be mmc-ish 38 * cards like DataFlash, which don't support that "native" protocol. 39 * 40 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to 41 * switch between driver stacks, and in any case if "native" mode 42 * is available, it will be faster and hence preferable. 43 * 44 * - MMC depends on a different chipselect management policy than the 45 * SPI interface currently supports for shared bus segments: it needs 46 * to issue multiple spi_message requests with the chipselect active, 47 * using the results of one message to decide the next one to issue. 48 * 49 * Pending updates to the programming interface, this driver expects 50 * that it not share the bus with other drivers (precluding conflicts). 51 * 52 * - We tell the controller to keep the chipselect active from the 53 * beginning of an mmc_host_ops.request until the end. So beware 54 * of SPI controller drivers that mis-handle the cs_change flag! 55 * 56 * However, many cards seem OK with chipselect flapping up/down 57 * during that time ... at least on unshared bus segments. 58 */ 59 60 61/* 62 * Local protocol constants, internal to data block protocols. 63 */ 64 65/* Response tokens used to ack each block written: */ 66#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) 67#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1) 68#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1) 69#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1) 70 71/* Read and write blocks start with these tokens and end with crc; 72 * on error, read tokens act like a subset of R2_SPI_* values. 73 */ 74#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */ 75#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */ 76#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */ 77 78#define MMC_SPI_BLOCKSIZE 512 79 80#define MMC_SPI_R1B_TIMEOUT_MS 3000 81#define MMC_SPI_INIT_TIMEOUT_MS 3000 82 83/* One of the critical speed parameters is the amount of data which may 84 * be transferred in one command. If this value is too low, the SD card 85 * controller has to do multiple partial block writes (argggh!). With 86 * today (2008) SD cards there is little speed gain if we transfer more 87 * than 64 KBytes at a time. So use this value until there is any indication 88 * that we should do more here. 89 */ 90#define MMC_SPI_BLOCKSATONCE 128 91 92/****************************************************************************/ 93 94/* 95 * Local Data Structures 96 */ 97 98/* "scratch" is per-{command,block} data exchanged with the card */ 99struct scratch { 100 u8 status[29]; 101 u8 data_token; 102 __be16 crc_val; 103}; 104 105struct mmc_spi_host { 106 struct mmc_host *mmc; 107 struct spi_device *spi; 108 109 unsigned char power_mode; 110 u16 powerup_msecs; 111 112 struct mmc_spi_platform_data *pdata; 113 114 /* for bulk data transfers */ 115 struct spi_transfer token, t, crc, early_status; 116 struct spi_message m; 117 118 /* for status readback */ 119 struct spi_transfer status; 120 struct spi_message readback; 121 122 /* buffer used for commands and for message "overhead" */ 123 struct scratch *data; 124 125 /* Specs say to write ones most of the time, even when the card 126 * has no need to read its input data; and many cards won't care. 127 * This is our source of those ones. 128 */ 129 void *ones; 130}; 131 132 133/****************************************************************************/ 134 135/* 136 * MMC-over-SPI protocol glue, used by the MMC stack interface 137 */ 138 139static inline int mmc_cs_off(struct mmc_spi_host *host) 140{ 141 /* chipselect will always be inactive after setup() */ 142 return spi_setup(host->spi); 143} 144 145static int mmc_spi_readbytes(struct mmc_spi_host *host, unsigned int len) 146{ 147 if (len > sizeof(*host->data)) { 148 WARN_ON(1); 149 return -EIO; 150 } 151 152 host->status.len = len; 153 154 return spi_sync_locked(host->spi, &host->readback); 155} 156 157static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout, 158 unsigned n, u8 byte) 159{ 160 u8 *cp = host->data->status; 161 unsigned long start = jiffies; 162 163 do { 164 int status; 165 unsigned i; 166 167 status = mmc_spi_readbytes(host, n); 168 if (status < 0) 169 return status; 170 171 for (i = 0; i < n; i++) { 172 if (cp[i] != byte) 173 return cp[i]; 174 } 175 176 /* If we need long timeouts, we may release the CPU */ 177 cond_resched(); 178 } while (time_is_after_jiffies(start + timeout)); 179 return -ETIMEDOUT; 180} 181 182static inline int 183mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout) 184{ 185 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); 186} 187 188static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout) 189{ 190 return mmc_spi_skip(host, timeout, 1, 0xff); 191} 192 193 194/* 195 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol 196 * hosts return! The low byte holds R1_SPI bits. The next byte may hold 197 * R2_SPI bits ... for SEND_STATUS, or after data read errors. 198 * 199 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on 200 * newer cards R7 (IF_COND). 201 */ 202 203static char *maptype(struct mmc_command *cmd) 204{ 205 switch (mmc_spi_resp_type(cmd)) { 206 case MMC_RSP_SPI_R1: return "R1"; 207 case MMC_RSP_SPI_R1B: return "R1B"; 208 case MMC_RSP_SPI_R2: return "R2/R5"; 209 case MMC_RSP_SPI_R3: return "R3/R4/R7"; 210 default: return "?"; 211 } 212} 213 214/* return zero, else negative errno after setting cmd->error */ 215static int mmc_spi_response_get(struct mmc_spi_host *host, 216 struct mmc_command *cmd, int cs_on) 217{ 218 unsigned long timeout_ms; 219 u8 *cp = host->data->status; 220 u8 *end = cp + host->t.len; 221 int value = 0; 222 int bitshift; 223 u8 leftover = 0; 224 unsigned short rotator; 225 int i; 226 char tag[32]; 227 228 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", 229 cmd->opcode, maptype(cmd)); 230 231 /* Except for data block reads, the whole response will already 232 * be stored in the scratch buffer. It's somewhere after the 233 * command and the first byte we read after it. We ignore that 234 * first byte. After STOP_TRANSMISSION command it may include 235 * two data bits, but otherwise it's all ones. 236 */ 237 cp += 8; 238 while (cp < end && *cp == 0xff) 239 cp++; 240 241 /* Data block reads (R1 response types) may need more data... */ 242 if (cp == end) { 243 cp = host->data->status; 244 end = cp+1; 245 246 /* Card sends N(CR) (== 1..8) bytes of all-ones then one 247 * status byte ... and we already scanned 2 bytes. 248 * 249 * REVISIT block read paths use nasty byte-at-a-time I/O 250 * so it can always DMA directly into the target buffer. 251 * It'd probably be better to memcpy() the first chunk and 252 * avoid extra i/o calls... 253 * 254 * Note we check for more than 8 bytes, because in practice, 255 * some SD cards are slow... 256 */ 257 for (i = 2; i < 16; i++) { 258 value = mmc_spi_readbytes(host, 1); 259 if (value < 0) 260 goto done; 261 if (*cp != 0xff) 262 goto checkstatus; 263 } 264 value = -ETIMEDOUT; 265 goto done; 266 } 267 268checkstatus: 269 bitshift = 0; 270 if (*cp & 0x80) { 271 /* Houston, we have an ugly card with a bit-shifted response */ 272 rotator = *cp++ << 8; 273 /* read the next byte */ 274 if (cp == end) { 275 value = mmc_spi_readbytes(host, 1); 276 if (value < 0) 277 goto done; 278 cp = host->data->status; 279 end = cp+1; 280 } 281 rotator |= *cp++; 282 while (rotator & 0x8000) { 283 bitshift++; 284 rotator <<= 1; 285 } 286 cmd->resp[0] = rotator >> 8; 287 leftover = rotator; 288 } else { 289 cmd->resp[0] = *cp++; 290 } 291 cmd->error = 0; 292 293 /* Status byte: the entire seven-bit R1 response. */ 294 if (cmd->resp[0] != 0) { 295 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS) 296 & cmd->resp[0]) 297 value = -EFAULT; /* Bad address */ 298 else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0]) 299 value = -ENOSYS; /* Function not implemented */ 300 else if (R1_SPI_COM_CRC & cmd->resp[0]) 301 value = -EILSEQ; /* Illegal byte sequence */ 302 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) 303 & cmd->resp[0]) 304 value = -EIO; /* I/O error */ 305 /* else R1_SPI_IDLE, "it's resetting" */ 306 } 307 308 switch (mmc_spi_resp_type(cmd)) { 309 310 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) 311 * and less-common stuff like various erase operations. 312 */ 313 case MMC_RSP_SPI_R1B: 314 /* maybe we read all the busy tokens already */ 315 while (cp < end && *cp == 0) 316 cp++; 317 if (cp == end) { 318 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : 319 MMC_SPI_R1B_TIMEOUT_MS; 320 mmc_spi_wait_unbusy(host, msecs_to_jiffies(timeout_ms)); 321 } 322 break; 323 324 /* SPI R2 == R1 + second status byte; SEND_STATUS 325 * SPI R5 == R1 + data byte; IO_RW_DIRECT 326 */ 327 case MMC_RSP_SPI_R2: 328 /* read the next byte */ 329 if (cp == end) { 330 value = mmc_spi_readbytes(host, 1); 331 if (value < 0) 332 goto done; 333 cp = host->data->status; 334 end = cp+1; 335 } 336 if (bitshift) { 337 rotator = leftover << 8; 338 rotator |= *cp << bitshift; 339 cmd->resp[0] |= (rotator & 0xFF00); 340 } else { 341 cmd->resp[0] |= *cp << 8; 342 } 343 break; 344 345 /* SPI R3, R4, or R7 == R1 + 4 bytes */ 346 case MMC_RSP_SPI_R3: 347 rotator = leftover << 8; 348 cmd->resp[1] = 0; 349 for (i = 0; i < 4; i++) { 350 cmd->resp[1] <<= 8; 351 /* read the next byte */ 352 if (cp == end) { 353 value = mmc_spi_readbytes(host, 1); 354 if (value < 0) 355 goto done; 356 cp = host->data->status; 357 end = cp+1; 358 } 359 if (bitshift) { 360 rotator |= *cp++ << bitshift; 361 cmd->resp[1] |= (rotator >> 8); 362 rotator <<= 8; 363 } else { 364 cmd->resp[1] |= *cp++; 365 } 366 } 367 break; 368 369 /* SPI R1 == just one status byte */ 370 case MMC_RSP_SPI_R1: 371 break; 372 373 default: 374 dev_dbg(&host->spi->dev, "bad response type %04x\n", 375 mmc_spi_resp_type(cmd)); 376 if (value >= 0) 377 value = -EINVAL; 378 goto done; 379 } 380 381 if (value < 0) 382 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n", 383 tag, cmd->resp[0], cmd->resp[1]); 384 385 /* disable chipselect on errors and some success cases */ 386 if (value >= 0 && cs_on) 387 return value; 388done: 389 if (value < 0) 390 cmd->error = value; 391 mmc_cs_off(host); 392 return value; 393} 394 395/* Issue command and read its response. 396 * Returns zero on success, negative for error. 397 * 398 * On error, caller must cope with mmc core retry mechanism. That 399 * means immediate low-level resubmit, which affects the bus lock... 400 */ 401static int 402mmc_spi_command_send(struct mmc_spi_host *host, 403 struct mmc_request *mrq, 404 struct mmc_command *cmd, int cs_on) 405{ 406 struct scratch *data = host->data; 407 u8 *cp = data->status; 408 int status; 409 struct spi_transfer *t; 410 411 /* We can handle most commands (except block reads) in one full 412 * duplex I/O operation before either starting the next transfer 413 * (data block or command) or else deselecting the card. 414 * 415 * First, write 7 bytes: 416 * - an all-ones byte to ensure the card is ready 417 * - opcode byte (plus start and transmission bits) 418 * - four bytes of big-endian argument 419 * - crc7 (plus end bit) ... always computed, it's cheap 420 * 421 * We init the whole buffer to all-ones, which is what we need 422 * to write while we're reading (later) response data. 423 */ 424 memset(cp, 0xff, sizeof(data->status)); 425 426 cp[1] = 0x40 | cmd->opcode; 427 put_unaligned_be32(cmd->arg, cp + 2); 428 cp[6] = crc7_be(0, cp + 1, 5) | 0x01; 429 cp += 7; 430 431 /* Then, read up to 13 bytes (while writing all-ones): 432 * - N(CR) (== 1..8) bytes of all-ones 433 * - status byte (for all response types) 434 * - the rest of the response, either: 435 * + nothing, for R1 or R1B responses 436 * + second status byte, for R2 responses 437 * + four data bytes, for R3 and R7 responses 438 * 439 * Finally, read some more bytes ... in the nice cases we know in 440 * advance how many, and reading 1 more is always OK: 441 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish 442 * - N(RC) (== 1..N) bytes of all-ones, before next command 443 * - N(WR) (== 1..N) bytes of all-ones, before data write 444 * 445 * So in those cases one full duplex I/O of at most 21 bytes will 446 * handle the whole command, leaving the card ready to receive a 447 * data block or new command. We do that whenever we can, shaving 448 * CPU and IRQ costs (especially when using DMA or FIFOs). 449 * 450 * There are two other cases, where it's not generally practical 451 * to rely on a single I/O: 452 * 453 * - R1B responses need at least N(EC) bytes of all-zeroes. 454 * 455 * In this case we can *try* to fit it into one I/O, then 456 * maybe read more data later. 457 * 458 * - Data block reads are more troublesome, since a variable 459 * number of padding bytes precede the token and data. 460 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID 461 * + N(AC) (== 1..many) bytes of all-ones 462 * 463 * In this case we currently only have minimal speedups here: 464 * when N(CR) == 1 we can avoid I/O in response_get(). 465 */ 466 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) { 467 cp += 2; /* min(N(CR)) + status */ 468 /* R1 */ 469 } else { 470 cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ 471 if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ 472 cp++; 473 else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */ 474 cp += 4; 475 else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ 476 cp = data->status + sizeof(data->status); 477 /* else: R1 (most commands) */ 478 } 479 480 dev_dbg(&host->spi->dev, " CMD%d, resp %s\n", 481 cmd->opcode, maptype(cmd)); 482 483 /* send command, leaving chipselect active */ 484 spi_message_init(&host->m); 485 486 t = &host->t; 487 memset(t, 0, sizeof(*t)); 488 t->tx_buf = t->rx_buf = data->status; 489 t->len = cp - data->status; 490 t->cs_change = 1; 491 spi_message_add_tail(t, &host->m); 492 493 status = spi_sync_locked(host->spi, &host->m); 494 if (status < 0) { 495 dev_dbg(&host->spi->dev, " ... write returned %d\n", status); 496 cmd->error = status; 497 return status; 498 } 499 500 /* after no-data commands and STOP_TRANSMISSION, chipselect off */ 501 return mmc_spi_response_get(host, cmd, cs_on); 502} 503 504/* Build data message with up to four separate transfers. For TX, we 505 * start by writing the data token. And in most cases, we finish with 506 * a status transfer. 507 * 508 * We always provide TX data for data and CRC. The MMC/SD protocol 509 * requires us to write ones; but Linux defaults to writing zeroes; 510 * so we explicitly initialize it to all ones on RX paths. 511 */ 512static void 513mmc_spi_setup_data_message( 514 struct mmc_spi_host *host, 515 bool multiple, 516 enum dma_data_direction direction) 517{ 518 struct spi_transfer *t; 519 struct scratch *scratch = host->data; 520 521 spi_message_init(&host->m); 522 523 /* for reads, readblock() skips 0xff bytes before finding 524 * the token; for writes, this transfer issues that token. 525 */ 526 if (direction == DMA_TO_DEVICE) { 527 t = &host->token; 528 memset(t, 0, sizeof(*t)); 529 t->len = 1; 530 if (multiple) 531 scratch->data_token = SPI_TOKEN_MULTI_WRITE; 532 else 533 scratch->data_token = SPI_TOKEN_SINGLE; 534 t->tx_buf = &scratch->data_token; 535 spi_message_add_tail(t, &host->m); 536 } 537 538 /* Body of transfer is buffer, then CRC ... 539 * either TX-only, or RX with TX-ones. 540 */ 541 t = &host->t; 542 memset(t, 0, sizeof(*t)); 543 t->tx_buf = host->ones; 544 /* length and actual buffer info are written later */ 545 spi_message_add_tail(t, &host->m); 546 547 t = &host->crc; 548 memset(t, 0, sizeof(*t)); 549 t->len = 2; 550 if (direction == DMA_TO_DEVICE) { 551 /* the actual CRC may get written later */ 552 t->tx_buf = &scratch->crc_val; 553 } else { 554 t->tx_buf = host->ones; 555 t->rx_buf = &scratch->crc_val; 556 } 557 spi_message_add_tail(t, &host->m); 558 559 /* 560 * A single block read is followed by N(EC) [0+] all-ones bytes 561 * before deselect ... don't bother. 562 * 563 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before 564 * the next block is read, or a STOP_TRANSMISSION is issued. We'll 565 * collect that single byte, so readblock() doesn't need to. 566 * 567 * For a write, the one-byte data response follows immediately, then 568 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. 569 * Then single block reads may deselect, and multiblock ones issue 570 * the next token (next data block, or STOP_TRAN). We can try to 571 * minimize I/O ops by using a single read to collect end-of-busy. 572 */ 573 if (multiple || direction == DMA_TO_DEVICE) { 574 t = &host->early_status; 575 memset(t, 0, sizeof(*t)); 576 t->len = (direction == DMA_TO_DEVICE) ? sizeof(scratch->status) : 1; 577 t->tx_buf = host->ones; 578 t->rx_buf = scratch->status; 579 t->cs_change = 1; 580 spi_message_add_tail(t, &host->m); 581 } 582} 583 584/* 585 * Write one block: 586 * - caller handled preceding N(WR) [1+] all-ones bytes 587 * - data block 588 * + token 589 * + data bytes 590 * + crc16 591 * - an all-ones byte ... card writes a data-response byte 592 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy' 593 * 594 * Return negative errno, else success. 595 */ 596static int 597mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, 598 unsigned long timeout) 599{ 600 struct spi_device *spi = host->spi; 601 int status, i; 602 struct scratch *scratch = host->data; 603 u32 pattern; 604 605 if (host->mmc->use_spi_crc) 606 scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len)); 607 608 status = spi_sync_locked(spi, &host->m); 609 if (status != 0) { 610 dev_dbg(&spi->dev, "write error (%d)\n", status); 611 return status; 612 } 613 614 /* 615 * Get the transmission data-response reply. It must follow 616 * immediately after the data block we transferred. This reply 617 * doesn't necessarily tell whether the write operation succeeded; 618 * it just says if the transmission was ok and whether *earlier* 619 * writes succeeded; see the standard. 620 * 621 * In practice, there are (even modern SDHC-)cards which are late 622 * in sending the response, and miss the time frame by a few bits, 623 * so we have to cope with this situation and check the response 624 * bit-by-bit. Arggh!!! 625 */ 626 pattern = get_unaligned_be32(scratch->status); 627 628 /* First 3 bit of pattern are undefined */ 629 pattern |= 0xE0000000; 630 631 /* left-adjust to leading 0 bit */ 632 while (pattern & 0x80000000) 633 pattern <<= 1; 634 /* right-adjust for pattern matching. Code is in bit 4..0 now. */ 635 pattern >>= 27; 636 637 switch (pattern) { 638 case SPI_RESPONSE_ACCEPTED: 639 status = 0; 640 break; 641 case SPI_RESPONSE_CRC_ERR: 642 /* host shall then issue MMC_STOP_TRANSMISSION */ 643 status = -EILSEQ; 644 break; 645 case SPI_RESPONSE_WRITE_ERR: 646 /* host shall then issue MMC_STOP_TRANSMISSION, 647 * and should MMC_SEND_STATUS to sort it out 648 */ 649 status = -EIO; 650 break; 651 default: 652 status = -EPROTO; 653 break; 654 } 655 if (status != 0) { 656 dev_dbg(&spi->dev, "write error %02x (%d)\n", 657 scratch->status[0], status); 658 return status; 659 } 660 661 t->tx_buf += t->len; 662 663 /* Return when not busy. If we didn't collect that status yet, 664 * we'll need some more I/O. 665 */ 666 for (i = 4; i < sizeof(scratch->status); i++) { 667 /* card is non-busy if the most recent bit is 1 */ 668 if (scratch->status[i] & 0x01) 669 return 0; 670 } 671 return mmc_spi_wait_unbusy(host, timeout); 672} 673 674/* 675 * Read one block: 676 * - skip leading all-ones bytes ... either 677 * + N(AC) [1..f(clock,CSD)] usually, else 678 * + N(CX) [0..8] when reading CSD or CID 679 * - data block 680 * + token ... if error token, no data or crc 681 * + data bytes 682 * + crc16 683 * 684 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow 685 * before dropping chipselect. 686 * 687 * For multiblock reads, caller either reads the next block or issues a 688 * STOP_TRANSMISSION command. 689 */ 690static int 691mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, 692 unsigned long timeout) 693{ 694 struct spi_device *spi = host->spi; 695 int status; 696 struct scratch *scratch = host->data; 697 unsigned int bitshift; 698 u8 leftover; 699 700 /* At least one SD card sends an all-zeroes byte when N(CX) 701 * applies, before the all-ones bytes ... just cope with that. 702 */ 703 status = mmc_spi_readbytes(host, 1); 704 if (status < 0) 705 return status; 706 status = scratch->status[0]; 707 if (status == 0xff || status == 0) 708 status = mmc_spi_readtoken(host, timeout); 709 710 if (status < 0) { 711 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status); 712 return status; 713 } 714 715 /* The token may be bit-shifted... 716 * the first 0-bit precedes the data stream. 717 */ 718 bitshift = 7; 719 while (status & 0x80) { 720 status <<= 1; 721 bitshift--; 722 } 723 leftover = status << 1; 724 725 status = spi_sync_locked(spi, &host->m); 726 if (status < 0) { 727 dev_dbg(&spi->dev, "read error %d\n", status); 728 return status; 729 } 730 731 if (bitshift) { 732 /* Walk through the data and the crc and do 733 * all the magic to get byte-aligned data. 734 */ 735 u8 *cp = t->rx_buf; 736 unsigned int len; 737 unsigned int bitright = 8 - bitshift; 738 u8 temp; 739 for (len = t->len; len; len--) { 740 temp = *cp; 741 *cp++ = leftover | (temp >> bitshift); 742 leftover = temp << bitright; 743 } 744 cp = (u8 *) &scratch->crc_val; 745 temp = *cp; 746 *cp++ = leftover | (temp >> bitshift); 747 leftover = temp << bitright; 748 temp = *cp; 749 *cp = leftover | (temp >> bitshift); 750 } 751 752 if (host->mmc->use_spi_crc) { 753 u16 crc = crc_itu_t(0, t->rx_buf, t->len); 754 755 be16_to_cpus(&scratch->crc_val); 756 if (scratch->crc_val != crc) { 757 dev_dbg(&spi->dev, 758 "read - crc error: crc_val=0x%04x, computed=0x%04x len=%d\n", 759 scratch->crc_val, crc, t->len); 760 return -EILSEQ; 761 } 762 } 763 764 t->rx_buf += t->len; 765 766 return 0; 767} 768 769/* 770 * An MMC/SD data stage includes one or more blocks, optional CRCs, 771 * and inline handshaking. That handhaking makes it unlike most 772 * other SPI protocol stacks. 773 */ 774static void 775mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, 776 struct mmc_data *data, u32 blk_size) 777{ 778 struct spi_device *spi = host->spi; 779 struct spi_transfer *t; 780 enum dma_data_direction direction = mmc_get_dma_dir(data); 781 struct scatterlist *sg; 782 unsigned n_sg; 783 bool multiple = (data->blocks > 1); 784 const char *write_or_read = (direction == DMA_TO_DEVICE) ? "write" : "read"; 785 u32 clock_rate; 786 unsigned long timeout; 787 788 mmc_spi_setup_data_message(host, multiple, direction); 789 t = &host->t; 790 791 if (t->speed_hz) 792 clock_rate = t->speed_hz; 793 else 794 clock_rate = spi->max_speed_hz; 795 796 timeout = data->timeout_ns / 1000 + 797 data->timeout_clks * 1000000 / clock_rate; 798 timeout = usecs_to_jiffies((unsigned int)timeout) + 1; 799 800 /* Handle scatterlist segments one at a time, with synch for 801 * each 512-byte block 802 */ 803 for_each_sg(data->sg, sg, data->sg_len, n_sg) { 804 int status = 0; 805 void *kmap_addr; 806 unsigned length = sg->length; 807 808 /* allow pio too; we don't allow highmem */ 809 kmap_addr = kmap(sg_page(sg)); 810 if (direction == DMA_TO_DEVICE) 811 t->tx_buf = kmap_addr + sg->offset; 812 else 813 t->rx_buf = kmap_addr + sg->offset; 814 815 /* transfer each block, and update request status */ 816 while (length) { 817 t->len = min(length, blk_size); 818 819 dev_dbg(&spi->dev, " %s block, %d bytes\n", write_or_read, t->len); 820 821 if (direction == DMA_TO_DEVICE) 822 status = mmc_spi_writeblock(host, t, timeout); 823 else 824 status = mmc_spi_readblock(host, t, timeout); 825 if (status < 0) 826 break; 827 828 data->bytes_xfered += t->len; 829 length -= t->len; 830 831 if (!multiple) 832 break; 833 } 834 835 /* discard mappings */ 836 if (direction == DMA_FROM_DEVICE) 837 flush_dcache_page(sg_page(sg)); 838 kunmap(sg_page(sg)); 839 840 if (status < 0) { 841 data->error = status; 842 dev_dbg(&spi->dev, "%s status %d\n", write_or_read, status); 843 break; 844 } 845 } 846 847 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that 848 * can be issued before multiblock writes. Unlike its more widely 849 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23), 850 * that can affect the STOP_TRAN logic. Complete (and current) 851 * MMC specs should sort that out before Linux starts using CMD23. 852 */ 853 if (direction == DMA_TO_DEVICE && multiple) { 854 struct scratch *scratch = host->data; 855 int tmp; 856 const unsigned statlen = sizeof(scratch->status); 857 858 dev_dbg(&spi->dev, " STOP_TRAN\n"); 859 860 /* Tweak the per-block message we set up earlier by morphing 861 * it to hold single buffer with the token followed by some 862 * all-ones bytes ... skip N(BR) (0..1), scan the rest for 863 * "not busy any longer" status, and leave chip selected. 864 */ 865 INIT_LIST_HEAD(&host->m.transfers); 866 list_add(&host->early_status.transfer_list, 867 &host->m.transfers); 868 869 memset(scratch->status, 0xff, statlen); 870 scratch->status[0] = SPI_TOKEN_STOP_TRAN; 871 872 host->early_status.tx_buf = host->early_status.rx_buf; 873 host->early_status.len = statlen; 874 875 tmp = spi_sync_locked(spi, &host->m); 876 if (tmp < 0) { 877 if (!data->error) 878 data->error = tmp; 879 return; 880 } 881 882 /* Ideally we collected "not busy" status with one I/O, 883 * avoiding wasteful byte-at-a-time scanning... but more 884 * I/O is often needed. 885 */ 886 for (tmp = 2; tmp < statlen; tmp++) { 887 if (scratch->status[tmp] != 0) 888 return; 889 } 890 tmp = mmc_spi_wait_unbusy(host, timeout); 891 if (tmp < 0 && !data->error) 892 data->error = tmp; 893 } 894} 895 896/****************************************************************************/ 897 898/* 899 * MMC driver implementation -- the interface to the MMC stack 900 */ 901 902static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) 903{ 904 struct mmc_spi_host *host = mmc_priv(mmc); 905 int status = -EINVAL; 906 int crc_retry = 5; 907 struct mmc_command stop; 908 909#ifdef DEBUG 910 /* MMC core and layered drivers *MUST* issue SPI-aware commands */ 911 { 912 struct mmc_command *cmd; 913 int invalid = 0; 914 915 cmd = mrq->cmd; 916 if (!mmc_spi_resp_type(cmd)) { 917 dev_dbg(&host->spi->dev, "bogus command\n"); 918 cmd->error = -EINVAL; 919 invalid = 1; 920 } 921 922 cmd = mrq->stop; 923 if (cmd && !mmc_spi_resp_type(cmd)) { 924 dev_dbg(&host->spi->dev, "bogus STOP command\n"); 925 cmd->error = -EINVAL; 926 invalid = 1; 927 } 928 929 if (invalid) { 930 dump_stack(); 931 mmc_request_done(host->mmc, mrq); 932 return; 933 } 934 } 935#endif 936 937 /* request exclusive bus access */ 938 spi_bus_lock(host->spi->master); 939 940crc_recover: 941 /* issue command; then optionally data and stop */ 942 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); 943 if (status == 0 && mrq->data) { 944 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz); 945 946 /* 947 * The SPI bus is not always reliable for large data transfers. 948 * If an occasional crc error is reported by the SD device with 949 * data read/write over SPI, it may be recovered by repeating 950 * the last SD command again. The retry count is set to 5 to 951 * ensure the driver passes stress tests. 952 */ 953 if (mrq->data->error == -EILSEQ && crc_retry) { 954 stop.opcode = MMC_STOP_TRANSMISSION; 955 stop.arg = 0; 956 stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; 957 status = mmc_spi_command_send(host, mrq, &stop, 0); 958 crc_retry--; 959 mrq->data->error = 0; 960 goto crc_recover; 961 } 962 963 if (mrq->stop) 964 status = mmc_spi_command_send(host, mrq, mrq->stop, 0); 965 else 966 mmc_cs_off(host); 967 } 968 969 /* release the bus */ 970 spi_bus_unlock(host->spi->master); 971 972 mmc_request_done(host->mmc, mrq); 973} 974 975/* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0" 976 * 977 * NOTE that here we can't know that the card has just been powered up; 978 * not all MMC/SD sockets support power switching. 979 * 980 * FIXME when the card is still in SPI mode, e.g. from a previous kernel, 981 * this doesn't seem to do the right thing at all... 982 */ 983static void mmc_spi_initsequence(struct mmc_spi_host *host) 984{ 985 /* Try to be very sure any previous command has completed; 986 * wait till not-busy, skip debris from any old commands. 987 */ 988 mmc_spi_wait_unbusy(host, msecs_to_jiffies(MMC_SPI_INIT_TIMEOUT_MS)); 989 mmc_spi_readbytes(host, 10); 990 991 /* 992 * Do a burst with chipselect active-high. We need to do this to 993 * meet the requirement of 74 clock cycles with both chipselect 994 * and CMD (MOSI) high before CMD0 ... after the card has been 995 * powered up to Vdd(min), and so is ready to take commands. 996 * 997 * Some cards are particularly needy of this (e.g. Viking "SD256") 998 * while most others don't seem to care. 999 * 1000 * Note that this is one of the places MMC/SD plays games with the 1001 * SPI protocol. Another is that when chipselect is released while 1002 * the card returns BUSY status, the clock must issue several cycles 1003 * with chipselect high before the card will stop driving its output. 1004 * 1005 * SPI_CS_HIGH means "asserted" here. In some cases like when using 1006 * GPIOs for chip select, SPI_CS_HIGH is set but this will be logically 1007 * inverted by gpiolib, so if we want to ascertain to drive it high 1008 * we should toggle the default with an XOR as we do here. 1009 */ 1010 host->spi->mode ^= SPI_CS_HIGH; 1011 if (spi_setup(host->spi) != 0) { 1012 /* Just warn; most cards work without it. */ 1013 dev_warn(&host->spi->dev, 1014 "can't change chip-select polarity\n"); 1015 host->spi->mode ^= SPI_CS_HIGH; 1016 } else { 1017 mmc_spi_readbytes(host, 18); 1018 1019 host->spi->mode ^= SPI_CS_HIGH; 1020 if (spi_setup(host->spi) != 0) { 1021 /* Wot, we can't get the same setup we had before? */ 1022 dev_err(&host->spi->dev, 1023 "can't restore chip-select polarity\n"); 1024 } 1025 } 1026} 1027 1028static char *mmc_powerstring(u8 power_mode) 1029{ 1030 switch (power_mode) { 1031 case MMC_POWER_OFF: return "off"; 1032 case MMC_POWER_UP: return "up"; 1033 case MMC_POWER_ON: return "on"; 1034 } 1035 return "?"; 1036} 1037 1038static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1039{ 1040 struct mmc_spi_host *host = mmc_priv(mmc); 1041 1042 if (host->power_mode != ios->power_mode) { 1043 int canpower; 1044 1045 canpower = host->pdata && host->pdata->setpower; 1046 1047 dev_dbg(&host->spi->dev, "power %s (%d)%s\n", 1048 mmc_powerstring(ios->power_mode), 1049 ios->vdd, 1050 canpower ? ", can switch" : ""); 1051 1052 /* switch power on/off if possible, accounting for 1053 * max 250msec powerup time if needed. 1054 */ 1055 if (canpower) { 1056 switch (ios->power_mode) { 1057 case MMC_POWER_OFF: 1058 case MMC_POWER_UP: 1059 host->pdata->setpower(&host->spi->dev, 1060 ios->vdd); 1061 if (ios->power_mode == MMC_POWER_UP) 1062 msleep(host->powerup_msecs); 1063 } 1064 } 1065 1066 /* See 6.4.1 in the simplified SD card physical spec 2.0 */ 1067 if (ios->power_mode == MMC_POWER_ON) 1068 mmc_spi_initsequence(host); 1069 1070 /* If powering down, ground all card inputs to avoid power 1071 * delivery from data lines! On a shared SPI bus, this 1072 * will probably be temporary; 6.4.2 of the simplified SD 1073 * spec says this must last at least 1msec. 1074 * 1075 * - Clock low means CPOL 0, e.g. mode 0 1076 * - MOSI low comes from writing zero 1077 * - Chipselect is usually active low... 1078 */ 1079 if (canpower && ios->power_mode == MMC_POWER_OFF) { 1080 int mres; 1081 u8 nullbyte = 0; 1082 1083 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA); 1084 mres = spi_setup(host->spi); 1085 if (mres < 0) 1086 dev_dbg(&host->spi->dev, 1087 "switch to SPI mode 0 failed\n"); 1088 1089 if (spi_write(host->spi, &nullbyte, 1) < 0) 1090 dev_dbg(&host->spi->dev, 1091 "put spi signals to low failed\n"); 1092 1093 /* 1094 * Now clock should be low due to spi mode 0; 1095 * MOSI should be low because of written 0x00; 1096 * chipselect should be low (it is active low) 1097 * power supply is off, so now MMC is off too! 1098 * 1099 * FIXME no, chipselect can be high since the 1100 * device is inactive and SPI_CS_HIGH is clear... 1101 */ 1102 msleep(10); 1103 if (mres == 0) { 1104 host->spi->mode |= (SPI_CPOL|SPI_CPHA); 1105 mres = spi_setup(host->spi); 1106 if (mres < 0) 1107 dev_dbg(&host->spi->dev, 1108 "switch back to SPI mode 3 failed\n"); 1109 } 1110 } 1111 1112 host->power_mode = ios->power_mode; 1113 } 1114 1115 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) { 1116 int status; 1117 1118 host->spi->max_speed_hz = ios->clock; 1119 status = spi_setup(host->spi); 1120 dev_dbg(&host->spi->dev, " clock to %d Hz, %d\n", 1121 host->spi->max_speed_hz, status); 1122 } 1123} 1124 1125static const struct mmc_host_ops mmc_spi_ops = { 1126 .request = mmc_spi_request, 1127 .set_ios = mmc_spi_set_ios, 1128 .get_ro = mmc_gpio_get_ro, 1129 .get_cd = mmc_gpio_get_cd, 1130}; 1131 1132 1133/****************************************************************************/ 1134 1135/* 1136 * SPI driver implementation 1137 */ 1138 1139static irqreturn_t 1140mmc_spi_detect_irq(int irq, void *mmc) 1141{ 1142 struct mmc_spi_host *host = mmc_priv(mmc); 1143 u16 delay_msec = max(host->pdata->detect_delay, (u16)100); 1144 1145 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); 1146 return IRQ_HANDLED; 1147} 1148 1149static int mmc_spi_probe(struct spi_device *spi) 1150{ 1151 void *ones; 1152 struct mmc_host *mmc; 1153 struct mmc_spi_host *host; 1154 int status; 1155 bool has_ro = false; 1156 1157 /* We rely on full duplex transfers, mostly to reduce 1158 * per-transfer overheads (by making fewer transfers). 1159 */ 1160 if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) 1161 return -EINVAL; 1162 1163 /* MMC and SD specs only seem to care that sampling is on the 1164 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode 1165 * should be legit. We'll use mode 0 since the steady state is 0, 1166 * which is appropriate for hotplugging, unless the platform data 1167 * specify mode 3 (if hardware is not compatible to mode 0). 1168 */ 1169 if (spi->mode != SPI_MODE_3) 1170 spi->mode = SPI_MODE_0; 1171 spi->bits_per_word = 8; 1172 1173 status = spi_setup(spi); 1174 if (status < 0) { 1175 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n", 1176 spi->mode, spi->max_speed_hz / 1000, 1177 status); 1178 return status; 1179 } 1180 1181 /* We need a supply of ones to transmit. This is the only time 1182 * the CPU touches these, so cache coherency isn't a concern. 1183 * 1184 * NOTE if many systems use more than one MMC-over-SPI connector 1185 * it'd save some memory to share this. That's evidently rare. 1186 */ 1187 status = -ENOMEM; 1188 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL); 1189 if (!ones) 1190 goto nomem; 1191 memset(ones, 0xff, MMC_SPI_BLOCKSIZE); 1192 1193 mmc = mmc_alloc_host(sizeof(*host), &spi->dev); 1194 if (!mmc) 1195 goto nomem; 1196 1197 mmc->ops = &mmc_spi_ops; 1198 mmc->max_blk_size = MMC_SPI_BLOCKSIZE; 1199 mmc->max_segs = MMC_SPI_BLOCKSATONCE; 1200 mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE; 1201 mmc->max_blk_count = MMC_SPI_BLOCKSATONCE; 1202 1203 mmc->caps = MMC_CAP_SPI; 1204 1205 /* SPI doesn't need the lowspeed device identification thing for 1206 * MMC or SD cards, since it never comes up in open drain mode. 1207 * That's good; some SPI masters can't handle very low speeds! 1208 * 1209 * However, low speed SDIO cards need not handle over 400 KHz; 1210 * that's the only reason not to use a few MHz for f_min (until 1211 * the upper layer reads the target frequency from the CSD). 1212 */ 1213 mmc->f_min = 400000; 1214 mmc->f_max = spi->max_speed_hz; 1215 1216 host = mmc_priv(mmc); 1217 host->mmc = mmc; 1218 host->spi = spi; 1219 1220 host->ones = ones; 1221 1222 dev_set_drvdata(&spi->dev, mmc); 1223 1224 /* Platform data is used to hook up things like card sensing 1225 * and power switching gpios. 1226 */ 1227 host->pdata = mmc_spi_get_pdata(spi); 1228 if (host->pdata) 1229 mmc->ocr_avail = host->pdata->ocr_mask; 1230 if (!mmc->ocr_avail) { 1231 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n"); 1232 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; 1233 } 1234 if (host->pdata && host->pdata->setpower) { 1235 host->powerup_msecs = host->pdata->powerup_msecs; 1236 if (!host->powerup_msecs || host->powerup_msecs > 250) 1237 host->powerup_msecs = 250; 1238 } 1239 1240 /* Preallocate buffers */ 1241 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL); 1242 if (!host->data) 1243 goto fail_nobuf1; 1244 1245 /* setup message for status/busy readback */ 1246 spi_message_init(&host->readback); 1247 1248 spi_message_add_tail(&host->status, &host->readback); 1249 host->status.tx_buf = host->ones; 1250 host->status.rx_buf = &host->data->status; 1251 host->status.cs_change = 1; 1252 1253 /* register card detect irq */ 1254 if (host->pdata && host->pdata->init) { 1255 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc); 1256 if (status != 0) 1257 goto fail_glue_init; 1258 } 1259 1260 /* pass platform capabilities, if any */ 1261 if (host->pdata) { 1262 mmc->caps |= host->pdata->caps; 1263 mmc->caps2 |= host->pdata->caps2; 1264 } 1265 1266 status = mmc_add_host(mmc); 1267 if (status != 0) 1268 goto fail_glue_init; 1269 1270 /* 1271 * Index 0 is card detect 1272 * Old boardfiles were specifying 1 ms as debounce 1273 */ 1274 status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000); 1275 if (status == -EPROBE_DEFER) 1276 goto fail_gpiod_request; 1277 if (!status) { 1278 /* 1279 * The platform has a CD GPIO signal that may support 1280 * interrupts, so let mmc_gpiod_request_cd_irq() decide 1281 * if polling is needed or not. 1282 */ 1283 mmc->caps &= ~MMC_CAP_NEEDS_POLL; 1284 mmc_gpiod_request_cd_irq(mmc); 1285 } 1286 mmc_detect_change(mmc, 0); 1287 1288 /* Index 1 is write protect/read only */ 1289 status = mmc_gpiod_request_ro(mmc, NULL, 1, 0); 1290 if (status == -EPROBE_DEFER) 1291 goto fail_gpiod_request; 1292 if (!status) 1293 has_ro = true; 1294 1295 dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n", 1296 dev_name(&mmc->class_dev), 1297 has_ro ? "" : ", no WP", 1298 (host->pdata && host->pdata->setpower) 1299 ? "" : ", no poweroff", 1300 (mmc->caps & MMC_CAP_NEEDS_POLL) 1301 ? ", cd polling" : ""); 1302 return 0; 1303 1304fail_gpiod_request: 1305 mmc_remove_host(mmc); 1306fail_glue_init: 1307 kfree(host->data); 1308fail_nobuf1: 1309 mmc_spi_put_pdata(spi); 1310 mmc_free_host(mmc); 1311nomem: 1312 kfree(ones); 1313 return status; 1314} 1315 1316 1317static void mmc_spi_remove(struct spi_device *spi) 1318{ 1319 struct mmc_host *mmc = dev_get_drvdata(&spi->dev); 1320 struct mmc_spi_host *host = mmc_priv(mmc); 1321 1322 /* prevent new mmc_detect_change() calls */ 1323 if (host->pdata && host->pdata->exit) 1324 host->pdata->exit(&spi->dev, mmc); 1325 1326 mmc_remove_host(mmc); 1327 1328 kfree(host->data); 1329 kfree(host->ones); 1330 1331 spi->max_speed_hz = mmc->f_max; 1332 mmc_spi_put_pdata(spi); 1333 mmc_free_host(mmc); 1334} 1335 1336static const struct spi_device_id mmc_spi_dev_ids[] = { 1337 { "mmc-spi-slot"}, 1338 { }, 1339}; 1340MODULE_DEVICE_TABLE(spi, mmc_spi_dev_ids); 1341 1342static const struct of_device_id mmc_spi_of_match_table[] = { 1343 { .compatible = "mmc-spi-slot", }, 1344 {}, 1345}; 1346MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table); 1347 1348static struct spi_driver mmc_spi_driver = { 1349 .driver = { 1350 .name = "mmc_spi", 1351 .of_match_table = mmc_spi_of_match_table, 1352 }, 1353 .id_table = mmc_spi_dev_ids, 1354 .probe = mmc_spi_probe, 1355 .remove = mmc_spi_remove, 1356}; 1357 1358module_spi_driver(mmc_spi_driver); 1359 1360MODULE_AUTHOR("Mike Lavender, David Brownell, Hans-Peter Nilsson, Jan Nikitenko"); 1361MODULE_DESCRIPTION("SPI SD/MMC host driver"); 1362MODULE_LICENSE("GPL"); 1363MODULE_ALIAS("spi:mmc_spi"); 1364