1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/of_graph.h> 15#include <linux/platform_device.h> 16#include <linux/pm_runtime.h> 17#include <linux/reset.h> 18#include <linux/sys_soc.h> 19#include <linux/units.h> 20 21#include <media/v4l2-ctrls.h> 22#include <media/v4l2-device.h> 23#include <media/v4l2-fwnode.h> 24#include <media/v4l2-mc.h> 25#include <media/v4l2-subdev.h> 26 27/* LINK registers */ 28/* Module Configuration Register */ 29#define CSI2nMCG 0x0 30#define CSI2nMCG_SDLN GENMASK(11, 8) 31 32/* Module Control Register 0 */ 33#define CSI2nMCT0 0x10 34#define CSI2nMCT0_VDLN(x) ((x) << 0) 35 36/* Module Control Register 2 */ 37#define CSI2nMCT2 0x18 38#define CSI2nMCT2_FRRSKW(x) ((x) << 16) 39#define CSI2nMCT2_FRRCLK(x) ((x) << 0) 40 41/* Module Control Register 3 */ 42#define CSI2nMCT3 0x1c 43#define CSI2nMCT3_RXEN BIT(0) 44 45/* Reset Control Register */ 46#define CSI2nRTCT 0x28 47#define CSI2nRTCT_VSRST BIT(0) 48 49/* Reset Status Register */ 50#define CSI2nRTST 0x2c 51#define CSI2nRTST_VSRSTS BIT(0) 52 53/* Receive Data Type Enable Low Register */ 54#define CSI2nDTEL 0x60 55 56/* Receive Data Type Enable High Register */ 57#define CSI2nDTEH 0x64 58 59/* DPHY registers */ 60/* D-PHY Control Register 0 */ 61#define CSIDPHYCTRL0 0x400 62#define CSIDPHYCTRL0_EN_LDO1200 BIT(1) 63#define CSIDPHYCTRL0_EN_BGR BIT(0) 64 65/* D-PHY Timing Register 0 */ 66#define CSIDPHYTIM0 0x404 67#define CSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) 68#define CSIDPHYTIM0_T_INIT(x) ((x) << 0) 69 70/* D-PHY Timing Register 1 */ 71#define CSIDPHYTIM1 0x408 72#define CSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) 73#define CSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) 74#define CSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) 75#define CSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) 76 77/* D-PHY Skew Adjustment Function */ 78#define CSIDPHYSKW0 0x460 79#define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) ((x) & 0x3) 80#define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4) 81#define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8) 82#define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12) 83#define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \ 84 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \ 85 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \ 86 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)) 87 88#define VSRSTS_RETRIES 20 89 90#define RZG2L_CSI2_MIN_WIDTH 320 91#define RZG2L_CSI2_MIN_HEIGHT 240 92#define RZG2L_CSI2_MAX_WIDTH 2800 93#define RZG2L_CSI2_MAX_HEIGHT 4095 94 95#define RZG2L_CSI2_DEFAULT_WIDTH RZG2L_CSI2_MIN_WIDTH 96#define RZG2L_CSI2_DEFAULT_HEIGHT RZG2L_CSI2_MIN_HEIGHT 97#define RZG2L_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_UYVY8_1X16 98 99enum rzg2l_csi2_pads { 100 RZG2L_CSI2_SINK = 0, 101 RZG2L_CSI2_SOURCE, 102 NR_OF_RZG2L_CSI2_PAD, 103}; 104 105struct rzg2l_csi2 { 106 struct device *dev; 107 void __iomem *base; 108 struct reset_control *presetn; 109 struct reset_control *cmn_rstb; 110 struct clk *sysclk; 111 unsigned long vclk_rate; 112 113 struct v4l2_subdev subdev; 114 struct media_pad pads[NR_OF_RZG2L_CSI2_PAD]; 115 116 struct v4l2_async_notifier notifier; 117 struct v4l2_subdev *remote_source; 118 119 unsigned short lanes; 120 unsigned long hsfreq; 121 122 bool dphy_enabled; 123}; 124 125struct rzg2l_csi2_timings { 126 u32 t_init; 127 u32 tclk_miss; 128 u32 tclk_settle; 129 u32 ths_settle; 130 u32 tclk_prepare; 131 u32 ths_prepare; 132 u32 max_hsfreq; 133}; 134 135static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = { 136 { 137 .max_hsfreq = 80, 138 .t_init = 79801, 139 .tclk_miss = 4, 140 .tclk_settle = 23, 141 .ths_settle = 31, 142 .tclk_prepare = 10, 143 .ths_prepare = 19, 144 }, 145 { 146 .max_hsfreq = 125, 147 .t_init = 79801, 148 .tclk_miss = 4, 149 .tclk_settle = 23, 150 .ths_settle = 28, 151 .tclk_prepare = 10, 152 .ths_prepare = 19, 153 }, 154 { 155 .max_hsfreq = 250, 156 .t_init = 79801, 157 .tclk_miss = 4, 158 .tclk_settle = 23, 159 .ths_settle = 22, 160 .tclk_prepare = 10, 161 .ths_prepare = 16, 162 }, 163 { 164 .max_hsfreq = 360, 165 .t_init = 79801, 166 .tclk_miss = 4, 167 .tclk_settle = 18, 168 .ths_settle = 19, 169 .tclk_prepare = 10, 170 .ths_prepare = 10, 171 }, 172 { 173 .max_hsfreq = 1500, 174 .t_init = 79801, 175 .tclk_miss = 4, 176 .tclk_settle = 18, 177 .ths_settle = 18, 178 .tclk_prepare = 10, 179 .ths_prepare = 10, 180 }, 181}; 182 183struct rzg2l_csi2_format { 184 u32 code; 185 unsigned int datatype; 186 unsigned int bpp; 187}; 188 189static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = { 190 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 }, 191}; 192 193static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 194{ 195 return container_of(sd, struct rzg2l_csi2, subdev); 196} 197 198static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code) 199{ 200 unsigned int i; 201 202 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++) 203 if (rzg2l_csi2_formats[i].code == code) 204 return &rzg2l_csi2_formats[i]; 205 206 return NULL; 207} 208 209static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 210{ 211 return container_of(n, struct rzg2l_csi2, notifier); 212} 213 214static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg) 215{ 216 return ioread32(csi2->base + reg); 217} 218 219static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg, 220 u32 data) 221{ 222 iowrite32(data, csi2->base + reg); 223} 224 225static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set) 226{ 227 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set); 228} 229 230static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr) 231{ 232 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr); 233} 234 235static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2) 236{ 237 struct v4l2_subdev *source = csi2->remote_source; 238 const struct rzg2l_csi2_format *format; 239 const struct v4l2_mbus_framefmt *fmt; 240 struct v4l2_subdev_state *state; 241 struct v4l2_ctrl *ctrl; 242 u64 mbps; 243 244 /* Read the pixel rate control from remote. */ 245 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 246 if (!ctrl) { 247 dev_err(csi2->dev, "no pixel rate control in subdev %s\n", 248 source->name); 249 return -EINVAL; 250 } 251 252 state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev); 253 fmt = v4l2_subdev_get_pad_format(&csi2->subdev, state, RZG2L_CSI2_SINK); 254 format = rzg2l_csi2_code_to_fmt(fmt->code); 255 v4l2_subdev_unlock_state(state); 256 257 /* 258 * Calculate hsfreq in Mbps 259 * hsfreq = (pixel_rate * bits_per_sample) / number_of_lanes 260 */ 261 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * format->bpp; 262 do_div(mbps, csi2->lanes * 1000000); 263 264 return mbps; 265} 266 267/* ----------------------------------------------------------------------------- 268 * DPHY setting 269 */ 270 271static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2) 272{ 273 int ret; 274 275 /* Reset the CRU (D-PHY) */ 276 ret = reset_control_assert(csi2->cmn_rstb); 277 if (ret) 278 return ret; 279 280 /* Stop the D-PHY clock */ 281 clk_disable_unprepare(csi2->sysclk); 282 283 /* Cancel the EN_LDO1200 register setting */ 284 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 285 286 /* Cancel the EN_BGR register setting */ 287 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 288 289 csi2->dphy_enabled = false; 290 291 return 0; 292} 293 294static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2) 295{ 296 const struct rzg2l_csi2_timings *dphy_timing; 297 u32 dphytim0, dphytim1; 298 unsigned int i; 299 int mbps; 300 int ret; 301 302 mbps = rzg2l_csi2_calc_mbps(csi2); 303 if (mbps < 0) 304 return mbps; 305 306 csi2->hsfreq = mbps; 307 308 /* Set DPHY timing parameters */ 309 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) { 310 dphy_timing = &rzg2l_csi2_global_timings[i]; 311 312 if (csi2->hsfreq <= dphy_timing->max_hsfreq) 313 break; 314 } 315 316 if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings)) 317 return -EINVAL; 318 319 /* Set D-PHY timing parameters */ 320 dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) | 321 CSIDPHYTIM0_T_INIT(dphy_timing->t_init); 322 dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) | 323 CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) | 324 CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) | 325 CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle); 326 rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0); 327 rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1); 328 329 /* Enable D-PHY power control 0 */ 330 rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW); 331 332 /* Set the EN_BGR bit */ 333 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 334 335 /* Delay 20us to be stable */ 336 usleep_range(20, 40); 337 338 /* Enable D-PHY power control 1 */ 339 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 340 341 /* Delay 10us to be stable */ 342 usleep_range(10, 20); 343 344 /* Start supplying the internal clock for the D-PHY block */ 345 ret = clk_prepare_enable(csi2->sysclk); 346 if (ret) 347 rzg2l_csi2_dphy_disable(csi2); 348 349 csi2->dphy_enabled = true; 350 351 return ret; 352} 353 354static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on) 355{ 356 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 357 358 if (on) 359 return rzg2l_csi2_dphy_enable(csi2); 360 361 return rzg2l_csi2_dphy_disable(csi2); 362} 363 364static void rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2) 365{ 366 unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ; 367 u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff; 368 369 /* Select data lanes */ 370 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes)); 371 372 frrskw_coeff = 3 * vclk_rate * 8; 373 frrclk_coeff = frrskw_coeff / 2; 374 frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq); 375 frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq); 376 rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) | 377 CSI2nMCT2_FRRCLK(frrclk)); 378 379 /* 380 * Select data type. 381 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8, 382 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit, 383 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit 384 * data types 1 to 8 385 */ 386 rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f); 387 rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f); 388 389 /* Enable LINK reception */ 390 rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 391} 392 393static void rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2) 394{ 395 unsigned int timeout = VSRSTS_RETRIES; 396 397 /* Stop LINK reception */ 398 rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 399 400 /* Request a software reset of the LINK Video Pixel Interface */ 401 rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST); 402 403 /* Make sure CSI2nRTST.VSRSTS bit is cleared */ 404 while (--timeout) { 405 if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS)) 406 break; 407 usleep_range(100, 200); 408 } 409 410 if (!timeout) 411 dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n"); 412} 413 414static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on) 415{ 416 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 417 418 if (on) 419 rzg2l_csi2_mipi_link_enable(csi2); 420 else 421 rzg2l_csi2_mipi_link_disable(csi2); 422 423 return 0; 424} 425 426static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable) 427{ 428 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 429 int s_stream_ret = 0; 430 int ret; 431 432 if (enable) { 433 ret = pm_runtime_resume_and_get(csi2->dev); 434 if (ret) 435 return ret; 436 437 ret = rzg2l_csi2_mipi_link_setting(sd, 1); 438 if (ret) 439 goto err_pm_put; 440 441 ret = reset_control_deassert(csi2->cmn_rstb); 442 if (ret) 443 goto err_mipi_link_disable; 444 } 445 446 ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable); 447 if (ret) 448 s_stream_ret = ret; 449 450 if (enable && ret) 451 goto err_assert_rstb; 452 453 if (!enable) { 454 ret = rzg2l_csi2_dphy_setting(sd, 0); 455 if (ret && !s_stream_ret) 456 s_stream_ret = ret; 457 ret = rzg2l_csi2_mipi_link_setting(sd, 0); 458 if (ret && !s_stream_ret) 459 s_stream_ret = ret; 460 461 pm_runtime_put_sync(csi2->dev); 462 } 463 464 return s_stream_ret; 465 466err_assert_rstb: 467 reset_control_assert(csi2->cmn_rstb); 468err_mipi_link_disable: 469 rzg2l_csi2_mipi_link_setting(sd, 0); 470err_pm_put: 471 pm_runtime_put_sync(csi2->dev); 472 return ret; 473} 474 475static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags) 476{ 477 return rzg2l_csi2_dphy_setting(sd, 1); 478} 479 480static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd) 481{ 482 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 483 484 /* 485 * In ideal case D-PHY will be disabled in s_stream(0) callback 486 * as mentioned in the HW manual. The below will only happen when 487 * pre_streamon succeeds and further down the line s_stream(1) 488 * fails so we need to undo things in post_streamoff. 489 */ 490 if (csi2->dphy_enabled) 491 return rzg2l_csi2_dphy_setting(sd, 0); 492 493 return 0; 494} 495 496static int rzg2l_csi2_set_format(struct v4l2_subdev *sd, 497 struct v4l2_subdev_state *state, 498 struct v4l2_subdev_format *fmt) 499{ 500 struct v4l2_mbus_framefmt *src_format; 501 struct v4l2_mbus_framefmt *sink_format; 502 503 src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SOURCE); 504 if (fmt->pad == RZG2L_CSI2_SOURCE) { 505 fmt->format = *src_format; 506 return 0; 507 } 508 509 sink_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SINK); 510 511 if (!rzg2l_csi2_code_to_fmt(fmt->format.code)) 512 sink_format->code = rzg2l_csi2_formats[0].code; 513 else 514 sink_format->code = fmt->format.code; 515 516 sink_format->field = V4L2_FIELD_NONE; 517 sink_format->colorspace = fmt->format.colorspace; 518 sink_format->xfer_func = fmt->format.xfer_func; 519 sink_format->ycbcr_enc = fmt->format.ycbcr_enc; 520 sink_format->quantization = fmt->format.quantization; 521 sink_format->width = clamp_t(u32, fmt->format.width, 522 RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH); 523 sink_format->height = clamp_t(u32, fmt->format.height, 524 RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT); 525 fmt->format = *sink_format; 526 527 /* propagate format to source pad */ 528 *src_format = *sink_format; 529 530 return 0; 531} 532 533static int rzg2l_csi2_init_config(struct v4l2_subdev *sd, 534 struct v4l2_subdev_state *sd_state) 535{ 536 struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, }; 537 538 fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH; 539 fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT; 540 fmt.format.field = V4L2_FIELD_NONE; 541 fmt.format.code = RZG2L_CSI2_DEFAULT_FMT; 542 fmt.format.colorspace = V4L2_COLORSPACE_SRGB; 543 fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 544 fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT; 545 fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT; 546 547 return rzg2l_csi2_set_format(sd, sd_state, &fmt); 548} 549 550static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd, 551 struct v4l2_subdev_state *sd_state, 552 struct v4l2_subdev_mbus_code_enum *code) 553{ 554 if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats)) 555 return -EINVAL; 556 557 code->code = rzg2l_csi2_formats[code->index].code; 558 559 return 0; 560} 561 562static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd, 563 struct v4l2_subdev_state *sd_state, 564 struct v4l2_subdev_frame_size_enum *fse) 565{ 566 if (fse->index != 0) 567 return -EINVAL; 568 569 fse->min_width = RZG2L_CSI2_MIN_WIDTH; 570 fse->min_height = RZG2L_CSI2_MIN_HEIGHT; 571 fse->max_width = RZG2L_CSI2_MAX_WIDTH; 572 fse->max_height = RZG2L_CSI2_MAX_HEIGHT; 573 574 return 0; 575} 576 577static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = { 578 .s_stream = rzg2l_csi2_s_stream, 579 .pre_streamon = rzg2l_csi2_pre_streamon, 580 .post_streamoff = rzg2l_csi2_post_streamoff, 581}; 582 583static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = { 584 .enum_mbus_code = rzg2l_csi2_enum_mbus_code, 585 .init_cfg = rzg2l_csi2_init_config, 586 .enum_frame_size = rzg2l_csi2_enum_frame_size, 587 .set_fmt = rzg2l_csi2_set_format, 588 .get_fmt = v4l2_subdev_get_fmt, 589}; 590 591static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = { 592 .video = &rzg2l_csi2_video_ops, 593 .pad = &rzg2l_csi2_pad_ops, 594}; 595 596/* ----------------------------------------------------------------------------- 597 * Async handling and registration of subdevices and links. 598 */ 599 600static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier, 601 struct v4l2_subdev *subdev, 602 struct v4l2_async_connection *asd) 603{ 604 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 605 606 csi2->remote_source = subdev; 607 608 dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name); 609 610 return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK, 611 &csi2->subdev.entity, 0, 612 MEDIA_LNK_FL_ENABLED | 613 MEDIA_LNK_FL_IMMUTABLE); 614} 615 616static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier, 617 struct v4l2_subdev *subdev, 618 struct v4l2_async_connection *asd) 619{ 620 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 621 622 csi2->remote_source = NULL; 623 624 dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name); 625} 626 627static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = { 628 .bound = rzg2l_csi2_notify_bound, 629 .unbind = rzg2l_csi2_notify_unbind, 630}; 631 632static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2, 633 struct v4l2_fwnode_endpoint *vep) 634{ 635 /* Only port 0 endpoint 0 is valid. */ 636 if (vep->base.port || vep->base.id) 637 return -ENOTCONN; 638 639 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes; 640 641 return 0; 642} 643 644static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2) 645{ 646 struct v4l2_fwnode_endpoint v4l2_ep = { 647 .bus_type = V4L2_MBUS_CSI2_DPHY 648 }; 649 struct v4l2_async_connection *asd; 650 struct fwnode_handle *fwnode; 651 struct fwnode_handle *ep; 652 int ret; 653 654 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0); 655 if (!ep) { 656 dev_err(csi2->dev, "Not connected to subdevice\n"); 657 return -EINVAL; 658 } 659 660 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 661 if (ret) { 662 dev_err(csi2->dev, "Could not parse v4l2 endpoint\n"); 663 fwnode_handle_put(ep); 664 return -EINVAL; 665 } 666 667 ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep); 668 if (ret) { 669 fwnode_handle_put(ep); 670 return ret; 671 } 672 673 fwnode = fwnode_graph_get_remote_endpoint(ep); 674 fwnode_handle_put(ep); 675 676 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev); 677 csi2->notifier.ops = &rzg2l_csi2_notify_ops; 678 679 asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode, 680 struct v4l2_async_connection); 681 fwnode_handle_put(fwnode); 682 if (IS_ERR(asd)) 683 return PTR_ERR(asd); 684 685 ret = v4l2_async_nf_register(&csi2->notifier); 686 if (ret) 687 v4l2_async_nf_cleanup(&csi2->notifier); 688 689 return ret; 690} 691 692static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2) 693{ 694 int lanes; 695 int ret; 696 697 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) { 698 dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n", 699 csi2->lanes); 700 return -EINVAL; 701 } 702 703 ret = pm_runtime_resume_and_get(csi2->dev); 704 if (ret) 705 return ret; 706 707 /* Checking the maximum lanes support for CSI-2 module */ 708 lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8; 709 if (lanes < csi2->lanes) { 710 dev_err(csi2->dev, 711 "Failed to support %d data lanes\n", csi2->lanes); 712 ret = -EINVAL; 713 } 714 715 pm_runtime_put_sync(csi2->dev); 716 717 return ret; 718} 719 720/* ----------------------------------------------------------------------------- 721 * Platform Device Driver. 722 */ 723 724static const struct media_entity_operations rzg2l_csi2_entity_ops = { 725 .link_validate = v4l2_subdev_link_validate, 726}; 727 728static int rzg2l_csi2_probe(struct platform_device *pdev) 729{ 730 struct rzg2l_csi2 *csi2; 731 struct clk *vclk; 732 int ret; 733 734 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL); 735 if (!csi2) 736 return -ENOMEM; 737 738 csi2->base = devm_platform_ioremap_resource(pdev, 0); 739 if (IS_ERR(csi2->base)) 740 return PTR_ERR(csi2->base); 741 742 csi2->cmn_rstb = devm_reset_control_get_exclusive(&pdev->dev, "cmn-rstb"); 743 if (IS_ERR(csi2->cmn_rstb)) 744 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->cmn_rstb), 745 "Failed to get cpg cmn-rstb\n"); 746 747 csi2->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn"); 748 if (IS_ERR(csi2->presetn)) 749 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->presetn), 750 "Failed to get cpg presetn\n"); 751 752 csi2->sysclk = devm_clk_get(&pdev->dev, "system"); 753 if (IS_ERR(csi2->sysclk)) 754 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->sysclk), 755 "Failed to get system clk\n"); 756 757 vclk = clk_get(&pdev->dev, "video"); 758 if (IS_ERR(vclk)) 759 return dev_err_probe(&pdev->dev, PTR_ERR(vclk), 760 "Failed to get video clock\n"); 761 csi2->vclk_rate = clk_get_rate(vclk); 762 clk_put(vclk); 763 764 csi2->dev = &pdev->dev; 765 766 platform_set_drvdata(pdev, csi2); 767 768 ret = rzg2l_csi2_parse_dt(csi2); 769 if (ret) 770 return ret; 771 772 pm_runtime_enable(&pdev->dev); 773 774 ret = rzg2l_validate_csi2_lanes(csi2); 775 if (ret) 776 goto error_pm; 777 778 csi2->subdev.dev = &pdev->dev; 779 v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops); 780 v4l2_set_subdevdata(&csi2->subdev, &pdev->dev); 781 snprintf(csi2->subdev.name, sizeof(csi2->subdev.name), 782 "csi-%s", dev_name(&pdev->dev)); 783 csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 784 785 csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 786 csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops; 787 788 csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 789 /* 790 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual 791 * channels should be implemented by streams API which is under 792 * development lets hardcode to VC0 for now. 793 */ 794 csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 795 ret = media_entity_pads_init(&csi2->subdev.entity, 2, csi2->pads); 796 if (ret) 797 goto error_pm; 798 799 ret = v4l2_subdev_init_finalize(&csi2->subdev); 800 if (ret < 0) 801 goto error_async; 802 803 ret = v4l2_async_register_subdev(&csi2->subdev); 804 if (ret < 0) 805 goto error_subdev; 806 807 return 0; 808 809error_subdev: 810 v4l2_subdev_cleanup(&csi2->subdev); 811error_async: 812 v4l2_async_nf_unregister(&csi2->notifier); 813 v4l2_async_nf_cleanup(&csi2->notifier); 814 media_entity_cleanup(&csi2->subdev.entity); 815error_pm: 816 pm_runtime_disable(&pdev->dev); 817 818 return ret; 819} 820 821static void rzg2l_csi2_remove(struct platform_device *pdev) 822{ 823 struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev); 824 825 v4l2_async_nf_unregister(&csi2->notifier); 826 v4l2_async_nf_cleanup(&csi2->notifier); 827 v4l2_async_unregister_subdev(&csi2->subdev); 828 v4l2_subdev_cleanup(&csi2->subdev); 829 media_entity_cleanup(&csi2->subdev.entity); 830 pm_runtime_disable(&pdev->dev); 831} 832 833static int __maybe_unused rzg2l_csi2_pm_runtime_suspend(struct device *dev) 834{ 835 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 836 837 reset_control_assert(csi2->presetn); 838 839 return 0; 840} 841 842static int __maybe_unused rzg2l_csi2_pm_runtime_resume(struct device *dev) 843{ 844 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 845 846 return reset_control_deassert(csi2->presetn); 847} 848 849static const struct dev_pm_ops rzg2l_csi2_pm_ops = { 850 SET_RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend, rzg2l_csi2_pm_runtime_resume, NULL) 851}; 852 853static const struct of_device_id rzg2l_csi2_of_table[] = { 854 { .compatible = "renesas,rzg2l-csi2", }, 855 { /* sentinel */ } 856}; 857 858static struct platform_driver rzg2l_csi2_pdrv = { 859 .remove_new = rzg2l_csi2_remove, 860 .probe = rzg2l_csi2_probe, 861 .driver = { 862 .name = "rzg2l-csi2", 863 .of_match_table = rzg2l_csi2_of_table, 864 .pm = &rzg2l_csi2_pm_ops, 865 }, 866}; 867 868module_platform_driver(rzg2l_csi2_pdrv); 869 870MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 871MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver"); 872MODULE_LICENSE("GPL"); 873