1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * R-Car Gen3 Digital Radio Interface (DRIF) driver 4 * 5 * Copyright (C) 2017 Renesas Electronics Corporation 6 */ 7 8/* 9 * The R-Car DRIF is a receive only MSIOF like controller with an 10 * external master device driving the SCK. It receives data into a FIFO, 11 * then this driver uses the SYS-DMAC engine to move the data from 12 * the device to memory. 13 * 14 * Each DRIF channel DRIFx (as per datasheet) contains two internal 15 * channels DRIFx0 & DRIFx1 within itself with each having its own resources 16 * like module clk, register set, irq and dma. These internal channels share 17 * common CLK & SYNC from master. The two data pins D0 & D1 shall be 18 * considered to represent the two internal channels. This internal split 19 * is not visible to the master device. 20 * 21 * Depending on the master device, a DRIF channel can use 22 * (1) both internal channels (D0 & D1) to receive data in parallel (or) 23 * (2) one internal channel (D0 or D1) to receive data 24 * 25 * The primary design goal of this controller is to act as a Digital Radio 26 * Interface that receives digital samples from a tuner device. Hence the 27 * driver exposes the device as a V4L2 SDR device. In order to qualify as 28 * a V4L2 SDR device, it should possess a tuner interface as mandated by the 29 * framework. This driver expects a tuner driver (sub-device) to bind 30 * asynchronously with this device and the combined drivers shall expose 31 * a V4L2 compliant SDR device. The DRIF driver is independent of the 32 * tuner vendor. 33 * 34 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode. 35 * This driver is tested for I2S mode only because of the availability of 36 * suitable master devices. Hence, not all configurable options of DRIF h/w 37 * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults 38 * are used. These can be exposed later if needed after testing. 39 */ 40#include <linux/bitops.h> 41#include <linux/clk.h> 42#include <linux/dma-mapping.h> 43#include <linux/dmaengine.h> 44#include <linux/ioctl.h> 45#include <linux/iopoll.h> 46#include <linux/module.h> 47#include <linux/of.h> 48#include <linux/of_graph.h> 49#include <linux/of_platform.h> 50#include <linux/platform_device.h> 51#include <linux/sched.h> 52#include <media/v4l2-async.h> 53#include <media/v4l2-ctrls.h> 54#include <media/v4l2-device.h> 55#include <media/v4l2-event.h> 56#include <media/v4l2-fh.h> 57#include <media/v4l2-ioctl.h> 58#include <media/videobuf2-v4l2.h> 59#include <media/videobuf2-vmalloc.h> 60 61/* DRIF register offsets */ 62#define RCAR_DRIF_SITMDR1 0x00 63#define RCAR_DRIF_SITMDR2 0x04 64#define RCAR_DRIF_SITMDR3 0x08 65#define RCAR_DRIF_SIRMDR1 0x10 66#define RCAR_DRIF_SIRMDR2 0x14 67#define RCAR_DRIF_SIRMDR3 0x18 68#define RCAR_DRIF_SICTR 0x28 69#define RCAR_DRIF_SIFCTR 0x30 70#define RCAR_DRIF_SISTR 0x40 71#define RCAR_DRIF_SIIER 0x44 72#define RCAR_DRIF_SIRFDR 0x60 73 74#define RCAR_DRIF_RFOVF BIT(3) /* Receive FIFO overflow */ 75#define RCAR_DRIF_RFUDF BIT(4) /* Receive FIFO underflow */ 76#define RCAR_DRIF_RFSERR BIT(5) /* Receive frame sync error */ 77#define RCAR_DRIF_REOF BIT(7) /* Frame reception end */ 78#define RCAR_DRIF_RDREQ BIT(12) /* Receive data xfer req */ 79#define RCAR_DRIF_RFFUL BIT(13) /* Receive FIFO full */ 80 81/* SIRMDR1 */ 82#define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME (0 << 28) 83#define RCAR_DRIF_SIRMDR1_SYNCMD_LR (3 << 28) 84 85#define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH (0 << 25) 86#define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW (1 << 25) 87 88#define RCAR_DRIF_SIRMDR1_MSB_FIRST (0 << 24) 89#define RCAR_DRIF_SIRMDR1_LSB_FIRST (1 << 24) 90 91#define RCAR_DRIF_SIRMDR1_DTDL_0 (0 << 20) 92#define RCAR_DRIF_SIRMDR1_DTDL_1 (1 << 20) 93#define RCAR_DRIF_SIRMDR1_DTDL_2 (2 << 20) 94#define RCAR_DRIF_SIRMDR1_DTDL_0PT5 (5 << 20) 95#define RCAR_DRIF_SIRMDR1_DTDL_1PT5 (6 << 20) 96 97#define RCAR_DRIF_SIRMDR1_SYNCDL_0 (0 << 20) 98#define RCAR_DRIF_SIRMDR1_SYNCDL_1 (1 << 20) 99#define RCAR_DRIF_SIRMDR1_SYNCDL_2 (2 << 20) 100#define RCAR_DRIF_SIRMDR1_SYNCDL_3 (3 << 20) 101#define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5 (5 << 20) 102#define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5 (6 << 20) 103 104#define RCAR_DRIF_MDR_GRPCNT(n) (((n) - 1) << 30) 105#define RCAR_DRIF_MDR_BITLEN(n) (((n) - 1) << 24) 106#define RCAR_DRIF_MDR_WDCNT(n) (((n) - 1) << 16) 107 108/* Hidden Transmit register that controls CLK & SYNC */ 109#define RCAR_DRIF_SITMDR1_PCON BIT(30) 110 111#define RCAR_DRIF_SICTR_RX_RISING_EDGE BIT(26) 112#define RCAR_DRIF_SICTR_RX_EN BIT(8) 113#define RCAR_DRIF_SICTR_RESET BIT(0) 114 115/* Constants */ 116#define RCAR_DRIF_NUM_HWBUFS 32 117#define RCAR_DRIF_MAX_DEVS 4 118#define RCAR_DRIF_DEFAULT_NUM_HWBUFS 16 119#define RCAR_DRIF_DEFAULT_HWBUF_SIZE (4 * PAGE_SIZE) 120#define RCAR_DRIF_MAX_CHANNEL 2 121#define RCAR_SDR_BUFFER_SIZE SZ_64K 122 123/* Internal buffer status flags */ 124#define RCAR_DRIF_BUF_DONE BIT(0) /* DMA completed */ 125#define RCAR_DRIF_BUF_OVERFLOW BIT(1) /* Overflow detected */ 126 127#define to_rcar_drif_buf_pair(sdr, ch_num, idx) \ 128 (&((sdr)->ch[!(ch_num)]->buf[(idx)])) 129 130#define for_each_rcar_drif_channel(ch, ch_mask) \ 131 for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL) 132 133/* Debug */ 134#define rdrif_dbg(sdr, fmt, arg...) \ 135 dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg) 136 137#define rdrif_err(sdr, fmt, arg...) \ 138 dev_err(sdr->v4l2_dev.dev, fmt, ## arg) 139 140/* Stream formats */ 141struct rcar_drif_format { 142 u32 pixelformat; 143 u32 buffersize; 144 u32 bitlen; 145 u32 wdcnt; 146 u32 num_ch; 147}; 148 149/* Format descriptions for capture */ 150static const struct rcar_drif_format formats[] = { 151 { 152 .pixelformat = V4L2_SDR_FMT_PCU16BE, 153 .buffersize = RCAR_SDR_BUFFER_SIZE, 154 .bitlen = 16, 155 .wdcnt = 1, 156 .num_ch = 2, 157 }, 158 { 159 .pixelformat = V4L2_SDR_FMT_PCU18BE, 160 .buffersize = RCAR_SDR_BUFFER_SIZE, 161 .bitlen = 18, 162 .wdcnt = 1, 163 .num_ch = 2, 164 }, 165 { 166 .pixelformat = V4L2_SDR_FMT_PCU20BE, 167 .buffersize = RCAR_SDR_BUFFER_SIZE, 168 .bitlen = 20, 169 .wdcnt = 1, 170 .num_ch = 2, 171 }, 172}; 173 174/* Buffer for a received frame from one or both internal channels */ 175struct rcar_drif_frame_buf { 176 /* Common v4l buffer stuff -- must be first */ 177 struct vb2_v4l2_buffer vb; 178 struct list_head list; 179}; 180 181/* OF graph endpoint's V4L2 async data */ 182struct rcar_drif_graph_ep { 183 struct v4l2_subdev *subdev; /* Async matched subdev */ 184}; 185 186/* DMA buffer */ 187struct rcar_drif_hwbuf { 188 void *addr; /* CPU-side address */ 189 unsigned int status; /* Buffer status flags */ 190}; 191 192/* Internal channel */ 193struct rcar_drif { 194 struct rcar_drif_sdr *sdr; /* Group device */ 195 struct platform_device *pdev; /* Channel's pdev */ 196 void __iomem *base; /* Base register address */ 197 resource_size_t start; /* I/O resource offset */ 198 struct dma_chan *dmach; /* Reserved DMA channel */ 199 struct clk *clk; /* Module clock */ 200 struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */ 201 dma_addr_t dma_handle; /* Handle for all bufs */ 202 unsigned int num; /* Channel number */ 203 bool acting_sdr; /* Channel acting as SDR device */ 204}; 205 206/* DRIF V4L2 SDR */ 207struct rcar_drif_sdr { 208 struct device *dev; /* Platform device */ 209 struct video_device *vdev; /* V4L2 SDR device */ 210 struct v4l2_device v4l2_dev; /* V4L2 device */ 211 212 /* Videobuf2 queue and queued buffers list */ 213 struct vb2_queue vb_queue; 214 struct list_head queued_bufs; 215 spinlock_t queued_bufs_lock; /* Protects queued_bufs */ 216 spinlock_t dma_lock; /* To serialize DMA cb of channels */ 217 218 struct mutex v4l2_mutex; /* To serialize ioctls */ 219 struct mutex vb_queue_mutex; /* To serialize streaming ioctls */ 220 struct v4l2_ctrl_handler ctrl_hdl; /* SDR control handler */ 221 struct v4l2_async_notifier notifier; /* For subdev (tuner) */ 222 struct rcar_drif_graph_ep ep; /* Endpoint V4L2 async data */ 223 224 /* Current V4L2 SDR format ptr */ 225 const struct rcar_drif_format *fmt; 226 227 /* Device tree SYNC properties */ 228 u32 mdr1; 229 230 /* Internals */ 231 struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */ 232 unsigned long hw_ch_mask; /* Enabled channels per DT */ 233 unsigned long cur_ch_mask; /* Used channels for an SDR FMT */ 234 u32 num_hw_ch; /* Num of DT enabled channels */ 235 u32 num_cur_ch; /* Num of used channels */ 236 u32 hwbuf_size; /* Each DMA buffer size */ 237 u32 produced; /* Buffers produced by sdr dev */ 238}; 239 240/* Register access functions */ 241static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data) 242{ 243 writel(data, ch->base + offset); 244} 245 246static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset) 247{ 248 return readl(ch->base + offset); 249} 250 251/* Release DMA channels */ 252static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr) 253{ 254 unsigned int i; 255 256 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) 257 if (sdr->ch[i]->dmach) { 258 dma_release_channel(sdr->ch[i]->dmach); 259 sdr->ch[i]->dmach = NULL; 260 } 261} 262 263/* Allocate DMA channels */ 264static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr) 265{ 266 struct dma_slave_config dma_cfg; 267 unsigned int i; 268 int ret; 269 270 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 271 struct rcar_drif *ch = sdr->ch[i]; 272 273 ch->dmach = dma_request_chan(&ch->pdev->dev, "rx"); 274 if (IS_ERR(ch->dmach)) { 275 ret = PTR_ERR(ch->dmach); 276 if (ret != -EPROBE_DEFER) 277 rdrif_err(sdr, 278 "ch%u: dma channel req failed: %pe\n", 279 i, ch->dmach); 280 ch->dmach = NULL; 281 goto dmach_error; 282 } 283 284 /* Configure slave */ 285 memset(&dma_cfg, 0, sizeof(dma_cfg)); 286 dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR); 287 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 288 ret = dmaengine_slave_config(ch->dmach, &dma_cfg); 289 if (ret) { 290 rdrif_err(sdr, "ch%u: dma slave config failed\n", i); 291 goto dmach_error; 292 } 293 } 294 return 0; 295 296dmach_error: 297 rcar_drif_release_dmachannels(sdr); 298 return ret; 299} 300 301/* Release queued vb2 buffers */ 302static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr, 303 enum vb2_buffer_state state) 304{ 305 struct rcar_drif_frame_buf *fbuf, *tmp; 306 unsigned long flags; 307 308 spin_lock_irqsave(&sdr->queued_bufs_lock, flags); 309 list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) { 310 list_del(&fbuf->list); 311 vb2_buffer_done(&fbuf->vb.vb2_buf, state); 312 } 313 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags); 314} 315 316/* Set MDR defaults */ 317static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr) 318{ 319 unsigned int i; 320 321 /* Set defaults for enabled internal channels */ 322 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 323 /* Refer MSIOF section in manual for this register setting */ 324 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1, 325 RCAR_DRIF_SITMDR1_PCON); 326 327 /* Setup MDR1 value */ 328 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1); 329 330 rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x", 331 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1)); 332 } 333} 334 335/* Set DRIF receive format */ 336static int rcar_drif_set_format(struct rcar_drif_sdr *sdr) 337{ 338 unsigned int i; 339 340 rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n", 341 sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch); 342 343 /* Sanity check */ 344 if (sdr->fmt->num_ch > sdr->num_cur_ch) { 345 rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n", 346 sdr->fmt->num_ch, sdr->num_cur_ch); 347 return -EINVAL; 348 } 349 350 /* Setup group, bitlen & wdcnt */ 351 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 352 u32 mdr; 353 354 /* Two groups */ 355 mdr = RCAR_DRIF_MDR_GRPCNT(2) | 356 RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) | 357 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt); 358 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr); 359 360 mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) | 361 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt); 362 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr); 363 364 rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n", 365 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2), 366 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3)); 367 } 368 return 0; 369} 370 371/* Release DMA buffers */ 372static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr) 373{ 374 unsigned int i; 375 376 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 377 struct rcar_drif *ch = sdr->ch[i]; 378 379 /* First entry contains the dma buf ptr */ 380 if (ch->buf[0].addr) { 381 dma_free_coherent(&ch->pdev->dev, 382 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS, 383 ch->buf[0].addr, ch->dma_handle); 384 ch->buf[0].addr = NULL; 385 } 386 } 387} 388 389/* Request DMA buffers */ 390static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr) 391{ 392 int ret = -ENOMEM; 393 unsigned int i, j; 394 void *addr; 395 396 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 397 struct rcar_drif *ch = sdr->ch[i]; 398 399 /* Allocate DMA buffers */ 400 addr = dma_alloc_coherent(&ch->pdev->dev, 401 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS, 402 &ch->dma_handle, GFP_KERNEL); 403 if (!addr) { 404 rdrif_err(sdr, 405 "ch%u: dma alloc failed. num hwbufs %u size %u\n", 406 i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size); 407 goto error; 408 } 409 410 /* Split the chunk and populate bufctxt */ 411 for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) { 412 ch->buf[j].addr = addr + (j * sdr->hwbuf_size); 413 ch->buf[j].status = 0; 414 } 415 } 416 return 0; 417error: 418 return ret; 419} 420 421/* Setup vb_queue minimum buffer requirements */ 422static int rcar_drif_queue_setup(struct vb2_queue *vq, 423 unsigned int *num_buffers, unsigned int *num_planes, 424 unsigned int sizes[], struct device *alloc_devs[]) 425{ 426 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq); 427 428 /* Need at least 16 buffers */ 429 if (vq->num_buffers + *num_buffers < 16) 430 *num_buffers = 16 - vq->num_buffers; 431 432 *num_planes = 1; 433 sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize); 434 rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]); 435 436 return 0; 437} 438 439/* Enqueue buffer */ 440static void rcar_drif_buf_queue(struct vb2_buffer *vb) 441{ 442 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 443 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue); 444 struct rcar_drif_frame_buf *fbuf = 445 container_of(vbuf, struct rcar_drif_frame_buf, vb); 446 unsigned long flags; 447 448 rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index); 449 spin_lock_irqsave(&sdr->queued_bufs_lock, flags); 450 list_add_tail(&fbuf->list, &sdr->queued_bufs); 451 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags); 452} 453 454/* Get a frame buf from list */ 455static struct rcar_drif_frame_buf * 456rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr) 457{ 458 struct rcar_drif_frame_buf *fbuf; 459 unsigned long flags; 460 461 spin_lock_irqsave(&sdr->queued_bufs_lock, flags); 462 fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct 463 rcar_drif_frame_buf, list); 464 if (!fbuf) { 465 /* 466 * App is late in enqueing buffers. Samples lost & there will 467 * be a gap in sequence number when app recovers 468 */ 469 rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced); 470 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags); 471 return NULL; 472 } 473 list_del(&fbuf->list); 474 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags); 475 476 return fbuf; 477} 478 479/* Helpers to set/clear buf pair status */ 480static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf) 481{ 482 return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE); 483} 484 485static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf) 486{ 487 return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW); 488} 489 490static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf, 491 unsigned int bit) 492{ 493 unsigned int i; 494 495 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++) 496 buf[i]->status &= ~bit; 497} 498 499/* Channel DMA complete */ 500static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx) 501{ 502 u32 str; 503 504 ch->buf[idx].status |= RCAR_DRIF_BUF_DONE; 505 506 /* Check for DRIF errors */ 507 str = rcar_drif_read(ch, RCAR_DRIF_SISTR); 508 if (unlikely(str & RCAR_DRIF_RFOVF)) { 509 /* Writing the same clears it */ 510 rcar_drif_write(ch, RCAR_DRIF_SISTR, str); 511 512 /* Overflow: some samples are lost */ 513 ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW; 514 } 515} 516 517/* DMA callback for each stage */ 518static void rcar_drif_dma_complete(void *dma_async_param) 519{ 520 struct rcar_drif *ch = dma_async_param; 521 struct rcar_drif_sdr *sdr = ch->sdr; 522 struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL]; 523 struct rcar_drif_frame_buf *fbuf; 524 bool overflow = false; 525 u32 idx, produced; 526 unsigned int i; 527 528 spin_lock(&sdr->dma_lock); 529 530 /* DMA can be terminated while the callback was waiting on lock */ 531 if (!vb2_is_streaming(&sdr->vb_queue)) { 532 spin_unlock(&sdr->dma_lock); 533 return; 534 } 535 536 idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS; 537 rcar_drif_channel_complete(ch, idx); 538 539 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) { 540 buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) : 541 &ch->buf[idx]; 542 buf[1] = ch->num ? &ch->buf[idx] : 543 to_rcar_drif_buf_pair(sdr, ch->num, idx); 544 545 /* Check if both DMA buffers are done */ 546 if (!rcar_drif_bufs_done(buf)) { 547 spin_unlock(&sdr->dma_lock); 548 return; 549 } 550 551 /* Clear buf done status */ 552 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE); 553 554 if (rcar_drif_bufs_overflow(buf)) { 555 overflow = true; 556 /* Clear the flag in status */ 557 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW); 558 } 559 } else { 560 buf[0] = &ch->buf[idx]; 561 if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) { 562 overflow = true; 563 /* Clear the flag in status */ 564 buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW; 565 } 566 } 567 568 /* Buffer produced for consumption */ 569 produced = sdr->produced++; 570 spin_unlock(&sdr->dma_lock); 571 572 rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced); 573 574 /* Get fbuf */ 575 fbuf = rcar_drif_get_fbuf(sdr); 576 if (!fbuf) 577 return; 578 579 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++) 580 memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) + 581 i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size); 582 583 fbuf->vb.field = V4L2_FIELD_NONE; 584 fbuf->vb.sequence = produced; 585 fbuf->vb.vb2_buf.timestamp = ktime_get_ns(); 586 vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize); 587 588 /* Set error state on overflow */ 589 vb2_buffer_done(&fbuf->vb.vb2_buf, 590 overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 591} 592 593static int rcar_drif_qbuf(struct rcar_drif *ch) 594{ 595 struct rcar_drif_sdr *sdr = ch->sdr; 596 dma_addr_t addr = ch->dma_handle; 597 struct dma_async_tx_descriptor *rxd; 598 dma_cookie_t cookie; 599 int ret = -EIO; 600 601 /* Setup cyclic DMA with given buffers */ 602 rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr, 603 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS, 604 sdr->hwbuf_size, DMA_DEV_TO_MEM, 605 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 606 if (!rxd) { 607 rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num); 608 return ret; 609 } 610 611 /* Submit descriptor */ 612 rxd->callback = rcar_drif_dma_complete; 613 rxd->callback_param = ch; 614 cookie = dmaengine_submit(rxd); 615 if (dma_submit_error(cookie)) { 616 rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num); 617 return ret; 618 } 619 620 dma_async_issue_pending(ch->dmach); 621 return 0; 622} 623 624/* Enable reception */ 625static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr) 626{ 627 unsigned int i; 628 u32 ctr; 629 int ret = -EINVAL; 630 631 /* 632 * When both internal channels are enabled, they can be synchronized 633 * only by the master 634 */ 635 636 /* Enable receive */ 637 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 638 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR); 639 ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE | 640 RCAR_DRIF_SICTR_RX_EN); 641 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr); 642 } 643 644 /* Check receive enabled */ 645 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 646 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR, 647 ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000); 648 if (ret) { 649 rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i, 650 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR)); 651 break; 652 } 653 } 654 return ret; 655} 656 657/* Disable reception */ 658static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr) 659{ 660 unsigned int i; 661 u32 ctr; 662 int ret; 663 664 /* Disable receive */ 665 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 666 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR); 667 ctr &= ~RCAR_DRIF_SICTR_RX_EN; 668 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr); 669 } 670 671 /* Check receive disabled */ 672 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 673 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR, 674 ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000); 675 if (ret) 676 dev_warn(&sdr->vdev->dev, 677 "ch%u: failed to disable rx. ctr 0x%08x\n", 678 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR)); 679 } 680} 681 682/* Stop channel */ 683static void rcar_drif_stop_channel(struct rcar_drif *ch) 684{ 685 /* Disable DMA receive interrupt */ 686 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000); 687 688 /* Terminate all DMA transfers */ 689 dmaengine_terminate_sync(ch->dmach); 690} 691 692/* Stop receive operation */ 693static void rcar_drif_stop(struct rcar_drif_sdr *sdr) 694{ 695 unsigned int i; 696 697 /* Disable Rx */ 698 rcar_drif_disable_rx(sdr); 699 700 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) 701 rcar_drif_stop_channel(sdr->ch[i]); 702} 703 704/* Start channel */ 705static int rcar_drif_start_channel(struct rcar_drif *ch) 706{ 707 struct rcar_drif_sdr *sdr = ch->sdr; 708 u32 ctr, str; 709 int ret; 710 711 /* Reset receive */ 712 rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET); 713 ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr, 714 !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000); 715 if (ret) { 716 rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n", 717 ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR)); 718 return ret; 719 } 720 721 /* Queue buffers for DMA */ 722 ret = rcar_drif_qbuf(ch); 723 if (ret) 724 return ret; 725 726 /* Clear status register flags */ 727 str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR | 728 RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF; 729 rcar_drif_write(ch, RCAR_DRIF_SISTR, str); 730 731 /* Enable DMA receive interrupt */ 732 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000); 733 734 return ret; 735} 736 737/* Start receive operation */ 738static int rcar_drif_start(struct rcar_drif_sdr *sdr) 739{ 740 unsigned long enabled = 0; 741 unsigned int i; 742 int ret; 743 744 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 745 ret = rcar_drif_start_channel(sdr->ch[i]); 746 if (ret) 747 goto start_error; 748 enabled |= BIT(i); 749 } 750 751 ret = rcar_drif_enable_rx(sdr); 752 if (ret) 753 goto enable_error; 754 755 sdr->produced = 0; 756 return ret; 757 758enable_error: 759 rcar_drif_disable_rx(sdr); 760start_error: 761 for_each_rcar_drif_channel(i, &enabled) 762 rcar_drif_stop_channel(sdr->ch[i]); 763 764 return ret; 765} 766 767/* Start streaming */ 768static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count) 769{ 770 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq); 771 unsigned long enabled = 0; 772 unsigned int i; 773 int ret; 774 775 mutex_lock(&sdr->v4l2_mutex); 776 777 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) { 778 ret = clk_prepare_enable(sdr->ch[i]->clk); 779 if (ret) 780 goto error; 781 enabled |= BIT(i); 782 } 783 784 /* Set default MDRx settings */ 785 rcar_drif_set_mdr1(sdr); 786 787 /* Set new format */ 788 ret = rcar_drif_set_format(sdr); 789 if (ret) 790 goto error; 791 792 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) 793 sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL; 794 else 795 sdr->hwbuf_size = sdr->fmt->buffersize; 796 797 rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n", 798 RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size); 799 800 /* Alloc DMA channel */ 801 ret = rcar_drif_alloc_dmachannels(sdr); 802 if (ret) 803 goto error; 804 805 /* Request buffers */ 806 ret = rcar_drif_request_buf(sdr); 807 if (ret) 808 goto error; 809 810 /* Start Rx */ 811 ret = rcar_drif_start(sdr); 812 if (ret) 813 goto error; 814 815 mutex_unlock(&sdr->v4l2_mutex); 816 817 return ret; 818 819error: 820 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED); 821 rcar_drif_release_buf(sdr); 822 rcar_drif_release_dmachannels(sdr); 823 for_each_rcar_drif_channel(i, &enabled) 824 clk_disable_unprepare(sdr->ch[i]->clk); 825 826 mutex_unlock(&sdr->v4l2_mutex); 827 828 return ret; 829} 830 831/* Stop streaming */ 832static void rcar_drif_stop_streaming(struct vb2_queue *vq) 833{ 834 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq); 835 unsigned int i; 836 837 mutex_lock(&sdr->v4l2_mutex); 838 839 /* Stop hardware streaming */ 840 rcar_drif_stop(sdr); 841 842 /* Return all queued buffers to vb2 */ 843 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR); 844 845 /* Release buf */ 846 rcar_drif_release_buf(sdr); 847 848 /* Release DMA channel resources */ 849 rcar_drif_release_dmachannels(sdr); 850 851 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) 852 clk_disable_unprepare(sdr->ch[i]->clk); 853 854 mutex_unlock(&sdr->v4l2_mutex); 855} 856 857/* Vb2 ops */ 858static const struct vb2_ops rcar_drif_vb2_ops = { 859 .queue_setup = rcar_drif_queue_setup, 860 .buf_queue = rcar_drif_buf_queue, 861 .start_streaming = rcar_drif_start_streaming, 862 .stop_streaming = rcar_drif_stop_streaming, 863 .wait_prepare = vb2_ops_wait_prepare, 864 .wait_finish = vb2_ops_wait_finish, 865}; 866 867static int rcar_drif_querycap(struct file *file, void *fh, 868 struct v4l2_capability *cap) 869{ 870 struct rcar_drif_sdr *sdr = video_drvdata(file); 871 872 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 873 strscpy(cap->card, sdr->vdev->name, sizeof(cap->card)); 874 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 875 sdr->vdev->name); 876 877 return 0; 878} 879 880static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr) 881{ 882 unsigned int i; 883 884 for (i = 0; i < ARRAY_SIZE(formats); i++) { 885 /* Matching fmt based on required channels is set as default */ 886 if (sdr->num_hw_ch == formats[i].num_ch) { 887 sdr->fmt = &formats[i]; 888 sdr->cur_ch_mask = sdr->hw_ch_mask; 889 sdr->num_cur_ch = sdr->num_hw_ch; 890 dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n", 891 i, sdr->cur_ch_mask, sdr->num_cur_ch); 892 return 0; 893 } 894 } 895 return -EINVAL; 896} 897 898static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv, 899 struct v4l2_fmtdesc *f) 900{ 901 if (f->index >= ARRAY_SIZE(formats)) 902 return -EINVAL; 903 904 f->pixelformat = formats[f->index].pixelformat; 905 906 return 0; 907} 908 909static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv, 910 struct v4l2_format *f) 911{ 912 struct rcar_drif_sdr *sdr = video_drvdata(file); 913 914 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat; 915 f->fmt.sdr.buffersize = sdr->fmt->buffersize; 916 917 return 0; 918} 919 920static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv, 921 struct v4l2_format *f) 922{ 923 struct rcar_drif_sdr *sdr = video_drvdata(file); 924 struct vb2_queue *q = &sdr->vb_queue; 925 unsigned int i; 926 927 if (vb2_is_busy(q)) 928 return -EBUSY; 929 930 for (i = 0; i < ARRAY_SIZE(formats); i++) { 931 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) 932 break; 933 } 934 935 if (i == ARRAY_SIZE(formats)) 936 i = 0; /* Set the 1st format as default on no match */ 937 938 sdr->fmt = &formats[i]; 939 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat; 940 f->fmt.sdr.buffersize = formats[i].buffersize; 941 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); 942 943 /* 944 * If a format demands one channel only out of two 945 * enabled channels, pick the 0th channel. 946 */ 947 if (formats[i].num_ch < sdr->num_hw_ch) { 948 sdr->cur_ch_mask = BIT(0); 949 sdr->num_cur_ch = formats[i].num_ch; 950 } else { 951 sdr->cur_ch_mask = sdr->hw_ch_mask; 952 sdr->num_cur_ch = sdr->num_hw_ch; 953 } 954 955 rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n", 956 i, sdr->cur_ch_mask, sdr->num_cur_ch); 957 958 return 0; 959} 960 961static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv, 962 struct v4l2_format *f) 963{ 964 unsigned int i; 965 966 for (i = 0; i < ARRAY_SIZE(formats); i++) { 967 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { 968 f->fmt.sdr.buffersize = formats[i].buffersize; 969 return 0; 970 } 971 } 972 973 f->fmt.sdr.pixelformat = formats[0].pixelformat; 974 f->fmt.sdr.buffersize = formats[0].buffersize; 975 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved)); 976 977 return 0; 978} 979 980/* Tuner subdev ioctls */ 981static int rcar_drif_enum_freq_bands(struct file *file, void *priv, 982 struct v4l2_frequency_band *band) 983{ 984 struct rcar_drif_sdr *sdr = video_drvdata(file); 985 986 return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band); 987} 988 989static int rcar_drif_g_frequency(struct file *file, void *priv, 990 struct v4l2_frequency *f) 991{ 992 struct rcar_drif_sdr *sdr = video_drvdata(file); 993 994 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f); 995} 996 997static int rcar_drif_s_frequency(struct file *file, void *priv, 998 const struct v4l2_frequency *f) 999{ 1000 struct rcar_drif_sdr *sdr = video_drvdata(file); 1001 1002 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f); 1003} 1004 1005static int rcar_drif_g_tuner(struct file *file, void *priv, 1006 struct v4l2_tuner *vt) 1007{ 1008 struct rcar_drif_sdr *sdr = video_drvdata(file); 1009 1010 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt); 1011} 1012 1013static int rcar_drif_s_tuner(struct file *file, void *priv, 1014 const struct v4l2_tuner *vt) 1015{ 1016 struct rcar_drif_sdr *sdr = video_drvdata(file); 1017 1018 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt); 1019} 1020 1021static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = { 1022 .vidioc_querycap = rcar_drif_querycap, 1023 1024 .vidioc_enum_fmt_sdr_cap = rcar_drif_enum_fmt_sdr_cap, 1025 .vidioc_g_fmt_sdr_cap = rcar_drif_g_fmt_sdr_cap, 1026 .vidioc_s_fmt_sdr_cap = rcar_drif_s_fmt_sdr_cap, 1027 .vidioc_try_fmt_sdr_cap = rcar_drif_try_fmt_sdr_cap, 1028 1029 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1030 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1031 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1032 .vidioc_querybuf = vb2_ioctl_querybuf, 1033 .vidioc_qbuf = vb2_ioctl_qbuf, 1034 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1035 1036 .vidioc_streamon = vb2_ioctl_streamon, 1037 .vidioc_streamoff = vb2_ioctl_streamoff, 1038 1039 .vidioc_s_frequency = rcar_drif_s_frequency, 1040 .vidioc_g_frequency = rcar_drif_g_frequency, 1041 .vidioc_s_tuner = rcar_drif_s_tuner, 1042 .vidioc_g_tuner = rcar_drif_g_tuner, 1043 .vidioc_enum_freq_bands = rcar_drif_enum_freq_bands, 1044 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1045 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1046 .vidioc_log_status = v4l2_ctrl_log_status, 1047}; 1048 1049static const struct v4l2_file_operations rcar_drif_fops = { 1050 .owner = THIS_MODULE, 1051 .open = v4l2_fh_open, 1052 .release = vb2_fop_release, 1053 .read = vb2_fop_read, 1054 .poll = vb2_fop_poll, 1055 .mmap = vb2_fop_mmap, 1056 .unlocked_ioctl = video_ioctl2, 1057}; 1058 1059static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr) 1060{ 1061 int ret; 1062 1063 /* Init video_device structure */ 1064 sdr->vdev = video_device_alloc(); 1065 if (!sdr->vdev) 1066 return -ENOMEM; 1067 1068 snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF"); 1069 sdr->vdev->fops = &rcar_drif_fops; 1070 sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops; 1071 sdr->vdev->release = video_device_release; 1072 sdr->vdev->lock = &sdr->v4l2_mutex; 1073 sdr->vdev->queue = &sdr->vb_queue; 1074 sdr->vdev->queue->lock = &sdr->vb_queue_mutex; 1075 sdr->vdev->ctrl_handler = &sdr->ctrl_hdl; 1076 sdr->vdev->v4l2_dev = &sdr->v4l2_dev; 1077 sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER | 1078 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; 1079 video_set_drvdata(sdr->vdev, sdr); 1080 1081 /* Register V4L2 SDR device */ 1082 ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1); 1083 if (ret) { 1084 video_device_release(sdr->vdev); 1085 sdr->vdev = NULL; 1086 dev_err(sdr->dev, "failed video_register_device (%d)\n", ret); 1087 } 1088 1089 return ret; 1090} 1091 1092static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr) 1093{ 1094 video_unregister_device(sdr->vdev); 1095 sdr->vdev = NULL; 1096} 1097 1098/* Sub-device bound callback */ 1099static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier, 1100 struct v4l2_subdev *subdev, 1101 struct v4l2_async_connection *asd) 1102{ 1103 struct rcar_drif_sdr *sdr = 1104 container_of(notifier, struct rcar_drif_sdr, notifier); 1105 1106 v4l2_set_subdev_hostdata(subdev, sdr); 1107 sdr->ep.subdev = subdev; 1108 rdrif_dbg(sdr, "bound asd %s\n", subdev->name); 1109 1110 return 0; 1111} 1112 1113/* Sub-device unbind callback */ 1114static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier, 1115 struct v4l2_subdev *subdev, 1116 struct v4l2_async_connection *asd) 1117{ 1118 struct rcar_drif_sdr *sdr = 1119 container_of(notifier, struct rcar_drif_sdr, notifier); 1120 1121 if (sdr->ep.subdev != subdev) { 1122 rdrif_err(sdr, "subdev %s is not bound\n", subdev->name); 1123 return; 1124 } 1125 1126 /* Free ctrl handler if initialized */ 1127 v4l2_ctrl_handler_free(&sdr->ctrl_hdl); 1128 sdr->v4l2_dev.ctrl_handler = NULL; 1129 sdr->ep.subdev = NULL; 1130 1131 rcar_drif_sdr_unregister(sdr); 1132 rdrif_dbg(sdr, "unbind asd %s\n", subdev->name); 1133} 1134 1135/* Sub-device registered notification callback */ 1136static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier) 1137{ 1138 struct rcar_drif_sdr *sdr = 1139 container_of(notifier, struct rcar_drif_sdr, notifier); 1140 int ret; 1141 1142 /* 1143 * The subdev tested at this point uses 4 controls. Using 10 as a worst 1144 * case scenario hint. When less controls are needed there will be some 1145 * unused memory and when more controls are needed the framework uses 1146 * hash to manage controls within this number. 1147 */ 1148 ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10); 1149 if (ret) 1150 return -ENOMEM; 1151 1152 sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl; 1153 ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev); 1154 if (ret) { 1155 rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret); 1156 goto error; 1157 } 1158 1159 ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl, 1160 sdr->ep.subdev->ctrl_handler, NULL, true); 1161 if (ret) { 1162 rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret); 1163 goto error; 1164 } 1165 1166 ret = rcar_drif_sdr_register(sdr); 1167 if (ret) 1168 goto error; 1169 1170 return ret; 1171 1172error: 1173 v4l2_ctrl_handler_free(&sdr->ctrl_hdl); 1174 1175 return ret; 1176} 1177 1178static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = { 1179 .bound = rcar_drif_notify_bound, 1180 .unbind = rcar_drif_notify_unbind, 1181 .complete = rcar_drif_notify_complete, 1182}; 1183 1184/* Read endpoint properties */ 1185static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr, 1186 struct fwnode_handle *fwnode) 1187{ 1188 u32 val; 1189 1190 /* Set the I2S defaults for SIRMDR1*/ 1191 sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST | 1192 RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0; 1193 1194 /* Parse sync polarity from endpoint */ 1195 if (!fwnode_property_read_u32(fwnode, "sync-active", &val)) 1196 sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH : 1197 RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW; 1198 else 1199 sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */ 1200 1201 dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1); 1202} 1203 1204/* Parse sub-devs (tuner) to find a matching device */ 1205static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr) 1206{ 1207 struct v4l2_async_notifier *notifier = &sdr->notifier; 1208 struct fwnode_handle *fwnode, *ep; 1209 struct v4l2_async_connection *asd; 1210 1211 v4l2_async_nf_init(&sdr->notifier, &sdr->v4l2_dev); 1212 1213 ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node), 1214 NULL); 1215 if (!ep) 1216 return 0; 1217 1218 /* Get the endpoint properties */ 1219 rcar_drif_get_ep_properties(sdr, ep); 1220 1221 fwnode = fwnode_graph_get_remote_port_parent(ep); 1222 fwnode_handle_put(ep); 1223 if (!fwnode) { 1224 dev_warn(sdr->dev, "bad remote port parent\n"); 1225 return -EINVAL; 1226 } 1227 1228 asd = v4l2_async_nf_add_fwnode(notifier, fwnode, 1229 struct v4l2_async_connection); 1230 fwnode_handle_put(fwnode); 1231 if (IS_ERR(asd)) 1232 return PTR_ERR(asd); 1233 1234 return 0; 1235} 1236 1237/* Check if the given device is the primary bond */ 1238static bool rcar_drif_primary_bond(struct platform_device *pdev) 1239{ 1240 return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond"); 1241} 1242 1243/* Check if both devices of the bond are enabled */ 1244static struct device_node *rcar_drif_bond_enabled(struct platform_device *p) 1245{ 1246 struct device_node *np; 1247 1248 np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0); 1249 if (np && of_device_is_available(np)) 1250 return np; 1251 1252 return NULL; 1253} 1254 1255/* Check if the bonded device is probed */ 1256static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr, 1257 struct device_node *np) 1258{ 1259 struct platform_device *pdev; 1260 struct rcar_drif *ch; 1261 int ret = 0; 1262 1263 pdev = of_find_device_by_node(np); 1264 if (!pdev) { 1265 dev_err(sdr->dev, "failed to get bonded device from node\n"); 1266 return -ENODEV; 1267 } 1268 1269 device_lock(&pdev->dev); 1270 ch = platform_get_drvdata(pdev); 1271 if (ch) { 1272 /* Update sdr data in the bonded device */ 1273 ch->sdr = sdr; 1274 1275 /* Update sdr with bonded device data */ 1276 sdr->ch[ch->num] = ch; 1277 sdr->hw_ch_mask |= BIT(ch->num); 1278 } else { 1279 /* Defer */ 1280 dev_info(sdr->dev, "defer probe\n"); 1281 ret = -EPROBE_DEFER; 1282 } 1283 device_unlock(&pdev->dev); 1284 1285 put_device(&pdev->dev); 1286 1287 return ret; 1288} 1289 1290/* V4L2 SDR device probe */ 1291static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr) 1292{ 1293 int ret; 1294 1295 /* Validate any supported format for enabled channels */ 1296 ret = rcar_drif_set_default_format(sdr); 1297 if (ret) { 1298 dev_err(sdr->dev, "failed to set default format\n"); 1299 return ret; 1300 } 1301 1302 /* Set defaults */ 1303 sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE; 1304 1305 mutex_init(&sdr->v4l2_mutex); 1306 mutex_init(&sdr->vb_queue_mutex); 1307 spin_lock_init(&sdr->queued_bufs_lock); 1308 spin_lock_init(&sdr->dma_lock); 1309 INIT_LIST_HEAD(&sdr->queued_bufs); 1310 1311 /* Init videobuf2 queue structure */ 1312 sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE; 1313 sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF; 1314 sdr->vb_queue.drv_priv = sdr; 1315 sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf); 1316 sdr->vb_queue.ops = &rcar_drif_vb2_ops; 1317 sdr->vb_queue.mem_ops = &vb2_vmalloc_memops; 1318 sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1319 1320 /* Init videobuf2 queue */ 1321 ret = vb2_queue_init(&sdr->vb_queue); 1322 if (ret) { 1323 dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret); 1324 return ret; 1325 } 1326 1327 /* Register the v4l2_device */ 1328 ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev); 1329 if (ret) { 1330 dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret); 1331 return ret; 1332 } 1333 1334 /* 1335 * Parse subdevs after v4l2_device_register because if the subdev 1336 * is already probed, bound and complete will be called immediately 1337 */ 1338 ret = rcar_drif_parse_subdevs(sdr); 1339 if (ret) 1340 goto error; 1341 1342 sdr->notifier.ops = &rcar_drif_notify_ops; 1343 1344 /* Register notifier */ 1345 ret = v4l2_async_nf_register(&sdr->notifier); 1346 if (ret < 0) { 1347 dev_err(sdr->dev, "failed: notifier register ret %d\n", ret); 1348 goto cleanup; 1349 } 1350 1351 return ret; 1352 1353cleanup: 1354 v4l2_async_nf_cleanup(&sdr->notifier); 1355error: 1356 v4l2_device_unregister(&sdr->v4l2_dev); 1357 1358 return ret; 1359} 1360 1361/* V4L2 SDR device remove */ 1362static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr) 1363{ 1364 v4l2_async_nf_unregister(&sdr->notifier); 1365 v4l2_async_nf_cleanup(&sdr->notifier); 1366 v4l2_device_unregister(&sdr->v4l2_dev); 1367} 1368 1369/* DRIF channel probe */ 1370static int rcar_drif_probe(struct platform_device *pdev) 1371{ 1372 struct rcar_drif_sdr *sdr; 1373 struct device_node *np; 1374 struct rcar_drif *ch; 1375 struct resource *res; 1376 int ret; 1377 1378 /* Reserve memory for enabled channel */ 1379 ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL); 1380 if (!ch) 1381 return -ENOMEM; 1382 1383 ch->pdev = pdev; 1384 1385 /* Module clock */ 1386 ch->clk = devm_clk_get(&pdev->dev, "fck"); 1387 if (IS_ERR(ch->clk)) { 1388 ret = PTR_ERR(ch->clk); 1389 dev_err(&pdev->dev, "clk get failed (%d)\n", ret); 1390 return ret; 1391 } 1392 1393 /* Register map */ 1394 ch->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1395 if (IS_ERR(ch->base)) 1396 return PTR_ERR(ch->base); 1397 1398 ch->start = res->start; 1399 platform_set_drvdata(pdev, ch); 1400 1401 /* Check if both channels of the bond are enabled */ 1402 np = rcar_drif_bond_enabled(pdev); 1403 if (np) { 1404 /* Check if current channel acting as primary-bond */ 1405 if (!rcar_drif_primary_bond(pdev)) { 1406 ch->num = 1; /* Primary bond is channel 0 always */ 1407 of_node_put(np); 1408 return 0; 1409 } 1410 } 1411 1412 /* Reserve memory for SDR structure */ 1413 sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL); 1414 if (!sdr) { 1415 of_node_put(np); 1416 return -ENOMEM; 1417 } 1418 ch->sdr = sdr; 1419 sdr->dev = &pdev->dev; 1420 1421 /* Establish links between SDR and channel(s) */ 1422 sdr->ch[ch->num] = ch; 1423 sdr->hw_ch_mask = BIT(ch->num); 1424 if (np) { 1425 /* Check if bonded device is ready */ 1426 ret = rcar_drif_bond_available(sdr, np); 1427 of_node_put(np); 1428 if (ret) 1429 return ret; 1430 } 1431 sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask); 1432 1433 return rcar_drif_sdr_probe(sdr); 1434} 1435 1436/* DRIF channel remove */ 1437static void rcar_drif_remove(struct platform_device *pdev) 1438{ 1439 struct rcar_drif *ch = platform_get_drvdata(pdev); 1440 struct rcar_drif_sdr *sdr = ch->sdr; 1441 1442 /* Channel 0 will be the SDR instance */ 1443 if (ch->num) 1444 return; 1445 1446 /* SDR instance */ 1447 rcar_drif_sdr_remove(sdr); 1448} 1449 1450/* FIXME: Implement suspend/resume support */ 1451static int __maybe_unused rcar_drif_suspend(struct device *dev) 1452{ 1453 return 0; 1454} 1455 1456static int __maybe_unused rcar_drif_resume(struct device *dev) 1457{ 1458 return 0; 1459} 1460 1461static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend, 1462 rcar_drif_resume); 1463 1464static const struct of_device_id rcar_drif_of_table[] = { 1465 { .compatible = "renesas,rcar-gen3-drif" }, 1466 { } 1467}; 1468MODULE_DEVICE_TABLE(of, rcar_drif_of_table); 1469 1470#define RCAR_DRIF_DRV_NAME "rcar_drif" 1471static struct platform_driver rcar_drif_driver = { 1472 .driver = { 1473 .name = RCAR_DRIF_DRV_NAME, 1474 .of_match_table = rcar_drif_of_table, 1475 .pm = &rcar_drif_pm_ops, 1476 }, 1477 .probe = rcar_drif_probe, 1478 .remove_new = rcar_drif_remove, 1479}; 1480 1481module_platform_driver(rcar_drif_driver); 1482 1483MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver"); 1484MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME); 1485MODULE_LICENSE("GPL"); 1486MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>"); 1487