1// SPDX-License-Identifier: GPL-2.0
2/*
3 * camss-vfe-170.c
4 *
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v170
6 *
7 * Copyright (C) 2020-2021 Linaro Ltd.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13
14#include "camss.h"
15#include "camss-vfe.h"
16
17#define VFE_HW_VERSION				(0x000)
18
19#define VFE_GLOBAL_RESET_CMD			(0x018)
20#define		GLOBAL_RESET_CMD_CORE		BIT(0)
21#define		GLOBAL_RESET_CMD_CAMIF		BIT(1)
22#define		GLOBAL_RESET_CMD_BUS		BIT(2)
23#define		GLOBAL_RESET_CMD_BUS_BDG	BIT(3)
24#define		GLOBAL_RESET_CMD_REGISTER	BIT(4)
25#define		GLOBAL_RESET_CMD_PM		BIT(5)
26#define		GLOBAL_RESET_CMD_BUS_MISR	BIT(6)
27#define		GLOBAL_RESET_CMD_TESTGEN	BIT(7)
28#define		GLOBAL_RESET_CMD_DSP		BIT(8)
29#define		GLOBAL_RESET_CMD_IDLE_CGC	BIT(9)
30#define		GLOBAL_RESET_CMD_RDI0		BIT(10)
31#define		GLOBAL_RESET_CMD_RDI1		BIT(11)
32#define		GLOBAL_RESET_CMD_RDI2		BIT(12)
33#define		GLOBAL_RESET_CMD_RDI3		BIT(13)
34#define		GLOBAL_RESET_CMD_VFE_DOMAIN	BIT(30)
35#define		GLOBAL_RESET_CMD_RESET_BYPASS	BIT(31)
36
37#define VFE_CORE_CFG				(0x050)
38#define		CFG_PIXEL_PATTERN_YCBYCR	(0x4)
39#define		CFG_PIXEL_PATTERN_YCRYCB	(0x5)
40#define		CFG_PIXEL_PATTERN_CBYCRY	(0x6)
41#define		CFG_PIXEL_PATTERN_CRYCBY	(0x7)
42#define		CFG_COMPOSITE_REG_UPDATE_EN	BIT(4)
43
44#define VFE_IRQ_CMD				(0x058)
45#define		CMD_GLOBAL_CLEAR		BIT(0)
46
47#define VFE_IRQ_MASK_0					(0x05c)
48#define		MASK_0_CAMIF_SOF			BIT(0)
49#define		MASK_0_CAMIF_EOF			BIT(1)
50#define		MASK_0_RDI_REG_UPDATE(n)		BIT((n) + 5)
51#define		MASK_0_IMAGE_MASTER_n_PING_PONG(n)	BIT((n) + 8)
52#define		MASK_0_IMAGE_COMPOSITE_DONE_n(n)	BIT((n) + 25)
53#define		MASK_0_RESET_ACK			BIT(31)
54
55#define VFE_IRQ_MASK_1					(0x060)
56#define		MASK_1_CAMIF_ERROR			BIT(0)
57#define		MASK_1_VIOLATION			BIT(7)
58#define		MASK_1_BUS_BDG_HALT_ACK			BIT(8)
59#define		MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n)	BIT((n) + 9)
60#define		MASK_1_RDI_SOF(n)			BIT((n) + 29)
61
62#define VFE_IRQ_CLEAR_0					(0x064)
63#define VFE_IRQ_CLEAR_1					(0x068)
64
65#define VFE_IRQ_STATUS_0				(0x06c)
66#define		STATUS_0_CAMIF_SOF			BIT(0)
67#define		STATUS_0_RDI_REG_UPDATE(n)		BIT((n) + 5)
68#define		STATUS_0_IMAGE_MASTER_PING_PONG(n)	BIT((n) + 8)
69#define		STATUS_0_IMAGE_COMPOSITE_DONE(n)	BIT((n) + 25)
70#define		STATUS_0_RESET_ACK			BIT(31)
71
72#define VFE_IRQ_STATUS_1				(0x070)
73#define		STATUS_1_VIOLATION			BIT(7)
74#define		STATUS_1_BUS_BDG_HALT_ACK		BIT(8)
75#define		STATUS_1_RDI_SOF(n)			BIT((n) + 27)
76
77#define VFE_VIOLATION_STATUS			(0x07c)
78
79#define VFE_CAMIF_CMD				(0x478)
80#define		CMD_CLEAR_CAMIF_STATUS		BIT(2)
81
82#define VFE_CAMIF_CFG				(0x47c)
83#define		CFG_VSYNC_SYNC_EDGE		(0)
84#define			VSYNC_ACTIVE_HIGH	(0)
85#define			VSYNC_ACTIVE_LOW	(1)
86#define		CFG_HSYNC_SYNC_EDGE		(1)
87#define			HSYNC_ACTIVE_HIGH	(0)
88#define			HSYNC_ACTIVE_LOW	(1)
89#define		CFG_VFE_SUBSAMPLE_ENABLE	BIT(4)
90#define		CFG_BUS_SUBSAMPLE_ENABLE	BIT(5)
91#define		CFG_VFE_OUTPUT_EN		BIT(6)
92#define		CFG_BUS_OUTPUT_EN		BIT(7)
93#define		CFG_BINNING_EN			BIT(9)
94#define		CFG_FRAME_BASED_EN		BIT(10)
95#define		CFG_RAW_CROP_EN			BIT(22)
96
97#define VFE_REG_UPDATE_CMD			(0x4ac)
98#define		REG_UPDATE_RDI(n)		BIT(1 + (n))
99
100#define VFE_BUS_IRQ_MASK(n)		(0x2044 + (n) * 4)
101#define VFE_BUS_IRQ_CLEAR(n)		(0x2050 + (n) * 4)
102#define VFE_BUS_IRQ_STATUS(n)		(0x205c + (n) * 4)
103#define		STATUS0_COMP_RESET_DONE		BIT(0)
104#define		STATUS0_COMP_REG_UPDATE0_DONE	BIT(1)
105#define		STATUS0_COMP_REG_UPDATE1_DONE	BIT(2)
106#define		STATUS0_COMP_REG_UPDATE2_DONE	BIT(3)
107#define		STATUS0_COMP_REG_UPDATE3_DONE	BIT(4)
108#define		STATUS0_COMP_REG_UPDATE_DONE(n)	BIT((n) + 1)
109#define		STATUS0_COMP0_BUF_DONE		BIT(5)
110#define		STATUS0_COMP1_BUF_DONE		BIT(6)
111#define		STATUS0_COMP2_BUF_DONE		BIT(7)
112#define		STATUS0_COMP3_BUF_DONE		BIT(8)
113#define		STATUS0_COMP4_BUF_DONE		BIT(9)
114#define		STATUS0_COMP5_BUF_DONE		BIT(10)
115#define		STATUS0_COMP_BUF_DONE(n)	BIT((n) + 5)
116#define		STATUS0_COMP_ERROR		BIT(11)
117#define		STATUS0_COMP_OVERWRITE		BIT(12)
118#define		STATUS0_OVERFLOW		BIT(13)
119#define		STATUS0_VIOLATION		BIT(14)
120/* WM_CLIENT_BUF_DONE defined for buffers 0:19 */
121#define		STATUS1_WM_CLIENT_BUF_DONE(n)		BIT(n)
122#define		STATUS1_EARLY_DONE			BIT(24)
123#define		STATUS2_DUAL_COMP0_BUF_DONE		BIT(0)
124#define		STATUS2_DUAL_COMP1_BUF_DONE		BIT(1)
125#define		STATUS2_DUAL_COMP2_BUF_DONE		BIT(2)
126#define		STATUS2_DUAL_COMP3_BUF_DONE		BIT(3)
127#define		STATUS2_DUAL_COMP4_BUF_DONE		BIT(4)
128#define		STATUS2_DUAL_COMP5_BUF_DONE		BIT(5)
129#define		STATUS2_DUAL_COMP_BUF_DONE(n)		BIT(n)
130#define		STATUS2_DUAL_COMP_ERROR			BIT(6)
131#define		STATUS2_DUAL_COMP_OVERWRITE		BIT(7)
132
133#define VFE_BUS_IRQ_CLEAR_GLOBAL		(0x2068)
134
135#define VFE_BUS_WM_DEBUG_STATUS_CFG		(0x226c)
136#define		DEBUG_STATUS_CFG_STATUS0(n)	BIT(n)
137#define		DEBUG_STATUS_CFG_STATUS1(n)	BIT(8 + (n))
138
139#define VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER	(0x2080)
140
141#define VFE_BUS_WM_ADDR_SYNC_NO_SYNC		(0x2084)
142#define		BUS_VER2_MAX_CLIENTS (24)
143#define		WM_ADDR_NO_SYNC_DEFAULT_VAL \
144				((1 << BUS_VER2_MAX_CLIENTS) - 1)
145
146#define VFE_BUS_WM_CGC_OVERRIDE			(0x200c)
147#define		WM_CGC_OVERRIDE_ALL		(0xFFFFF)
148
149#define VFE_BUS_WM_TEST_BUS_CTRL		(0x211c)
150
151#define VFE_BUS_WM_STATUS0(n)			(0x2200 + (n) * 0x100)
152#define VFE_BUS_WM_STATUS1(n)			(0x2204 + (n) * 0x100)
153#define VFE_BUS_WM_CFG(n)			(0x2208 + (n) * 0x100)
154#define		WM_CFG_EN			(0)
155#define		WM_CFG_MODE			(1)
156#define			MODE_QCOM_PLAIN	(0)
157#define			MODE_MIPI_RAW	(1)
158#define		WM_CFG_VIRTUALFRAME		(2)
159#define VFE_BUS_WM_HEADER_ADDR(n)		(0x220c + (n) * 0x100)
160#define VFE_BUS_WM_HEADER_CFG(n)		(0x2210 + (n) * 0x100)
161#define VFE_BUS_WM_IMAGE_ADDR(n)		(0x2214 + (n) * 0x100)
162#define VFE_BUS_WM_IMAGE_ADDR_OFFSET(n)		(0x2218 + (n) * 0x100)
163#define VFE_BUS_WM_BUFFER_WIDTH_CFG(n)		(0x221c + (n) * 0x100)
164#define		WM_BUFFER_DEFAULT_WIDTH		(0xFF01)
165
166#define VFE_BUS_WM_BUFFER_HEIGHT_CFG(n)		(0x2220 + (n) * 0x100)
167#define VFE_BUS_WM_PACKER_CFG(n)		(0x2224 + (n) * 0x100)
168
169#define VFE_BUS_WM_STRIDE(n)			(0x2228 + (n) * 0x100)
170#define		WM_STRIDE_DEFAULT_STRIDE	(0xFF01)
171
172#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n)	(0x2248 + (n) * 0x100)
173#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n)	(0x224c + (n) * 0x100)
174#define VFE_BUS_WM_FRAMEDROP_PERIOD(n)		(0x2250 + (n) * 0x100)
175#define VFE_BUS_WM_FRAMEDROP_PATTERN(n)		(0x2254 + (n) * 0x100)
176#define VFE_BUS_WM_FRAME_INC(n)			(0x2258 + (n) * 0x100)
177#define VFE_BUS_WM_BURST_LIMIT(n)		(0x225c + (n) * 0x100)
178
179static u32 vfe_hw_version(struct vfe_device *vfe)
180{
181	u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION);
182
183	u32 gen = (hw_version >> 28) & 0xF;
184	u32 rev = (hw_version >> 16) & 0xFFF;
185	u32 step = hw_version & 0xFFFF;
186
187	dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n",
188		gen, rev, step);
189
190	return hw_version;
191}
192
193static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
194{
195	u32 bits = readl_relaxed(vfe->base + reg);
196
197	writel_relaxed(bits | set_bits, vfe->base + reg);
198}
199
200static void vfe_global_reset(struct vfe_device *vfe)
201{
202	u32 reset_bits = GLOBAL_RESET_CMD_CORE		|
203			 GLOBAL_RESET_CMD_CAMIF		|
204			 GLOBAL_RESET_CMD_BUS		|
205			 GLOBAL_RESET_CMD_BUS_BDG	|
206			 GLOBAL_RESET_CMD_REGISTER	|
207			 GLOBAL_RESET_CMD_TESTGEN	|
208			 GLOBAL_RESET_CMD_DSP		|
209			 GLOBAL_RESET_CMD_IDLE_CGC	|
210			 GLOBAL_RESET_CMD_RDI0		|
211			 GLOBAL_RESET_CMD_RDI1		|
212			 GLOBAL_RESET_CMD_RDI2;
213
214	writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0);
215
216	/* Make sure IRQ mask has been written before resetting */
217	wmb();
218
219	writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD);
220}
221
222static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
223{
224	u32 val;
225
226	/*Set Debug Registers*/
227	val = DEBUG_STATUS_CFG_STATUS0(1) |
228	      DEBUG_STATUS_CFG_STATUS0(7);
229	writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);
230
231	/* BUS_WM_INPUT_IF_ADDR_SYNC_FRAME_HEADER */
232	writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);
233
234	/* no clock gating at bus input */
235	val = WM_CGC_OVERRIDE_ALL;
236	writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
237
238	writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
239
240	/* if addr_no_sync has default value then config the addr no sync reg */
241	val = WM_ADDR_NO_SYNC_DEFAULT_VAL;
242	writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);
243
244	writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
245
246	val = WM_BUFFER_DEFAULT_WIDTH;
247	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));
248
249	val = 0;
250	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));
251
252	val = 0;
253	writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8?
254
255	/* Configure stride for RDIs */
256	val = WM_STRIDE_DEFAULT_STRIDE;
257	writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));
258
259	/* Enable WM */
260	val = 1 << WM_CFG_EN |
261	      MODE_MIPI_RAW << WM_CFG_MODE;
262	writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));
263}
264
265static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
266{
267	/* Disable WM */
268	writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
269}
270
271static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
272			  struct vfe_line *line)
273{
274	struct v4l2_pix_format_mplane *pix =
275		&line->video_out.active_fmt.fmt.pix_mp;
276	u32 stride = pix->plane_fmt[0].bytesperline;
277
278	writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
279	writel_relaxed(stride * pix->height, vfe->base + VFE_BUS_WM_FRAME_INC(wm));
280}
281
282static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
283{
284	vfe->reg_update |= REG_UPDATE_RDI(line_id);
285
286	/* Enforce ordering between previous reg writes and reg update */
287	wmb();
288
289	writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
290
291	/* Enforce ordering between reg update and subsequent reg writes */
292	wmb();
293}
294
295static inline void vfe_reg_update_clear(struct vfe_device *vfe,
296					enum vfe_line_id line_id)
297{
298	vfe->reg_update &= ~REG_UPDATE_RDI(line_id);
299}
300
301static void vfe_enable_irq_common(struct vfe_device *vfe)
302{
303	vfe_reg_set(vfe, VFE_IRQ_MASK_0, ~0u);
304	vfe_reg_set(vfe, VFE_IRQ_MASK_1, ~0u);
305
306	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(0));
307	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(1));
308	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(2));
309}
310
311static void vfe_isr_halt_ack(struct vfe_device *vfe)
312{
313	complete(&vfe->halt_complete);
314}
315
316static void vfe_isr_read(struct vfe_device *vfe, u32 *status0, u32 *status1)
317{
318	*status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
319	*status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
320
321	writel_relaxed(*status0, vfe->base + VFE_IRQ_CLEAR_0);
322	writel_relaxed(*status1, vfe->base + VFE_IRQ_CLEAR_1);
323
324	/* Enforce ordering between IRQ Clear and Global IRQ Clear */
325	wmb();
326	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
327}
328
329static void vfe_violation_read(struct vfe_device *vfe)
330{
331	u32 violation = readl_relaxed(vfe->base + VFE_VIOLATION_STATUS);
332
333	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);
334}
335
336/*
337 * vfe_isr - VFE module interrupt handler
338 * @irq: Interrupt line
339 * @dev: VFE device
340 *
341 * Return IRQ_HANDLED on success
342 */
343static irqreturn_t vfe_isr(int irq, void *dev)
344{
345	struct vfe_device *vfe = dev;
346	u32 status0, status1, vfe_bus_status[3];
347	int i, wm;
348
349	status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
350	status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
351
352	writel_relaxed(status0, vfe->base + VFE_IRQ_CLEAR_0);
353	writel_relaxed(status1, vfe->base + VFE_IRQ_CLEAR_1);
354
355	for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) {
356		vfe_bus_status[i] = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(i));
357		writel_relaxed(vfe_bus_status[i], vfe->base + VFE_BUS_IRQ_CLEAR(i));
358	}
359
360	/* Enforce ordering between IRQ reading and interpretation */
361	wmb();
362
363	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
364	writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
365
366	if (status0 & STATUS_0_RESET_ACK)
367		vfe->isr_ops.reset_ack(vfe);
368
369	for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++)
370		if (status0 & STATUS_0_RDI_REG_UPDATE(i))
371			vfe->isr_ops.reg_update(vfe, i);
372
373	for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++)
374		if (status0 & STATUS_1_RDI_SOF(i))
375			vfe->isr_ops.sof(vfe, i);
376
377	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)
378		if (vfe_bus_status[0] & STATUS0_COMP_BUF_DONE(i))
379			vfe->isr_ops.comp_done(vfe, i);
380
381	for (wm = 0; wm < MSM_VFE_IMAGE_MASTERS_NUM; wm++)
382		if (status0 & BIT(9))
383			if (vfe_bus_status[1] & STATUS1_WM_CLIENT_BUF_DONE(wm))
384				vfe->isr_ops.wm_done(vfe, wm);
385
386	return IRQ_HANDLED;
387}
388
389/*
390 * vfe_halt - Trigger halt on VFE module and wait to complete
391 * @vfe: VFE device
392 *
393 * Return 0 on success or a negative error code otherwise
394 */
395static int vfe_halt(struct vfe_device *vfe)
396{
397	/* rely on vfe_disable_output() to stop the VFE */
398	return 0;
399}
400
401static int vfe_get_output(struct vfe_line *line)
402{
403	struct vfe_device *vfe = to_vfe(line);
404	struct vfe_output *output;
405	unsigned long flags;
406	int wm_idx;
407
408	spin_lock_irqsave(&vfe->output_lock, flags);
409
410	output = &line->output;
411	if (output->state > VFE_OUTPUT_RESERVED) {
412		dev_err(vfe->camss->dev, "Output is running\n");
413		goto error;
414	}
415
416	output->wm_num = 1;
417
418	wm_idx = vfe_reserve_wm(vfe, line->id);
419	if (wm_idx < 0) {
420		dev_err(vfe->camss->dev, "Can not reserve wm\n");
421		goto error_get_wm;
422	}
423	output->wm_idx[0] = wm_idx;
424
425	output->drop_update_idx = 0;
426
427	spin_unlock_irqrestore(&vfe->output_lock, flags);
428
429	return 0;
430
431error_get_wm:
432	vfe_release_wm(vfe, output->wm_idx[0]);
433	output->state = VFE_OUTPUT_OFF;
434error:
435	spin_unlock_irqrestore(&vfe->output_lock, flags);
436
437	return -EINVAL;
438}
439
440static int vfe_enable_output(struct vfe_line *line)
441{
442	struct vfe_device *vfe = to_vfe(line);
443	struct vfe_output *output = &line->output;
444	const struct vfe_hw_ops *ops = vfe->ops;
445	struct media_entity *sensor;
446	unsigned long flags;
447	unsigned int frame_skip = 0;
448	unsigned int i;
449
450	sensor = camss_find_sensor(&line->subdev.entity);
451	if (sensor) {
452		struct v4l2_subdev *subdev = media_entity_to_v4l2_subdev(sensor);
453
454		v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip);
455		/* Max frame skip is 29 frames */
456		if (frame_skip > VFE_FRAME_DROP_VAL - 1)
457			frame_skip = VFE_FRAME_DROP_VAL - 1;
458	}
459
460	spin_lock_irqsave(&vfe->output_lock, flags);
461
462	ops->reg_update_clear(vfe, line->id);
463
464	if (output->state > VFE_OUTPUT_RESERVED) {
465		dev_err(vfe->camss->dev, "Output is not in reserved state %d\n",
466			output->state);
467		spin_unlock_irqrestore(&vfe->output_lock, flags);
468		return -EINVAL;
469	}
470
471	WARN_ON(output->gen2.active_num);
472
473	output->state = VFE_OUTPUT_ON;
474
475	output->sequence = 0;
476	output->wait_reg_update = 0;
477	reinit_completion(&output->reg_update);
478
479	vfe_wm_start(vfe, output->wm_idx[0], line);
480
481	for (i = 0; i < 2; i++) {
482		output->buf[i] = vfe_buf_get_pending(output);
483		if (!output->buf[i])
484			break;
485		output->gen2.active_num++;
486		vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line);
487	}
488
489	ops->reg_update(vfe, line->id);
490
491	spin_unlock_irqrestore(&vfe->output_lock, flags);
492
493	return 0;
494}
495
496static void vfe_disable_output(struct vfe_line *line)
497{
498	struct vfe_device *vfe = to_vfe(line);
499	struct vfe_output *output = &line->output;
500	unsigned long flags;
501	unsigned int i;
502
503	spin_lock_irqsave(&vfe->output_lock, flags);
504	for (i = 0; i < output->wm_num; i++)
505		vfe_wm_stop(vfe, output->wm_idx[i]);
506	output->gen2.active_num = 0;
507	spin_unlock_irqrestore(&vfe->output_lock, flags);
508
509	vfe_reset(vfe);
510}
511
512/*
513 * vfe_enable - Enable streaming on VFE line
514 * @line: VFE line
515 *
516 * Return 0 on success or a negative error code otherwise
517 */
518static int vfe_enable(struct vfe_line *line)
519{
520	struct vfe_device *vfe = to_vfe(line);
521	int ret;
522
523	mutex_lock(&vfe->stream_lock);
524
525	if (!vfe->stream_count)
526		vfe_enable_irq_common(vfe);
527
528	vfe->stream_count++;
529
530	mutex_unlock(&vfe->stream_lock);
531
532	ret = vfe_get_output(line);
533	if (ret < 0)
534		goto error_get_output;
535
536	ret = vfe_enable_output(line);
537	if (ret < 0)
538		goto error_enable_output;
539
540	vfe->was_streaming = 1;
541
542	return 0;
543
544error_enable_output:
545	vfe_put_output(line);
546
547error_get_output:
548	mutex_lock(&vfe->stream_lock);
549
550	vfe->stream_count--;
551
552	mutex_unlock(&vfe->stream_lock);
553
554	return ret;
555}
556
557/*
558 * vfe_disable - Disable streaming on VFE line
559 * @line: VFE line
560 *
561 * Return 0 on success or a negative error code otherwise
562 */
563static int vfe_disable(struct vfe_line *line)
564{
565	struct vfe_device *vfe = to_vfe(line);
566
567	vfe_disable_output(line);
568
569	vfe_put_output(line);
570
571	mutex_lock(&vfe->stream_lock);
572
573	vfe->stream_count--;
574
575	mutex_unlock(&vfe->stream_lock);
576
577	return 0;
578}
579
580/*
581 * vfe_isr_sof - Process start of frame interrupt
582 * @vfe: VFE Device
583 * @line_id: VFE line
584 */
585static void vfe_isr_sof(struct vfe_device *vfe, enum vfe_line_id line_id)
586{
587	/* nop */
588}
589
590/*
591 * vfe_isr_reg_update - Process reg update interrupt
592 * @vfe: VFE Device
593 * @line_id: VFE line
594 */
595static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
596{
597	struct vfe_output *output;
598	unsigned long flags;
599
600	spin_lock_irqsave(&vfe->output_lock, flags);
601	vfe->ops->reg_update_clear(vfe, line_id);
602
603	output = &vfe->line[line_id].output;
604
605	if (output->wait_reg_update) {
606		output->wait_reg_update = 0;
607		complete(&output->reg_update);
608	}
609
610	spin_unlock_irqrestore(&vfe->output_lock, flags);
611}
612
613/*
614 * vfe_isr_wm_done - Process write master done interrupt
615 * @vfe: VFE Device
616 * @wm: Write master id
617 */
618static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm)
619{
620	struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]];
621	struct camss_buffer *ready_buf;
622	struct vfe_output *output;
623	unsigned long flags;
624	u32 index;
625	u64 ts = ktime_get_ns();
626
627	spin_lock_irqsave(&vfe->output_lock, flags);
628
629	if (vfe->wm_output_map[wm] == VFE_LINE_NONE) {
630		dev_err_ratelimited(vfe->camss->dev,
631				    "Received wm done for unmapped index\n");
632		goto out_unlock;
633	}
634	output = &vfe->line[vfe->wm_output_map[wm]].output;
635
636	ready_buf = output->buf[0];
637	if (!ready_buf) {
638		dev_err_ratelimited(vfe->camss->dev,
639				    "Missing ready buf %d!\n", output->state);
640		goto out_unlock;
641	}
642
643	ready_buf->vb.vb2_buf.timestamp = ts;
644	ready_buf->vb.sequence = output->sequence++;
645
646	index = 0;
647	output->buf[0] = output->buf[1];
648	if (output->buf[0])
649		index = 1;
650
651	output->buf[index] = vfe_buf_get_pending(output);
652
653	if (output->buf[index])
654		vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line);
655	else
656		output->gen2.active_num--;
657
658	spin_unlock_irqrestore(&vfe->output_lock, flags);
659
660	vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
661
662	return;
663
664out_unlock:
665	spin_unlock_irqrestore(&vfe->output_lock, flags);
666}
667
668/*
669 * vfe_pm_domain_off - Disable power domains specific to this VFE.
670 * @vfe: VFE Device
671 */
672static void vfe_pm_domain_off(struct vfe_device *vfe)
673{
674	struct camss *camss = vfe->camss;
675
676	if (vfe->id >= camss->vfe_num)
677		return;
678
679	device_link_del(camss->genpd_link[vfe->id]);
680}
681
682/*
683 * vfe_pm_domain_on - Enable power domains specific to this VFE.
684 * @vfe: VFE Device
685 */
686static int vfe_pm_domain_on(struct vfe_device *vfe)
687{
688	struct camss *camss = vfe->camss;
689	enum vfe_line_id id = vfe->id;
690
691	if (id >= camss->vfe_num)
692		return 0;
693
694	camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id],
695						DL_FLAG_STATELESS |
696						DL_FLAG_PM_RUNTIME |
697						DL_FLAG_RPM_ACTIVE);
698	if (!camss->genpd_link[id])
699		return -EINVAL;
700
701	return 0;
702}
703
704/*
705 * vfe_queue_buffer - Add empty buffer
706 * @vid: Video device structure
707 * @buf: Buffer to be enqueued
708 *
709 * Add an empty buffer - depending on the current number of buffers it will be
710 * put in pending buffer queue or directly given to the hardware to be filled.
711 *
712 * Return 0 on success or a negative error code otherwise
713 */
714static int vfe_queue_buffer(struct camss_video *vid,
715			    struct camss_buffer *buf)
716{
717	struct vfe_line *line = container_of(vid, struct vfe_line, video_out);
718	struct vfe_device *vfe = to_vfe(line);
719	struct vfe_output *output;
720	unsigned long flags;
721
722	output = &line->output;
723
724	spin_lock_irqsave(&vfe->output_lock, flags);
725
726	if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) {
727		output->buf[output->gen2.active_num++] = buf;
728		vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line);
729	} else {
730		vfe_buf_add_pending(output, buf);
731	}
732
733	spin_unlock_irqrestore(&vfe->output_lock, flags);
734
735	return 0;
736}
737
738static const struct vfe_isr_ops vfe_isr_ops_170 = {
739	.reset_ack = vfe_isr_reset_ack,
740	.halt_ack = vfe_isr_halt_ack,
741	.reg_update = vfe_isr_reg_update,
742	.sof = vfe_isr_sof,
743	.comp_done = vfe_isr_comp_done,
744	.wm_done = vfe_isr_wm_done,
745};
746
747static const struct camss_video_ops vfe_video_ops_170 = {
748	.queue_buffer = vfe_queue_buffer,
749	.flush_buffers = vfe_flush_buffers,
750};
751
752static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
753{
754	vfe->isr_ops = vfe_isr_ops_170;
755	vfe->video_ops = vfe_video_ops_170;
756
757	vfe->line_num = VFE_LINE_NUM_GEN2;
758}
759
760const struct vfe_hw_ops vfe_ops_170 = {
761	.global_reset = vfe_global_reset,
762	.hw_version = vfe_hw_version,
763	.isr_read = vfe_isr_read,
764	.isr = vfe_isr,
765	.pm_domain_off = vfe_pm_domain_off,
766	.pm_domain_on = vfe_pm_domain_on,
767	.reg_update_clear = vfe_reg_update_clear,
768	.reg_update = vfe_reg_update,
769	.subdev_init = vfe_subdev_init,
770	.vfe_disable = vfe_disable,
771	.vfe_enable = vfe_enable,
772	.vfe_halt = vfe_halt,
773	.violation_read = vfe_violation_read,
774};
775