1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NVIDIA Tegra Video decoder driver 4 * 5 * Copyright (C) 2019-2022 Dmitry Osipenko <digetx@gmail.com> 6 * 7 * Based on Cedrus driver by Bootlin. 8 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 9 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 10 * 11 * Based on Rockchip driver by Collabora. 12 * Copyright (C) 2019 Boris Brezillon <boris.brezillon@collabora.com> 13 */ 14 15#include <linux/err.h> 16#include <linux/slab.h> 17 18#include "vde.h" 19 20static const struct v4l2_ctrl_config ctrl_cfgs[] = { 21 { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, }, 22 { .id = V4L2_CID_STATELESS_H264_SPS, }, 23 { .id = V4L2_CID_STATELESS_H264_PPS, }, 24 { 25 .id = V4L2_CID_STATELESS_H264_DECODE_MODE, 26 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 27 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 28 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 29 }, 30 { 31 .id = V4L2_CID_STATELESS_H264_START_CODE, 32 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 33 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 34 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 35 }, 36 { 37 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, 38 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 39 .max = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 40 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 41 }, 42 { 43 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, 44 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, 45 .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 46 }, 47}; 48 49static inline struct tegra_ctx *fh_to_tegra_ctx(struct v4l2_fh *fh) 50{ 51 return container_of(fh, struct tegra_ctx, fh); 52} 53 54static void tegra_set_control_data(struct tegra_ctx *ctx, void *data, u32 id) 55{ 56 switch (id) { 57 case V4L2_CID_STATELESS_H264_DECODE_PARAMS: 58 ctx->h264.decode_params = data; 59 break; 60 case V4L2_CID_STATELESS_H264_SPS: 61 ctx->h264.sps = data; 62 break; 63 case V4L2_CID_STATELESS_H264_PPS: 64 ctx->h264.pps = data; 65 break; 66 } 67} 68 69void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id) 70{ 71 unsigned int i; 72 73 for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { 74 if (ctx->ctrls[i]->id == id) { 75 tegra_set_control_data(ctx, ctx->ctrls[i]->p_cur.p, id); 76 return; 77 } 78 } 79 80 tegra_set_control_data(ctx, NULL, id); 81} 82 83static int tegra_queue_setup(struct vb2_queue *vq, 84 unsigned int *nbufs, 85 unsigned int *num_planes, 86 unsigned int sizes[], 87 struct device *alloc_devs[]) 88{ 89 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 90 struct v4l2_format *f; 91 unsigned int i; 92 93 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 94 f = &ctx->coded_fmt; 95 else 96 f = &ctx->decoded_fmt; 97 98 if (*num_planes) { 99 if (*num_planes != f->fmt.pix_mp.num_planes) 100 return -EINVAL; 101 102 for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { 103 if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage) 104 return -EINVAL; 105 } 106 } else { 107 *num_planes = f->fmt.pix_mp.num_planes; 108 109 for (i = 0; i < f->fmt.pix_mp.num_planes; i++) 110 sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage; 111 } 112 113 return 0; 114} 115 116static int tegra_buf_out_validate(struct vb2_buffer *vb) 117{ 118 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 119 120 vbuf->field = V4L2_FIELD_NONE; 121 return 0; 122} 123 124static void __tegra_buf_cleanup(struct vb2_buffer *vb, unsigned int i) 125{ 126 struct vb2_queue *vq = vb->vb2_queue; 127 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 128 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 129 130 while (i--) { 131 if (tb->a[i]) { 132 tegra_vde_dmabuf_cache_unmap(ctx->vde, tb->a[i], true); 133 tb->a[i] = NULL; 134 } 135 136 if (tb->iova[i]) { 137 tegra_vde_iommu_unmap(ctx->vde, tb->iova[i]); 138 tb->iova[i] = NULL; 139 } 140 } 141 142 if (tb->aux) { 143 tegra_vde_free_bo(tb->aux); 144 tb->aux = NULL; 145 } 146} 147 148static int tegra_buf_init(struct vb2_buffer *vb) 149{ 150 struct vb2_queue *vq = vb->vb2_queue; 151 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 152 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 153 struct tegra_vde *vde = ctx->vde; 154 enum dma_data_direction dma_dir; 155 struct sg_table *sgt; 156 unsigned int i; 157 int err; 158 159 if (V4L2_TYPE_IS_CAPTURE(vq->type) && vb->num_planes > 1) { 160 /* 161 * Tegra decoder writes auxiliary data for I/P frames. 162 * This data is needed for decoding of B frames. 163 */ 164 err = tegra_vde_alloc_bo(vde, &tb->aux, DMA_FROM_DEVICE, 165 vb2_plane_size(vb, 1)); 166 if (err) 167 return err; 168 } 169 170 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 171 dma_dir = DMA_TO_DEVICE; 172 else 173 dma_dir = DMA_FROM_DEVICE; 174 175 for (i = 0; i < vb->num_planes; i++) { 176 if (vq->memory == VB2_MEMORY_DMABUF) { 177 get_dma_buf(vb->planes[i].dbuf); 178 179 err = tegra_vde_dmabuf_cache_map(vde, vb->planes[i].dbuf, 180 dma_dir, &tb->a[i], 181 &tb->dma_base[i]); 182 if (err) { 183 dma_buf_put(vb->planes[i].dbuf); 184 goto cleanup; 185 } 186 187 continue; 188 } 189 190 if (vde->domain) { 191 sgt = vb2_dma_sg_plane_desc(vb, i); 192 193 err = tegra_vde_iommu_map(vde, sgt, &tb->iova[i], 194 vb2_plane_size(vb, i)); 195 if (err) 196 goto cleanup; 197 198 tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]); 199 } else { 200 tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i); 201 } 202 } 203 204 return 0; 205 206cleanup: 207 __tegra_buf_cleanup(vb, i); 208 209 return err; 210} 211 212static void tegra_buf_cleanup(struct vb2_buffer *vb) 213{ 214 __tegra_buf_cleanup(vb, vb->num_planes); 215} 216 217static int tegra_buf_prepare(struct vb2_buffer *vb) 218{ 219 struct vb2_queue *vq = vb->vb2_queue; 220 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 221 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 222 size_t hw_align, hw_size, hw_payload, size, offset; 223 struct v4l2_pix_format_mplane *pixfmt; 224 unsigned int i; 225 void *vb_data; 226 227 if (V4L2_TYPE_IS_OUTPUT(vq->type)) { 228 hw_align = BSEV_ALIGN; 229 pixfmt = &ctx->coded_fmt.fmt.pix_mp; 230 } else { 231 hw_align = FRAMEID_ALIGN; 232 pixfmt = &ctx->decoded_fmt.fmt.pix_mp; 233 } 234 235 for (i = 0; i < vb->num_planes; i++) { 236 offset = vb->planes[i].data_offset; 237 238 if (offset & (hw_align - 1)) 239 return -EINVAL; 240 241 if (V4L2_TYPE_IS_CAPTURE(vq->type)) { 242 size = pixfmt->plane_fmt[i].sizeimage; 243 hw_payload = ALIGN(size, VDE_ATOM); 244 } else { 245 size = vb2_get_plane_payload(vb, i) - offset; 246 hw_payload = ALIGN(size + VDE_ATOM, SXE_BUFFER); 247 } 248 249 hw_size = offset + hw_payload; 250 251 if (vb2_plane_size(vb, i) < hw_size) 252 return -EINVAL; 253 254 vb2_set_plane_payload(vb, i, hw_payload); 255 256 if (V4L2_TYPE_IS_OUTPUT(vq->type)) { 257 vb_data = vb2_plane_vaddr(vb, i); 258 259 /* 260 * Hardware requires zero-padding of coded data. 261 * Otherwise it will fail to parse the trailing 262 * data and abort the decoding. 263 */ 264 if (vb_data) 265 memset(vb_data + offset + size, 0, 266 hw_size - offset - size); 267 } 268 269 tb->dma_addr[i] = tb->dma_base[i] + offset; 270 } 271 272 switch (pixfmt->pixelformat) { 273 case V4L2_PIX_FMT_YVU420M: 274 swap(tb->dma_addr[1], tb->dma_addr[2]); 275 break; 276 } 277 278 return 0; 279} 280 281static void tegra_buf_queue(struct vb2_buffer *vb) 282{ 283 struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 284 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 285 286 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 287} 288 289static void tegra_buf_request_complete(struct vb2_buffer *vb) 290{ 291 struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 292 293 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl); 294} 295 296static int tegra_start_streaming(struct vb2_queue *vq, unsigned int count) 297{ 298 return 0; 299} 300 301static void tegra_stop_streaming(struct vb2_queue *vq) 302{ 303 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 304 305 while (true) { 306 struct vb2_v4l2_buffer *vbuf; 307 308 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 309 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 310 else 311 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 312 313 if (!vbuf) 314 break; 315 316 v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &ctx->hdl); 317 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); 318 } 319} 320 321static const struct vb2_ops tegra_qops = { 322 .queue_setup = tegra_queue_setup, 323 .buf_init = tegra_buf_init, 324 .buf_cleanup = tegra_buf_cleanup, 325 .buf_prepare = tegra_buf_prepare, 326 .buf_queue = tegra_buf_queue, 327 .buf_out_validate = tegra_buf_out_validate, 328 .buf_request_complete = tegra_buf_request_complete, 329 .start_streaming = tegra_start_streaming, 330 .stop_streaming = tegra_stop_streaming, 331 .wait_prepare = vb2_ops_wait_prepare, 332 .wait_finish = vb2_ops_wait_finish, 333}; 334 335static int tegra_queue_init(void *priv, 336 struct vb2_queue *src_vq, 337 struct vb2_queue *dst_vq) 338{ 339 struct tegra_ctx *ctx = priv; 340 struct tegra_vde *vde = ctx->vde; 341 const struct vb2_mem_ops *mem_ops; 342 unsigned long dma_attrs; 343 int err; 344 345 /* 346 * TODO: Switch to use of vb2_dma_contig_memops uniformly once we 347 * will add IOMMU_DOMAIN support for video decoder to tegra-smmu 348 * driver. For now we need to stick with SG ops in order to be able 349 * to get SGT table easily. This is suboptimal since SG mappings are 350 * wasting CPU cache and we don't need that caching. 351 */ 352 if (vde->domain) 353 mem_ops = &vb2_dma_sg_memops; 354 else 355 mem_ops = &vb2_dma_contig_memops; 356 357 dma_attrs = DMA_ATTR_WRITE_COMBINE; 358 359 src_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); 360 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 361 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 362 src_vq->io_modes = VB2_DMABUF | VB2_MMAP; 363 src_vq->supports_requests = true; 364 src_vq->requires_requests = true; 365 src_vq->lock = &vde->v4l2_lock; 366 src_vq->dma_attrs = dma_attrs; 367 src_vq->mem_ops = mem_ops; 368 src_vq->ops = &tegra_qops; 369 src_vq->drv_priv = ctx; 370 src_vq->dev = vde->dev; 371 372 err = vb2_queue_init(src_vq); 373 if (err) { 374 v4l2_err(&vde->v4l2_dev, 375 "failed to initialize src queue: %d\n", err); 376 return err; 377 } 378 379 /* 380 * We may need to zero the end of bitstream in kernel if userspace 381 * doesn't do that, hence kmap is needed for the coded data. It's not 382 * needed for framebuffers. 383 */ 384 dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 385 386 dst_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); 387 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 388 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 389 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP; 390 dst_vq->lock = &vde->v4l2_lock; 391 dst_vq->dma_attrs = dma_attrs; 392 dst_vq->mem_ops = mem_ops; 393 dst_vq->ops = &tegra_qops; 394 dst_vq->drv_priv = ctx; 395 dst_vq->dev = vde->dev; 396 397 err = vb2_queue_init(dst_vq); 398 if (err) { 399 v4l2_err(&vde->v4l2_dev, 400 "failed to initialize dst queue: %d\n", err); 401 return err; 402 } 403 404 return 0; 405} 406 407static void tegra_reset_fmt(struct tegra_ctx *ctx, struct v4l2_format *f, 408 u32 fourcc) 409{ 410 memset(f, 0, sizeof(*f)); 411 f->fmt.pix_mp.pixelformat = fourcc; 412 f->fmt.pix_mp.field = V4L2_FIELD_NONE; 413 f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; 414 f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 415 f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; 416 f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; 417} 418 419static void tegra_reset_coded_fmt(struct tegra_ctx *ctx) 420{ 421 const struct tegra_vde_soc *soc = ctx->vde->soc; 422 struct v4l2_format *f = &ctx->coded_fmt; 423 424 ctx->coded_fmt_desc = &soc->coded_fmts[0]; 425 tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); 426 427 f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 428 f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width; 429 f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height; 430} 431 432static void tegra_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, 433 u32 pixelformat, u32 width, u32 height) 434{ 435 const struct v4l2_format_info *info = v4l2_format_info(pixelformat); 436 struct v4l2_plane_pix_format *plane; 437 unsigned int i; 438 439 switch (pixelformat) { 440 case V4L2_PIX_FMT_YUV420M: 441 case V4L2_PIX_FMT_YVU420M: 442 pixfmt->width = width; 443 pixfmt->height = height; 444 pixfmt->pixelformat = pixelformat; 445 pixfmt->num_planes = info->mem_planes; 446 447 for (i = 0; i < pixfmt->num_planes; i++) { 448 unsigned int hdiv = (i == 0) ? 1 : 2; 449 unsigned int vdiv = (i == 0) ? 1 : 2; 450 451 /* 452 * VDE is connected to Graphics Memory using 128bit port, 453 * all memory accesses are made using 16B atoms. 454 * 455 * V4L requires Cb/Cr strides to be exactly half of the 456 * Y stride, hence we're aligning Y to 16B x 2. 457 */ 458 plane = &pixfmt->plane_fmt[i]; 459 plane->bytesperline = ALIGN(width, VDE_ATOM * 2) / hdiv; 460 plane->sizeimage = plane->bytesperline * height / vdiv; 461 } 462 463 break; 464 } 465} 466 467static void tegra_reset_decoded_fmt(struct tegra_ctx *ctx) 468{ 469 struct v4l2_format *f = &ctx->decoded_fmt; 470 471 tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); 472 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 473 tegra_fill_pixfmt_mp(&f->fmt.pix_mp, 474 ctx->coded_fmt_desc->decoded_fmts[0], 475 ctx->coded_fmt.fmt.pix_mp.width, 476 ctx->coded_fmt.fmt.pix_mp.height); 477} 478 479static void tegra_job_finish(struct tegra_ctx *ctx, 480 enum vb2_buffer_state result) 481{ 482 v4l2_m2m_buf_done_and_job_finish(ctx->vde->m2m, ctx->fh.m2m_ctx, 483 result); 484} 485 486static void tegra_decode_complete(struct work_struct *work) 487{ 488 struct tegra_ctx *ctx = container_of(work, struct tegra_ctx, work); 489 int err; 490 491 err = ctx->coded_fmt_desc->decode_wait(ctx); 492 if (err) 493 tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); 494 else 495 tegra_job_finish(ctx, VB2_BUF_STATE_DONE); 496} 497 498static int tegra_querycap(struct file *file, void *priv, 499 struct v4l2_capability *cap) 500{ 501 strscpy(cap->bus_info, "platform:tegra-vde", sizeof(cap->bus_info)); 502 strscpy(cap->driver, "tegra-vde", sizeof(cap->driver)); 503 strscpy(cap->card, "tegra-vde", sizeof(cap->card)); 504 505 return 0; 506} 507 508static int tegra_enum_decoded_fmt(struct file *file, void *priv, 509 struct v4l2_fmtdesc *f) 510{ 511 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 512 513 if (WARN_ON(!ctx->coded_fmt_desc)) 514 return -EINVAL; 515 516 if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) 517 return -EINVAL; 518 519 f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; 520 521 return 0; 522} 523 524static int tegra_g_decoded_fmt(struct file *file, void *priv, 525 struct v4l2_format *f) 526{ 527 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 528 529 *f = ctx->decoded_fmt; 530 return 0; 531} 532 533static int tegra_try_decoded_fmt(struct file *file, void *priv, 534 struct v4l2_format *f) 535{ 536 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; 537 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 538 const struct tegra_coded_fmt_desc *coded_desc; 539 unsigned int i; 540 541 /* 542 * The codec context should point to a coded format desc, if the format 543 * on the coded end has not been set yet, it should point to the 544 * default value. 545 */ 546 coded_desc = ctx->coded_fmt_desc; 547 if (WARN_ON(!coded_desc)) 548 return -EINVAL; 549 550 if (!coded_desc->num_decoded_fmts) 551 return -EINVAL; 552 553 for (i = 0; i < coded_desc->num_decoded_fmts; i++) { 554 if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) 555 break; 556 } 557 558 if (i == coded_desc->num_decoded_fmts) 559 pix_mp->pixelformat = coded_desc->decoded_fmts[0]; 560 561 /* always apply the frmsize constraint of the coded end */ 562 v4l2_apply_frmsize_constraints(&pix_mp->width, 563 &pix_mp->height, 564 &coded_desc->frmsize); 565 566 tegra_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, 567 pix_mp->width, pix_mp->height); 568 pix_mp->field = V4L2_FIELD_NONE; 569 570 return 0; 571} 572 573static int tegra_s_decoded_fmt(struct file *file, void *priv, 574 struct v4l2_format *f) 575{ 576 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 577 struct vb2_queue *vq; 578 int err; 579 580 /* change not allowed if queue is busy */ 581 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 582 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 583 if (vb2_is_busy(vq)) 584 return -EBUSY; 585 586 err = tegra_try_decoded_fmt(file, priv, f); 587 if (err) 588 return err; 589 590 ctx->decoded_fmt = *f; 591 592 return 0; 593} 594 595static int tegra_enum_coded_fmt(struct file *file, void *priv, 596 struct v4l2_fmtdesc *f) 597{ 598 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 599 const struct tegra_vde_soc *soc = ctx->vde->soc; 600 601 if (f->index >= soc->num_coded_fmts) 602 return -EINVAL; 603 604 f->pixelformat = soc->coded_fmts[f->index].fourcc; 605 606 return 0; 607} 608 609static int tegra_g_coded_fmt(struct file *file, void *priv, 610 struct v4l2_format *f) 611{ 612 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 613 614 *f = ctx->coded_fmt; 615 return 0; 616} 617 618static const struct tegra_coded_fmt_desc * 619tegra_find_coded_fmt_desc(struct tegra_ctx *ctx, u32 fourcc) 620{ 621 const struct tegra_vde_soc *soc = ctx->vde->soc; 622 unsigned int i; 623 624 for (i = 0; i < soc->num_coded_fmts; i++) { 625 if (soc->coded_fmts[i].fourcc == fourcc) 626 return &soc->coded_fmts[i]; 627 } 628 629 return NULL; 630} 631 632static int tegra_try_coded_fmt(struct file *file, void *priv, 633 struct v4l2_format *f) 634{ 635 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; 636 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 637 const struct tegra_vde_soc *soc = ctx->vde->soc; 638 int size = pix_mp->plane_fmt[0].sizeimage; 639 const struct tegra_coded_fmt_desc *desc; 640 641 desc = tegra_find_coded_fmt_desc(ctx, pix_mp->pixelformat); 642 if (!desc) { 643 pix_mp->pixelformat = soc->coded_fmts[0].fourcc; 644 desc = &soc->coded_fmts[0]; 645 } 646 647 v4l2_apply_frmsize_constraints(&pix_mp->width, 648 &pix_mp->height, 649 &desc->frmsize); 650 651 pix_mp->plane_fmt[0].sizeimage = max(ALIGN(size, SXE_BUFFER), SZ_2M); 652 pix_mp->field = V4L2_FIELD_NONE; 653 pix_mp->num_planes = 1; 654 655 return 0; 656} 657 658static int tegra_s_coded_fmt(struct file *file, void *priv, 659 struct v4l2_format *f) 660{ 661 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 662 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 663 const struct tegra_coded_fmt_desc *desc; 664 struct vb2_queue *peer_vq, *vq; 665 struct v4l2_format *cap_fmt; 666 int err; 667 668 /* 669 * In order to support dynamic resolution change, the decoder admits 670 * a resolution change, as long as the pixelformat remains. Can't be 671 * done if streaming. 672 */ 673 vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 674 if (vb2_is_streaming(vq) || 675 (vb2_is_busy(vq) && 676 f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat)) 677 return -EBUSY; 678 679 /* 680 * Since format change on the OUTPUT queue will reset the CAPTURE 681 * queue, we can't allow doing so when the CAPTURE queue has buffers 682 * allocated. 683 */ 684 peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 685 if (vb2_is_busy(peer_vq)) 686 return -EBUSY; 687 688 err = tegra_try_coded_fmt(file, priv, f); 689 if (err) 690 return err; 691 692 desc = tegra_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); 693 if (!desc) 694 return -EINVAL; 695 696 ctx->coded_fmt_desc = desc; 697 ctx->coded_fmt = *f; 698 699 /* 700 * Current decoded format might have become invalid with newly 701 * selected codec, so reset it to default just to be safe and 702 * keep internal driver state sane. User is mandated to set 703 * the decoded format again after we return, so we don't need 704 * anything smarter. 705 * 706 * Note that this will propagates any size changes to the decoded format. 707 */ 708 tegra_reset_decoded_fmt(ctx); 709 710 /* propagate colorspace information to capture */ 711 cap_fmt = &ctx->decoded_fmt; 712 cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; 713 cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; 714 cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace; 715 cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; 716 717 return 0; 718} 719 720static int tegra_enum_framesizes(struct file *file, void *priv, 721 struct v4l2_frmsizeenum *fsize) 722{ 723 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 724 const struct tegra_coded_fmt_desc *fmt; 725 726 if (fsize->index) 727 return -EINVAL; 728 729 fmt = tegra_find_coded_fmt_desc(ctx, fsize->pixel_format); 730 if (!fmt) 731 return -EINVAL; 732 733 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 734 fsize->stepwise = fmt->frmsize; 735 736 return 0; 737} 738 739static const struct v4l2_ioctl_ops tegra_v4l2_ioctl_ops = { 740 .vidioc_querycap = tegra_querycap, 741 .vidioc_enum_framesizes = tegra_enum_framesizes, 742 743 .vidioc_try_fmt_vid_out_mplane = tegra_try_coded_fmt, 744 .vidioc_g_fmt_vid_out_mplane = tegra_g_coded_fmt, 745 .vidioc_s_fmt_vid_out_mplane = tegra_s_coded_fmt, 746 .vidioc_enum_fmt_vid_out = tegra_enum_coded_fmt, 747 748 .vidioc_try_fmt_vid_cap_mplane = tegra_try_decoded_fmt, 749 .vidioc_g_fmt_vid_cap_mplane = tegra_g_decoded_fmt, 750 .vidioc_s_fmt_vid_cap_mplane = tegra_s_decoded_fmt, 751 .vidioc_enum_fmt_vid_cap = tegra_enum_decoded_fmt, 752 753 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 754 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 755 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 756 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 757 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 758 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 759 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 760 761 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 762 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 763 764 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 765 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 766}; 767 768static int tegra_init_ctrls(struct tegra_ctx *ctx) 769{ 770 unsigned int i; 771 int err; 772 773 err = v4l2_ctrl_handler_init(&ctx->hdl, ARRAY_SIZE(ctrl_cfgs)); 774 if (err) 775 return err; 776 777 for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { 778 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->hdl, &ctrl_cfgs[i], 779 NULL); 780 if (ctx->hdl.error) { 781 err = ctx->hdl.error; 782 goto free_ctrls; 783 } 784 } 785 786 err = v4l2_ctrl_handler_setup(&ctx->hdl); 787 if (err) 788 goto free_ctrls; 789 790 ctx->fh.ctrl_handler = &ctx->hdl; 791 792 return 0; 793 794free_ctrls: 795 v4l2_ctrl_handler_free(&ctx->hdl); 796 797 return err; 798} 799 800static int tegra_init_m2m(struct tegra_ctx *ctx) 801{ 802 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ctx->vde->m2m, 803 ctx, tegra_queue_init); 804 if (IS_ERR(ctx->fh.m2m_ctx)) 805 return PTR_ERR(ctx->fh.m2m_ctx); 806 807 return 0; 808} 809 810static int tegra_open(struct file *file) 811{ 812 struct tegra_vde *vde = video_drvdata(file); 813 struct tegra_ctx *ctx; 814 int err; 815 816 ctx = kzalloc(offsetof(struct tegra_ctx, ctrls[ARRAY_SIZE(ctrl_cfgs)]), 817 GFP_KERNEL); 818 if (!ctx) 819 return -ENOMEM; 820 821 ctx->vde = vde; 822 v4l2_fh_init(&ctx->fh, video_devdata(file)); 823 INIT_WORK(&ctx->work, tegra_decode_complete); 824 825 err = tegra_init_ctrls(ctx); 826 if (err) { 827 v4l2_err(&vde->v4l2_dev, "failed to add controls: %d\n", err); 828 goto free_ctx; 829 } 830 831 err = tegra_init_m2m(ctx); 832 if (err) { 833 v4l2_err(&vde->v4l2_dev, "failed to initialize m2m: %d\n", err); 834 goto free_ctrls; 835 } 836 837 file->private_data = &ctx->fh; 838 v4l2_fh_add(&ctx->fh); 839 840 tegra_reset_coded_fmt(ctx); 841 tegra_try_coded_fmt(file, file->private_data, &ctx->coded_fmt); 842 843 tegra_reset_decoded_fmt(ctx); 844 tegra_try_decoded_fmt(file, file->private_data, &ctx->decoded_fmt); 845 846 return 0; 847 848free_ctrls: 849 v4l2_ctrl_handler_free(&ctx->hdl); 850free_ctx: 851 kfree(ctx); 852 853 return err; 854} 855 856static int tegra_release(struct file *file) 857{ 858 struct v4l2_fh *fh = file->private_data; 859 struct tegra_ctx *ctx = fh_to_tegra_ctx(fh); 860 struct tegra_vde *vde = ctx->vde; 861 862 v4l2_fh_del(fh); 863 v4l2_m2m_ctx_release(fh->m2m_ctx); 864 v4l2_ctrl_handler_free(&ctx->hdl); 865 v4l2_fh_exit(fh); 866 kfree(ctx); 867 868 tegra_vde_dmabuf_cache_unmap_sync(vde); 869 870 return 0; 871} 872 873static const struct v4l2_file_operations tegra_v4l2_fops = { 874 .owner = THIS_MODULE, 875 .open = tegra_open, 876 .poll = v4l2_m2m_fop_poll, 877 .mmap = v4l2_m2m_fop_mmap, 878 .release = tegra_release, 879 .unlocked_ioctl = video_ioctl2, 880}; 881 882static void tegra_device_run(void *priv) 883{ 884 struct tegra_ctx *ctx = priv; 885 struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 886 struct media_request *src_req = src->vb2_buf.req_obj.req; 887 int err; 888 889 v4l2_ctrl_request_setup(src_req, &ctx->hdl); 890 891 err = ctx->coded_fmt_desc->decode_run(ctx); 892 893 v4l2_ctrl_request_complete(src_req, &ctx->hdl); 894 895 if (err) 896 tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); 897 else 898 queue_work(ctx->vde->wq, &ctx->work); 899} 900 901static const struct v4l2_m2m_ops tegra_v4l2_m2m_ops = { 902 .device_run = tegra_device_run, 903}; 904 905static int tegra_request_validate(struct media_request *req) 906{ 907 unsigned int count; 908 909 count = vb2_request_buffer_cnt(req); 910 if (!count) 911 return -ENOENT; 912 else if (count > 1) 913 return -EINVAL; 914 915 return vb2_request_validate(req); 916} 917 918static const struct media_device_ops tegra_media_device_ops = { 919 .req_validate = tegra_request_validate, 920 .req_queue = v4l2_m2m_request_queue, 921}; 922 923int tegra_vde_v4l2_init(struct tegra_vde *vde) 924{ 925 struct device *dev = vde->dev; 926 int err; 927 928 mutex_init(&vde->v4l2_lock); 929 media_device_init(&vde->mdev); 930 video_set_drvdata(&vde->vdev, vde); 931 932 vde->vdev.lock = &vde->v4l2_lock, 933 vde->vdev.fops = &tegra_v4l2_fops, 934 vde->vdev.vfl_dir = VFL_DIR_M2M, 935 vde->vdev.release = video_device_release_empty, 936 vde->vdev.v4l2_dev = &vde->v4l2_dev; 937 vde->vdev.ioctl_ops = &tegra_v4l2_ioctl_ops, 938 vde->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, 939 940 vde->v4l2_dev.mdev = &vde->mdev; 941 vde->mdev.ops = &tegra_media_device_ops; 942 vde->mdev.dev = dev; 943 944 strscpy(vde->mdev.model, "tegra-vde", sizeof(vde->mdev.model)); 945 strscpy(vde->vdev.name, "tegra-vde", sizeof(vde->vdev.name)); 946 strscpy(vde->mdev.bus_info, "platform:tegra-vde", 947 sizeof(vde->mdev.bus_info)); 948 949 vde->wq = create_workqueue("tegra-vde"); 950 if (!vde->wq) 951 return -ENOMEM; 952 953 err = media_device_register(&vde->mdev); 954 if (err) { 955 dev_err(dev, "failed to register media device: %d\n", err); 956 goto clean_up_media_device; 957 } 958 959 err = v4l2_device_register(dev, &vde->v4l2_dev); 960 if (err) { 961 dev_err(dev, "failed to register v4l2 device: %d\n", err); 962 goto unreg_media_device; 963 } 964 965 err = video_register_device(&vde->vdev, VFL_TYPE_VIDEO, -1); 966 if (err) { 967 dev_err(dev, "failed to register video device: %d\n", err); 968 goto unreg_v4l2; 969 } 970 971 vde->m2m = v4l2_m2m_init(&tegra_v4l2_m2m_ops); 972 err = PTR_ERR_OR_ZERO(vde->m2m); 973 if (err) { 974 dev_err(dev, "failed to initialize m2m device: %d\n", err); 975 goto unreg_video_device; 976 } 977 978 err = v4l2_m2m_register_media_controller(vde->m2m, &vde->vdev, 979 MEDIA_ENT_F_PROC_VIDEO_DECODER); 980 if (err) { 981 dev_err(dev, "failed to register media controller: %d\n", err); 982 goto release_m2m; 983 } 984 985 v4l2_info(&vde->v4l2_dev, "v4l2 device registered as /dev/video%d\n", 986 vde->vdev.num); 987 988 return 0; 989 990release_m2m: 991 v4l2_m2m_release(vde->m2m); 992unreg_video_device: 993 video_unregister_device(&vde->vdev); 994unreg_v4l2: 995 v4l2_device_unregister(&vde->v4l2_dev); 996unreg_media_device: 997 media_device_unregister(&vde->mdev); 998clean_up_media_device: 999 media_device_cleanup(&vde->mdev); 1000 1001 destroy_workqueue(vde->wq); 1002 1003 return err; 1004} 1005 1006void tegra_vde_v4l2_deinit(struct tegra_vde *vde) 1007{ 1008 v4l2_m2m_unregister_media_controller(vde->m2m); 1009 v4l2_m2m_release(vde->m2m); 1010 1011 video_unregister_device(&vde->vdev); 1012 v4l2_device_unregister(&vde->v4l2_dev); 1013 1014 media_device_unregister(&vde->mdev); 1015 media_device_cleanup(&vde->mdev); 1016 1017 destroy_workqueue(vde->wq); 1018} 1019