1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Holmes Chiou <holmes.chiou@mediatek.com>
5 *         Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
6 */
7
8#ifndef __MTK_IMG_IPI_H__
9#define __MTK_IMG_IPI_H__
10
11#include <linux/err.h>
12#include "mdp_sm_mt8183.h"
13#include "mtk-mdp3-type.h"
14
15/* ISP-MDP generic input information */
16
17#define IMG_IPI_INIT    1
18#define IMG_IPI_DEINIT  2
19#define IMG_IPI_FRAME   3
20#define IMG_IPI_DEBUG   4
21
22struct img_timeval {
23	u32 tv_sec;
24	u32 tv_usec;
25} __packed;
26
27struct img_addr {
28	u64 va; /* Used for Linux OS access */
29	u32 pa; /* Used for CM4 access */
30	u32 iova; /* Used for IOMMU HW access */
31} __packed;
32
33struct tuning_addr {
34	u64	present;
35	u32	pa;	/* Used for CM4 access */
36	u32	iova;	/* Used for IOMMU HW access */
37} __packed;
38
39struct img_sw_addr {
40	u64 va; /* Used for APMCU access */
41	u32 pa; /* Used for CM4 access */
42} __packed;
43
44struct img_plane_format {
45	u32 size;
46	u32 stride;
47} __packed;
48
49struct img_pix_format {
50	u32 width;
51	u32 height;
52	u32 colorformat; /* enum mdp_color */
53	u32 ycbcr_prof; /* enum mdp_ycbcr_profile */
54	struct img_plane_format plane_fmt[IMG_MAX_PLANES];
55} __packed;
56
57struct img_image_buffer {
58	struct img_pix_format format;
59	u32 iova[IMG_MAX_PLANES];
60	/* enum mdp_buffer_usage, FD or advanced ISP usages */
61	u32 usage;
62} __packed;
63
64#define IMG_SUBPIXEL_SHIFT	20
65
66#define IMG_CTRL_FLAG_HFLIP	BIT(0)
67#define IMG_CTRL_FLAG_DITHER	BIT(1)
68#define IMG_CTRL_FLAG_SHARPNESS	BIT(4)
69#define IMG_CTRL_FLAG_HDR	BIT(5)
70#define IMG_CTRL_FLAG_DRE	BIT(6)
71
72struct img_input {
73	struct img_image_buffer buffer;
74	u32 flags; /* HDR, DRE, dither */
75} __packed;
76
77struct img_output {
78	struct img_image_buffer buffer;
79	struct img_crop crop;
80	s32 rotation;
81	u32 flags; /* H-flip, sharpness, dither */
82} __packed;
83
84struct img_ipi_frameparam {
85	u32 index;
86	u32 frame_no;
87	struct img_timeval timestamp;
88	u32 type; /* enum mdp_stream_type */
89	u32 state;
90	u32 num_inputs;
91	u32 num_outputs;
92	u64 drv_data;
93	struct img_input inputs[IMG_MAX_HW_INPUTS];
94	struct img_output outputs[IMG_MAX_HW_OUTPUTS];
95	struct tuning_addr tuning_data;
96	struct img_addr subfrm_data;
97	struct img_sw_addr config_data;
98	struct img_sw_addr self_data;
99} __packed;
100
101struct img_sw_buffer {
102	u64	handle;		/* Used for APMCU access */
103	u32	scp_addr;	/* Used for CM4 access */
104} __packed;
105
106struct img_ipi_param {
107	u32 usage;
108	struct img_sw_buffer frm_param;
109} __packed;
110
111struct img_frameparam {
112	struct list_head list_entry;
113	struct img_ipi_frameparam frameparam;
114} __packed;
115
116/* Platform config indicator */
117#define MT8183 8183
118
119#define CFG_CHECK(plat, p_id) ((plat) == (p_id))
120
121#define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst)))
122#define CFG_OFST(plat, cfg, ofst) \
123	(IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst))
124
125#define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem))
126#define CFG_ADDR(plat, cfg, mem) \
127	(IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem))
128
129#define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem)
130#define CFG_GET(plat, cfg, mem) \
131	(IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem))
132
133#define _CFG_COMP(plat, comp, mem) ((comp)->comp_##plat.mem)
134#define CFG_COMP(plat, comp, mem) \
135	(IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem))
136
137struct img_config {
138	union {
139		struct img_config_8183 config_8183;
140	};
141} __packed;
142
143struct img_compparam {
144	union {
145		struct img_compparam_8183 comp_8183;
146	};
147} __packed;
148
149#endif  /* __MTK_IMG_IPI_H__ */
150