1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ov5695 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 */
7
8#include <linux/clk.h>
9#include <linux/device.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/i2c.h>
13#include <linux/module.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/sysfs.h>
17#include <media/media-entity.h>
18#include <media/v4l2-async.h>
19#include <media/v4l2-ctrls.h>
20#include <media/v4l2-subdev.h>
21
22#ifndef V4L2_CID_DIGITAL_GAIN
23#define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
24#endif
25
26/* 45Mhz * 4 Binning */
27#define OV5695_PIXEL_RATE		(45 * 1000 * 1000 * 4)
28#define OV5695_XVCLK_FREQ		24000000
29
30#define CHIP_ID				0x005695
31#define OV5695_REG_CHIP_ID		0x300a
32
33#define OV5695_REG_CTRL_MODE		0x0100
34#define OV5695_MODE_SW_STANDBY		0x0
35#define OV5695_MODE_STREAMING		BIT(0)
36
37#define OV5695_REG_EXPOSURE		0x3500
38#define	OV5695_EXPOSURE_MIN		4
39#define	OV5695_EXPOSURE_STEP		1
40#define OV5695_VTS_MAX			0x7fff
41
42#define OV5695_REG_ANALOG_GAIN		0x3509
43#define	ANALOG_GAIN_MIN			0x10
44#define	ANALOG_GAIN_MAX			0xf8
45#define	ANALOG_GAIN_STEP		1
46#define	ANALOG_GAIN_DEFAULT		0xf8
47
48#define OV5695_REG_DIGI_GAIN_H		0x350a
49#define OV5695_REG_DIGI_GAIN_L		0x350b
50#define OV5695_DIGI_GAIN_L_MASK		0x3f
51#define OV5695_DIGI_GAIN_H_SHIFT	6
52#define OV5695_DIGI_GAIN_MIN		0
53#define OV5695_DIGI_GAIN_MAX		(0x4000 - 1)
54#define OV5695_DIGI_GAIN_STEP		1
55#define OV5695_DIGI_GAIN_DEFAULT	1024
56
57#define OV5695_REG_TEST_PATTERN		0x4503
58#define	OV5695_TEST_PATTERN_ENABLE	0x80
59#define	OV5695_TEST_PATTERN_DISABLE	0x0
60
61#define OV5695_REG_VTS			0x380e
62
63#define REG_NULL			0xFFFF
64
65#define OV5695_REG_VALUE_08BIT		1
66#define OV5695_REG_VALUE_16BIT		2
67#define OV5695_REG_VALUE_24BIT		3
68
69#define OV5695_LANES			2
70#define OV5695_BITS_PER_SAMPLE		10
71
72static const char * const ov5695_supply_names[] = {
73	"avdd",		/* Analog power */
74	"dovdd",	/* Digital I/O power */
75	"dvdd",		/* Digital core power */
76};
77
78#define OV5695_NUM_SUPPLIES ARRAY_SIZE(ov5695_supply_names)
79
80struct regval {
81	u16 addr;
82	u8 val;
83};
84
85struct ov5695_mode {
86	u32 width;
87	u32 height;
88	u32 max_fps;
89	u32 hts_def;
90	u32 vts_def;
91	u32 exp_def;
92	const struct regval *reg_list;
93};
94
95struct ov5695 {
96	struct i2c_client	*client;
97	struct clk		*xvclk;
98	struct gpio_desc	*reset_gpio;
99	struct regulator_bulk_data supplies[OV5695_NUM_SUPPLIES];
100
101	struct v4l2_subdev	subdev;
102	struct media_pad	pad;
103	struct v4l2_ctrl_handler ctrl_handler;
104	struct v4l2_ctrl	*exposure;
105	struct v4l2_ctrl	*anal_gain;
106	struct v4l2_ctrl	*digi_gain;
107	struct v4l2_ctrl	*hblank;
108	struct v4l2_ctrl	*vblank;
109	struct v4l2_ctrl	*test_pattern;
110	struct mutex		mutex;
111	bool			streaming;
112	const struct ov5695_mode *cur_mode;
113};
114
115#define to_ov5695(sd) container_of(sd, struct ov5695, subdev)
116
117/*
118 * Xclk 24Mhz
119 * Pclk 45Mhz
120 * linelength 672(0x2a0)
121 * framelength 2232(0x8b8)
122 * grabwindow_width 1296
123 * grabwindow_height 972
124 * max_framerate 30fps
125 * mipi_datarate per lane 840Mbps
126 */
127static const struct regval ov5695_global_regs[] = {
128	{0x0103, 0x01},
129	{0x0100, 0x00},
130	{0x0300, 0x04},
131	{0x0301, 0x00},
132	{0x0302, 0x69},
133	{0x0303, 0x00},
134	{0x0304, 0x00},
135	{0x0305, 0x01},
136	{0x0307, 0x00},
137	{0x030b, 0x00},
138	{0x030c, 0x00},
139	{0x030d, 0x1e},
140	{0x030e, 0x04},
141	{0x030f, 0x03},
142	{0x0312, 0x01},
143	{0x3000, 0x00},
144	{0x3002, 0xa1},
145	{0x3008, 0x00},
146	{0x3010, 0x00},
147	{0x3022, 0x51},
148	{0x3106, 0x15},
149	{0x3107, 0x01},
150	{0x3108, 0x05},
151	{0x3500, 0x00},
152	{0x3501, 0x45},
153	{0x3502, 0x00},
154	{0x3503, 0x08},
155	{0x3504, 0x03},
156	{0x3505, 0x8c},
157	{0x3507, 0x03},
158	{0x3508, 0x00},
159	{0x3509, 0x10},
160	{0x350c, 0x00},
161	{0x350d, 0x80},
162	{0x3510, 0x00},
163	{0x3511, 0x02},
164	{0x3512, 0x00},
165	{0x3601, 0x55},
166	{0x3602, 0x58},
167	{0x3614, 0x30},
168	{0x3615, 0x77},
169	{0x3621, 0x08},
170	{0x3624, 0x40},
171	{0x3633, 0x0c},
172	{0x3634, 0x0c},
173	{0x3635, 0x0c},
174	{0x3636, 0x0c},
175	{0x3638, 0x00},
176	{0x3639, 0x00},
177	{0x363a, 0x00},
178	{0x363b, 0x00},
179	{0x363c, 0xff},
180	{0x363d, 0xfa},
181	{0x3650, 0x44},
182	{0x3651, 0x44},
183	{0x3652, 0x44},
184	{0x3653, 0x44},
185	{0x3654, 0x44},
186	{0x3655, 0x44},
187	{0x3656, 0x44},
188	{0x3657, 0x44},
189	{0x3660, 0x00},
190	{0x3661, 0x00},
191	{0x3662, 0x00},
192	{0x366a, 0x00},
193	{0x366e, 0x0c},
194	{0x3673, 0x04},
195	{0x3700, 0x14},
196	{0x3703, 0x0c},
197	{0x3715, 0x01},
198	{0x3733, 0x10},
199	{0x3734, 0x40},
200	{0x373f, 0xa0},
201	{0x3765, 0x20},
202	{0x37a1, 0x1d},
203	{0x37a8, 0x26},
204	{0x37ab, 0x14},
205	{0x37c2, 0x04},
206	{0x37cb, 0x09},
207	{0x37cc, 0x13},
208	{0x37cd, 0x1f},
209	{0x37ce, 0x1f},
210	{0x3800, 0x00},
211	{0x3801, 0x00},
212	{0x3802, 0x00},
213	{0x3803, 0x00},
214	{0x3804, 0x0a},
215	{0x3805, 0x3f},
216	{0x3806, 0x07},
217	{0x3807, 0xaf},
218	{0x3808, 0x05},
219	{0x3809, 0x10},
220	{0x380a, 0x03},
221	{0x380b, 0xcc},
222	{0x380c, 0x02},
223	{0x380d, 0xa0},
224	{0x380e, 0x08},
225	{0x380f, 0xb8},
226	{0x3810, 0x00},
227	{0x3811, 0x06},
228	{0x3812, 0x00},
229	{0x3813, 0x06},
230	{0x3814, 0x03},
231	{0x3815, 0x01},
232	{0x3816, 0x03},
233	{0x3817, 0x01},
234	{0x3818, 0x00},
235	{0x3819, 0x00},
236	{0x381a, 0x00},
237	{0x381b, 0x01},
238	{0x3820, 0x8b},
239	{0x3821, 0x01},
240	{0x3c80, 0x08},
241	{0x3c82, 0x00},
242	{0x3c83, 0x00},
243	{0x3c88, 0x00},
244	{0x3d85, 0x14},
245	{0x3f02, 0x08},
246	{0x3f03, 0x10},
247	{0x4008, 0x02},
248	{0x4009, 0x09},
249	{0x404e, 0x20},
250	{0x4501, 0x00},
251	{0x4502, 0x10},
252	{0x4800, 0x00},
253	{0x481f, 0x2a},
254	{0x4837, 0x13},
255	{0x5000, 0x17},
256	{0x5780, 0x3e},
257	{0x5781, 0x0f},
258	{0x5782, 0x44},
259	{0x5783, 0x02},
260	{0x5784, 0x01},
261	{0x5785, 0x01},
262	{0x5786, 0x00},
263	{0x5787, 0x04},
264	{0x5788, 0x02},
265	{0x5789, 0x0f},
266	{0x578a, 0xfd},
267	{0x578b, 0xf5},
268	{0x578c, 0xf5},
269	{0x578d, 0x03},
270	{0x578e, 0x08},
271	{0x578f, 0x0c},
272	{0x5790, 0x08},
273	{0x5791, 0x06},
274	{0x5792, 0x00},
275	{0x5793, 0x52},
276	{0x5794, 0xa3},
277	{0x5b00, 0x00},
278	{0x5b01, 0x1c},
279	{0x5b02, 0x00},
280	{0x5b03, 0x7f},
281	{0x5b05, 0x6c},
282	{0x5e10, 0xfc},
283	{0x4010, 0xf1},
284	{0x3503, 0x08},
285	{0x3505, 0x8c},
286	{0x3507, 0x03},
287	{0x3508, 0x00},
288	{0x3509, 0xf8},
289	{REG_NULL, 0x00},
290};
291
292/*
293 * Xclk 24Mhz
294 * Pclk 45Mhz
295 * linelength 740(0x2e4)
296 * framelength 2024(0x7e8)
297 * grabwindow_width 2592
298 * grabwindow_height 1944
299 * max_framerate 30fps
300 * mipi_datarate per lane 840Mbps
301 */
302static const struct regval ov5695_2592x1944_regs[] = {
303	{0x3501, 0x7e},
304	{0x366e, 0x18},
305	{0x3800, 0x00},
306	{0x3801, 0x00},
307	{0x3802, 0x00},
308	{0x3803, 0x04},
309	{0x3804, 0x0a},
310	{0x3805, 0x3f},
311	{0x3806, 0x07},
312	{0x3807, 0xab},
313	{0x3808, 0x0a},
314	{0x3809, 0x20},
315	{0x380a, 0x07},
316	{0x380b, 0x98},
317	{0x380c, 0x02},
318	{0x380d, 0xe4},
319	{0x380e, 0x07},
320	{0x380f, 0xe8},
321	{0x3811, 0x06},
322	{0x3813, 0x08},
323	{0x3814, 0x01},
324	{0x3816, 0x01},
325	{0x3817, 0x01},
326	{0x3820, 0x88},
327	{0x3821, 0x00},
328	{0x4501, 0x00},
329	{0x4008, 0x04},
330	{0x4009, 0x13},
331	{REG_NULL, 0x00},
332};
333
334/*
335 * Xclk 24Mhz
336 * Pclk 45Mhz
337 * linelength 672(0x2a0)
338 * framelength 2232(0x8b8)
339 * grabwindow_width 1920
340 * grabwindow_height 1080
341 * max_framerate 30fps
342 * mipi_datarate per lane 840Mbps
343 */
344static const struct regval ov5695_1920x1080_regs[] = {
345	{0x3501, 0x45},
346	{0x366e, 0x18},
347	{0x3800, 0x01},
348	{0x3801, 0x50},
349	{0x3802, 0x01},
350	{0x3803, 0xb8},
351	{0x3804, 0x08},
352	{0x3805, 0xef},
353	{0x3806, 0x05},
354	{0x3807, 0xf7},
355	{0x3808, 0x07},
356	{0x3809, 0x80},
357	{0x380a, 0x04},
358	{0x380b, 0x38},
359	{0x380c, 0x02},
360	{0x380d, 0xa0},
361	{0x380e, 0x08},
362	{0x380f, 0xb8},
363	{0x3811, 0x06},
364	{0x3813, 0x04},
365	{0x3814, 0x01},
366	{0x3816, 0x01},
367	{0x3817, 0x01},
368	{0x3820, 0x88},
369	{0x3821, 0x00},
370	{0x4501, 0x00},
371	{0x4008, 0x04},
372	{0x4009, 0x13},
373	{REG_NULL, 0x00}
374};
375
376/*
377 * Xclk 24Mhz
378 * Pclk 45Mhz
379 * linelength 740(0x02e4)
380 * framelength 1012(0x03f4)
381 * grabwindow_width 1296
382 * grabwindow_height 972
383 * max_framerate 60fps
384 * mipi_datarate per lane 840Mbps
385 */
386static const struct regval ov5695_1296x972_regs[] = {
387	{0x0103, 0x01},
388	{0x0100, 0x00},
389	{0x0300, 0x04},
390	{0x0301, 0x00},
391	{0x0302, 0x69},
392	{0x0303, 0x00},
393	{0x0304, 0x00},
394	{0x0305, 0x01},
395	{0x0307, 0x00},
396	{0x030b, 0x00},
397	{0x030c, 0x00},
398	{0x030d, 0x1e},
399	{0x030e, 0x04},
400	{0x030f, 0x03},
401	{0x0312, 0x01},
402	{0x3000, 0x00},
403	{0x3002, 0xa1},
404	{0x3008, 0x00},
405	{0x3010, 0x00},
406	{0x3016, 0x32},
407	{0x3022, 0x51},
408	{0x3106, 0x15},
409	{0x3107, 0x01},
410	{0x3108, 0x05},
411	{0x3500, 0x00},
412	{0x3501, 0x3e},
413	{0x3502, 0x00},
414	{0x3503, 0x08},
415	{0x3504, 0x03},
416	{0x3505, 0x8c},
417	{0x3507, 0x03},
418	{0x3508, 0x00},
419	{0x3509, 0x10},
420	{0x350c, 0x00},
421	{0x350d, 0x80},
422	{0x3510, 0x00},
423	{0x3511, 0x02},
424	{0x3512, 0x00},
425	{0x3601, 0x55},
426	{0x3602, 0x58},
427	{0x3611, 0x58},
428	{0x3614, 0x30},
429	{0x3615, 0x77},
430	{0x3621, 0x08},
431	{0x3624, 0x40},
432	{0x3633, 0x0c},
433	{0x3634, 0x0c},
434	{0x3635, 0x0c},
435	{0x3636, 0x0c},
436	{0x3638, 0x00},
437	{0x3639, 0x00},
438	{0x363a, 0x00},
439	{0x363b, 0x00},
440	{0x363c, 0xff},
441	{0x363d, 0xfa},
442	{0x3650, 0x44},
443	{0x3651, 0x44},
444	{0x3652, 0x44},
445	{0x3653, 0x44},
446	{0x3654, 0x44},
447	{0x3655, 0x44},
448	{0x3656, 0x44},
449	{0x3657, 0x44},
450	{0x3660, 0x00},
451	{0x3661, 0x00},
452	{0x3662, 0x00},
453	{0x366a, 0x00},
454	{0x366e, 0x0c},
455	{0x3673, 0x04},
456	{0x3700, 0x14},
457	{0x3703, 0x0c},
458	{0x3706, 0x24},
459	{0x3714, 0x27},
460	{0x3715, 0x01},
461	{0x3716, 0x00},
462	{0x3717, 0x02},
463	{0x3733, 0x10},
464	{0x3734, 0x40},
465	{0x373f, 0xa0},
466	{0x3765, 0x20},
467	{0x37a1, 0x1d},
468	{0x37a8, 0x26},
469	{0x37ab, 0x14},
470	{0x37c2, 0x04},
471	{0x37c3, 0xf0},
472	{0x37cb, 0x09},
473	{0x37cc, 0x13},
474	{0x37cd, 0x1f},
475	{0x37ce, 0x1f},
476	{0x3800, 0x00},
477	{0x3801, 0x00},
478	{0x3802, 0x00},
479	{0x3803, 0x00},
480	{0x3804, 0x0a},
481	{0x3805, 0x3f},
482	{0x3806, 0x07},
483	{0x3807, 0xaf},
484	{0x3808, 0x05},
485	{0x3809, 0x10},
486	{0x380a, 0x03},
487	{0x380b, 0xcc},
488	{0x380c, 0x02},
489	{0x380d, 0xe4},
490	{0x380e, 0x03},
491	{0x380f, 0xf4},
492	{0x3810, 0x00},
493	{0x3811, 0x00},
494	{0x3812, 0x00},
495	{0x3813, 0x06},
496	{0x3814, 0x03},
497	{0x3815, 0x01},
498	{0x3816, 0x03},
499	{0x3817, 0x01},
500	{0x3818, 0x00},
501	{0x3819, 0x00},
502	{0x381a, 0x00},
503	{0x381b, 0x01},
504	{0x3820, 0x8b},
505	{0x3821, 0x01},
506	{0x3c80, 0x08},
507	{0x3c82, 0x00},
508	{0x3c83, 0x00},
509	{0x3c88, 0x00},
510	{0x3d85, 0x14},
511	{0x3f02, 0x08},
512	{0x3f03, 0x10},
513	{0x4008, 0x02},
514	{0x4009, 0x09},
515	{0x404e, 0x20},
516	{0x4501, 0x00},
517	{0x4502, 0x10},
518	{0x4800, 0x00},
519	{0x481f, 0x2a},
520	{0x4837, 0x13},
521	{0x5000, 0x13},
522	{0x5780, 0x3e},
523	{0x5781, 0x0f},
524	{0x5782, 0x44},
525	{0x5783, 0x02},
526	{0x5784, 0x01},
527	{0x5785, 0x01},
528	{0x5786, 0x00},
529	{0x5787, 0x04},
530	{0x5788, 0x02},
531	{0x5789, 0x0f},
532	{0x578a, 0xfd},
533	{0x578b, 0xf5},
534	{0x578c, 0xf5},
535	{0x578d, 0x03},
536	{0x578e, 0x08},
537	{0x578f, 0x0c},
538	{0x5790, 0x08},
539	{0x5791, 0x06},
540	{0x5792, 0x00},
541	{0x5793, 0x52},
542	{0x5794, 0xa3},
543	{0x5b00, 0x00},
544	{0x5b01, 0x1c},
545	{0x5b02, 0x00},
546	{0x5b03, 0x7f},
547	{0x5b05, 0x6c},
548	{0x5e10, 0xfc},
549	{0x4010, 0xf1},
550	{0x3503, 0x08},
551	{0x3505, 0x8c},
552	{0x3507, 0x03},
553	{0x3508, 0x00},
554	{0x3509, 0xf8},
555	{0x0100, 0x01},
556	{REG_NULL, 0x00}
557};
558
559/*
560 * Xclk 24Mhz
561 * Pclk 45Mhz
562 * linelength 672(0x2a0)
563 * framelength 2232(0x8b8)
564 * grabwindow_width 1280
565 * grabwindow_height 720
566 * max_framerate 30fps
567 * mipi_datarate per lane 840Mbps
568 */
569static const struct regval ov5695_1280x720_regs[] = {
570	{0x3501, 0x45},
571	{0x366e, 0x0c},
572	{0x3800, 0x00},
573	{0x3801, 0x00},
574	{0x3802, 0x01},
575	{0x3803, 0x00},
576	{0x3804, 0x0a},
577	{0x3805, 0x3f},
578	{0x3806, 0x06},
579	{0x3807, 0xaf},
580	{0x3808, 0x05},
581	{0x3809, 0x00},
582	{0x380a, 0x02},
583	{0x380b, 0xd0},
584	{0x380c, 0x02},
585	{0x380d, 0xa0},
586	{0x380e, 0x08},
587	{0x380f, 0xb8},
588	{0x3811, 0x06},
589	{0x3813, 0x02},
590	{0x3814, 0x03},
591	{0x3816, 0x03},
592	{0x3817, 0x01},
593	{0x3820, 0x8b},
594	{0x3821, 0x01},
595	{0x4501, 0x00},
596	{0x4008, 0x02},
597	{0x4009, 0x09},
598	{REG_NULL, 0x00}
599};
600
601/*
602 * Xclk 24Mhz
603 * Pclk 45Mhz
604 * linelength 672(0x2a0)
605 * framelength 558(0x22e)
606 * grabwindow_width 640
607 * grabwindow_height 480
608 * max_framerate 120fps
609 * mipi_datarate per lane 840Mbps
610 */
611static const struct regval ov5695_640x480_regs[] = {
612	{0x3501, 0x22},
613	{0x366e, 0x0c},
614	{0x3800, 0x00},
615	{0x3801, 0x00},
616	{0x3802, 0x00},
617	{0x3803, 0x08},
618	{0x3804, 0x0a},
619	{0x3805, 0x3f},
620	{0x3806, 0x07},
621	{0x3807, 0xa7},
622	{0x3808, 0x02},
623	{0x3809, 0x80},
624	{0x380a, 0x01},
625	{0x380b, 0xe0},
626	{0x380c, 0x02},
627	{0x380d, 0xa0},
628	{0x380e, 0x02},
629	{0x380f, 0x2e},
630	{0x3811, 0x06},
631	{0x3813, 0x04},
632	{0x3814, 0x07},
633	{0x3816, 0x05},
634	{0x3817, 0x03},
635	{0x3820, 0x8d},
636	{0x3821, 0x01},
637	{0x4501, 0x00},
638	{0x4008, 0x02},
639	{0x4009, 0x09},
640	{REG_NULL, 0x00}
641};
642
643static const struct ov5695_mode supported_modes[] = {
644	{
645		.width = 2592,
646		.height = 1944,
647		.max_fps = 30,
648		.exp_def = 0x0450,
649		.hts_def = 0x02e4 * 4,
650		.vts_def = 0x07e8,
651		.reg_list = ov5695_2592x1944_regs,
652	},
653	{
654		.width = 1920,
655		.height = 1080,
656		.max_fps = 30,
657		.exp_def = 0x0450,
658		.hts_def = 0x02a0 * 4,
659		.vts_def = 0x08b8,
660		.reg_list = ov5695_1920x1080_regs,
661	},
662	{
663		.width = 1296,
664		.height = 972,
665		.max_fps = 60,
666		.exp_def = 0x03e0,
667		.hts_def = 0x02e4 * 4,
668		.vts_def = 0x03f4,
669		.reg_list = ov5695_1296x972_regs,
670	},
671	{
672		.width = 1280,
673		.height = 720,
674		.max_fps = 30,
675		.exp_def = 0x0450,
676		.hts_def = 0x02a0 * 4,
677		.vts_def = 0x08b8,
678		.reg_list = ov5695_1280x720_regs,
679	},
680	{
681		.width = 640,
682		.height = 480,
683		.max_fps = 120,
684		.exp_def = 0x0450,
685		.hts_def = 0x02a0 * 4,
686		.vts_def = 0x022e,
687		.reg_list = ov5695_640x480_regs,
688	},
689};
690
691#define OV5695_LINK_FREQ_420MHZ		420000000
692static const s64 link_freq_menu_items[] = {
693	OV5695_LINK_FREQ_420MHZ
694};
695
696static const char * const ov5695_test_pattern_menu[] = {
697	"Disabled",
698	"Vertical Color Bar Type 1",
699	"Vertical Color Bar Type 2",
700	"Vertical Color Bar Type 3",
701	"Vertical Color Bar Type 4"
702};
703
704/* Write registers up to 4 at a time */
705static int ov5695_write_reg(struct i2c_client *client, u16 reg,
706			    u32 len, u32 val)
707{
708	u32 buf_i, val_i;
709	u8 buf[6];
710	u8 *val_p;
711	__be32 val_be;
712
713	if (len > 4)
714		return -EINVAL;
715
716	buf[0] = reg >> 8;
717	buf[1] = reg & 0xff;
718
719	val_be = cpu_to_be32(val);
720	val_p = (u8 *)&val_be;
721	buf_i = 2;
722	val_i = 4 - len;
723
724	while (val_i < 4)
725		buf[buf_i++] = val_p[val_i++];
726
727	if (i2c_master_send(client, buf, len + 2) != len + 2)
728		return -EIO;
729
730	return 0;
731}
732
733static int ov5695_write_array(struct i2c_client *client,
734			      const struct regval *regs)
735{
736	u32 i;
737	int ret = 0;
738
739	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
740		ret = ov5695_write_reg(client, regs[i].addr,
741				       OV5695_REG_VALUE_08BIT, regs[i].val);
742
743	return ret;
744}
745
746/* Read registers up to 4 at a time */
747static int ov5695_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
748			   u32 *val)
749{
750	struct i2c_msg msgs[2];
751	u8 *data_be_p;
752	__be32 data_be = 0;
753	__be16 reg_addr_be = cpu_to_be16(reg);
754	int ret;
755
756	if (len > 4)
757		return -EINVAL;
758
759	data_be_p = (u8 *)&data_be;
760	/* Write register address */
761	msgs[0].addr = client->addr;
762	msgs[0].flags = 0;
763	msgs[0].len = 2;
764	msgs[0].buf = (u8 *)&reg_addr_be;
765
766	/* Read data from register */
767	msgs[1].addr = client->addr;
768	msgs[1].flags = I2C_M_RD;
769	msgs[1].len = len;
770	msgs[1].buf = &data_be_p[4 - len];
771
772	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
773	if (ret != ARRAY_SIZE(msgs))
774		return -EIO;
775
776	*val = be32_to_cpu(data_be);
777
778	return 0;
779}
780
781static int ov5695_get_reso_dist(const struct ov5695_mode *mode,
782				struct v4l2_mbus_framefmt *framefmt)
783{
784	return abs(mode->width - framefmt->width) +
785	       abs(mode->height - framefmt->height);
786}
787
788static const struct ov5695_mode *
789ov5695_find_best_fit(struct v4l2_subdev_format *fmt)
790{
791	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
792	int dist;
793	int cur_best_fit = 0;
794	int cur_best_fit_dist = -1;
795	int i;
796
797	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
798		dist = ov5695_get_reso_dist(&supported_modes[i], framefmt);
799		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
800			cur_best_fit_dist = dist;
801			cur_best_fit = i;
802		}
803	}
804
805	return &supported_modes[cur_best_fit];
806}
807
808static int ov5695_set_fmt(struct v4l2_subdev *sd,
809			  struct v4l2_subdev_state *sd_state,
810			  struct v4l2_subdev_format *fmt)
811{
812	struct ov5695 *ov5695 = to_ov5695(sd);
813	const struct ov5695_mode *mode;
814	s64 h_blank, vblank_def;
815
816	mutex_lock(&ov5695->mutex);
817
818	mode = ov5695_find_best_fit(fmt);
819	fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
820	fmt->format.width = mode->width;
821	fmt->format.height = mode->height;
822	fmt->format.field = V4L2_FIELD_NONE;
823	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
824#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
825		*v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
826#endif
827	} else {
828		ov5695->cur_mode = mode;
829		h_blank = mode->hts_def - mode->width;
830		__v4l2_ctrl_modify_range(ov5695->hblank, h_blank,
831					 h_blank, 1, h_blank);
832		vblank_def = mode->vts_def - mode->height;
833		__v4l2_ctrl_modify_range(ov5695->vblank, vblank_def,
834					 OV5695_VTS_MAX - mode->height,
835					 1, vblank_def);
836	}
837
838	mutex_unlock(&ov5695->mutex);
839
840	return 0;
841}
842
843static int ov5695_get_fmt(struct v4l2_subdev *sd,
844			  struct v4l2_subdev_state *sd_state,
845			  struct v4l2_subdev_format *fmt)
846{
847	struct ov5695 *ov5695 = to_ov5695(sd);
848	const struct ov5695_mode *mode = ov5695->cur_mode;
849
850	mutex_lock(&ov5695->mutex);
851	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
852#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
853		fmt->format = *v4l2_subdev_get_try_format(sd, sd_state,
854							  fmt->pad);
855#else
856		mutex_unlock(&ov5695->mutex);
857		return -EINVAL;
858#endif
859	} else {
860		fmt->format.width = mode->width;
861		fmt->format.height = mode->height;
862		fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
863		fmt->format.field = V4L2_FIELD_NONE;
864	}
865	mutex_unlock(&ov5695->mutex);
866
867	return 0;
868}
869
870static int ov5695_enum_mbus_code(struct v4l2_subdev *sd,
871				 struct v4l2_subdev_state *sd_state,
872				 struct v4l2_subdev_mbus_code_enum *code)
873{
874	if (code->index != 0)
875		return -EINVAL;
876	code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
877
878	return 0;
879}
880
881static int ov5695_enum_frame_sizes(struct v4l2_subdev *sd,
882				   struct v4l2_subdev_state *sd_state,
883				   struct v4l2_subdev_frame_size_enum *fse)
884{
885	if (fse->index >= ARRAY_SIZE(supported_modes))
886		return -EINVAL;
887
888	if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
889		return -EINVAL;
890
891	fse->min_width  = supported_modes[fse->index].width;
892	fse->max_width  = supported_modes[fse->index].width;
893	fse->max_height = supported_modes[fse->index].height;
894	fse->min_height = supported_modes[fse->index].height;
895
896	return 0;
897}
898
899static int ov5695_enable_test_pattern(struct ov5695 *ov5695, u32 pattern)
900{
901	u32 val;
902
903	if (pattern)
904		val = (pattern - 1) | OV5695_TEST_PATTERN_ENABLE;
905	else
906		val = OV5695_TEST_PATTERN_DISABLE;
907
908	return ov5695_write_reg(ov5695->client, OV5695_REG_TEST_PATTERN,
909				OV5695_REG_VALUE_08BIT, val);
910}
911
912static int __ov5695_start_stream(struct ov5695 *ov5695)
913{
914	int ret;
915
916	ret = ov5695_write_array(ov5695->client, ov5695_global_regs);
917	if (ret)
918		return ret;
919	ret = ov5695_write_array(ov5695->client, ov5695->cur_mode->reg_list);
920	if (ret)
921		return ret;
922
923	/* In case these controls are set before streaming */
924	ret = __v4l2_ctrl_handler_setup(&ov5695->ctrl_handler);
925	if (ret)
926		return ret;
927
928	return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
929				OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
930}
931
932static int __ov5695_stop_stream(struct ov5695 *ov5695)
933{
934	return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
935				OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
936}
937
938static int ov5695_s_stream(struct v4l2_subdev *sd, int on)
939{
940	struct ov5695 *ov5695 = to_ov5695(sd);
941	struct i2c_client *client = ov5695->client;
942	int ret = 0;
943
944	mutex_lock(&ov5695->mutex);
945	on = !!on;
946	if (on == ov5695->streaming)
947		goto unlock_and_return;
948
949	if (on) {
950		ret = pm_runtime_resume_and_get(&client->dev);
951		if (ret < 0)
952			goto unlock_and_return;
953
954		ret = __ov5695_start_stream(ov5695);
955		if (ret) {
956			v4l2_err(sd, "start stream failed while write regs\n");
957			pm_runtime_put(&client->dev);
958			goto unlock_and_return;
959		}
960	} else {
961		__ov5695_stop_stream(ov5695);
962		pm_runtime_put(&client->dev);
963	}
964
965	ov5695->streaming = on;
966
967unlock_and_return:
968	mutex_unlock(&ov5695->mutex);
969
970	return ret;
971}
972
973static int __ov5695_power_on(struct ov5695 *ov5695)
974{
975	int i, ret;
976	struct device *dev = &ov5695->client->dev;
977
978	ret = clk_prepare_enable(ov5695->xvclk);
979	if (ret < 0) {
980		dev_err(dev, "Failed to enable xvclk\n");
981		return ret;
982	}
983
984	gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
985
986	/*
987	 * The hardware requires the regulators to be powered on in order,
988	 * so enable them one by one.
989	 */
990	for (i = 0; i < OV5695_NUM_SUPPLIES; i++) {
991		ret = regulator_enable(ov5695->supplies[i].consumer);
992		if (ret) {
993			dev_err(dev, "Failed to enable %s: %d\n",
994				ov5695->supplies[i].supply, ret);
995			goto disable_reg_clk;
996		}
997	}
998
999	gpiod_set_value_cansleep(ov5695->reset_gpio, 0);
1000
1001	usleep_range(1000, 1200);
1002
1003	return 0;
1004
1005disable_reg_clk:
1006	for (--i; i >= 0; i--)
1007		regulator_disable(ov5695->supplies[i].consumer);
1008	clk_disable_unprepare(ov5695->xvclk);
1009
1010	return ret;
1011}
1012
1013static void __ov5695_power_off(struct ov5695 *ov5695)
1014{
1015	struct device *dev = &ov5695->client->dev;
1016	int i, ret;
1017
1018	clk_disable_unprepare(ov5695->xvclk);
1019	gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
1020
1021	/*
1022	 * The hardware requires the regulators to be powered off in order,
1023	 * so disable them one by one.
1024	 */
1025	for (i = OV5695_NUM_SUPPLIES - 1; i >= 0; i--) {
1026		ret = regulator_disable(ov5695->supplies[i].consumer);
1027		if (ret)
1028			dev_err(dev, "Failed to disable %s: %d\n",
1029				ov5695->supplies[i].supply, ret);
1030	}
1031}
1032
1033static int __maybe_unused ov5695_runtime_resume(struct device *dev)
1034{
1035	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1036	struct ov5695 *ov5695 = to_ov5695(sd);
1037
1038	return __ov5695_power_on(ov5695);
1039}
1040
1041static int __maybe_unused ov5695_runtime_suspend(struct device *dev)
1042{
1043	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1044	struct ov5695 *ov5695 = to_ov5695(sd);
1045
1046	__ov5695_power_off(ov5695);
1047
1048	return 0;
1049}
1050
1051#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1052static int ov5695_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1053{
1054	struct ov5695 *ov5695 = to_ov5695(sd);
1055	struct v4l2_mbus_framefmt *try_fmt =
1056				v4l2_subdev_get_try_format(sd, fh->state, 0);
1057	const struct ov5695_mode *def_mode = &supported_modes[0];
1058
1059	mutex_lock(&ov5695->mutex);
1060	/* Initialize try_fmt */
1061	try_fmt->width = def_mode->width;
1062	try_fmt->height = def_mode->height;
1063	try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1064	try_fmt->field = V4L2_FIELD_NONE;
1065
1066	mutex_unlock(&ov5695->mutex);
1067	/* No crop or compose */
1068
1069	return 0;
1070}
1071#endif
1072
1073static const struct dev_pm_ops ov5695_pm_ops = {
1074	SET_RUNTIME_PM_OPS(ov5695_runtime_suspend,
1075			   ov5695_runtime_resume, NULL)
1076};
1077
1078#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1079static const struct v4l2_subdev_internal_ops ov5695_internal_ops = {
1080	.open = ov5695_open,
1081};
1082#endif
1083
1084static const struct v4l2_subdev_video_ops ov5695_video_ops = {
1085	.s_stream = ov5695_s_stream,
1086};
1087
1088static const struct v4l2_subdev_pad_ops ov5695_pad_ops = {
1089	.enum_mbus_code = ov5695_enum_mbus_code,
1090	.enum_frame_size = ov5695_enum_frame_sizes,
1091	.get_fmt = ov5695_get_fmt,
1092	.set_fmt = ov5695_set_fmt,
1093};
1094
1095static const struct v4l2_subdev_ops ov5695_subdev_ops = {
1096	.video	= &ov5695_video_ops,
1097	.pad	= &ov5695_pad_ops,
1098};
1099
1100static int ov5695_set_ctrl(struct v4l2_ctrl *ctrl)
1101{
1102	struct ov5695 *ov5695 = container_of(ctrl->handler,
1103					     struct ov5695, ctrl_handler);
1104	struct i2c_client *client = ov5695->client;
1105	s64 max;
1106	int ret = 0;
1107
1108	/* Propagate change of current control to all related controls */
1109	switch (ctrl->id) {
1110	case V4L2_CID_VBLANK:
1111		/* Update max exposure while meeting expected vblanking */
1112		max = ov5695->cur_mode->height + ctrl->val - 4;
1113		__v4l2_ctrl_modify_range(ov5695->exposure,
1114					 ov5695->exposure->minimum, max,
1115					 ov5695->exposure->step,
1116					 ov5695->exposure->default_value);
1117		break;
1118	}
1119
1120	if (!pm_runtime_get_if_in_use(&client->dev))
1121		return 0;
1122
1123	switch (ctrl->id) {
1124	case V4L2_CID_EXPOSURE:
1125		/* 4 least significant bits of exposure are fractional part */
1126		ret = ov5695_write_reg(ov5695->client, OV5695_REG_EXPOSURE,
1127				       OV5695_REG_VALUE_24BIT, ctrl->val << 4);
1128		break;
1129	case V4L2_CID_ANALOGUE_GAIN:
1130		ret = ov5695_write_reg(ov5695->client, OV5695_REG_ANALOG_GAIN,
1131				       OV5695_REG_VALUE_08BIT, ctrl->val);
1132		break;
1133	case V4L2_CID_DIGITAL_GAIN:
1134		ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_L,
1135				       OV5695_REG_VALUE_08BIT,
1136				       ctrl->val & OV5695_DIGI_GAIN_L_MASK);
1137		ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_H,
1138				       OV5695_REG_VALUE_08BIT,
1139				       ctrl->val >> OV5695_DIGI_GAIN_H_SHIFT);
1140		break;
1141	case V4L2_CID_VBLANK:
1142		ret = ov5695_write_reg(ov5695->client, OV5695_REG_VTS,
1143				       OV5695_REG_VALUE_16BIT,
1144				       ctrl->val + ov5695->cur_mode->height);
1145		break;
1146	case V4L2_CID_TEST_PATTERN:
1147		ret = ov5695_enable_test_pattern(ov5695, ctrl->val);
1148		break;
1149	default:
1150		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1151			 __func__, ctrl->id, ctrl->val);
1152		break;
1153	}
1154
1155	pm_runtime_put(&client->dev);
1156
1157	return ret;
1158}
1159
1160static const struct v4l2_ctrl_ops ov5695_ctrl_ops = {
1161	.s_ctrl = ov5695_set_ctrl,
1162};
1163
1164static int ov5695_initialize_controls(struct ov5695 *ov5695)
1165{
1166	const struct ov5695_mode *mode;
1167	struct v4l2_ctrl_handler *handler;
1168	struct v4l2_ctrl *ctrl;
1169	s64 exposure_max, vblank_def;
1170	u32 h_blank;
1171	int ret;
1172
1173	handler = &ov5695->ctrl_handler;
1174	mode = ov5695->cur_mode;
1175	ret = v4l2_ctrl_handler_init(handler, 8);
1176	if (ret)
1177		return ret;
1178	handler->lock = &ov5695->mutex;
1179
1180	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1181				      0, 0, link_freq_menu_items);
1182	if (ctrl)
1183		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1184
1185	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1186			  0, OV5695_PIXEL_RATE, 1, OV5695_PIXEL_RATE);
1187
1188	h_blank = mode->hts_def - mode->width;
1189	ov5695->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1190				h_blank, h_blank, 1, h_blank);
1191	if (ov5695->hblank)
1192		ov5695->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1193
1194	vblank_def = mode->vts_def - mode->height;
1195	ov5695->vblank = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1196				V4L2_CID_VBLANK, vblank_def,
1197				OV5695_VTS_MAX - mode->height,
1198				1, vblank_def);
1199
1200	exposure_max = mode->vts_def - 4;
1201	ov5695->exposure = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1202				V4L2_CID_EXPOSURE, OV5695_EXPOSURE_MIN,
1203				exposure_max, OV5695_EXPOSURE_STEP,
1204				mode->exp_def);
1205
1206	ov5695->anal_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1207				V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1208				ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1209				ANALOG_GAIN_DEFAULT);
1210
1211	/* Digital gain */
1212	ov5695->digi_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1213				V4L2_CID_DIGITAL_GAIN, OV5695_DIGI_GAIN_MIN,
1214				OV5695_DIGI_GAIN_MAX, OV5695_DIGI_GAIN_STEP,
1215				OV5695_DIGI_GAIN_DEFAULT);
1216
1217	ov5695->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1218				&ov5695_ctrl_ops, V4L2_CID_TEST_PATTERN,
1219				ARRAY_SIZE(ov5695_test_pattern_menu) - 1,
1220				0, 0, ov5695_test_pattern_menu);
1221
1222	if (handler->error) {
1223		ret = handler->error;
1224		dev_err(&ov5695->client->dev,
1225			"Failed to init controls(%d)\n", ret);
1226		goto err_free_handler;
1227	}
1228
1229	ov5695->subdev.ctrl_handler = handler;
1230
1231	return 0;
1232
1233err_free_handler:
1234	v4l2_ctrl_handler_free(handler);
1235
1236	return ret;
1237}
1238
1239static int ov5695_check_sensor_id(struct ov5695 *ov5695,
1240				  struct i2c_client *client)
1241{
1242	struct device *dev = &ov5695->client->dev;
1243	u32 id = 0;
1244	int ret;
1245
1246	ret = ov5695_read_reg(client, OV5695_REG_CHIP_ID,
1247			      OV5695_REG_VALUE_24BIT, &id);
1248	if (id != CHIP_ID) {
1249		dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1250		return ret;
1251	}
1252
1253	dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1254
1255	return 0;
1256}
1257
1258static int ov5695_configure_regulators(struct ov5695 *ov5695)
1259{
1260	int i;
1261
1262	for (i = 0; i < OV5695_NUM_SUPPLIES; i++)
1263		ov5695->supplies[i].supply = ov5695_supply_names[i];
1264
1265	return devm_regulator_bulk_get(&ov5695->client->dev,
1266				       OV5695_NUM_SUPPLIES,
1267				       ov5695->supplies);
1268}
1269
1270static int ov5695_probe(struct i2c_client *client)
1271{
1272	struct device *dev = &client->dev;
1273	struct ov5695 *ov5695;
1274	struct v4l2_subdev *sd;
1275	int ret;
1276
1277	ov5695 = devm_kzalloc(dev, sizeof(*ov5695), GFP_KERNEL);
1278	if (!ov5695)
1279		return -ENOMEM;
1280
1281	ov5695->client = client;
1282	ov5695->cur_mode = &supported_modes[0];
1283
1284	ov5695->xvclk = devm_clk_get(dev, "xvclk");
1285	if (IS_ERR(ov5695->xvclk)) {
1286		dev_err(dev, "Failed to get xvclk\n");
1287		return -EINVAL;
1288	}
1289	ret = clk_set_rate(ov5695->xvclk, OV5695_XVCLK_FREQ);
1290	if (ret < 0) {
1291		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1292		return ret;
1293	}
1294	if (clk_get_rate(ov5695->xvclk) != OV5695_XVCLK_FREQ)
1295		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1296
1297	ov5695->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1298	if (IS_ERR(ov5695->reset_gpio)) {
1299		dev_err(dev, "Failed to get reset-gpios\n");
1300		return -EINVAL;
1301	}
1302
1303	ret = ov5695_configure_regulators(ov5695);
1304	if (ret) {
1305		dev_err(dev, "Failed to get power regulators\n");
1306		return ret;
1307	}
1308
1309	mutex_init(&ov5695->mutex);
1310
1311	sd = &ov5695->subdev;
1312	v4l2_i2c_subdev_init(sd, client, &ov5695_subdev_ops);
1313	ret = ov5695_initialize_controls(ov5695);
1314	if (ret)
1315		goto err_destroy_mutex;
1316
1317	ret = __ov5695_power_on(ov5695);
1318	if (ret)
1319		goto err_free_handler;
1320
1321	ret = ov5695_check_sensor_id(ov5695, client);
1322	if (ret)
1323		goto err_power_off;
1324
1325#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1326	sd->internal_ops = &ov5695_internal_ops;
1327	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1328#endif
1329#if defined(CONFIG_MEDIA_CONTROLLER)
1330	ov5695->pad.flags = MEDIA_PAD_FL_SOURCE;
1331	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1332	ret = media_entity_pads_init(&sd->entity, 1, &ov5695->pad);
1333	if (ret < 0)
1334		goto err_power_off;
1335#endif
1336
1337	ret = v4l2_async_register_subdev_sensor(sd);
1338	if (ret) {
1339		dev_err(dev, "v4l2 async register subdev failed\n");
1340		goto err_clean_entity;
1341	}
1342
1343	pm_runtime_set_active(dev);
1344	pm_runtime_enable(dev);
1345	pm_runtime_idle(dev);
1346
1347	return 0;
1348
1349err_clean_entity:
1350#if defined(CONFIG_MEDIA_CONTROLLER)
1351	media_entity_cleanup(&sd->entity);
1352#endif
1353err_power_off:
1354	__ov5695_power_off(ov5695);
1355err_free_handler:
1356	v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1357err_destroy_mutex:
1358	mutex_destroy(&ov5695->mutex);
1359
1360	return ret;
1361}
1362
1363static void ov5695_remove(struct i2c_client *client)
1364{
1365	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1366	struct ov5695 *ov5695 = to_ov5695(sd);
1367
1368	v4l2_async_unregister_subdev(sd);
1369#if defined(CONFIG_MEDIA_CONTROLLER)
1370	media_entity_cleanup(&sd->entity);
1371#endif
1372	v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1373	mutex_destroy(&ov5695->mutex);
1374
1375	pm_runtime_disable(&client->dev);
1376	if (!pm_runtime_status_suspended(&client->dev))
1377		__ov5695_power_off(ov5695);
1378	pm_runtime_set_suspended(&client->dev);
1379}
1380
1381#if IS_ENABLED(CONFIG_OF)
1382static const struct of_device_id ov5695_of_match[] = {
1383	{ .compatible = "ovti,ov5695" },
1384	{},
1385};
1386MODULE_DEVICE_TABLE(of, ov5695_of_match);
1387#endif
1388
1389static struct i2c_driver ov5695_i2c_driver = {
1390	.driver = {
1391		.name = "ov5695",
1392		.pm = &ov5695_pm_ops,
1393		.of_match_table = of_match_ptr(ov5695_of_match),
1394	},
1395	.probe		= ov5695_probe,
1396	.remove		= ov5695_remove,
1397};
1398
1399module_i2c_driver(ov5695_i2c_driver);
1400
1401MODULE_DESCRIPTION("OmniVision ov5695 sensor driver");
1402MODULE_LICENSE("GPL v2");
1403