1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2021 Intel Corporation. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/delay.h> 7#include <linux/gpio/consumer.h> 8#include <linux/i2c.h> 9#include <linux/module.h> 10#include <linux/pm_runtime.h> 11#include <media/v4l2-ctrls.h> 12#include <media/v4l2-device.h> 13#include <media/v4l2-fwnode.h> 14 15#define OV13B10_REG_VALUE_08BIT 1 16#define OV13B10_REG_VALUE_16BIT 2 17#define OV13B10_REG_VALUE_24BIT 3 18 19#define OV13B10_REG_MODE_SELECT 0x0100 20#define OV13B10_MODE_STANDBY 0x00 21#define OV13B10_MODE_STREAMING 0x01 22 23#define OV13B10_REG_SOFTWARE_RST 0x0103 24#define OV13B10_SOFTWARE_RST 0x01 25 26/* Chip ID */ 27#define OV13B10_REG_CHIP_ID 0x300a 28#define OV13B10_CHIP_ID 0x560d42 29 30/* V_TIMING internal */ 31#define OV13B10_REG_VTS 0x380e 32#define OV13B10_VTS_30FPS 0x0c7c 33#define OV13B10_VTS_60FPS 0x063e 34#define OV13B10_VTS_MAX 0x7fff 35 36/* HBLANK control - read only */ 37#define OV13B10_PPL_560MHZ 4704 38 39/* Exposure control */ 40#define OV13B10_REG_EXPOSURE 0x3500 41#define OV13B10_EXPOSURE_MIN 4 42#define OV13B10_EXPOSURE_STEP 1 43#define OV13B10_EXPOSURE_DEFAULT 0x40 44 45/* Analog gain control */ 46#define OV13B10_REG_ANALOG_GAIN 0x3508 47#define OV13B10_ANA_GAIN_MIN 0x80 48#define OV13B10_ANA_GAIN_MAX 0x07c0 49#define OV13B10_ANA_GAIN_STEP 1 50#define OV13B10_ANA_GAIN_DEFAULT 0x80 51 52/* Digital gain control */ 53#define OV13B10_REG_DGTL_GAIN_H 0x350a 54#define OV13B10_REG_DGTL_GAIN_M 0x350b 55#define OV13B10_REG_DGTL_GAIN_L 0x350c 56 57#define OV13B10_DGTL_GAIN_MIN 1024 /* Min = 1 X */ 58#define OV13B10_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */ 59#define OV13B10_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */ 60#define OV13B10_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 61 62#define OV13B10_DGTL_GAIN_L_SHIFT 6 63#define OV13B10_DGTL_GAIN_L_MASK 0x3 64#define OV13B10_DGTL_GAIN_M_SHIFT 2 65#define OV13B10_DGTL_GAIN_M_MASK 0xff 66#define OV13B10_DGTL_GAIN_H_SHIFT 10 67#define OV13B10_DGTL_GAIN_H_MASK 0x3 68 69/* Test Pattern Control */ 70#define OV13B10_REG_TEST_PATTERN 0x5080 71#define OV13B10_TEST_PATTERN_ENABLE BIT(7) 72#define OV13B10_TEST_PATTERN_MASK 0xf3 73#define OV13B10_TEST_PATTERN_BAR_SHIFT 2 74 75/* Flip Control */ 76#define OV13B10_REG_FORMAT1 0x3820 77#define OV13B10_REG_FORMAT2 0x3821 78 79/* Horizontal Window Offset */ 80#define OV13B10_REG_H_WIN_OFFSET 0x3811 81 82/* Vertical Window Offset */ 83#define OV13B10_REG_V_WIN_OFFSET 0x3813 84 85struct ov13b10_reg { 86 u16 address; 87 u8 val; 88}; 89 90struct ov13b10_reg_list { 91 u32 num_of_regs; 92 const struct ov13b10_reg *regs; 93}; 94 95/* Link frequency config */ 96struct ov13b10_link_freq_config { 97 u32 pixels_per_line; 98 99 /* registers for this link frequency */ 100 struct ov13b10_reg_list reg_list; 101}; 102 103/* Mode : resolution and related config&values */ 104struct ov13b10_mode { 105 /* Frame width */ 106 u32 width; 107 /* Frame height */ 108 u32 height; 109 110 /* V-timing */ 111 u32 vts_def; 112 u32 vts_min; 113 114 /* Index of Link frequency config to be used */ 115 u32 link_freq_index; 116 /* Default register values */ 117 struct ov13b10_reg_list reg_list; 118}; 119 120/* 4208x3120 needs 1120Mbps/lane, 4 lanes */ 121static const struct ov13b10_reg mipi_data_rate_1120mbps[] = { 122 {0x0103, 0x01}, 123 {0x0303, 0x04}, 124 {0x0305, 0xaf}, 125 {0x0321, 0x00}, 126 {0x0323, 0x04}, 127 {0x0324, 0x01}, 128 {0x0325, 0xa4}, 129 {0x0326, 0x81}, 130 {0x0327, 0x04}, 131 {0x3012, 0x07}, 132 {0x3013, 0x32}, 133 {0x3107, 0x23}, 134 {0x3501, 0x0c}, 135 {0x3502, 0x10}, 136 {0x3504, 0x08}, 137 {0x3508, 0x07}, 138 {0x3509, 0xc0}, 139 {0x3600, 0x16}, 140 {0x3601, 0x54}, 141 {0x3612, 0x4e}, 142 {0x3620, 0x00}, 143 {0x3621, 0x68}, 144 {0x3622, 0x66}, 145 {0x3623, 0x03}, 146 {0x3662, 0x92}, 147 {0x3666, 0xbb}, 148 {0x3667, 0x44}, 149 {0x366e, 0xff}, 150 {0x366f, 0xf3}, 151 {0x3675, 0x44}, 152 {0x3676, 0x00}, 153 {0x367f, 0xe9}, 154 {0x3681, 0x32}, 155 {0x3682, 0x1f}, 156 {0x3683, 0x0b}, 157 {0x3684, 0x0b}, 158 {0x3704, 0x0f}, 159 {0x3706, 0x40}, 160 {0x3708, 0x3b}, 161 {0x3709, 0x72}, 162 {0x370b, 0xa2}, 163 {0x3714, 0x24}, 164 {0x371a, 0x3e}, 165 {0x3725, 0x42}, 166 {0x3739, 0x12}, 167 {0x3767, 0x00}, 168 {0x377a, 0x0d}, 169 {0x3789, 0x18}, 170 {0x3790, 0x40}, 171 {0x3791, 0xa2}, 172 {0x37c2, 0x04}, 173 {0x37c3, 0xf1}, 174 {0x37d9, 0x0c}, 175 {0x37da, 0x02}, 176 {0x37dc, 0x02}, 177 {0x37e1, 0x04}, 178 {0x37e2, 0x0a}, 179 {0x3800, 0x00}, 180 {0x3801, 0x00}, 181 {0x3802, 0x00}, 182 {0x3803, 0x08}, 183 {0x3804, 0x10}, 184 {0x3805, 0x8f}, 185 {0x3806, 0x0c}, 186 {0x3807, 0x47}, 187 {0x3808, 0x10}, 188 {0x3809, 0x70}, 189 {0x380a, 0x0c}, 190 {0x380b, 0x30}, 191 {0x380c, 0x04}, 192 {0x380d, 0x98}, 193 {0x380e, 0x0c}, 194 {0x380f, 0x7c}, 195 {0x3811, 0x0f}, 196 {0x3813, 0x09}, 197 {0x3814, 0x01}, 198 {0x3815, 0x01}, 199 {0x3816, 0x01}, 200 {0x3817, 0x01}, 201 {0x381f, 0x08}, 202 {0x3820, 0x88}, 203 {0x3821, 0x00}, 204 {0x3822, 0x14}, 205 {0x382e, 0xe6}, 206 {0x3c80, 0x00}, 207 {0x3c87, 0x01}, 208 {0x3c8c, 0x19}, 209 {0x3c8d, 0x1c}, 210 {0x3ca0, 0x00}, 211 {0x3ca1, 0x00}, 212 {0x3ca2, 0x00}, 213 {0x3ca3, 0x00}, 214 {0x3ca4, 0x50}, 215 {0x3ca5, 0x11}, 216 {0x3ca6, 0x01}, 217 {0x3ca7, 0x00}, 218 {0x3ca8, 0x00}, 219 {0x4008, 0x02}, 220 {0x4009, 0x0f}, 221 {0x400a, 0x01}, 222 {0x400b, 0x19}, 223 {0x4011, 0x21}, 224 {0x4017, 0x08}, 225 {0x4019, 0x04}, 226 {0x401a, 0x58}, 227 {0x4032, 0x1e}, 228 {0x4050, 0x02}, 229 {0x4051, 0x09}, 230 {0x405e, 0x00}, 231 {0x4066, 0x02}, 232 {0x4501, 0x00}, 233 {0x4502, 0x10}, 234 {0x4505, 0x00}, 235 {0x4800, 0x64}, 236 {0x481b, 0x3e}, 237 {0x481f, 0x30}, 238 {0x4825, 0x34}, 239 {0x4837, 0x0e}, 240 {0x484b, 0x01}, 241 {0x4883, 0x02}, 242 {0x5000, 0xff}, 243 {0x5001, 0x0f}, 244 {0x5045, 0x20}, 245 {0x5046, 0x20}, 246 {0x5047, 0xa4}, 247 {0x5048, 0x20}, 248 {0x5049, 0xa4}, 249}; 250 251static const struct ov13b10_reg mode_4208x3120_regs[] = { 252 {0x0305, 0xaf}, 253 {0x3501, 0x0c}, 254 {0x3662, 0x92}, 255 {0x3714, 0x24}, 256 {0x3739, 0x12}, 257 {0x37c2, 0x04}, 258 {0x37d9, 0x0c}, 259 {0x37e2, 0x0a}, 260 {0x3800, 0x00}, 261 {0x3801, 0x00}, 262 {0x3802, 0x00}, 263 {0x3803, 0x08}, 264 {0x3804, 0x10}, 265 {0x3805, 0x8f}, 266 {0x3806, 0x0c}, 267 {0x3807, 0x47}, 268 {0x3808, 0x10}, 269 {0x3809, 0x70}, 270 {0x380a, 0x0c}, 271 {0x380b, 0x30}, 272 {0x380c, 0x04}, 273 {0x380d, 0x98}, 274 {0x380e, 0x0c}, 275 {0x380f, 0x7c}, 276 {0x3810, 0x00}, 277 {0x3811, 0x0f}, 278 {0x3812, 0x00}, 279 {0x3813, 0x09}, 280 {0x3814, 0x01}, 281 {0x3816, 0x01}, 282 {0x3820, 0x88}, 283 {0x3c8c, 0x19}, 284 {0x4008, 0x02}, 285 {0x4009, 0x0f}, 286 {0x4050, 0x02}, 287 {0x4051, 0x09}, 288 {0x4501, 0x00}, 289 {0x4505, 0x00}, 290 {0x4837, 0x0e}, 291 {0x5000, 0xff}, 292 {0x5001, 0x0f}, 293}; 294 295static const struct ov13b10_reg mode_4160x3120_regs[] = { 296 {0x0305, 0xaf}, 297 {0x3501, 0x0c}, 298 {0x3662, 0x92}, 299 {0x3714, 0x24}, 300 {0x3739, 0x12}, 301 {0x37c2, 0x04}, 302 {0x37d9, 0x0c}, 303 {0x37e2, 0x0a}, 304 {0x3800, 0x00}, 305 {0x3801, 0x00}, 306 {0x3802, 0x00}, 307 {0x3803, 0x08}, 308 {0x3804, 0x10}, 309 {0x3805, 0x8f}, 310 {0x3806, 0x0c}, 311 {0x3807, 0x47}, 312 {0x3808, 0x10}, 313 {0x3809, 0x40}, 314 {0x380a, 0x0c}, 315 {0x380b, 0x30}, 316 {0x380c, 0x04}, 317 {0x380d, 0x98}, 318 {0x380e, 0x0c}, 319 {0x380f, 0x7c}, 320 {0x3810, 0x00}, 321 {0x3811, 0x27}, 322 {0x3812, 0x00}, 323 {0x3813, 0x09}, 324 {0x3814, 0x01}, 325 {0x3816, 0x01}, 326 {0x3820, 0x88}, 327 {0x3c8c, 0x19}, 328 {0x4008, 0x02}, 329 {0x4009, 0x0f}, 330 {0x4050, 0x02}, 331 {0x4051, 0x09}, 332 {0x4501, 0x00}, 333 {0x4505, 0x00}, 334 {0x4837, 0x0e}, 335 {0x5000, 0xff}, 336 {0x5001, 0x0f}, 337}; 338 339static const struct ov13b10_reg mode_4160x2340_regs[] = { 340 {0x0305, 0xaf}, 341 {0x3501, 0x0c}, 342 {0x3662, 0x92}, 343 {0x3714, 0x24}, 344 {0x3739, 0x12}, 345 {0x37c2, 0x04}, 346 {0x37d9, 0x0c}, 347 {0x37e2, 0x0a}, 348 {0x3800, 0x00}, 349 {0x3801, 0x00}, 350 {0x3802, 0x00}, 351 {0x3803, 0x08}, 352 {0x3804, 0x10}, 353 {0x3805, 0x8f}, 354 {0x3806, 0x0c}, 355 {0x3807, 0x47}, 356 {0x3808, 0x10}, 357 {0x3809, 0x40}, 358 {0x380a, 0x09}, 359 {0x380b, 0x24}, 360 {0x380c, 0x04}, 361 {0x380d, 0x98}, 362 {0x380e, 0x0c}, 363 {0x380f, 0x7c}, 364 {0x3810, 0x00}, 365 {0x3811, 0x27}, 366 {0x3812, 0x01}, 367 {0x3813, 0x8f}, 368 {0x3814, 0x01}, 369 {0x3816, 0x01}, 370 {0x3820, 0x88}, 371 {0x3c8c, 0x19}, 372 {0x4008, 0x02}, 373 {0x4009, 0x0f}, 374 {0x4050, 0x02}, 375 {0x4051, 0x09}, 376 {0x4501, 0x00}, 377 {0x4505, 0x00}, 378 {0x4837, 0x0e}, 379 {0x5000, 0xff}, 380 {0x5001, 0x0f}, 381}; 382 383static const struct ov13b10_reg mode_2104x1560_regs[] = { 384 {0x0305, 0xaf}, 385 {0x3501, 0x06}, 386 {0x3662, 0x88}, 387 {0x3714, 0x28}, 388 {0x3739, 0x10}, 389 {0x37c2, 0x14}, 390 {0x37d9, 0x06}, 391 {0x37e2, 0x0c}, 392 {0x3800, 0x00}, 393 {0x3801, 0x00}, 394 {0x3802, 0x00}, 395 {0x3803, 0x08}, 396 {0x3804, 0x10}, 397 {0x3805, 0x8f}, 398 {0x3806, 0x0c}, 399 {0x3807, 0x47}, 400 {0x3808, 0x08}, 401 {0x3809, 0x38}, 402 {0x380a, 0x06}, 403 {0x380b, 0x18}, 404 {0x380c, 0x04}, 405 {0x380d, 0x98}, 406 {0x380e, 0x06}, 407 {0x380f, 0x3e}, 408 {0x3810, 0x00}, 409 {0x3811, 0x07}, 410 {0x3812, 0x00}, 411 {0x3813, 0x05}, 412 {0x3814, 0x03}, 413 {0x3816, 0x03}, 414 {0x3820, 0x8b}, 415 {0x3c8c, 0x18}, 416 {0x4008, 0x00}, 417 {0x4009, 0x05}, 418 {0x4050, 0x00}, 419 {0x4051, 0x05}, 420 {0x4501, 0x08}, 421 {0x4505, 0x00}, 422 {0x4837, 0x0e}, 423 {0x5000, 0xfd}, 424 {0x5001, 0x0d}, 425}; 426 427static const struct ov13b10_reg mode_2080x1170_regs[] = { 428 {0x0305, 0xaf}, 429 {0x3501, 0x06}, 430 {0x3662, 0x88}, 431 {0x3714, 0x28}, 432 {0x3739, 0x10}, 433 {0x37c2, 0x14}, 434 {0x37d9, 0x06}, 435 {0x37e2, 0x0c}, 436 {0x3800, 0x00}, 437 {0x3801, 0x00}, 438 {0x3802, 0x00}, 439 {0x3803, 0x08}, 440 {0x3804, 0x10}, 441 {0x3805, 0x8f}, 442 {0x3806, 0x0c}, 443 {0x3807, 0x47}, 444 {0x3808, 0x08}, 445 {0x3809, 0x20}, 446 {0x380a, 0x04}, 447 {0x380b, 0x92}, 448 {0x380c, 0x04}, 449 {0x380d, 0x98}, 450 {0x380e, 0x06}, 451 {0x380f, 0x3e}, 452 {0x3810, 0x00}, 453 {0x3811, 0x13}, 454 {0x3812, 0x00}, 455 {0x3813, 0xc9}, 456 {0x3814, 0x03}, 457 {0x3816, 0x03}, 458 {0x3820, 0x8b}, 459 {0x3c8c, 0x18}, 460 {0x4008, 0x00}, 461 {0x4009, 0x05}, 462 {0x4050, 0x00}, 463 {0x4051, 0x05}, 464 {0x4501, 0x08}, 465 {0x4505, 0x00}, 466 {0x4837, 0x0e}, 467 {0x5000, 0xfd}, 468 {0x5001, 0x0d}, 469}; 470 471static const char * const ov13b10_test_pattern_menu[] = { 472 "Disabled", 473 "Vertical Color Bar Type 1", 474 "Vertical Color Bar Type 2", 475 "Vertical Color Bar Type 3", 476 "Vertical Color Bar Type 4" 477}; 478 479/* Configurations for supported link frequencies */ 480#define OV13B10_LINK_FREQ_560MHZ 560000000ULL 481#define OV13B10_LINK_FREQ_INDEX_0 0 482 483#define OV13B10_EXT_CLK 19200000 484#define OV13B10_DATA_LANES 4 485 486/* 487 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample 488 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 489 */ 490static u64 link_freq_to_pixel_rate(u64 f) 491{ 492 f *= 2 * OV13B10_DATA_LANES; 493 do_div(f, 10); 494 495 return f; 496} 497 498/* Menu items for LINK_FREQ V4L2 control */ 499static const s64 link_freq_menu_items[] = { 500 OV13B10_LINK_FREQ_560MHZ 501}; 502 503/* Link frequency configs */ 504static const struct ov13b10_link_freq_config 505 link_freq_configs[] = { 506 { 507 .pixels_per_line = OV13B10_PPL_560MHZ, 508 .reg_list = { 509 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps), 510 .regs = mipi_data_rate_1120mbps, 511 } 512 } 513}; 514 515/* Mode configs */ 516static const struct ov13b10_mode supported_modes[] = { 517 { 518 .width = 4208, 519 .height = 3120, 520 .vts_def = OV13B10_VTS_30FPS, 521 .vts_min = OV13B10_VTS_30FPS, 522 .reg_list = { 523 .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs), 524 .regs = mode_4208x3120_regs, 525 }, 526 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 527 }, 528 { 529 .width = 4160, 530 .height = 3120, 531 .vts_def = OV13B10_VTS_30FPS, 532 .vts_min = OV13B10_VTS_30FPS, 533 .reg_list = { 534 .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs), 535 .regs = mode_4160x3120_regs, 536 }, 537 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 538 }, 539 { 540 .width = 4160, 541 .height = 2340, 542 .vts_def = OV13B10_VTS_30FPS, 543 .vts_min = OV13B10_VTS_30FPS, 544 .reg_list = { 545 .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs), 546 .regs = mode_4160x2340_regs, 547 }, 548 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 549 }, 550 { 551 .width = 2104, 552 .height = 1560, 553 .vts_def = OV13B10_VTS_60FPS, 554 .vts_min = OV13B10_VTS_60FPS, 555 .reg_list = { 556 .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs), 557 .regs = mode_2104x1560_regs, 558 }, 559 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 560 }, 561 { 562 .width = 2080, 563 .height = 1170, 564 .vts_def = OV13B10_VTS_60FPS, 565 .vts_min = OV13B10_VTS_60FPS, 566 .reg_list = { 567 .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs), 568 .regs = mode_2080x1170_regs, 569 }, 570 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 571 } 572}; 573 574struct ov13b10 { 575 struct v4l2_subdev sd; 576 struct media_pad pad; 577 578 struct v4l2_ctrl_handler ctrl_handler; 579 580 struct clk *img_clk; 581 struct regulator *avdd; 582 struct gpio_desc *reset; 583 584 /* V4L2 Controls */ 585 struct v4l2_ctrl *link_freq; 586 struct v4l2_ctrl *pixel_rate; 587 struct v4l2_ctrl *vblank; 588 struct v4l2_ctrl *hblank; 589 struct v4l2_ctrl *exposure; 590 591 /* Current mode */ 592 const struct ov13b10_mode *cur_mode; 593 594 /* Mutex for serialized access */ 595 struct mutex mutex; 596 597 /* Streaming on/off */ 598 bool streaming; 599 600 /* True if the device has been identified */ 601 bool identified; 602}; 603 604#define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd) 605 606/* Read registers up to 4 at a time */ 607static int ov13b10_read_reg(struct ov13b10 *ov13b, 608 u16 reg, u32 len, u32 *val) 609{ 610 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 611 struct i2c_msg msgs[2]; 612 u8 *data_be_p; 613 int ret; 614 __be32 data_be = 0; 615 __be16 reg_addr_be = cpu_to_be16(reg); 616 617 if (len > 4) 618 return -EINVAL; 619 620 data_be_p = (u8 *)&data_be; 621 /* Write register address */ 622 msgs[0].addr = client->addr; 623 msgs[0].flags = 0; 624 msgs[0].len = 2; 625 msgs[0].buf = (u8 *)®_addr_be; 626 627 /* Read data from register */ 628 msgs[1].addr = client->addr; 629 msgs[1].flags = I2C_M_RD; 630 msgs[1].len = len; 631 msgs[1].buf = &data_be_p[4 - len]; 632 633 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 634 if (ret != ARRAY_SIZE(msgs)) 635 return -EIO; 636 637 *val = be32_to_cpu(data_be); 638 639 return 0; 640} 641 642/* Write registers up to 4 at a time */ 643static int ov13b10_write_reg(struct ov13b10 *ov13b, 644 u16 reg, u32 len, u32 __val) 645{ 646 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 647 int buf_i, val_i; 648 u8 buf[6], *val_p; 649 __be32 val; 650 651 if (len > 4) 652 return -EINVAL; 653 654 buf[0] = reg >> 8; 655 buf[1] = reg & 0xff; 656 657 val = cpu_to_be32(__val); 658 val_p = (u8 *)&val; 659 buf_i = 2; 660 val_i = 4 - len; 661 662 while (val_i < 4) 663 buf[buf_i++] = val_p[val_i++]; 664 665 if (i2c_master_send(client, buf, len + 2) != len + 2) 666 return -EIO; 667 668 return 0; 669} 670 671/* Write a list of registers */ 672static int ov13b10_write_regs(struct ov13b10 *ov13b, 673 const struct ov13b10_reg *regs, u32 len) 674{ 675 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 676 int ret; 677 u32 i; 678 679 for (i = 0; i < len; i++) { 680 ret = ov13b10_write_reg(ov13b, regs[i].address, 1, 681 regs[i].val); 682 if (ret) { 683 dev_err_ratelimited(&client->dev, 684 "Failed to write reg 0x%4.4x. error = %d\n", 685 regs[i].address, ret); 686 687 return ret; 688 } 689 } 690 691 return 0; 692} 693 694static int ov13b10_write_reg_list(struct ov13b10 *ov13b, 695 const struct ov13b10_reg_list *r_list) 696{ 697 return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs); 698} 699 700/* Open sub-device */ 701static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 702{ 703 const struct ov13b10_mode *default_mode = &supported_modes[0]; 704 struct ov13b10 *ov13b = to_ov13b10(sd); 705 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd, 706 fh->state, 707 0); 708 709 mutex_lock(&ov13b->mutex); 710 711 /* Initialize try_fmt */ 712 try_fmt->width = default_mode->width; 713 try_fmt->height = default_mode->height; 714 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 715 try_fmt->field = V4L2_FIELD_NONE; 716 717 /* No crop or compose */ 718 mutex_unlock(&ov13b->mutex); 719 720 return 0; 721} 722 723static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain) 724{ 725 int ret; 726 u32 val; 727 728 /* 729 * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0] 730 */ 731 732 val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT; 733 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L, 734 OV13B10_REG_VALUE_08BIT, val); 735 if (ret) 736 return ret; 737 738 val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK; 739 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M, 740 OV13B10_REG_VALUE_08BIT, val); 741 if (ret) 742 return ret; 743 744 val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK; 745 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H, 746 OV13B10_REG_VALUE_08BIT, val); 747 748 return ret; 749} 750 751static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern) 752{ 753 int ret; 754 u32 val; 755 756 ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN, 757 OV13B10_REG_VALUE_08BIT, &val); 758 if (ret) 759 return ret; 760 761 if (pattern) { 762 val &= OV13B10_TEST_PATTERN_MASK; 763 val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) | 764 OV13B10_TEST_PATTERN_ENABLE; 765 } else { 766 val &= ~OV13B10_TEST_PATTERN_ENABLE; 767 } 768 769 return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN, 770 OV13B10_REG_VALUE_08BIT, val); 771} 772 773static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val) 774{ 775 int ret; 776 u32 val; 777 778 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1, 779 OV13B10_REG_VALUE_08BIT, &val); 780 if (ret) 781 return ret; 782 783 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1, 784 OV13B10_REG_VALUE_08BIT, 785 ctrl_val ? val & ~BIT(3) : val); 786 787 if (ret) 788 return ret; 789 790 ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET, 791 OV13B10_REG_VALUE_08BIT, &val); 792 if (ret) 793 return ret; 794 795 /* 796 * Applying cropping offset to reverse the change of Bayer order 797 * after mirroring image 798 */ 799 return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET, 800 OV13B10_REG_VALUE_08BIT, 801 ctrl_val ? ++val : val); 802} 803 804static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val) 805{ 806 int ret; 807 u32 val; 808 809 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1, 810 OV13B10_REG_VALUE_08BIT, &val); 811 if (ret) 812 return ret; 813 814 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1, 815 OV13B10_REG_VALUE_08BIT, 816 ctrl_val ? val | BIT(4) | BIT(5) : val); 817 818 if (ret) 819 return ret; 820 821 ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET, 822 OV13B10_REG_VALUE_08BIT, &val); 823 if (ret) 824 return ret; 825 826 /* 827 * Applying cropping offset to reverse the change of Bayer order 828 * after flipping image 829 */ 830 return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET, 831 OV13B10_REG_VALUE_08BIT, 832 ctrl_val ? --val : val); 833} 834 835static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl) 836{ 837 struct ov13b10 *ov13b = container_of(ctrl->handler, 838 struct ov13b10, ctrl_handler); 839 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 840 s64 max; 841 int ret; 842 843 /* Propagate change of current control to all related controls */ 844 switch (ctrl->id) { 845 case V4L2_CID_VBLANK: 846 /* Update max exposure while meeting expected vblanking */ 847 max = ov13b->cur_mode->height + ctrl->val - 8; 848 __v4l2_ctrl_modify_range(ov13b->exposure, 849 ov13b->exposure->minimum, 850 max, ov13b->exposure->step, max); 851 break; 852 } 853 854 /* 855 * Applying V4L2 control value only happens 856 * when power is up for streaming 857 */ 858 if (!pm_runtime_get_if_in_use(&client->dev)) 859 return 0; 860 861 ret = 0; 862 switch (ctrl->id) { 863 case V4L2_CID_ANALOGUE_GAIN: 864 ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN, 865 OV13B10_REG_VALUE_16BIT, 866 ctrl->val << 1); 867 break; 868 case V4L2_CID_DIGITAL_GAIN: 869 ret = ov13b10_update_digital_gain(ov13b, ctrl->val); 870 break; 871 case V4L2_CID_EXPOSURE: 872 ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE, 873 OV13B10_REG_VALUE_24BIT, 874 ctrl->val); 875 break; 876 case V4L2_CID_VBLANK: 877 ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS, 878 OV13B10_REG_VALUE_16BIT, 879 ov13b->cur_mode->height 880 + ctrl->val); 881 break; 882 case V4L2_CID_TEST_PATTERN: 883 ret = ov13b10_enable_test_pattern(ov13b, ctrl->val); 884 break; 885 case V4L2_CID_HFLIP: 886 ov13b10_set_ctrl_hflip(ov13b, ctrl->val); 887 break; 888 case V4L2_CID_VFLIP: 889 ov13b10_set_ctrl_vflip(ov13b, ctrl->val); 890 break; 891 default: 892 dev_info(&client->dev, 893 "ctrl(id:0x%x,val:0x%x) is not handled\n", 894 ctrl->id, ctrl->val); 895 break; 896 } 897 898 pm_runtime_put(&client->dev); 899 900 return ret; 901} 902 903static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = { 904 .s_ctrl = ov13b10_set_ctrl, 905}; 906 907static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd, 908 struct v4l2_subdev_state *sd_state, 909 struct v4l2_subdev_mbus_code_enum *code) 910{ 911 /* Only one bayer order(GRBG) is supported */ 912 if (code->index > 0) 913 return -EINVAL; 914 915 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 916 917 return 0; 918} 919 920static int ov13b10_enum_frame_size(struct v4l2_subdev *sd, 921 struct v4l2_subdev_state *sd_state, 922 struct v4l2_subdev_frame_size_enum *fse) 923{ 924 if (fse->index >= ARRAY_SIZE(supported_modes)) 925 return -EINVAL; 926 927 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 928 return -EINVAL; 929 930 fse->min_width = supported_modes[fse->index].width; 931 fse->max_width = fse->min_width; 932 fse->min_height = supported_modes[fse->index].height; 933 fse->max_height = fse->min_height; 934 935 return 0; 936} 937 938static void ov13b10_update_pad_format(const struct ov13b10_mode *mode, 939 struct v4l2_subdev_format *fmt) 940{ 941 fmt->format.width = mode->width; 942 fmt->format.height = mode->height; 943 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 944 fmt->format.field = V4L2_FIELD_NONE; 945} 946 947static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b, 948 struct v4l2_subdev_state *sd_state, 949 struct v4l2_subdev_format *fmt) 950{ 951 struct v4l2_mbus_framefmt *framefmt; 952 struct v4l2_subdev *sd = &ov13b->sd; 953 954 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 955 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 956 fmt->format = *framefmt; 957 } else { 958 ov13b10_update_pad_format(ov13b->cur_mode, fmt); 959 } 960 961 return 0; 962} 963 964static int ov13b10_get_pad_format(struct v4l2_subdev *sd, 965 struct v4l2_subdev_state *sd_state, 966 struct v4l2_subdev_format *fmt) 967{ 968 struct ov13b10 *ov13b = to_ov13b10(sd); 969 int ret; 970 971 mutex_lock(&ov13b->mutex); 972 ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt); 973 mutex_unlock(&ov13b->mutex); 974 975 return ret; 976} 977 978static int 979ov13b10_set_pad_format(struct v4l2_subdev *sd, 980 struct v4l2_subdev_state *sd_state, 981 struct v4l2_subdev_format *fmt) 982{ 983 struct ov13b10 *ov13b = to_ov13b10(sd); 984 const struct ov13b10_mode *mode; 985 struct v4l2_mbus_framefmt *framefmt; 986 s32 vblank_def; 987 s32 vblank_min; 988 s64 h_blank; 989 s64 pixel_rate; 990 s64 link_freq; 991 992 mutex_lock(&ov13b->mutex); 993 994 /* Only one raw bayer(GRBG) order is supported */ 995 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 996 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 997 998 mode = v4l2_find_nearest_size(supported_modes, 999 ARRAY_SIZE(supported_modes), 1000 width, height, 1001 fmt->format.width, fmt->format.height); 1002 ov13b10_update_pad_format(mode, fmt); 1003 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1004 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 1005 *framefmt = fmt->format; 1006 } else { 1007 ov13b->cur_mode = mode; 1008 __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index); 1009 link_freq = link_freq_menu_items[mode->link_freq_index]; 1010 pixel_rate = link_freq_to_pixel_rate(link_freq); 1011 __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate); 1012 1013 /* Update limits and set FPS to default */ 1014 vblank_def = ov13b->cur_mode->vts_def - 1015 ov13b->cur_mode->height; 1016 vblank_min = ov13b->cur_mode->vts_min - 1017 ov13b->cur_mode->height; 1018 __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min, 1019 OV13B10_VTS_MAX 1020 - ov13b->cur_mode->height, 1021 1, 1022 vblank_def); 1023 __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def); 1024 h_blank = 1025 link_freq_configs[mode->link_freq_index].pixels_per_line 1026 - ov13b->cur_mode->width; 1027 __v4l2_ctrl_modify_range(ov13b->hblank, h_blank, 1028 h_blank, 1, h_blank); 1029 } 1030 1031 mutex_unlock(&ov13b->mutex); 1032 1033 return 0; 1034} 1035 1036/* Verify chip ID */ 1037static int ov13b10_identify_module(struct ov13b10 *ov13b) 1038{ 1039 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 1040 int ret; 1041 u32 val; 1042 1043 if (ov13b->identified) 1044 return 0; 1045 1046 ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID, 1047 OV13B10_REG_VALUE_24BIT, &val); 1048 if (ret) 1049 return ret; 1050 1051 if (val != OV13B10_CHIP_ID) { 1052 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 1053 OV13B10_CHIP_ID, val); 1054 return -EIO; 1055 } 1056 1057 ov13b->identified = true; 1058 1059 return 0; 1060} 1061 1062static int ov13b10_power_off(struct device *dev) 1063{ 1064 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1065 struct ov13b10 *ov13b10 = to_ov13b10(sd); 1066 1067 gpiod_set_value_cansleep(ov13b10->reset, 1); 1068 1069 if (ov13b10->avdd) 1070 regulator_disable(ov13b10->avdd); 1071 1072 clk_disable_unprepare(ov13b10->img_clk); 1073 1074 return 0; 1075} 1076 1077static int ov13b10_power_on(struct device *dev) 1078{ 1079 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1080 struct ov13b10 *ov13b10 = to_ov13b10(sd); 1081 int ret; 1082 1083 ret = clk_prepare_enable(ov13b10->img_clk); 1084 if (ret < 0) { 1085 dev_err(dev, "failed to enable imaging clock: %d", ret); 1086 return ret; 1087 } 1088 1089 if (ov13b10->avdd) { 1090 ret = regulator_enable(ov13b10->avdd); 1091 if (ret < 0) { 1092 dev_err(dev, "failed to enable avdd: %d", ret); 1093 clk_disable_unprepare(ov13b10->img_clk); 1094 return ret; 1095 } 1096 } 1097 1098 gpiod_set_value_cansleep(ov13b10->reset, 0); 1099 /* 5ms to wait ready after XSHUTDN assert */ 1100 usleep_range(5000, 5500); 1101 1102 return 0; 1103} 1104 1105static int ov13b10_start_streaming(struct ov13b10 *ov13b) 1106{ 1107 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 1108 const struct ov13b10_reg_list *reg_list; 1109 int ret, link_freq_index; 1110 1111 ret = ov13b10_identify_module(ov13b); 1112 if (ret) 1113 return ret; 1114 1115 /* Get out of from software reset */ 1116 ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST, 1117 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST); 1118 if (ret) { 1119 dev_err(&client->dev, "%s failed to set powerup registers\n", 1120 __func__); 1121 return ret; 1122 } 1123 1124 link_freq_index = ov13b->cur_mode->link_freq_index; 1125 reg_list = &link_freq_configs[link_freq_index].reg_list; 1126 ret = ov13b10_write_reg_list(ov13b, reg_list); 1127 if (ret) { 1128 dev_err(&client->dev, "%s failed to set plls\n", __func__); 1129 return ret; 1130 } 1131 1132 /* Apply default values of current mode */ 1133 reg_list = &ov13b->cur_mode->reg_list; 1134 ret = ov13b10_write_reg_list(ov13b, reg_list); 1135 if (ret) { 1136 dev_err(&client->dev, "%s failed to set mode\n", __func__); 1137 return ret; 1138 } 1139 1140 /* Apply customized values from user */ 1141 ret = __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler); 1142 if (ret) 1143 return ret; 1144 1145 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT, 1146 OV13B10_REG_VALUE_08BIT, 1147 OV13B10_MODE_STREAMING); 1148} 1149 1150/* Stop streaming */ 1151static int ov13b10_stop_streaming(struct ov13b10 *ov13b) 1152{ 1153 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT, 1154 OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY); 1155} 1156 1157static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable) 1158{ 1159 struct ov13b10 *ov13b = to_ov13b10(sd); 1160 struct i2c_client *client = v4l2_get_subdevdata(sd); 1161 int ret = 0; 1162 1163 mutex_lock(&ov13b->mutex); 1164 if (ov13b->streaming == enable) { 1165 mutex_unlock(&ov13b->mutex); 1166 return 0; 1167 } 1168 1169 if (enable) { 1170 ret = pm_runtime_resume_and_get(&client->dev); 1171 if (ret < 0) 1172 goto err_unlock; 1173 1174 /* 1175 * Apply default & customized values 1176 * and then start streaming. 1177 */ 1178 ret = ov13b10_start_streaming(ov13b); 1179 if (ret) 1180 goto err_rpm_put; 1181 } else { 1182 ov13b10_stop_streaming(ov13b); 1183 pm_runtime_put(&client->dev); 1184 } 1185 1186 ov13b->streaming = enable; 1187 mutex_unlock(&ov13b->mutex); 1188 1189 return ret; 1190 1191err_rpm_put: 1192 pm_runtime_put(&client->dev); 1193err_unlock: 1194 mutex_unlock(&ov13b->mutex); 1195 1196 return ret; 1197} 1198 1199static int ov13b10_suspend(struct device *dev) 1200{ 1201 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1202 struct ov13b10 *ov13b = to_ov13b10(sd); 1203 1204 if (ov13b->streaming) 1205 ov13b10_stop_streaming(ov13b); 1206 1207 ov13b10_power_off(dev); 1208 1209 return 0; 1210} 1211 1212static int ov13b10_resume(struct device *dev) 1213{ 1214 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1215 struct ov13b10 *ov13b = to_ov13b10(sd); 1216 int ret; 1217 1218 ret = ov13b10_power_on(dev); 1219 if (ret) 1220 goto pm_fail; 1221 1222 if (ov13b->streaming) { 1223 ret = ov13b10_start_streaming(ov13b); 1224 if (ret) 1225 goto stop_streaming; 1226 } 1227 1228 return 0; 1229 1230stop_streaming: 1231 ov13b10_stop_streaming(ov13b); 1232 ov13b10_power_off(dev); 1233pm_fail: 1234 ov13b->streaming = false; 1235 1236 return ret; 1237} 1238 1239static const struct v4l2_subdev_video_ops ov13b10_video_ops = { 1240 .s_stream = ov13b10_set_stream, 1241}; 1242 1243static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = { 1244 .enum_mbus_code = ov13b10_enum_mbus_code, 1245 .get_fmt = ov13b10_get_pad_format, 1246 .set_fmt = ov13b10_set_pad_format, 1247 .enum_frame_size = ov13b10_enum_frame_size, 1248}; 1249 1250static const struct v4l2_subdev_ops ov13b10_subdev_ops = { 1251 .video = &ov13b10_video_ops, 1252 .pad = &ov13b10_pad_ops, 1253}; 1254 1255static const struct media_entity_operations ov13b10_subdev_entity_ops = { 1256 .link_validate = v4l2_subdev_link_validate, 1257}; 1258 1259static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = { 1260 .open = ov13b10_open, 1261}; 1262 1263/* Initialize control handlers */ 1264static int ov13b10_init_controls(struct ov13b10 *ov13b) 1265{ 1266 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 1267 struct v4l2_fwnode_device_properties props; 1268 struct v4l2_ctrl_handler *ctrl_hdlr; 1269 s64 exposure_max; 1270 s64 vblank_def; 1271 s64 vblank_min; 1272 s64 hblank; 1273 s64 pixel_rate_min; 1274 s64 pixel_rate_max; 1275 const struct ov13b10_mode *mode; 1276 u32 max; 1277 int ret; 1278 1279 ctrl_hdlr = &ov13b->ctrl_handler; 1280 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 1281 if (ret) 1282 return ret; 1283 1284 mutex_init(&ov13b->mutex); 1285 ctrl_hdlr->lock = &ov13b->mutex; 1286 max = ARRAY_SIZE(link_freq_menu_items) - 1; 1287 ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1288 &ov13b10_ctrl_ops, 1289 V4L2_CID_LINK_FREQ, 1290 max, 1291 0, 1292 link_freq_menu_items); 1293 if (ov13b->link_freq) 1294 ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1295 1296 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); 1297 pixel_rate_min = 0; 1298 /* By default, PIXEL_RATE is read only */ 1299 ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1300 V4L2_CID_PIXEL_RATE, 1301 pixel_rate_min, pixel_rate_max, 1302 1, pixel_rate_max); 1303 1304 mode = ov13b->cur_mode; 1305 vblank_def = mode->vts_def - mode->height; 1306 vblank_min = mode->vts_min - mode->height; 1307 ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1308 V4L2_CID_VBLANK, 1309 vblank_min, 1310 OV13B10_VTS_MAX - mode->height, 1, 1311 vblank_def); 1312 1313 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line - 1314 mode->width; 1315 ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1316 V4L2_CID_HBLANK, 1317 hblank, hblank, 1, hblank); 1318 if (ov13b->hblank) 1319 ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1320 1321 exposure_max = mode->vts_def - 8; 1322 ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1323 V4L2_CID_EXPOSURE, 1324 OV13B10_EXPOSURE_MIN, 1325 exposure_max, OV13B10_EXPOSURE_STEP, 1326 exposure_max); 1327 1328 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1329 OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX, 1330 OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT); 1331 1332 /* Digital gain */ 1333 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1334 OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX, 1335 OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT); 1336 1337 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops, 1338 V4L2_CID_TEST_PATTERN, 1339 ARRAY_SIZE(ov13b10_test_pattern_menu) - 1, 1340 0, 0, ov13b10_test_pattern_menu); 1341 1342 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1343 V4L2_CID_HFLIP, 0, 1, 1, 0); 1344 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1345 V4L2_CID_VFLIP, 0, 1, 1, 0); 1346 1347 if (ctrl_hdlr->error) { 1348 ret = ctrl_hdlr->error; 1349 dev_err(&client->dev, "%s control init failed (%d)\n", 1350 __func__, ret); 1351 goto error; 1352 } 1353 1354 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1355 if (ret) 1356 goto error; 1357 1358 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops, 1359 &props); 1360 if (ret) 1361 goto error; 1362 1363 ov13b->sd.ctrl_handler = ctrl_hdlr; 1364 1365 return 0; 1366 1367error: 1368 v4l2_ctrl_handler_free(ctrl_hdlr); 1369 mutex_destroy(&ov13b->mutex); 1370 1371 return ret; 1372} 1373 1374static void ov13b10_free_controls(struct ov13b10 *ov13b) 1375{ 1376 v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler); 1377 mutex_destroy(&ov13b->mutex); 1378} 1379 1380static int ov13b10_get_pm_resources(struct device *dev) 1381{ 1382 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1383 struct ov13b10 *ov13b = to_ov13b10(sd); 1384 int ret; 1385 1386 ov13b->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1387 if (IS_ERR(ov13b->reset)) 1388 return dev_err_probe(dev, PTR_ERR(ov13b->reset), 1389 "failed to get reset gpio\n"); 1390 1391 ov13b->img_clk = devm_clk_get_optional(dev, NULL); 1392 if (IS_ERR(ov13b->img_clk)) 1393 return dev_err_probe(dev, PTR_ERR(ov13b->img_clk), 1394 "failed to get imaging clock\n"); 1395 1396 ov13b->avdd = devm_regulator_get_optional(dev, "avdd"); 1397 if (IS_ERR(ov13b->avdd)) { 1398 ret = PTR_ERR(ov13b->avdd); 1399 ov13b->avdd = NULL; 1400 if (ret != -ENODEV) 1401 return dev_err_probe(dev, ret, 1402 "failed to get avdd regulator\n"); 1403 } 1404 1405 return 0; 1406} 1407 1408static int ov13b10_check_hwcfg(struct device *dev) 1409{ 1410 struct v4l2_fwnode_endpoint bus_cfg = { 1411 .bus_type = V4L2_MBUS_CSI2_DPHY 1412 }; 1413 struct fwnode_handle *ep; 1414 struct fwnode_handle *fwnode = dev_fwnode(dev); 1415 unsigned int i, j; 1416 int ret; 1417 u32 ext_clk; 1418 1419 if (!fwnode) 1420 return -ENXIO; 1421 1422 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1423 if (!ep) 1424 return -EPROBE_DEFER; 1425 1426 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1427 &ext_clk); 1428 if (ret) { 1429 dev_err(dev, "can't get clock frequency"); 1430 return ret; 1431 } 1432 1433 if (ext_clk != OV13B10_EXT_CLK) { 1434 dev_err(dev, "external clock %d is not supported", 1435 ext_clk); 1436 return -EINVAL; 1437 } 1438 1439 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1440 fwnode_handle_put(ep); 1441 if (ret) 1442 return ret; 1443 1444 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV13B10_DATA_LANES) { 1445 dev_err(dev, "number of CSI2 data lanes %d is not supported", 1446 bus_cfg.bus.mipi_csi2.num_data_lanes); 1447 ret = -EINVAL; 1448 goto out_err; 1449 } 1450 1451 if (!bus_cfg.nr_of_link_frequencies) { 1452 dev_err(dev, "no link frequencies defined"); 1453 ret = -EINVAL; 1454 goto out_err; 1455 } 1456 1457 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1458 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1459 if (link_freq_menu_items[i] == 1460 bus_cfg.link_frequencies[j]) 1461 break; 1462 } 1463 1464 if (j == bus_cfg.nr_of_link_frequencies) { 1465 dev_err(dev, "no link frequency %lld supported", 1466 link_freq_menu_items[i]); 1467 ret = -EINVAL; 1468 goto out_err; 1469 } 1470 } 1471 1472out_err: 1473 v4l2_fwnode_endpoint_free(&bus_cfg); 1474 1475 return ret; 1476} 1477 1478static int ov13b10_probe(struct i2c_client *client) 1479{ 1480 struct ov13b10 *ov13b; 1481 bool full_power; 1482 int ret; 1483 1484 /* Check HW config */ 1485 ret = ov13b10_check_hwcfg(&client->dev); 1486 if (ret) { 1487 dev_err(&client->dev, "failed to check hwcfg: %d", ret); 1488 return ret; 1489 } 1490 1491 ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL); 1492 if (!ov13b) 1493 return -ENOMEM; 1494 1495 /* Initialize subdev */ 1496 v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops); 1497 1498 ret = ov13b10_get_pm_resources(&client->dev); 1499 if (ret) 1500 return ret; 1501 1502 full_power = acpi_dev_state_d0(&client->dev); 1503 if (full_power) { 1504 ret = ov13b10_power_on(&client->dev); 1505 if (ret) { 1506 dev_err(&client->dev, "failed to power on\n"); 1507 return ret; 1508 } 1509 1510 /* Check module identity */ 1511 ret = ov13b10_identify_module(ov13b); 1512 if (ret) { 1513 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 1514 goto error_power_off; 1515 } 1516 } 1517 1518 /* Set default mode to max resolution */ 1519 ov13b->cur_mode = &supported_modes[0]; 1520 1521 ret = ov13b10_init_controls(ov13b); 1522 if (ret) 1523 goto error_power_off; 1524 1525 /* Initialize subdev */ 1526 ov13b->sd.internal_ops = &ov13b10_internal_ops; 1527 ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1528 ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops; 1529 ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1530 1531 /* Initialize source pad */ 1532 ov13b->pad.flags = MEDIA_PAD_FL_SOURCE; 1533 ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad); 1534 if (ret) { 1535 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1536 goto error_handler_free; 1537 } 1538 1539 1540 /* 1541 * Device is already turned on by i2c-core with ACPI domain PM. 1542 * Enable runtime PM and turn off the device. 1543 */ 1544 /* Set the device's state to active if it's in D0 state. */ 1545 if (full_power) 1546 pm_runtime_set_active(&client->dev); 1547 pm_runtime_enable(&client->dev); 1548 pm_runtime_idle(&client->dev); 1549 1550 ret = v4l2_async_register_subdev_sensor(&ov13b->sd); 1551 if (ret < 0) 1552 goto error_media_entity_runtime_pm; 1553 1554 return 0; 1555 1556error_media_entity_runtime_pm: 1557 pm_runtime_disable(&client->dev); 1558 if (full_power) 1559 pm_runtime_set_suspended(&client->dev); 1560 media_entity_cleanup(&ov13b->sd.entity); 1561 1562error_handler_free: 1563 ov13b10_free_controls(ov13b); 1564 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1565 1566error_power_off: 1567 ov13b10_power_off(&client->dev); 1568 1569 return ret; 1570} 1571 1572static void ov13b10_remove(struct i2c_client *client) 1573{ 1574 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1575 struct ov13b10 *ov13b = to_ov13b10(sd); 1576 1577 v4l2_async_unregister_subdev(sd); 1578 media_entity_cleanup(&sd->entity); 1579 ov13b10_free_controls(ov13b); 1580 1581 pm_runtime_disable(&client->dev); 1582 pm_runtime_set_suspended(&client->dev); 1583} 1584 1585static DEFINE_RUNTIME_DEV_PM_OPS(ov13b10_pm_ops, ov13b10_suspend, 1586 ov13b10_resume, NULL); 1587 1588#ifdef CONFIG_ACPI 1589static const struct acpi_device_id ov13b10_acpi_ids[] = { 1590 {"OVTIDB10"}, 1591 {"OVTI13B1"}, 1592 { /* sentinel */ } 1593}; 1594 1595MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids); 1596#endif 1597 1598static struct i2c_driver ov13b10_i2c_driver = { 1599 .driver = { 1600 .name = "ov13b10", 1601 .pm = pm_ptr(&ov13b10_pm_ops), 1602 .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids), 1603 }, 1604 .probe = ov13b10_probe, 1605 .remove = ov13b10_remove, 1606 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1607}; 1608 1609module_i2c_driver(ov13b10_i2c_driver); 1610 1611MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>"); 1612MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver"); 1613MODULE_LICENSE("GPL v2"); 1614