162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef _ARM_SMMU_QCOM_H 762306a36Sopenharmony_ci#define _ARM_SMMU_QCOM_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_cistruct qcom_smmu { 1062306a36Sopenharmony_ci struct arm_smmu_device smmu; 1162306a36Sopenharmony_ci const struct qcom_smmu_config *cfg; 1262306a36Sopenharmony_ci bool bypass_quirk; 1362306a36Sopenharmony_ci u8 bypass_cbndx; 1462306a36Sopenharmony_ci u32 stall_enabled; 1562306a36Sopenharmony_ci}; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_cienum qcom_smmu_impl_reg_offset { 1862306a36Sopenharmony_ci QCOM_SMMU_TBU_PWR_STATUS, 1962306a36Sopenharmony_ci QCOM_SMMU_STATS_SYNC_INV_TBU_ACK, 2062306a36Sopenharmony_ci QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR, 2162306a36Sopenharmony_ci}; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_cistruct qcom_smmu_config { 2462306a36Sopenharmony_ci const u32 *reg_offset; 2562306a36Sopenharmony_ci}; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistruct qcom_smmu_match_data { 2862306a36Sopenharmony_ci const struct qcom_smmu_config *cfg; 2962306a36Sopenharmony_ci const struct arm_smmu_impl *impl; 3062306a36Sopenharmony_ci const struct arm_smmu_impl *adreno_impl; 3162306a36Sopenharmony_ci}; 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG 3462306a36Sopenharmony_civoid qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu); 3562306a36Sopenharmony_ci#else 3662306a36Sopenharmony_cistatic inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { } 3762306a36Sopenharmony_ci#endif 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#endif /* _ARM_SMMU_QCOM_H */ 40