1/*
2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses.  You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 *     Redistribution and use in source and binary forms, with or
13 *     without modification, are permitted provided that the following
14 *     conditions are met:
15 *
16 *      - Redistributions of source code must retain the above
17 *        copyright notice, this list of conditions and the following
18 *        disclaimer.
19 *
20 *      - Redistributions in binary form must reproduce the above
21 *        copyright notice, this list of conditions and the following
22 *        disclaimer in the documentation and/or other materials
23 *        provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/delay.h>
36#include <linux/pci.h>
37#include <linux/vmalloc.h>
38
39#include "qib.h"
40
41/*
42 * QLogic_IB "Two Wire Serial Interface" driver.
43 * Originally written for a not-quite-i2c serial eeprom, which is
44 * still used on some supported boards. Later boards have added a
45 * variety of other uses, most board-specific, so the bit-boffing
46 * part has been split off to this file, while the other parts
47 * have been moved to chip-specific files.
48 *
49 * We have also dropped all pretense of fully generic (e.g. pretend
50 * we don't know whether '1' is the higher voltage) interface, as
51 * the restrictions of the generic i2c interface (e.g. no access from
52 * driver itself) make it unsuitable for this use.
53 */
54
55#define READ_CMD 1
56#define WRITE_CMD 0
57
58/**
59 * i2c_wait_for_writes - wait for a write
60 * @dd: the qlogic_ib device
61 *
62 * We use this instead of udelay directly, so we can make sure
63 * that previous register writes have been flushed all the way
64 * to the chip.  Since we are delaying anyway, the cost doesn't
65 * hurt, and makes the bit twiddling more regular
66 */
67static void i2c_wait_for_writes(struct qib_devdata *dd)
68{
69	/*
70	 * implicit read of EXTStatus is as good as explicit
71	 * read of scratch, if all we want to do is flush
72	 * writes.
73	 */
74	dd->f_gpio_mod(dd, 0, 0, 0);
75	rmb(); /* inlined, so prevent compiler reordering */
76}
77
78/*
79 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
80 * for "almost compliant" modules
81 */
82#define SCL_WAIT_USEC 1000
83
84/* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
85 * Should be 20, but some chips need more.
86 */
87#define TWSI_BUF_WAIT_USEC 60
88
89static void scl_out(struct qib_devdata *dd, u8 bit)
90{
91	u32 mask;
92
93	udelay(1);
94
95	mask = 1UL << dd->gpio_scl_num;
96
97	/* SCL is meant to be bare-drain, so never set "OUT", just DIR */
98	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
99
100	/*
101	 * Allow for slow slaves by simple
102	 * delay for falling edge, sampling on rise.
103	 */
104	if (!bit)
105		udelay(2);
106	else {
107		int rise_usec;
108
109		for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
110			if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
111				break;
112			udelay(2);
113		}
114		if (rise_usec <= 0)
115			qib_dev_err(dd, "SCL interface stuck low > %d uSec\n",
116				    SCL_WAIT_USEC);
117	}
118	i2c_wait_for_writes(dd);
119}
120
121static void sda_out(struct qib_devdata *dd, u8 bit)
122{
123	u32 mask;
124
125	mask = 1UL << dd->gpio_sda_num;
126
127	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
128	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
129
130	i2c_wait_for_writes(dd);
131	udelay(2);
132}
133
134static u8 sda_in(struct qib_devdata *dd, int wait)
135{
136	int bnum;
137	u32 read_val, mask;
138
139	bnum = dd->gpio_sda_num;
140	mask = (1UL << bnum);
141	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
142	dd->f_gpio_mod(dd, 0, 0, mask);
143	read_val = dd->f_gpio_mod(dd, 0, 0, 0);
144	if (wait)
145		i2c_wait_for_writes(dd);
146	return (read_val & mask) >> bnum;
147}
148
149/**
150 * i2c_ackrcv - see if ack following write is true
151 * @dd: the qlogic_ib device
152 */
153static int i2c_ackrcv(struct qib_devdata *dd)
154{
155	u8 ack_received;
156
157	/* AT ENTRY SCL = LOW */
158	/* change direction, ignore data */
159	ack_received = sda_in(dd, 1);
160	scl_out(dd, 1);
161	ack_received = sda_in(dd, 1) == 0;
162	scl_out(dd, 0);
163	return ack_received;
164}
165
166static void stop_cmd(struct qib_devdata *dd);
167
168/**
169 * rd_byte - read a byte, sending STOP on last, else ACK
170 * @dd: the qlogic_ib device
171 * @last: identifies the last read
172 *
173 * Returns byte shifted out of device
174 */
175static int rd_byte(struct qib_devdata *dd, int last)
176{
177	int bit_cntr, data;
178
179	data = 0;
180
181	for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
182		data <<= 1;
183		scl_out(dd, 1);
184		data |= sda_in(dd, 0);
185		scl_out(dd, 0);
186	}
187	if (last) {
188		scl_out(dd, 1);
189		stop_cmd(dd);
190	} else {
191		sda_out(dd, 0);
192		scl_out(dd, 1);
193		scl_out(dd, 0);
194		sda_out(dd, 1);
195	}
196	return data;
197}
198
199/**
200 * wr_byte - write a byte, one bit at a time
201 * @dd: the qlogic_ib device
202 * @data: the byte to write
203 *
204 * Returns 0 if we got the following ack, otherwise 1
205 */
206static int wr_byte(struct qib_devdata *dd, u8 data)
207{
208	int bit_cntr;
209	u8 bit;
210
211	for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
212		bit = (data >> bit_cntr) & 1;
213		sda_out(dd, bit);
214		scl_out(dd, 1);
215		scl_out(dd, 0);
216	}
217	return (!i2c_ackrcv(dd)) ? 1 : 0;
218}
219
220/*
221 * issue TWSI start sequence:
222 * (both clock/data high, clock high, data low while clock is high)
223 */
224static void start_seq(struct qib_devdata *dd)
225{
226	sda_out(dd, 1);
227	scl_out(dd, 1);
228	sda_out(dd, 0);
229	udelay(1);
230	scl_out(dd, 0);
231}
232
233/**
234 * stop_seq - transmit the stop sequence
235 * @dd: the qlogic_ib device
236 *
237 * (both clock/data low, clock high, data high while clock is high)
238 */
239static void stop_seq(struct qib_devdata *dd)
240{
241	scl_out(dd, 0);
242	sda_out(dd, 0);
243	scl_out(dd, 1);
244	sda_out(dd, 1);
245}
246
247/**
248 * stop_cmd - transmit the stop condition
249 * @dd: the qlogic_ib device
250 *
251 * (both clock/data low, clock high, data high while clock is high)
252 */
253static void stop_cmd(struct qib_devdata *dd)
254{
255	stop_seq(dd);
256	udelay(TWSI_BUF_WAIT_USEC);
257}
258
259/**
260 * qib_twsi_reset - reset I2C communication
261 * @dd: the qlogic_ib device
262 */
263
264int qib_twsi_reset(struct qib_devdata *dd)
265{
266	int clock_cycles_left = 9;
267	int was_high = 0;
268	u32 pins, mask;
269
270	/* Both SCL and SDA should be high. If not, there
271	 * is something wrong.
272	 */
273	mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);
274
275	/*
276	 * Force pins to desired innocuous state.
277	 * This is the default power-on state with out=0 and dir=0,
278	 * So tri-stated and should be floating high (barring HW problems)
279	 */
280	dd->f_gpio_mod(dd, 0, 0, mask);
281
282	/*
283	 * Clock nine times to get all listeners into a sane state.
284	 * If SDA does not go high at any point, we are wedged.
285	 * One vendor recommends then issuing START followed by STOP.
286	 * we cannot use our "normal" functions to do that, because
287	 * if SCL drops between them, another vendor's part will
288	 * wedge, dropping SDA and keeping it low forever, at the end of
289	 * the next transaction (even if it was not the device addressed).
290	 * So our START and STOP take place with SCL held high.
291	 */
292	while (clock_cycles_left--) {
293		scl_out(dd, 0);
294		scl_out(dd, 1);
295		/* Note if SDA is high, but keep clocking to sync slave */
296		was_high |= sda_in(dd, 0);
297	}
298
299	if (was_high) {
300		/*
301		 * We saw a high, which we hope means the slave is sync'd.
302		 * Issue START, STOP, pause for T_BUF.
303		 */
304
305		pins = dd->f_gpio_mod(dd, 0, 0, 0);
306		if ((pins & mask) != mask)
307			qib_dev_err(dd, "GPIO pins not at rest: %d\n",
308				    pins & mask);
309		/* Drop SDA to issue START */
310		udelay(1); /* Guarantee .6 uSec setup */
311		sda_out(dd, 0);
312		udelay(1); /* Guarantee .6 uSec hold */
313		/* At this point, SCL is high, SDA low. Raise SDA for STOP */
314		sda_out(dd, 1);
315		udelay(TWSI_BUF_WAIT_USEC);
316	}
317
318	return !was_high;
319}
320
321#define QIB_TWSI_START 0x100
322#define QIB_TWSI_STOP 0x200
323
324/* Write byte to TWSI, optionally prefixed with START or suffixed with
325 * STOP.
326 * returns 0 if OK (ACK received), else != 0
327 */
328static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags)
329{
330	int ret = 1;
331
332	if (flags & QIB_TWSI_START)
333		start_seq(dd);
334
335	ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */
336
337	if (flags & QIB_TWSI_STOP)
338		stop_cmd(dd);
339	return ret;
340}
341
342/* Added functionality for IBA7220-based cards */
343#define QIB_TEMP_DEV 0x98
344
345/*
346 * qib_twsi_blk_rd
347 * Formerly called qib_eeprom_internal_read, and only used for eeprom,
348 * but now the general interface for data transfer from twsi devices.
349 * One vestige of its former role is that it recognizes a device
350 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
351 * which responded to all TWSI device codes, interpreting them as
352 * address within device. On all other devices found on board handled by
353 * this driver, the device is followed by a one-byte "address" which selects
354 * the "register" or "offset" within the device from which data should
355 * be read.
356 */
357int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr,
358		    void *buffer, int len)
359{
360	int ret;
361	u8 *bp = buffer;
362
363	ret = 1;
364
365	if (dev == QIB_TWSI_NO_DEV) {
366		/* legacy not-really-I2C */
367		addr = (addr << 1) | READ_CMD;
368		ret = qib_twsi_wr(dd, addr, QIB_TWSI_START);
369	} else {
370		/* Actual I2C */
371		ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START);
372		if (ret) {
373			stop_cmd(dd);
374			ret = 1;
375			goto bail;
376		}
377		/*
378		 * SFF spec claims we do _not_ stop after the addr
379		 * but simply issue a start with the "read" dev-addr.
380		 * Since we are implicitely waiting for ACK here,
381		 * we need t_buf (nominally 20uSec) before that start,
382		 * and cannot rely on the delay built in to the STOP
383		 */
384		ret = qib_twsi_wr(dd, addr, 0);
385		udelay(TWSI_BUF_WAIT_USEC);
386
387		if (ret) {
388			qib_dev_err(dd,
389				"Failed to write interface read addr %02X\n",
390				addr);
391			ret = 1;
392			goto bail;
393		}
394		ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START);
395	}
396	if (ret) {
397		stop_cmd(dd);
398		ret = 1;
399		goto bail;
400	}
401
402	/*
403	 * block devices keeps clocking data out as long as we ack,
404	 * automatically incrementing the address. Some have "pages"
405	 * whose boundaries will not be crossed, but the handling
406	 * of these is left to the caller, who is in a better
407	 * position to know.
408	 */
409	while (len-- > 0) {
410		/*
411		 * Get and store data, sending ACK if length remaining,
412		 * else STOP
413		 */
414		*bp++ = rd_byte(dd, !len);
415	}
416
417	ret = 0;
418
419bail:
420	return ret;
421}
422
423/*
424 * qib_twsi_blk_wr
425 * Formerly called qib_eeprom_internal_write, and only used for eeprom,
426 * but now the general interface for data transfer to twsi devices.
427 * One vestige of its former role is that it recognizes a device
428 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
429 * which responded to all TWSI device codes, interpreting them as
430 * address within device. On all other devices found on board handled by
431 * this driver, the device is followed by a one-byte "address" which selects
432 * the "register" or "offset" within the device to which data should
433 * be written.
434 */
435int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
436		    const void *buffer, int len)
437{
438	int sub_len;
439	const u8 *bp = buffer;
440	int max_wait_time, i;
441	int ret = 1;
442
443	while (len > 0) {
444		if (dev == QIB_TWSI_NO_DEV) {
445			if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,
446					QIB_TWSI_START)) {
447				goto failed_write;
448			}
449		} else {
450			/* Real I2C */
451			if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START))
452				goto failed_write;
453			ret = qib_twsi_wr(dd, addr, 0);
454			if (ret) {
455				qib_dev_err(dd,
456					"Failed to write interface write addr %02X\n",
457					addr);
458				goto failed_write;
459			}
460		}
461
462		sub_len = min(len, 4);
463		addr += sub_len;
464		len -= sub_len;
465
466		for (i = 0; i < sub_len; i++)
467			if (qib_twsi_wr(dd, *bp++, 0))
468				goto failed_write;
469
470		stop_cmd(dd);
471
472		/*
473		 * Wait for write complete by waiting for a successful
474		 * read (the chip replies with a zero after the write
475		 * cmd completes, and before it writes to the eeprom.
476		 * The startcmd for the read will fail the ack until
477		 * the writes have completed.   We do this inline to avoid
478		 * the debug prints that are in the real read routine
479		 * if the startcmd fails.
480		 * We also use the proper device address, so it doesn't matter
481		 * whether we have real eeprom_dev. Legacy likes any address.
482		 */
483		max_wait_time = 100;
484		while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) {
485			stop_cmd(dd);
486			if (!--max_wait_time)
487				goto failed_write;
488		}
489		/* now read (and ignore) the resulting byte */
490		rd_byte(dd, 1);
491	}
492
493	ret = 0;
494	goto bail;
495
496failed_write:
497	stop_cmd(dd);
498	ret = 1;
499
500bail:
501	return ret;
502}
503