1/* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef _HNS_ROCE_DEVICE_H 34#define _HNS_ROCE_DEVICE_H 35 36#include <rdma/ib_verbs.h> 37#include <rdma/hns-abi.h> 38 39#define PCI_REVISION_ID_HIP08 0x21 40#define PCI_REVISION_ID_HIP09 0x30 41 42#define HNS_ROCE_MAX_MSG_LEN 0x80000000 43 44#define HNS_ROCE_IB_MIN_SQ_STRIDE 6 45 46#define BA_BYTE_LEN 8 47 48#define HNS_ROCE_MIN_CQE_NUM 0x40 49#define HNS_ROCE_MIN_SRQ_WQE_NUM 1 50 51#define HNS_ROCE_MAX_IRQ_NUM 128 52 53#define HNS_ROCE_SGE_IN_WQE 2 54#define HNS_ROCE_SGE_SHIFT 4 55 56#define EQ_ENABLE 1 57#define EQ_DISABLE 0 58 59#define HNS_ROCE_CEQ 0 60#define HNS_ROCE_AEQ 1 61 62#define HNS_ROCE_CEQE_SIZE 0x4 63#define HNS_ROCE_AEQE_SIZE 0x10 64 65#define HNS_ROCE_V3_EQE_SIZE 0x40 66 67#define HNS_ROCE_V2_CQE_SIZE 32 68#define HNS_ROCE_V3_CQE_SIZE 64 69 70#define HNS_ROCE_V2_QPC_SZ 256 71#define HNS_ROCE_V3_QPC_SZ 512 72 73#define HNS_ROCE_MAX_PORTS 6 74#define HNS_ROCE_GID_SIZE 16 75#define HNS_ROCE_SGE_SIZE 16 76#define HNS_ROCE_DWQE_SIZE 65536 77 78#define HNS_ROCE_HOP_NUM_0 0xff 79 80#define MR_TYPE_MR 0x00 81#define MR_TYPE_FRMR 0x01 82#define MR_TYPE_DMA 0x03 83 84#define HNS_ROCE_FRMR_MAX_PA 512 85 86#define PKEY_ID 0xffff 87#define NODE_DESC_SIZE 64 88#define DB_REG_OFFSET 0x1000 89 90/* Configure to HW for PAGE_SIZE larger than 4KB */ 91#define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 92 93#define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 94#define SRQ_DB_REG 0x230 95 96#define HNS_ROCE_QP_BANK_NUM 8 97#define HNS_ROCE_CQ_BANK_NUM 4 98 99#define CQ_BANKID_SHIFT 2 100#define CQ_BANKID_MASK GENMASK(1, 0) 101 102enum { 103 SERV_TYPE_RC, 104 SERV_TYPE_UC, 105 SERV_TYPE_RD, 106 SERV_TYPE_UD, 107 SERV_TYPE_XRC = 5, 108}; 109 110enum hns_roce_event { 111 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 112 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 113 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 114 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 115 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 116 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 117 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 118 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 119 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 120 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 121 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 122 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 123 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 124 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 125 /* 0x10 and 0x11 is unused in currently application case */ 126 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 127 HNS_ROCE_EVENT_TYPE_MB = 0x13, 128 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 129 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 130 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 131}; 132 133enum { 134 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 135 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 136 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 137 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 138 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 139 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 140 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 141 HNS_ROCE_CAP_FLAG_MW = BIT(7), 142 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 143 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 144 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 145 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 146 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 147 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 148 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 149}; 150 151#define HNS_ROCE_DB_TYPE_COUNT 2 152#define HNS_ROCE_DB_UNIT_SIZE 4 153 154enum { 155 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 156}; 157 158enum hns_roce_reset_stage { 159 HNS_ROCE_STATE_NON_RST, 160 HNS_ROCE_STATE_RST_BEF_DOWN, 161 HNS_ROCE_STATE_RST_DOWN, 162 HNS_ROCE_STATE_RST_UNINIT, 163 HNS_ROCE_STATE_RST_INIT, 164 HNS_ROCE_STATE_RST_INITED, 165}; 166 167enum hns_roce_instance_state { 168 HNS_ROCE_STATE_NON_INIT, 169 HNS_ROCE_STATE_INIT, 170 HNS_ROCE_STATE_INITED, 171 HNS_ROCE_STATE_UNINIT, 172}; 173 174enum { 175 HNS_ROCE_RST_DIRECT_RETURN = 0, 176}; 177 178#define HNS_ROCE_CMD_SUCCESS 1 179 180/* The minimum page size is 4K for hardware */ 181#define HNS_HW_PAGE_SHIFT 12 182#define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 183 184struct hns_roce_uar { 185 u64 pfn; 186 unsigned long index; 187 unsigned long logic_idx; 188}; 189 190enum hns_roce_mmap_type { 191 HNS_ROCE_MMAP_TYPE_DB = 1, 192 HNS_ROCE_MMAP_TYPE_DWQE, 193}; 194 195struct hns_user_mmap_entry { 196 struct rdma_user_mmap_entry rdma_entry; 197 enum hns_roce_mmap_type mmap_type; 198 u64 address; 199}; 200 201struct hns_roce_ucontext { 202 struct ib_ucontext ibucontext; 203 struct hns_roce_uar uar; 204 struct list_head page_list; 205 struct mutex page_mutex; 206 struct hns_user_mmap_entry *db_mmap_entry; 207 u32 config; 208}; 209 210struct hns_roce_pd { 211 struct ib_pd ibpd; 212 unsigned long pdn; 213}; 214 215struct hns_roce_xrcd { 216 struct ib_xrcd ibxrcd; 217 u32 xrcdn; 218}; 219 220struct hns_roce_bitmap { 221 /* Bitmap Traversal last a bit which is 1 */ 222 unsigned long last; 223 unsigned long top; 224 unsigned long max; 225 unsigned long reserved_top; 226 unsigned long mask; 227 spinlock_t lock; 228 unsigned long *table; 229}; 230 231struct hns_roce_ida { 232 struct ida ida; 233 u32 min; /* Lowest ID to allocate. */ 234 u32 max; /* Highest ID to allocate. */ 235}; 236 237/* For Hardware Entry Memory */ 238struct hns_roce_hem_table { 239 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 240 u32 type; 241 /* HEM array elment num */ 242 unsigned long num_hem; 243 /* Single obj size */ 244 unsigned long obj_size; 245 unsigned long table_chunk_size; 246 struct mutex mutex; 247 struct hns_roce_hem **hem; 248 u64 **bt_l1; 249 dma_addr_t *bt_l1_dma_addr; 250 u64 **bt_l0; 251 dma_addr_t *bt_l0_dma_addr; 252}; 253 254struct hns_roce_buf_region { 255 u32 offset; /* page offset */ 256 u32 count; /* page count */ 257 int hopnum; /* addressing hop num */ 258}; 259 260#define HNS_ROCE_MAX_BT_REGION 3 261#define HNS_ROCE_MAX_BT_LEVEL 3 262struct hns_roce_hem_list { 263 struct list_head root_bt; 264 /* link all bt dma mem by hop config */ 265 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 266 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 267 dma_addr_t root_ba; /* pointer to the root ba table */ 268}; 269 270struct hns_roce_buf_attr { 271 struct { 272 size_t size; /* region size */ 273 int hopnum; /* multi-hop addressing hop num */ 274 } region[HNS_ROCE_MAX_BT_REGION]; 275 unsigned int region_count; /* valid region count */ 276 unsigned int page_shift; /* buffer page shift */ 277 unsigned int user_access; /* umem access flag */ 278 bool mtt_only; /* only alloc buffer-required MTT memory */ 279}; 280 281struct hns_roce_hem_cfg { 282 dma_addr_t root_ba; /* root BA table's address */ 283 bool is_direct; /* addressing without BA table */ 284 unsigned int ba_pg_shift; /* BA table page shift */ 285 unsigned int buf_pg_shift; /* buffer page shift */ 286 unsigned int buf_pg_count; /* buffer page count */ 287 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 288 unsigned int region_count; 289}; 290 291/* memory translate region */ 292struct hns_roce_mtr { 293 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 294 struct ib_umem *umem; /* user space buffer */ 295 struct hns_roce_buf *kmem; /* kernel space buffer */ 296 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 297}; 298 299struct hns_roce_mw { 300 struct ib_mw ibmw; 301 u32 pdn; 302 u32 rkey; 303 int enabled; /* MW's active status */ 304 u32 pbl_hop_num; 305 u32 pbl_ba_pg_sz; 306 u32 pbl_buf_pg_sz; 307}; 308 309struct hns_roce_mr { 310 struct ib_mr ibmr; 311 u64 iova; /* MR's virtual original addr */ 312 u64 size; /* Address range of MR */ 313 u32 key; /* Key of MR */ 314 u32 pd; /* PD num of MR */ 315 u32 access; /* Access permission of MR */ 316 int enabled; /* MR's active status */ 317 int type; /* MR's register type */ 318 u32 pbl_hop_num; /* multi-hop number */ 319 struct hns_roce_mtr pbl_mtr; 320 u32 npages; 321 dma_addr_t *page_list; 322}; 323 324struct hns_roce_mr_table { 325 struct hns_roce_ida mtpt_ida; 326 struct hns_roce_hem_table mtpt_table; 327}; 328 329struct hns_roce_wq { 330 u64 *wrid; /* Work request ID */ 331 spinlock_t lock; 332 u32 wqe_cnt; /* WQE num */ 333 u32 max_gs; 334 u32 rsv_sge; 335 u32 offset; 336 u32 wqe_shift; /* WQE size */ 337 u32 head; 338 u32 tail; 339 void __iomem *db_reg; 340 u32 ext_sge_cnt; 341}; 342 343struct hns_roce_sge { 344 unsigned int sge_cnt; /* SGE num */ 345 u32 offset; 346 u32 sge_shift; /* SGE size */ 347}; 348 349struct hns_roce_buf_list { 350 void *buf; 351 dma_addr_t map; 352}; 353 354/* 355 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 356 * dma address range. 357 * 358 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 359 * 360 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 361 * the allocated size is smaller than the required size. 362 */ 363enum { 364 HNS_ROCE_BUF_DIRECT = BIT(0), 365 HNS_ROCE_BUF_NOSLEEP = BIT(1), 366 HNS_ROCE_BUF_NOFAIL = BIT(2), 367}; 368 369struct hns_roce_buf { 370 struct hns_roce_buf_list *trunk_list; 371 u32 ntrunks; 372 u32 npages; 373 unsigned int trunk_shift; 374 unsigned int page_shift; 375}; 376 377struct hns_roce_db_pgdir { 378 struct list_head list; 379 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 380 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 381 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 382 u32 *page; 383 dma_addr_t db_dma; 384}; 385 386struct hns_roce_user_db_page { 387 struct list_head list; 388 struct ib_umem *umem; 389 unsigned long user_virt; 390 refcount_t refcount; 391}; 392 393struct hns_roce_db { 394 u32 *db_record; 395 union { 396 struct hns_roce_db_pgdir *pgdir; 397 struct hns_roce_user_db_page *user_page; 398 } u; 399 dma_addr_t dma; 400 void *virt_addr; 401 unsigned long index; 402 unsigned long order; 403}; 404 405struct hns_roce_cq { 406 struct ib_cq ib_cq; 407 struct hns_roce_mtr mtr; 408 struct hns_roce_db db; 409 u32 flags; 410 spinlock_t lock; 411 u32 cq_depth; 412 u32 cons_index; 413 u32 *set_ci_db; 414 void __iomem *db_reg; 415 int arm_sn; 416 int cqe_size; 417 unsigned long cqn; 418 u32 vector; 419 refcount_t refcount; 420 struct completion free; 421 struct list_head sq_list; /* all qps on this send cq */ 422 struct list_head rq_list; /* all qps on this recv cq */ 423 int is_armed; /* cq is armed */ 424 struct list_head node; /* all armed cqs are on a list */ 425}; 426 427struct hns_roce_idx_que { 428 struct hns_roce_mtr mtr; 429 u32 entry_shift; 430 unsigned long *bitmap; 431 u32 head; 432 u32 tail; 433}; 434 435struct hns_roce_srq { 436 struct ib_srq ibsrq; 437 unsigned long srqn; 438 u32 wqe_cnt; 439 int max_gs; 440 u32 rsv_sge; 441 u32 wqe_shift; 442 u32 cqn; 443 u32 xrcdn; 444 void __iomem *db_reg; 445 446 refcount_t refcount; 447 struct completion free; 448 449 struct hns_roce_mtr buf_mtr; 450 451 u64 *wrid; 452 struct hns_roce_idx_que idx_que; 453 spinlock_t lock; 454 struct mutex mutex; 455 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 456}; 457 458struct hns_roce_uar_table { 459 struct hns_roce_bitmap bitmap; 460}; 461 462struct hns_roce_bank { 463 struct ida ida; 464 u32 inuse; /* Number of IDs allocated */ 465 u32 min; /* Lowest ID to allocate. */ 466 u32 max; /* Highest ID to allocate. */ 467 u32 next; /* Next ID to allocate. */ 468}; 469 470struct hns_roce_idx_table { 471 u32 *spare_idx; 472 u32 head; 473 u32 tail; 474}; 475 476struct hns_roce_qp_table { 477 struct hns_roce_hem_table qp_table; 478 struct hns_roce_hem_table irrl_table; 479 struct hns_roce_hem_table trrl_table; 480 struct hns_roce_hem_table sccc_table; 481 struct mutex scc_mutex; 482 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 483 struct mutex bank_mutex; 484 struct hns_roce_idx_table idx_table; 485}; 486 487struct hns_roce_cq_table { 488 struct xarray array; 489 struct hns_roce_hem_table table; 490 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 491 struct mutex bank_mutex; 492}; 493 494struct hns_roce_srq_table { 495 struct hns_roce_ida srq_ida; 496 struct xarray xa; 497 struct hns_roce_hem_table table; 498}; 499 500struct hns_roce_av { 501 u8 port; 502 u8 gid_index; 503 u8 stat_rate; 504 u8 hop_limit; 505 u32 flowlabel; 506 u16 udp_sport; 507 u8 sl; 508 u8 tclass; 509 u8 dgid[HNS_ROCE_GID_SIZE]; 510 u8 mac[ETH_ALEN]; 511 u16 vlan_id; 512 u8 vlan_en; 513}; 514 515struct hns_roce_ah { 516 struct ib_ah ibah; 517 struct hns_roce_av av; 518}; 519 520struct hns_roce_cmd_context { 521 struct completion done; 522 int result; 523 int next; 524 u64 out_param; 525 u16 token; 526 u16 busy; 527}; 528 529enum hns_roce_cmdq_state { 530 HNS_ROCE_CMDQ_STATE_NORMAL, 531 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 532}; 533 534struct hns_roce_cmdq { 535 struct dma_pool *pool; 536 struct semaphore poll_sem; 537 /* 538 * Event mode: cmd register mutex protection, 539 * ensure to not exceed max_cmds and user use limit region 540 */ 541 struct semaphore event_sem; 542 int max_cmds; 543 spinlock_t context_lock; 544 int free_head; 545 struct hns_roce_cmd_context *context; 546 /* 547 * Process whether use event mode, init default non-zero 548 * After the event queue of cmd event ready, 549 * can switch into event mode 550 * close device, switch into poll mode(non event mode) 551 */ 552 u8 use_events; 553 enum hns_roce_cmdq_state state; 554}; 555 556struct hns_roce_cmd_mailbox { 557 void *buf; 558 dma_addr_t dma; 559}; 560 561struct hns_roce_mbox_msg { 562 u64 in_param; 563 u64 out_param; 564 u8 cmd; 565 u32 tag; 566 u16 token; 567 u8 event_en; 568}; 569 570struct hns_roce_dev; 571 572enum { 573 HNS_ROCE_FLUSH_FLAG = 0, 574}; 575 576struct hns_roce_work { 577 struct hns_roce_dev *hr_dev; 578 struct work_struct work; 579 int event_type; 580 int sub_type; 581 u32 queue_num; 582}; 583 584enum hns_roce_cong_type { 585 CONG_TYPE_DCQCN, 586 CONG_TYPE_LDCP, 587 CONG_TYPE_HC3, 588 CONG_TYPE_DIP, 589}; 590 591struct hns_roce_qp { 592 struct ib_qp ibqp; 593 struct hns_roce_wq rq; 594 struct hns_roce_db rdb; 595 struct hns_roce_db sdb; 596 unsigned long en_flags; 597 enum ib_sig_type sq_signal_bits; 598 struct hns_roce_wq sq; 599 600 struct hns_roce_mtr mtr; 601 602 u32 buff_size; 603 struct mutex mutex; 604 u8 port; 605 u8 phy_port; 606 u8 sl; 607 u8 resp_depth; 608 u8 state; 609 u32 atomic_rd_en; 610 u32 qkey; 611 void (*event)(struct hns_roce_qp *qp, 612 enum hns_roce_event event_type); 613 unsigned long qpn; 614 615 u32 xrcdn; 616 617 refcount_t refcount; 618 struct completion free; 619 620 struct hns_roce_sge sge; 621 u32 next_sge; 622 enum ib_mtu path_mtu; 623 u32 max_inline_data; 624 u8 free_mr_en; 625 626 /* 0: flush needed, 1: unneeded */ 627 unsigned long flush_flag; 628 struct hns_roce_work flush_work; 629 struct list_head node; /* all qps are on a list */ 630 struct list_head rq_node; /* all recv qps are on a list */ 631 struct list_head sq_node; /* all send qps are on a list */ 632 struct hns_user_mmap_entry *dwqe_mmap_entry; 633 u32 config; 634 enum hns_roce_cong_type cong_type; 635}; 636 637struct hns_roce_ib_iboe { 638 spinlock_t lock; 639 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 640 struct notifier_block nb; 641 u8 phy_port[HNS_ROCE_MAX_PORTS]; 642}; 643 644struct hns_roce_ceqe { 645 __le32 comp; 646 __le32 rsv[15]; 647}; 648 649#define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 650 651#define CEQE_CQN CEQE_FIELD_LOC(23, 0) 652#define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 653 654struct hns_roce_aeqe { 655 __le32 asyn; 656 union { 657 struct { 658 __le32 num; 659 u32 rsv0; 660 u32 rsv1; 661 } queue_event; 662 663 struct { 664 __le64 out_param; 665 __le16 token; 666 u8 status; 667 u8 rsv0; 668 } __packed cmd; 669 } event; 670 __le32 rsv[12]; 671}; 672 673#define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 674 675#define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 676#define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 677#define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 678#define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 679 680struct hns_roce_eq { 681 struct hns_roce_dev *hr_dev; 682 void __iomem *db_reg; 683 684 int type_flag; /* Aeq:1 ceq:0 */ 685 int eqn; 686 u32 entries; 687 int eqe_size; 688 int irq; 689 u32 cons_index; 690 int over_ignore; 691 int coalesce; 692 int arm_st; 693 int hop_num; 694 struct hns_roce_mtr mtr; 695 u16 eq_max_cnt; 696 u32 eq_period; 697 int shift; 698 int event_type; 699 int sub_type; 700}; 701 702struct hns_roce_eq_table { 703 struct hns_roce_eq *eq; 704}; 705 706struct hns_roce_caps { 707 u64 fw_ver; 708 u8 num_ports; 709 int gid_table_len[HNS_ROCE_MAX_PORTS]; 710 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 711 int local_ca_ack_delay; 712 int num_uars; 713 u32 phy_num_uars; 714 u32 max_sq_sg; 715 u32 max_sq_inline; 716 u32 max_rq_sg; 717 u32 rsv0; 718 u32 num_qps; 719 u32 reserved_qps; 720 u32 num_srqs; 721 u32 max_wqes; 722 u32 max_srq_wrs; 723 u32 max_srq_sges; 724 u32 max_sq_desc_sz; 725 u32 max_rq_desc_sz; 726 u32 rsv2; 727 int max_qp_init_rdma; 728 int max_qp_dest_rdma; 729 u32 num_cqs; 730 u32 max_cqes; 731 u32 min_cqes; 732 u32 min_wqes; 733 u32 reserved_cqs; 734 u32 reserved_srqs; 735 int num_aeq_vectors; 736 int num_comp_vectors; 737 int num_other_vectors; 738 u32 num_mtpts; 739 u32 rsv1; 740 u32 num_srqwqe_segs; 741 u32 num_idx_segs; 742 int reserved_mrws; 743 int reserved_uars; 744 int num_pds; 745 int reserved_pds; 746 u32 num_xrcds; 747 u32 reserved_xrcds; 748 u32 mtt_entry_sz; 749 u32 cqe_sz; 750 u32 page_size_cap; 751 u32 reserved_lkey; 752 int mtpt_entry_sz; 753 int qpc_sz; 754 int irrl_entry_sz; 755 int trrl_entry_sz; 756 int cqc_entry_sz; 757 int sccc_sz; 758 int qpc_timer_entry_sz; 759 int cqc_timer_entry_sz; 760 int srqc_entry_sz; 761 int idx_entry_sz; 762 u32 pbl_ba_pg_sz; 763 u32 pbl_buf_pg_sz; 764 u32 pbl_hop_num; 765 int aeqe_depth; 766 int ceqe_depth; 767 u32 aeqe_size; 768 u32 ceqe_size; 769 enum ib_mtu max_mtu; 770 u32 qpc_bt_num; 771 u32 qpc_timer_bt_num; 772 u32 srqc_bt_num; 773 u32 cqc_bt_num; 774 u32 cqc_timer_bt_num; 775 u32 mpt_bt_num; 776 u32 eqc_bt_num; 777 u32 smac_bt_num; 778 u32 sgid_bt_num; 779 u32 sccc_bt_num; 780 u32 gmv_bt_num; 781 u32 qpc_ba_pg_sz; 782 u32 qpc_buf_pg_sz; 783 u32 qpc_hop_num; 784 u32 srqc_ba_pg_sz; 785 u32 srqc_buf_pg_sz; 786 u32 srqc_hop_num; 787 u32 cqc_ba_pg_sz; 788 u32 cqc_buf_pg_sz; 789 u32 cqc_hop_num; 790 u32 mpt_ba_pg_sz; 791 u32 mpt_buf_pg_sz; 792 u32 mpt_hop_num; 793 u32 mtt_ba_pg_sz; 794 u32 mtt_buf_pg_sz; 795 u32 mtt_hop_num; 796 u32 wqe_sq_hop_num; 797 u32 wqe_sge_hop_num; 798 u32 wqe_rq_hop_num; 799 u32 sccc_ba_pg_sz; 800 u32 sccc_buf_pg_sz; 801 u32 sccc_hop_num; 802 u32 qpc_timer_ba_pg_sz; 803 u32 qpc_timer_buf_pg_sz; 804 u32 qpc_timer_hop_num; 805 u32 cqc_timer_ba_pg_sz; 806 u32 cqc_timer_buf_pg_sz; 807 u32 cqc_timer_hop_num; 808 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 809 u32 cqe_buf_pg_sz; 810 u32 cqe_hop_num; 811 u32 srqwqe_ba_pg_sz; 812 u32 srqwqe_buf_pg_sz; 813 u32 srqwqe_hop_num; 814 u32 idx_ba_pg_sz; 815 u32 idx_buf_pg_sz; 816 u32 idx_hop_num; 817 u32 eqe_ba_pg_sz; 818 u32 eqe_buf_pg_sz; 819 u32 eqe_hop_num; 820 u32 gmv_entry_num; 821 u32 gmv_entry_sz; 822 u32 gmv_ba_pg_sz; 823 u32 gmv_buf_pg_sz; 824 u32 gmv_hop_num; 825 u32 sl_num; 826 u32 llm_buf_pg_sz; 827 u32 chunk_sz; /* chunk size in non multihop mode */ 828 u64 flags; 829 u16 default_ceq_max_cnt; 830 u16 default_ceq_period; 831 u16 default_aeq_max_cnt; 832 u16 default_aeq_period; 833 u16 default_aeq_arm_st; 834 u16 default_ceq_arm_st; 835 enum hns_roce_cong_type cong_type; 836}; 837 838enum hns_roce_device_state { 839 HNS_ROCE_DEVICE_STATE_INITED, 840 HNS_ROCE_DEVICE_STATE_RST_DOWN, 841 HNS_ROCE_DEVICE_STATE_UNINIT, 842}; 843 844enum hns_roce_hw_pkt_stat_index { 845 HNS_ROCE_HW_RX_RC_PKT_CNT, 846 HNS_ROCE_HW_RX_UC_PKT_CNT, 847 HNS_ROCE_HW_RX_UD_PKT_CNT, 848 HNS_ROCE_HW_RX_XRC_PKT_CNT, 849 HNS_ROCE_HW_RX_PKT_CNT, 850 HNS_ROCE_HW_RX_ERR_PKT_CNT, 851 HNS_ROCE_HW_RX_CNP_PKT_CNT, 852 HNS_ROCE_HW_TX_RC_PKT_CNT, 853 HNS_ROCE_HW_TX_UC_PKT_CNT, 854 HNS_ROCE_HW_TX_UD_PKT_CNT, 855 HNS_ROCE_HW_TX_XRC_PKT_CNT, 856 HNS_ROCE_HW_TX_PKT_CNT, 857 HNS_ROCE_HW_TX_ERR_PKT_CNT, 858 HNS_ROCE_HW_TX_CNP_PKT_CNT, 859 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 860 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 861 HNS_ROCE_HW_ECN_DB_CNT, 862 HNS_ROCE_HW_RX_BUF_CNT, 863 HNS_ROCE_HW_TRP_RX_SOF_CNT, 864 HNS_ROCE_HW_CQ_CQE_CNT, 865 HNS_ROCE_HW_CQ_POE_CNT, 866 HNS_ROCE_HW_CQ_NOTIFY_CNT, 867 HNS_ROCE_HW_CNT_TOTAL 868}; 869 870struct hns_roce_hw { 871 int (*cmq_init)(struct hns_roce_dev *hr_dev); 872 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 873 int (*hw_profile)(struct hns_roce_dev *hr_dev); 874 int (*hw_init)(struct hns_roce_dev *hr_dev); 875 void (*hw_exit)(struct hns_roce_dev *hr_dev); 876 int (*post_mbox)(struct hns_roce_dev *hr_dev, 877 struct hns_roce_mbox_msg *mbox_msg); 878 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 879 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 880 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 881 const union ib_gid *gid, const struct ib_gid_attr *attr); 882 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 883 const u8 *addr); 884 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 885 struct hns_roce_mr *mr); 886 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 887 struct hns_roce_mr *mr, int flags, 888 void *mb_buf); 889 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 890 struct hns_roce_mr *mr); 891 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 892 void (*write_cqc)(struct hns_roce_dev *hr_dev, 893 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 894 dma_addr_t dma_handle); 895 int (*set_hem)(struct hns_roce_dev *hr_dev, 896 struct hns_roce_hem_table *table, int obj, u32 step_idx); 897 int (*clear_hem)(struct hns_roce_dev *hr_dev, 898 struct hns_roce_hem_table *table, int obj, 899 u32 step_idx); 900 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 901 int attr_mask, enum ib_qp_state cur_state, 902 enum ib_qp_state new_state, struct ib_udata *udata); 903 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 904 struct hns_roce_qp *hr_qp); 905 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 906 int (*init_eq)(struct hns_roce_dev *hr_dev); 907 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 908 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 909 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 910 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 911 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 912 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 913 u64 *stats, u32 port, int *hw_counters); 914 const struct ib_device_ops *hns_roce_dev_ops; 915 const struct ib_device_ops *hns_roce_dev_srq_ops; 916}; 917 918struct hns_roce_dev { 919 struct ib_device ib_dev; 920 struct pci_dev *pci_dev; 921 struct device *dev; 922 struct hns_roce_uar priv_uar; 923 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 924 spinlock_t sm_lock; 925 bool active; 926 bool is_reset; 927 bool dis_db; 928 unsigned long reset_cnt; 929 struct hns_roce_ib_iboe iboe; 930 enum hns_roce_device_state state; 931 struct list_head qp_list; /* list of all qps on this dev */ 932 spinlock_t qp_list_lock; /* protect qp_list */ 933 struct list_head dip_list; /* list of all dest ips on this dev */ 934 spinlock_t dip_list_lock; /* protect dip_list */ 935 936 struct list_head pgdir_list; 937 struct mutex pgdir_mutex; 938 int irq[HNS_ROCE_MAX_IRQ_NUM]; 939 u8 __iomem *reg_base; 940 void __iomem *mem_base; 941 struct hns_roce_caps caps; 942 struct xarray qp_table_xa; 943 944 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 945 u64 sys_image_guid; 946 u32 vendor_id; 947 u32 vendor_part_id; 948 u32 hw_rev; 949 void __iomem *priv_addr; 950 951 struct hns_roce_cmdq cmd; 952 struct hns_roce_ida pd_ida; 953 struct hns_roce_ida xrcd_ida; 954 struct hns_roce_ida uar_ida; 955 struct hns_roce_mr_table mr_table; 956 struct hns_roce_cq_table cq_table; 957 struct hns_roce_srq_table srq_table; 958 struct hns_roce_qp_table qp_table; 959 struct hns_roce_eq_table eq_table; 960 struct hns_roce_hem_table qpc_timer_table; 961 struct hns_roce_hem_table cqc_timer_table; 962 /* GMV is the memory area that the driver allocates for the hardware 963 * to store SGID, SMAC and VLAN information. 964 */ 965 struct hns_roce_hem_table gmv_table; 966 967 int cmd_mod; 968 int loop_idc; 969 u32 sdb_offset; 970 u32 odb_offset; 971 const struct hns_roce_hw *hw; 972 void *priv; 973 struct workqueue_struct *irq_workq; 974 struct work_struct ecc_work; 975 u32 func_num; 976 u32 is_vf; 977 u32 cong_algo_tmpl_id; 978 u64 dwqe_page; 979}; 980 981static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 982{ 983 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 984} 985 986static inline struct hns_roce_ucontext 987 *to_hr_ucontext(struct ib_ucontext *ibucontext) 988{ 989 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 990} 991 992static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 993{ 994 return container_of(ibpd, struct hns_roce_pd, ibpd); 995} 996 997static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 998{ 999 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1000} 1001 1002static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1003{ 1004 return container_of(ibah, struct hns_roce_ah, ibah); 1005} 1006 1007static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1008{ 1009 return container_of(ibmr, struct hns_roce_mr, ibmr); 1010} 1011 1012static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1013{ 1014 return container_of(ibmw, struct hns_roce_mw, ibmw); 1015} 1016 1017static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1018{ 1019 return container_of(ibqp, struct hns_roce_qp, ibqp); 1020} 1021 1022static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1023{ 1024 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1025} 1026 1027static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1028{ 1029 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1030} 1031 1032static inline struct hns_user_mmap_entry * 1033to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1034{ 1035 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1036} 1037 1038static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1039{ 1040 writeq(*(u64 *)val, dest); 1041} 1042 1043static inline struct hns_roce_qp 1044 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1045{ 1046 return xa_load(&hr_dev->qp_table_xa, qpn); 1047} 1048 1049static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1050 unsigned int offset) 1051{ 1052 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1053 (offset & ((1 << buf->trunk_shift) - 1)); 1054} 1055 1056static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1057 unsigned int offset) 1058{ 1059 return buf->trunk_list[offset >> buf->trunk_shift].map + 1060 (offset & ((1 << buf->trunk_shift) - 1)); 1061} 1062 1063static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1064{ 1065 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1066} 1067 1068#define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1069 1070static inline u64 to_hr_hw_page_addr(u64 addr) 1071{ 1072 return addr >> HNS_HW_PAGE_SHIFT; 1073} 1074 1075static inline u32 to_hr_hw_page_shift(u32 page_shift) 1076{ 1077 return page_shift - HNS_HW_PAGE_SHIFT; 1078} 1079 1080static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1081{ 1082 if (count > 0) 1083 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1084 1085 return 0; 1086} 1087 1088static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1089{ 1090 return hr_hw_page_align(count << buf_shift); 1091} 1092 1093static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1094{ 1095 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1096} 1097 1098static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1099{ 1100 if (!count) 1101 return 0; 1102 1103 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1104} 1105 1106#define DSCP_SHIFT 2 1107 1108static inline u8 get_tclass(const struct ib_global_route *grh) 1109{ 1110 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1111 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1112} 1113 1114void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1115int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1116 1117int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1118void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1119void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1120 u64 out_param); 1121int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1122void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1123 1124/* hns roce hw need current block and next block addr from mtt */ 1125#define MTT_MIN_COUNT 2 1126int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1127 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1128int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1129 struct hns_roce_buf_attr *buf_attr, 1130 unsigned int page_shift, struct ib_udata *udata, 1131 unsigned long user_addr); 1132void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1133 struct hns_roce_mtr *mtr); 1134int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1135 dma_addr_t *pages, unsigned int page_cnt); 1136 1137void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1138void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1139void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1140int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1141void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1142void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1143 1144void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1145void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1146 1147void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1148 1149int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1150 struct ib_udata *udata); 1151int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1152static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1153{ 1154 return 0; 1155} 1156 1157int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1158int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1159 1160struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1161struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1162 u64 virt_addr, int access_flags, 1163 struct ib_udata *udata); 1164struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1165 u64 length, u64 virt_addr, 1166 int mr_access_flags, struct ib_pd *pd, 1167 struct ib_udata *udata); 1168struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1169 u32 max_num_sg); 1170int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1171 unsigned int *sg_offset); 1172int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1173unsigned long key_to_hw_index(u32 key); 1174 1175int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1176int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1177 1178void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1179struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1180 u32 page_shift, u32 flags); 1181 1182int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1183 int buf_cnt, struct hns_roce_buf *buf, 1184 unsigned int page_shift); 1185int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1186 int buf_cnt, struct ib_umem *umem, 1187 unsigned int page_shift); 1188 1189int hns_roce_create_srq(struct ib_srq *srq, 1190 struct ib_srq_init_attr *srq_init_attr, 1191 struct ib_udata *udata); 1192int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1193 1194int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1195int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1196 1197int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1198 struct ib_udata *udata); 1199int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1200 int attr_mask, struct ib_udata *udata); 1201void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1202void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1203void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1204void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1205bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1206 struct ib_cq *ib_cq); 1207void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1208 struct hns_roce_cq *recv_cq); 1209void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1210 struct hns_roce_cq *recv_cq); 1211void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1212void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1213 struct ib_udata *udata); 1214__be32 send_ieth(const struct ib_send_wr *wr); 1215int to_hr_qp_type(int qp_type); 1216 1217int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1218 struct ib_udata *udata); 1219 1220int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1221int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1222 struct hns_roce_db *db); 1223void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1224 struct hns_roce_db *db); 1225int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1226 int order); 1227void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1228 1229void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1230void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1231void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1232void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1233void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1234void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1235int hns_roce_init(struct hns_roce_dev *hr_dev); 1236void hns_roce_exit(struct hns_roce_dev *hr_dev); 1237int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1238int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1239int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1240int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1241int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1242int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1243struct hns_user_mmap_entry * 1244hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1245 size_t length, 1246 enum hns_roce_mmap_type mmap_type); 1247#endif /* _HNS_ROCE_DEVICE_H */ 1248