1/* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RoCE HSI File - Autogenerated 37 */ 38 39#ifndef __BNXT_RE_HSI_H__ 40#define __BNXT_RE_HSI_H__ 41 42/* include bnxt_hsi.h from bnxt_en driver */ 43#include "bnxt_hsi.h" 44 45/* tx_doorbell (size:32b/4B) */ 46struct tx_doorbell { 47 __le32 key_idx; 48 #define TX_DOORBELL_IDX_MASK 0xffffffUL 49 #define TX_DOORBELL_IDX_SFT 0 50 #define TX_DOORBELL_KEY_MASK 0xf0000000UL 51 #define TX_DOORBELL_KEY_SFT 28 52 #define TX_DOORBELL_KEY_TX (0x0UL << 28) 53 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX 54}; 55 56/* rx_doorbell (size:32b/4B) */ 57struct rx_doorbell { 58 __le32 key_idx; 59 #define RX_DOORBELL_IDX_MASK 0xffffffUL 60 #define RX_DOORBELL_IDX_SFT 0 61 #define RX_DOORBELL_KEY_MASK 0xf0000000UL 62 #define RX_DOORBELL_KEY_SFT 28 63 #define RX_DOORBELL_KEY_RX (0x1UL << 28) 64 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX 65}; 66 67/* cmpl_doorbell (size:32b/4B) */ 68struct cmpl_doorbell { 69 __le32 key_mask_valid_idx; 70 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 71 #define CMPL_DOORBELL_IDX_SFT 0 72 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 73 #define CMPL_DOORBELL_MASK 0x8000000UL 74 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 75 #define CMPL_DOORBELL_KEY_SFT 28 76 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 77 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL 78}; 79 80/* status_doorbell (size:32b/4B) */ 81struct status_doorbell { 82 __le32 key_idx; 83 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 84 #define STATUS_DOORBELL_IDX_SFT 0 85 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 86 #define STATUS_DOORBELL_KEY_SFT 28 87 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 88 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT 89}; 90 91/* cmdq_init (size:128b/16B) */ 92struct cmdq_init { 93 __le64 cmdq_pbl; 94 __le16 cmdq_size_cmdq_lvl; 95 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 96 #define CMDQ_INIT_CMDQ_LVL_SFT 0 97 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 98 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 99 __le16 creq_ring_id; 100 __le32 prod_idx; 101}; 102 103/* cmdq_base (size:128b/16B) */ 104struct cmdq_base { 105 u8 opcode; 106 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 107 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 108 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 109 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 110 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 111 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 112 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 113 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 114 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 115 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 116 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 117 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 118 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 119 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 120 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 121 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 122 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 123 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 124 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 125 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 126 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 127 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 128 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 129 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 130 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 131 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 132 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 133 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 134 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 135 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 136 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 137 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 138 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 139 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 140 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL 141 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL 142 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 143 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 144 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL 145 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL 146 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 147 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 148 u8 cmd_size; 149 __le16 flags; 150 __le16 cookie; 151 u8 resp_size; 152 u8 reserved8; 153 __le64 resp_addr; 154}; 155 156/* creq_base (size:128b/16B) */ 157struct creq_base { 158 u8 type; 159 #define CREQ_BASE_TYPE_MASK 0x3fUL 160 #define CREQ_BASE_TYPE_SFT 0 161 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 162 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 163 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT 164 u8 reserved56[7]; 165 u8 v; 166 #define CREQ_BASE_V 0x1UL 167 u8 event; 168 u8 reserved48[6]; 169}; 170 171/* cmdq_query_version (size:128b/16B) */ 172struct cmdq_query_version { 173 u8 opcode; 174 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 175 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 176 u8 cmd_size; 177 __le16 flags; 178 __le16 cookie; 179 u8 resp_size; 180 u8 reserved8; 181 __le64 resp_addr; 182}; 183 184/* creq_query_version_resp (size:128b/16B) */ 185struct creq_query_version_resp { 186 u8 type; 187 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 188 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 189 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 190 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 191 u8 status; 192 __le16 cookie; 193 u8 fw_maj; 194 u8 fw_minor; 195 u8 fw_bld; 196 u8 fw_rsvd; 197 u8 v; 198 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 199 u8 event; 200 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 201 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \ 202 CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 203 __le16 reserved16; 204 u8 intf_maj; 205 u8 intf_minor; 206 u8 intf_bld; 207 u8 intf_rsvd; 208}; 209 210/* cmdq_initialize_fw (size:896b/112B) */ 211struct cmdq_initialize_fw { 212 u8 opcode; 213 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 214 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 215 u8 cmd_size; 216 __le16 flags; 217 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 218 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL 219 __le16 cookie; 220 u8 resp_size; 221 u8 reserved8; 222 __le64 resp_addr; 223 u8 qpc_pg_size_qpc_lvl; 224 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 225 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 226 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 227 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 228 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 229 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 230 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 231 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 232 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 233 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 234 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 235 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 236 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 237 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 238 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G 239 u8 mrw_pg_size_mrw_lvl; 240 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 241 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 242 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 243 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 244 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 245 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 246 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 247 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 248 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 249 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 250 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 251 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 252 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 253 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 254 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G 255 u8 srq_pg_size_srq_lvl; 256 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 257 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 258 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 259 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 260 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 261 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 262 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 263 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 264 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 265 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 266 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 267 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 268 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 269 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 270 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G 271 u8 cq_pg_size_cq_lvl; 272 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 273 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 274 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 275 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 276 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 277 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 278 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 279 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 280 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 281 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 282 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 283 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 284 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 285 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 286 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G 287 u8 tqm_pg_size_tqm_lvl; 288 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 289 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 290 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 291 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 292 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 293 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 294 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 295 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 296 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 297 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 298 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 299 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 300 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 301 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 302 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G 303 u8 tim_pg_size_tim_lvl; 304 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 305 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 306 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 307 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 308 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 309 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 310 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 311 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 312 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 313 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 314 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 315 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 316 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 317 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 318 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G 319 __le16 log2_dbr_pg_size; 320 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 321 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 322 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 323 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 324 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 325 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 326 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 327 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 328 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 329 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 330 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 331 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 332 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 333 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 334 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 335 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 336 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 337 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 338 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 339 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 340 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL 341 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 342 __le64 qpc_page_dir; 343 __le64 mrw_page_dir; 344 __le64 srq_page_dir; 345 __le64 cq_page_dir; 346 __le64 tqm_page_dir; 347 __le64 tim_page_dir; 348 __le32 number_of_qp; 349 __le32 number_of_mrw; 350 __le32 number_of_srq; 351 __le32 number_of_cq; 352 __le32 max_qp_per_vf; 353 __le32 max_mrw_per_vf; 354 __le32 max_srq_per_vf; 355 __le32 max_cq_per_vf; 356 __le32 max_gid_per_vf; 357 __le32 stat_ctx_id; 358}; 359 360/* creq_initialize_fw_resp (size:128b/16B) */ 361struct creq_initialize_fw_resp { 362 u8 type; 363 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 364 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 365 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 366 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 367 u8 status; 368 __le16 cookie; 369 __le32 reserved32; 370 u8 v; 371 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 372 u8 event; 373 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 374 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \ 375 CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 376 u8 reserved48[6]; 377}; 378 379/* cmdq_deinitialize_fw (size:128b/16B) */ 380struct cmdq_deinitialize_fw { 381 u8 opcode; 382 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 383 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \ 384 CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 385 u8 cmd_size; 386 __le16 flags; 387 __le16 cookie; 388 u8 resp_size; 389 u8 reserved8; 390 __le64 resp_addr; 391}; 392 393/* creq_deinitialize_fw_resp (size:128b/16B) */ 394struct creq_deinitialize_fw_resp { 395 u8 type; 396 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 397 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 398 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 399 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 400 u8 status; 401 __le16 cookie; 402 __le32 reserved32; 403 u8 v; 404 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 405 u8 event; 406 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 407 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \ 408 CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 409 u8 reserved48[6]; 410}; 411 412/* cmdq_create_qp (size:768b/96B) */ 413struct cmdq_create_qp { 414 u8 opcode; 415 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 416 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP 417 u8 cmd_size; 418 __le16 flags; 419 __le16 cookie; 420 u8 resp_size; 421 u8 reserved8; 422 __le64 resp_addr; 423 __le64 qp_handle; 424 __le32 qp_flags; 425 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 426 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 427 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 428 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 429 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 430 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL 431 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL 432 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 433 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \ 434 CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 435 u8 type; 436 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 437 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 438 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 439 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 440 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI 441 u8 sq_pg_size_sq_lvl; 442 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 443 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 444 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 445 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 446 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 447 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 448 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 449 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 450 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 451 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 452 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 453 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 454 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 455 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 456 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G 457 u8 rq_pg_size_rq_lvl; 458 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 459 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 460 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 461 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 462 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 463 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 464 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 465 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 466 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 467 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 468 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 469 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 470 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 471 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 472 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G 473 u8 unused_0; 474 __le32 dpi; 475 __le32 sq_size; 476 __le32 rq_size; 477 __le16 sq_fwo_sq_sge; 478 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 479 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 480 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 481 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 482 __le16 rq_fwo_rq_sge; 483 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 484 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 485 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 486 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 487 __le32 scq_cid; 488 __le32 rcq_cid; 489 __le32 srq_cid; 490 __le32 pd_id; 491 __le64 sq_pbl; 492 __le64 rq_pbl; 493 __le64 irrq_addr; 494 __le64 orrq_addr; 495}; 496 497/* creq_create_qp_resp (size:128b/16B) */ 498struct creq_create_qp_resp { 499 u8 type; 500 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 501 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 502 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 503 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 504 u8 status; 505 __le16 cookie; 506 __le32 xid; 507 u8 v; 508 #define CREQ_CREATE_QP_RESP_V 0x1UL 509 u8 event; 510 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 511 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 512 u8 optimized_transmit_enabled; 513 u8 reserved48[5]; 514}; 515 516/* cmdq_destroy_qp (size:192b/24B) */ 517struct cmdq_destroy_qp { 518 u8 opcode; 519 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 520 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 521 u8 cmd_size; 522 __le16 flags; 523 __le16 cookie; 524 u8 resp_size; 525 u8 reserved8; 526 __le64 resp_addr; 527 __le32 qp_cid; 528 __le32 unused_0; 529}; 530 531/* creq_destroy_qp_resp (size:128b/16B) */ 532struct creq_destroy_qp_resp { 533 u8 type; 534 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 535 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 536 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 537 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 538 u8 status; 539 __le16 cookie; 540 __le32 xid; 541 u8 v; 542 #define CREQ_DESTROY_QP_RESP_V 0x1UL 543 u8 event; 544 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 545 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 546 u8 reserved48[6]; 547}; 548 549/* cmdq_modify_qp (size:1024b/128B) */ 550struct cmdq_modify_qp { 551 u8 opcode; 552 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 553 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 554 u8 cmd_size; 555 __le16 flags; 556 __le16 cookie; 557 u8 resp_size; 558 u8 reserved8; 559 __le64 resp_addr; 560 __le32 modify_mask; 561 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 562 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 563 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 564 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 565 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 566 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 567 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 568 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 569 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 570 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 571 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 572 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL 573 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 574 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 575 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 576 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 577 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 578 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 579 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 580 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 581 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 582 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 583 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 584 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 585 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 586 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 587 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 588 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 589 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 590 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 591 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 592 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 593 __le32 qp_cid; 594 u8 network_type_en_sqd_async_notify_new_state; 595 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 596 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 597 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 598 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 599 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 600 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 601 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 602 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 603 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 604 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR 605 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 606 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL 607 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 608 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 609 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 610 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 611 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 612 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 613 u8 access; 614 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK \ 615 0xffUL 616 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT \ 617 0 618 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 619 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 620 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 621 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 622 __le16 pkey; 623 __le32 qkey; 624 __le32 dgid[4]; 625 __le32 flow_label; 626 __le16 sgid_index; 627 u8 hop_limit; 628 u8 traffic_class; 629 __le16 dest_mac[3]; 630 u8 tos_dscp_tos_ecn; 631 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 632 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 633 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 634 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 635 u8 path_mtu_pingpong_push_enable; 636 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL 637 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL 638 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 639 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 640 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 641 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 642 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 643 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 644 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 645 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 646 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 647 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 648 u8 timeout; 649 u8 retry_cnt; 650 u8 rnr_retry; 651 u8 min_rnr_timer; 652 __le32 rq_psn; 653 __le32 sq_psn; 654 u8 max_rd_atomic; 655 u8 max_dest_rd_atomic; 656 __le16 enable_cc; 657 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 658 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL 659 #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 660 __le32 sq_size; 661 __le32 rq_size; 662 __le16 sq_sge; 663 __le16 rq_sge; 664 __le32 max_inline_data; 665 __le32 dest_qp_id; 666 __le32 pingpong_push_dpi; 667 __le16 src_mac[3]; 668 __le16 vlan_pcp_vlan_dei_vlan_id; 669 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 670 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 671 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 672 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 673 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 674 __le64 irrq_addr; 675 __le64 orrq_addr; 676}; 677 678/* creq_modify_qp_resp (size:128b/16B) */ 679struct creq_modify_qp_resp { 680 u8 type; 681 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 682 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 683 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 684 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 685 u8 status; 686 __le16 cookie; 687 __le32 xid; 688 u8 v; 689 #define CREQ_MODIFY_QP_RESP_V 0x1UL 690 u8 event; 691 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 692 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 693 u8 pingpong_push_state_index_enabled; 694 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL 695 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 696 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 697 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 698 u8 reserved8; 699 __le32 lag_src_mac; 700}; 701 702/* cmdq_query_qp (size:192b/24B) */ 703struct cmdq_query_qp { 704 u8 opcode; 705 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 706 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP 707 u8 cmd_size; 708 __le16 flags; 709 __le16 cookie; 710 u8 resp_size; 711 u8 reserved8; 712 __le64 resp_addr; 713 __le32 qp_cid; 714 __le32 unused_0; 715}; 716 717/* creq_query_qp_resp (size:128b/16B) */ 718struct creq_query_qp_resp { 719 u8 type; 720 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 721 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 722 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 723 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 724 u8 status; 725 __le16 cookie; 726 __le32 size; 727 u8 v; 728 #define CREQ_QUERY_QP_RESP_V 0x1UL 729 u8 event; 730 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 731 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 732 u8 reserved48[6]; 733}; 734 735/* creq_query_qp_resp_sb (size:832b/104B) */ 736struct creq_query_qp_resp_sb { 737 u8 opcode; 738 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 739 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 740 u8 status; 741 __le16 cookie; 742 __le16 flags; 743 u8 resp_size; 744 u8 reserved8; 745 __le32 xid; 746 u8 en_sqd_async_notify_state; 747 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 748 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 749 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 750 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 751 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 752 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 753 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 754 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 755 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 756 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR 757 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 758 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL 759 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 760 u8 access; 761 #define \ 762 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\ 763 0xffUL 764 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\ 765 0 766 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 767 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 768 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 769 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 770 __le16 pkey; 771 __le32 qkey; 772 __le32 reserved32; 773 __le32 dgid[4]; 774 __le32 flow_label; 775 __le16 sgid_index; 776 u8 hop_limit; 777 u8 traffic_class; 778 __le16 dest_mac[3]; 779 __le16 path_mtu_dest_vlan_id; 780 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 781 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 782 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 783 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 784 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 785 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 786 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 787 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 788 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 789 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 790 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 791 u8 timeout; 792 u8 retry_cnt; 793 u8 rnr_retry; 794 u8 min_rnr_timer; 795 __le32 rq_psn; 796 __le32 sq_psn; 797 u8 max_rd_atomic; 798 u8 max_dest_rd_atomic; 799 u8 tos_dscp_tos_ecn; 800 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 801 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 802 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 803 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 804 u8 enable_cc; 805 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 806 __le32 sq_size; 807 __le32 rq_size; 808 __le16 sq_sge; 809 __le16 rq_sge; 810 __le32 max_inline_data; 811 __le32 dest_qp_id; 812 __le16 port_id; 813 u8 unused_0; 814 u8 stat_collection_id; 815 __le16 src_mac[3]; 816 __le16 vlan_pcp_vlan_dei_vlan_id; 817 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 818 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 819 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 820 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 821 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 822}; 823 824/* cmdq_query_qp_extend (size:192b/24B) */ 825struct cmdq_query_qp_extend { 826 u8 opcode; 827 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL 828 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 829 u8 cmd_size; 830 __le16 flags; 831 __le16 cookie; 832 u8 resp_size; 833 u8 num_qps; 834 __le64 resp_addr; 835 __le32 function_id; 836 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL 837 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 838 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL 839 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 840 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL 841 __le32 current_index; 842}; 843 844/* creq_query_qp_extend_resp (size:128b/16B) */ 845struct creq_query_qp_extend_resp { 846 u8 type; 847 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL 848 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 849 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL 850 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 851 u8 status; 852 __le16 cookie; 853 __le32 size; 854 u8 v; 855 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL 856 u8 event; 857 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL 858 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 859 __le16 reserved16; 860 __le32 current_index; 861}; 862 863/* creq_query_qp_extend_resp_sb (size:384b/48B) */ 864struct creq_query_qp_extend_resp_sb { 865 u8 opcode; 866 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL 867 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \ 868 CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 869 u8 status; 870 __le16 cookie; 871 __le16 flags; 872 u8 resp_size; 873 u8 reserved8; 874 __le32 xid; 875 u8 state; 876 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL 877 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 878 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL 879 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL 880 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL 881 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL 882 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL 883 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL 884 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL 885 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 886 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL 887 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 888 u8 reserved_8; 889 __le16 port_id; 890 __le32 qkey; 891 __le16 sgid_index; 892 u8 network_type; 893 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL 894 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 895 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 896 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \ 897 CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 898 u8 unused_0; 899 __le32 dgid[4]; 900 __le32 dest_qp_id; 901 u8 stat_collection_id; 902 u8 reservred_8; 903 __le16 reserved_16; 904}; 905 906/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ 907struct creq_query_qp_extend_resp_sb_tlv { 908 __le16 cmd_discr; 909 u8 reserved_8b; 910 u8 tlv_flags; 911 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 912 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 913 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 914 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 915 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 916 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 917 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 918 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 919 __le16 tlv_type; 920 __le16 length; 921 u8 total_size; 922 u8 reserved56[7]; 923 u8 opcode; 924 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL 925 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \ 926 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 927 u8 status; 928 __le16 cookie; 929 __le16 flags; 930 u8 resp_size; 931 u8 reserved8; 932 __le32 xid; 933 u8 state; 934 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL 935 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 936 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL 937 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL 938 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL 939 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL 940 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL 941 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL 942 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL 943 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \ 944 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 945 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL 946 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 947 u8 reserved_8; 948 __le16 port_id; 949 __le32 qkey; 950 __le16 sgid_index; 951 u8 network_type; 952 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL 953 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 954 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 955 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \ 956 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 957 u8 unused_0; 958 __le32 dgid[4]; 959 __le32 dest_qp_id; 960 u8 stat_collection_id; 961 u8 reservred_8; 962 __le16 reserved_16; 963}; 964 965/* cmdq_create_srq (size:384b/48B) */ 966struct cmdq_create_srq { 967 u8 opcode; 968 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 969 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 970 u8 cmd_size; 971 __le16 flags; 972 __le16 cookie; 973 u8 resp_size; 974 u8 reserved8; 975 __le64 resp_addr; 976 __le64 srq_handle; 977 __le16 pg_size_lvl; 978 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 979 #define CMDQ_CREATE_SRQ_LVL_SFT 0 980 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 981 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 982 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 983 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 984 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 985 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 986 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 987 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 988 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 989 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 990 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 991 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 992 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G 993 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL 994 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 995 __le16 eventq_id; 996 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 997 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 998 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL 999 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 1000 __le16 srq_size; 1001 __le16 srq_fwo; 1002 __le32 dpi; 1003 __le32 pd_id; 1004 __le64 pbl; 1005}; 1006 1007/* creq_create_srq_resp (size:128b/16B) */ 1008struct creq_create_srq_resp { 1009 u8 type; 1010 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 1011 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 1012 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1013 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 1014 u8 status; 1015 __le16 cookie; 1016 __le32 xid; 1017 u8 v; 1018 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 1019 u8 event; 1020 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 1021 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 1022 u8 reserved48[6]; 1023}; 1024 1025/* cmdq_destroy_srq (size:192b/24B) */ 1026struct cmdq_destroy_srq { 1027 u8 opcode; 1028 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1029 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 1030 u8 cmd_size; 1031 __le16 flags; 1032 __le16 cookie; 1033 u8 resp_size; 1034 u8 reserved8; 1035 __le64 resp_addr; 1036 __le32 srq_cid; 1037 __le32 unused_0; 1038}; 1039 1040/* creq_destroy_srq_resp (size:128b/16B) */ 1041struct creq_destroy_srq_resp { 1042 u8 type; 1043 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 1044 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 1045 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1046 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 1047 u8 status; 1048 __le16 cookie; 1049 __le32 xid; 1050 u8 v; 1051 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 1052 u8 event; 1053 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 1054 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 1055 __le16 enable_for_arm[3]; 1056 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL 1057 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 1058 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 1059 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 1060}; 1061 1062/* cmdq_query_srq (size:192b/24B) */ 1063struct cmdq_query_srq { 1064 u8 opcode; 1065 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1066 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 1067 u8 cmd_size; 1068 __le16 flags; 1069 __le16 cookie; 1070 u8 resp_size; 1071 u8 reserved8; 1072 __le64 resp_addr; 1073 __le32 srq_cid; 1074 __le32 unused_0; 1075}; 1076 1077/* creq_query_srq_resp (size:128b/16B) */ 1078struct creq_query_srq_resp { 1079 u8 type; 1080 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 1081 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 1082 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1083 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 1084 u8 status; 1085 __le16 cookie; 1086 __le32 size; 1087 u8 v; 1088 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 1089 u8 event; 1090 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 1091 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 1092 u8 reserved48[6]; 1093}; 1094 1095/* creq_query_srq_resp_sb (size:256b/32B) */ 1096struct creq_query_srq_resp_sb { 1097 u8 opcode; 1098 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 1099 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 1100 u8 status; 1101 __le16 cookie; 1102 __le16 flags; 1103 u8 resp_size; 1104 u8 reserved8; 1105 __le32 xid; 1106 __le16 srq_limit; 1107 __le16 reserved16; 1108 __le32 data[4]; 1109}; 1110 1111/* cmdq_create_cq (size:384b/48B) */ 1112struct cmdq_create_cq { 1113 u8 opcode; 1114 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1115 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 1116 u8 cmd_size; 1117 __le16 flags; 1118 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL 1119 __le16 cookie; 1120 u8 resp_size; 1121 u8 reserved8; 1122 __le64 resp_addr; 1123 __le64 cq_handle; 1124 __le32 pg_size_lvl; 1125 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1126 #define CMDQ_CREATE_CQ_LVL_SFT 0 1127 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1128 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1129 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1130 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 1131 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1132 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1133 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1134 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1135 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1136 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1137 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1138 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1139 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G 1140 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL 1141 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 1142 __le32 cq_fco_cnq_id; 1143 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1144 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1145 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1146 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1147 __le32 dpi; 1148 __le32 cq_size; 1149 __le64 pbl; 1150}; 1151 1152/* creq_create_cq_resp (size:128b/16B) */ 1153struct creq_create_cq_resp { 1154 u8 type; 1155 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 1156 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 1157 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1158 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 1159 u8 status; 1160 __le16 cookie; 1161 __le32 xid; 1162 u8 v; 1163 #define CREQ_CREATE_CQ_RESP_V 0x1UL 1164 u8 event; 1165 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 1166 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 1167 u8 reserved48[6]; 1168}; 1169 1170/* cmdq_destroy_cq (size:192b/24B) */ 1171struct cmdq_destroy_cq { 1172 u8 opcode; 1173 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1174 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 1175 u8 cmd_size; 1176 __le16 flags; 1177 __le16 cookie; 1178 u8 resp_size; 1179 u8 reserved8; 1180 __le64 resp_addr; 1181 __le32 cq_cid; 1182 __le32 unused_0; 1183}; 1184 1185/* creq_destroy_cq_resp (size:128b/16B) */ 1186struct creq_destroy_cq_resp { 1187 u8 type; 1188 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 1189 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 1190 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 1191 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 1192 u8 status; 1193 __le16 cookie; 1194 __le32 xid; 1195 u8 v; 1196 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 1197 u8 event; 1198 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 1199 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 1200 __le16 cq_arm_lvl; 1201 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 1202 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 1203 __le16 total_cnq_events; 1204 __le16 reserved16; 1205}; 1206 1207/* cmdq_resize_cq (size:320b/40B) */ 1208struct cmdq_resize_cq { 1209 u8 opcode; 1210 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1211 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 1212 u8 cmd_size; 1213 __le16 flags; 1214 __le16 cookie; 1215 u8 resp_size; 1216 u8 reserved8; 1217 __le64 resp_addr; 1218 __le32 cq_cid; 1219 __le32 new_cq_size_pg_size_lvl; 1220 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1221 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1222 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1223 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1224 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1225 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 1226 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1227 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1228 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1229 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1230 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1231 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1232 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1233 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1234 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G 1235 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL 1236 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1237 __le64 new_pbl; 1238 __le32 new_cq_fco; 1239 __le32 unused_0; 1240}; 1241 1242/* creq_resize_cq_resp (size:128b/16B) */ 1243struct creq_resize_cq_resp { 1244 u8 type; 1245 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 1246 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 1247 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1248 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 1249 u8 status; 1250 __le16 cookie; 1251 __le32 xid; 1252 u8 v; 1253 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 1254 u8 event; 1255 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 1256 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 1257 u8 reserved48[6]; 1258}; 1259 1260/* cmdq_allocate_mrw (size:256b/32B) */ 1261struct cmdq_allocate_mrw { 1262 u8 opcode; 1263 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1264 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 1265 u8 cmd_size; 1266 __le16 flags; 1267 __le16 cookie; 1268 u8 resp_size; 1269 u8 reserved8; 1270 __le64 resp_addr; 1271 __le64 mrw_handle; 1272 u8 mrw_flags; 1273 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1274 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1275 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1276 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1277 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1278 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1279 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1280 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 1281 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xf0UL 1282 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 4 1283 u8 access; 1284 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1285 __le16 unused16; 1286 __le32 pd_id; 1287}; 1288 1289/* creq_allocate_mrw_resp (size:128b/16B) */ 1290struct creq_allocate_mrw_resp { 1291 u8 type; 1292 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 1293 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 1294 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 1295 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 1296 u8 status; 1297 __le16 cookie; 1298 __le32 xid; 1299 u8 v; 1300 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 1301 u8 event; 1302 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 1303 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 1304 u8 reserved48[6]; 1305}; 1306 1307/* cmdq_deallocate_key (size:192b/24B) */ 1308struct cmdq_deallocate_key { 1309 u8 opcode; 1310 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1311 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 1312 u8 cmd_size; 1313 __le16 flags; 1314 __le16 cookie; 1315 u8 resp_size; 1316 u8 reserved8; 1317 __le64 resp_addr; 1318 u8 mrw_flags; 1319 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1320 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1321 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1322 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1323 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1324 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1325 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1326 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 1327 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL 1328 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 1329 u8 unused24[3]; 1330 __le32 key; 1331}; 1332 1333/* creq_deallocate_key_resp (size:128b/16B) */ 1334struct creq_deallocate_key_resp { 1335 u8 type; 1336 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 1337 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 1338 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 1339 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 1340 u8 status; 1341 __le16 cookie; 1342 __le32 xid; 1343 u8 v; 1344 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 1345 u8 event; 1346 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 1347 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 1348 __le16 reserved16; 1349 __le32 bound_window_info; 1350}; 1351 1352/* cmdq_register_mr (size:384b/48B) */ 1353struct cmdq_register_mr { 1354 u8 opcode; 1355 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1356 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 1357 u8 cmd_size; 1358 __le16 flags; 1359 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL 1360 __le16 cookie; 1361 u8 resp_size; 1362 u8 reserved8; 1363 __le64 resp_addr; 1364 u8 log2_pg_size_lvl; 1365 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1366 #define CMDQ_REGISTER_MR_LVL_SFT 0 1367 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1368 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1369 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1370 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1371 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1372 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1373 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1374 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1375 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1376 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1377 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1378 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1379 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1380 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1381 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1382 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1383 u8 access; 1384 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1385 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1386 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1387 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1388 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1389 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1390 __le16 log2_pbl_pg_size; 1391 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1392 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1393 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1394 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1395 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1396 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1397 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1398 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1399 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1400 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1401 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1402 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1403 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1404 __le32 key; 1405 __le64 pbl; 1406 __le64 va; 1407 __le64 mr_size; 1408}; 1409 1410/* creq_register_mr_resp (size:128b/16B) */ 1411struct creq_register_mr_resp { 1412 u8 type; 1413 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 1414 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 1415 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1416 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 1417 u8 status; 1418 __le16 cookie; 1419 __le32 xid; 1420 u8 v; 1421 #define CREQ_REGISTER_MR_RESP_V 0x1UL 1422 u8 event; 1423 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 1424 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 1425 u8 reserved48[6]; 1426}; 1427 1428/* cmdq_deregister_mr (size:192b/24B) */ 1429struct cmdq_deregister_mr { 1430 u8 opcode; 1431 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1432 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 1433 u8 cmd_size; 1434 __le16 flags; 1435 __le16 cookie; 1436 u8 resp_size; 1437 u8 reserved8; 1438 __le64 resp_addr; 1439 __le32 lkey; 1440 __le32 unused_0; 1441}; 1442 1443/* creq_deregister_mr_resp (size:128b/16B) */ 1444struct creq_deregister_mr_resp { 1445 u8 type; 1446 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 1447 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 1448 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1449 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 1450 u8 status; 1451 __le16 cookie; 1452 __le32 xid; 1453 u8 v; 1454 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 1455 u8 event; 1456 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 1457 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 1458 __le16 reserved16; 1459 __le32 bound_windows; 1460}; 1461 1462/* cmdq_add_gid (size:384b/48B) */ 1463struct cmdq_add_gid { 1464 u8 opcode; 1465 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1466 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID 1467 u8 cmd_size; 1468 __le16 flags; 1469 __le16 cookie; 1470 u8 resp_size; 1471 u8 reserved8; 1472 __le64 resp_addr; 1473 __be32 gid[4]; 1474 __be16 src_mac[3]; 1475 __le16 vlan; 1476 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1477 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1478 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1479 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1480 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1481 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1482 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1483 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1484 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1485 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1486 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1487 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1488 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1489 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1490 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1491 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1492 __le16 ipid; 1493 __le16 stats_ctx; 1494 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL 1495 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 1496 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1497 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1498 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1499 __le32 unused_0; 1500}; 1501 1502/* creq_add_gid_resp (size:128b/16B) */ 1503struct creq_add_gid_resp { 1504 u8 type; 1505 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 1506 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 1507 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 1508 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT 1509 u8 status; 1510 __le16 cookie; 1511 __le32 xid; 1512 u8 v; 1513 #define CREQ_ADD_GID_RESP_V 0x1UL 1514 u8 event; 1515 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 1516 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID 1517 u8 reserved48[6]; 1518}; 1519 1520/* cmdq_delete_gid (size:192b/24B) */ 1521struct cmdq_delete_gid { 1522 u8 opcode; 1523 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1524 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID 1525 u8 cmd_size; 1526 __le16 flags; 1527 __le16 cookie; 1528 u8 resp_size; 1529 u8 reserved8; 1530 __le64 resp_addr; 1531 __le16 gid_index; 1532 u8 unused_0[6]; 1533}; 1534 1535/* creq_delete_gid_resp (size:128b/16B) */ 1536struct creq_delete_gid_resp { 1537 u8 type; 1538 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 1539 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 1540 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 1541 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 1542 u8 status; 1543 __le16 cookie; 1544 __le32 xid; 1545 u8 v; 1546 #define CREQ_DELETE_GID_RESP_V 0x1UL 1547 u8 event; 1548 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 1549 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 1550 u8 reserved48[6]; 1551}; 1552 1553/* cmdq_modify_gid (size:384b/48B) */ 1554struct cmdq_modify_gid { 1555 u8 opcode; 1556 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1557 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 1558 u8 cmd_size; 1559 __le16 flags; 1560 __le16 cookie; 1561 u8 resp_size; 1562 u8 reserved8; 1563 __le64 resp_addr; 1564 __be32 gid[4]; 1565 __be16 src_mac[3]; 1566 __le16 vlan; 1567 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1568 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1569 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1570 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1571 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1572 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1573 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1574 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1575 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1576 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1577 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1578 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1579 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1580 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1581 __le16 ipid; 1582 __le16 gid_index; 1583 __le16 stats_ctx; 1584 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1585 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1586 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1587 __le16 unused_0; 1588}; 1589 1590/* creq_modify_gid_resp (size:128b/16B) */ 1591struct creq_modify_gid_resp { 1592 u8 type; 1593 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 1594 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 1595 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 1596 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 1597 u8 status; 1598 __le16 cookie; 1599 __le32 xid; 1600 u8 v; 1601 #define CREQ_MODIFY_GID_RESP_V 0x1UL 1602 u8 event; 1603 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 1604 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 1605 u8 reserved48[6]; 1606}; 1607 1608/* cmdq_query_gid (size:192b/24B) */ 1609struct cmdq_query_gid { 1610 u8 opcode; 1611 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1612 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID 1613 u8 cmd_size; 1614 __le16 flags; 1615 __le16 cookie; 1616 u8 resp_size; 1617 u8 reserved8; 1618 __le64 resp_addr; 1619 __le16 gid_index; 1620 u8 unused16[6]; 1621}; 1622 1623/* creq_query_gid_resp (size:128b/16B) */ 1624struct creq_query_gid_resp { 1625 u8 type; 1626 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 1627 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 1628 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 1629 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 1630 u8 status; 1631 __le16 cookie; 1632 __le32 size; 1633 u8 v; 1634 #define CREQ_QUERY_GID_RESP_V 0x1UL 1635 u8 event; 1636 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 1637 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 1638 u8 reserved48[6]; 1639}; 1640 1641/* creq_query_gid_resp_sb (size:320b/40B) */ 1642struct creq_query_gid_resp_sb { 1643 u8 opcode; 1644 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 1645 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 1646 u8 status; 1647 __le16 cookie; 1648 __le16 flags; 1649 u8 resp_size; 1650 u8 reserved8; 1651 __le32 gid[4]; 1652 __le16 src_mac[3]; 1653 __le16 vlan; 1654 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1655 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1656 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 1657 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 1658 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 1659 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 1660 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1661 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 1662 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 1663 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 1664 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 1665 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1666 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1667 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1668 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 1669 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 1670 __le16 ipid; 1671 __le16 gid_index; 1672 __le32 unused_0; 1673}; 1674 1675/* cmdq_create_qp1 (size:640b/80B) */ 1676struct cmdq_create_qp1 { 1677 u8 opcode; 1678 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1679 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 1680 u8 cmd_size; 1681 __le16 flags; 1682 __le16 cookie; 1683 u8 resp_size; 1684 u8 reserved8; 1685 __le64 resp_addr; 1686 __le64 qp_handle; 1687 __le32 qp_flags; 1688 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1689 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1690 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1691 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 1692 u8 type; 1693 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1694 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI 1695 u8 sq_pg_size_sq_lvl; 1696 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1697 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1698 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1699 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1700 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1701 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 1702 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1703 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1704 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1705 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1706 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1707 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1708 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1709 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1710 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G 1711 u8 rq_pg_size_rq_lvl; 1712 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1713 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1714 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1715 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1716 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1717 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 1718 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1719 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1720 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1721 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1722 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1723 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1724 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1725 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1726 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G 1727 u8 unused_0; 1728 __le32 dpi; 1729 __le32 sq_size; 1730 __le32 rq_size; 1731 __le16 sq_fwo_sq_sge; 1732 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1733 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1734 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1735 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1736 __le16 rq_fwo_rq_sge; 1737 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1738 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1739 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1740 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1741 __le32 scq_cid; 1742 __le32 rcq_cid; 1743 __le32 srq_cid; 1744 __le32 pd_id; 1745 __le64 sq_pbl; 1746 __le64 rq_pbl; 1747}; 1748 1749/* creq_create_qp1_resp (size:128b/16B) */ 1750struct creq_create_qp1_resp { 1751 u8 type; 1752 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 1753 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 1754 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 1755 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 1756 u8 status; 1757 __le16 cookie; 1758 __le32 xid; 1759 u8 v; 1760 #define CREQ_CREATE_QP1_RESP_V 0x1UL 1761 u8 event; 1762 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 1763 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 1764 u8 reserved48[6]; 1765}; 1766 1767/* cmdq_destroy_qp1 (size:192b/24B) */ 1768struct cmdq_destroy_qp1 { 1769 u8 opcode; 1770 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1771 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 1772 u8 cmd_size; 1773 __le16 flags; 1774 __le16 cookie; 1775 u8 resp_size; 1776 u8 reserved8; 1777 __le64 resp_addr; 1778 __le32 qp1_cid; 1779 __le32 unused_0; 1780}; 1781 1782/* creq_destroy_qp1_resp (size:128b/16B) */ 1783struct creq_destroy_qp1_resp { 1784 u8 type; 1785 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 1786 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 1787 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 1788 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 1789 u8 status; 1790 __le16 cookie; 1791 __le32 xid; 1792 u8 v; 1793 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 1794 u8 event; 1795 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 1796 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 1797 u8 reserved48[6]; 1798}; 1799 1800/* cmdq_create_ah (size:512b/64B) */ 1801struct cmdq_create_ah { 1802 u8 opcode; 1803 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1804 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH 1805 u8 cmd_size; 1806 __le16 flags; 1807 __le16 cookie; 1808 u8 resp_size; 1809 u8 reserved8; 1810 __le64 resp_addr; 1811 __le64 ah_handle; 1812 __le32 dgid[4]; 1813 u8 type; 1814 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1815 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1816 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1817 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 1818 u8 hop_limit; 1819 __le16 sgid_index; 1820 __le32 dest_vlan_id_flow_label; 1821 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1822 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1823 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1824 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1825 __le32 pd_id; 1826 __le32 unused_0; 1827 __le16 dest_mac[3]; 1828 u8 traffic_class; 1829 u8 enable_cc; 1830 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL 1831}; 1832 1833/* creq_create_ah_resp (size:128b/16B) */ 1834struct creq_create_ah_resp { 1835 u8 type; 1836 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 1837 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 1838 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 1839 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 1840 u8 status; 1841 __le16 cookie; 1842 __le32 xid; 1843 u8 v; 1844 #define CREQ_CREATE_AH_RESP_V 0x1UL 1845 u8 event; 1846 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 1847 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 1848 u8 reserved48[6]; 1849}; 1850 1851/* cmdq_destroy_ah (size:192b/24B) */ 1852struct cmdq_destroy_ah { 1853 u8 opcode; 1854 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1855 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 1856 u8 cmd_size; 1857 __le16 flags; 1858 __le16 cookie; 1859 u8 resp_size; 1860 u8 reserved8; 1861 __le64 resp_addr; 1862 __le32 ah_cid; 1863 __le32 unused_0; 1864}; 1865 1866/* creq_destroy_ah_resp (size:128b/16B) */ 1867struct creq_destroy_ah_resp { 1868 u8 type; 1869 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 1870 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 1871 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 1872 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 1873 u8 status; 1874 __le16 cookie; 1875 __le32 xid; 1876 u8 v; 1877 #define CREQ_DESTROY_AH_RESP_V 0x1UL 1878 u8 event; 1879 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 1880 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 1881 u8 reserved48[6]; 1882}; 1883 1884/* cmdq_query_roce_stats (size:192b/24B) */ 1885struct cmdq_query_roce_stats { 1886 u8 opcode; 1887 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 1888 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 1889 u8 cmd_size; 1890 __le16 flags; 1891 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL 1892 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL 1893 __le16 cookie; 1894 u8 resp_size; 1895 u8 collection_id; 1896 __le64 resp_addr; 1897 __le32 function_id; 1898 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL 1899 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 1900 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL 1901 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 1902 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL 1903 __le32 reserved32; 1904}; 1905 1906/* creq_query_roce_stats_resp (size:128b/16B) */ 1907struct creq_query_roce_stats_resp { 1908 u8 type; 1909 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 1910 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 1911 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 1912 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 1913 u8 status; 1914 __le16 cookie; 1915 __le32 size; 1916 u8 v; 1917 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 1918 u8 event; 1919 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 1920 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 1921 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 1922 u8 reserved48[6]; 1923}; 1924 1925/* creq_query_roce_stats_resp_sb (size:2944b/368B) */ 1926struct creq_query_roce_stats_resp_sb { 1927 u8 opcode; 1928 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 1929 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 1930 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 1931 u8 status; 1932 __le16 cookie; 1933 __le16 flags; 1934 u8 resp_size; 1935 u8 rsvd; 1936 __le32 num_counters; 1937 __le32 rsvd1; 1938 __le64 to_retransmits; 1939 __le64 seq_err_naks_rcvd; 1940 __le64 max_retry_exceeded; 1941 __le64 rnr_naks_rcvd; 1942 __le64 missing_resp; 1943 __le64 unrecoverable_err; 1944 __le64 bad_resp_err; 1945 __le64 local_qp_op_err; 1946 __le64 local_protection_err; 1947 __le64 mem_mgmt_op_err; 1948 __le64 remote_invalid_req_err; 1949 __le64 remote_access_err; 1950 __le64 remote_op_err; 1951 __le64 dup_req; 1952 __le64 res_exceed_max; 1953 __le64 res_length_mismatch; 1954 __le64 res_exceeds_wqe; 1955 __le64 res_opcode_err; 1956 __le64 res_rx_invalid_rkey; 1957 __le64 res_rx_domain_err; 1958 __le64 res_rx_no_perm; 1959 __le64 res_rx_range_err; 1960 __le64 res_tx_invalid_rkey; 1961 __le64 res_tx_domain_err; 1962 __le64 res_tx_no_perm; 1963 __le64 res_tx_range_err; 1964 __le64 res_irrq_oflow; 1965 __le64 res_unsup_opcode; 1966 __le64 res_unaligned_atomic; 1967 __le64 res_rem_inv_err; 1968 __le64 res_mem_error; 1969 __le64 res_srq_err; 1970 __le64 res_cmp_err; 1971 __le64 res_invalid_dup_rkey; 1972 __le64 res_wqe_format_err; 1973 __le64 res_cq_load_err; 1974 __le64 res_srq_load_err; 1975 __le64 res_tx_pci_err; 1976 __le64 res_rx_pci_err; 1977 __le64 res_oos_drop_count; 1978 __le64 active_qp_count_p0; 1979 __le64 active_qp_count_p1; 1980 __le64 active_qp_count_p2; 1981 __le64 active_qp_count_p3; 1982}; 1983 1984/* cmdq_query_roce_stats_ext (size:192b/24B) */ 1985struct cmdq_query_roce_stats_ext { 1986 u8 opcode; 1987 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 1988 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \ 1989 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 1990 u8 cmd_size; 1991 __le16 flags; 1992 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 1993 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 1994 __le16 cookie; 1995 u8 resp_size; 1996 u8 collection_id; 1997 __le64 resp_addr; 1998 __le32 function_id; 1999 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 2000 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 2001 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 2002 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 2003 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 2004 __le32 reserved32; 2005}; 2006 2007/* creq_query_roce_stats_ext_resp (size:128b/16B) */ 2008struct creq_query_roce_stats_ext_resp { 2009 u8 type; 2010 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 2011 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 2012 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 2013 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \ 2014 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 2015 u8 status; 2016 __le16 cookie; 2017 __le32 size; 2018 u8 v; 2019 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 2020 u8 event; 2021 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 2022 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \ 2023 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 2024 u8 reserved48[6]; 2025}; 2026 2027/* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */ 2028struct creq_query_roce_stats_ext_resp_sb { 2029 u8 opcode; 2030 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 2031 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \ 2032 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 2033 u8 status; 2034 __le16 cookie; 2035 __le16 flags; 2036 u8 resp_size; 2037 u8 rsvd; 2038 __le64 tx_atomic_req_pkts; 2039 __le64 tx_read_req_pkts; 2040 __le64 tx_read_res_pkts; 2041 __le64 tx_write_req_pkts; 2042 __le64 tx_send_req_pkts; 2043 __le64 tx_roce_pkts; 2044 __le64 tx_roce_bytes; 2045 __le64 rx_atomic_req_pkts; 2046 __le64 rx_read_req_pkts; 2047 __le64 rx_read_res_pkts; 2048 __le64 rx_write_req_pkts; 2049 __le64 rx_send_req_pkts; 2050 __le64 rx_roce_pkts; 2051 __le64 rx_roce_bytes; 2052 __le64 rx_roce_good_pkts; 2053 __le64 rx_roce_good_bytes; 2054 __le64 rx_out_of_buffer_pkts; 2055 __le64 rx_out_of_sequence_pkts; 2056 __le64 tx_cnp_pkts; 2057 __le64 rx_cnp_pkts; 2058 __le64 rx_ecn_marked_pkts; 2059 __le64 tx_cnp_bytes; 2060 __le64 rx_cnp_bytes; 2061 __le64 seq_err_naks_rcvd; 2062 __le64 rnr_naks_rcvd; 2063 __le64 missing_resp; 2064 __le64 to_retransmit; 2065 __le64 dup_req; 2066}; 2067 2068/* cmdq_query_func (size:128b/16B) */ 2069struct cmdq_query_func { 2070 u8 opcode; 2071 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 2072 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 2073 u8 cmd_size; 2074 __le16 flags; 2075 __le16 cookie; 2076 u8 resp_size; 2077 u8 reserved8; 2078 __le64 resp_addr; 2079}; 2080 2081/* creq_query_func_resp (size:128b/16B) */ 2082struct creq_query_func_resp { 2083 u8 type; 2084 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2085 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2086 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2087 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 2088 u8 status; 2089 __le16 cookie; 2090 __le32 size; 2091 u8 v; 2092 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2093 u8 event; 2094 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2095 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 2096 u8 reserved48[6]; 2097}; 2098 2099/* creq_query_func_resp_sb (size:1088b/136B) */ 2100struct creq_query_func_resp_sb { 2101 u8 opcode; 2102 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2103 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 2104 u8 status; 2105 __le16 cookie; 2106 __le16 flags; 2107 u8 resp_size; 2108 u8 reserved8; 2109 __le64 max_mr_size; 2110 __le32 max_qp; 2111 __le16 max_qp_wr; 2112 __le16 dev_cap_flags; 2113 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL 2114 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL 2115 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 2116 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1) 2117 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1) 2118 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1) 2119 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \ 2120 CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT 2121 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2122 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL 2123 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL 2124 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL 2125 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL 2126 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL 2127 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL 2128 __le32 max_cq; 2129 __le32 max_cqe; 2130 __le32 max_pd; 2131 u8 max_sge; 2132 u8 max_srq_sge; 2133 u8 max_qp_rd_atom; 2134 u8 max_qp_init_rd_atom; 2135 __le32 max_mr; 2136 __le32 max_mw; 2137 __le32 max_raw_eth_qp; 2138 __le32 max_ah; 2139 __le32 max_fmr; 2140 __le32 max_srq_wr; 2141 __le32 max_pkeys; 2142 __le32 max_inline_data; 2143 u8 max_map_per_fmr; 2144 u8 l2_db_space_size; 2145 __le16 max_srq; 2146 __le32 max_gid; 2147 __le32 tqm_alloc_reqs[12]; 2148 __le32 max_dpi; 2149 u8 max_sge_var_wqe; 2150 u8 reserved_8; 2151 __le16 max_inline_data_var_wqe; 2152}; 2153 2154/* cmdq_set_func_resources (size:448b/56B) */ 2155struct cmdq_set_func_resources { 2156 u8 opcode; 2157 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2158 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\ 2159 CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 2160 u8 cmd_size; 2161 __le16 flags; 2162 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 2163 __le16 cookie; 2164 u8 resp_size; 2165 u8 reserved8; 2166 __le64 resp_addr; 2167 __le32 number_of_qp; 2168 __le32 number_of_mrw; 2169 __le32 number_of_srq; 2170 __le32 number_of_cq; 2171 __le32 max_qp_per_vf; 2172 __le32 max_mrw_per_vf; 2173 __le32 max_srq_per_vf; 2174 __le32 max_cq_per_vf; 2175 __le32 max_gid_per_vf; 2176 __le32 stat_ctx_id; 2177}; 2178 2179/* creq_set_func_resources_resp (size:128b/16B) */ 2180struct creq_set_func_resources_resp { 2181 u8 type; 2182 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2183 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2184 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2185 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 2186 u8 status; 2187 __le16 cookie; 2188 __le32 reserved32; 2189 u8 v; 2190 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2191 u8 event; 2192 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2193 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \ 2194 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 2195 u8 reserved48[6]; 2196}; 2197 2198/* cmdq_map_tc_to_cos (size:192b/24B) */ 2199struct cmdq_map_tc_to_cos { 2200 u8 opcode; 2201 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2202 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 2203 u8 cmd_size; 2204 __le16 flags; 2205 __le16 cookie; 2206 u8 resp_size; 2207 u8 reserved8; 2208 __le64 resp_addr; 2209 __le16 cos0; 2210 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2211 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 2212 __le16 cos1; 2213 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2214 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2215 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 2216 __le32 unused_0; 2217}; 2218 2219/* creq_map_tc_to_cos_resp (size:128b/16B) */ 2220struct creq_map_tc_to_cos_resp { 2221 u8 type; 2222 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2223 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2224 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2225 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 2226 u8 status; 2227 __le16 cookie; 2228 __le32 reserved32; 2229 u8 v; 2230 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2231 u8 event; 2232 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2233 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 2234 u8 reserved48[6]; 2235}; 2236 2237/* cmdq_query_roce_cc (size:128b/16B) */ 2238struct cmdq_query_roce_cc { 2239 u8 opcode; 2240 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL 2241 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 2242 u8 cmd_size; 2243 __le16 flags; 2244 __le16 cookie; 2245 u8 resp_size; 2246 u8 reserved8; 2247 __le64 resp_addr; 2248}; 2249 2250/* creq_query_roce_cc_resp (size:128b/16B) */ 2251struct creq_query_roce_cc_resp { 2252 u8 type; 2253 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2254 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 2255 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2256 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 2257 u8 status; 2258 __le16 cookie; 2259 __le32 size; 2260 u8 v; 2261 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL 2262 u8 event; 2263 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL 2264 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 2265 u8 reserved48[6]; 2266}; 2267 2268/* creq_query_roce_cc_resp_sb (size:256b/32B) */ 2269struct creq_query_roce_cc_resp_sb { 2270 u8 opcode; 2271 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL 2272 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \ 2273 CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 2274 u8 status; 2275 __le16 cookie; 2276 __le16 flags; 2277 u8 resp_size; 2278 u8 reserved8; 2279 u8 enable_cc; 2280 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL 2281 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL 2282 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 2283 u8 tos_dscp_tos_ecn; 2284 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2285 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 2286 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2287 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 2288 u8 g; 2289 u8 num_phases_per_state; 2290 __le16 init_cr; 2291 __le16 init_tr; 2292 u8 alt_vlan_pcp; 2293 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL 2294 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 2295 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL 2296 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 2297 u8 alt_tos_dscp; 2298 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL 2299 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 2300 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL 2301 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 2302 u8 cc_mode; 2303 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL 2304 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL 2305 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \ 2306 CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 2307 u8 tx_queue; 2308 __le16 rtt; 2309 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL 2310 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 2311 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL 2312 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 2313 __le16 tcp_cp; 2314 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL 2315 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 2316 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL 2317 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 2318 __le16 inactivity_th; 2319 u8 pkts_per_phase; 2320 u8 time_per_phase; 2321 __le32 reserved32; 2322}; 2323 2324/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ 2325struct creq_query_roce_cc_resp_sb_tlv { 2326 __le16 cmd_discr; 2327 u8 reserved_8b; 2328 u8 tlv_flags; 2329 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2330 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2331 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2332 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2333 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2334 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2335 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2336 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2337 __le16 tlv_type; 2338 __le16 length; 2339 u8 total_size; 2340 u8 reserved56[7]; 2341 u8 opcode; 2342 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL 2343 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \ 2344 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 2345 u8 status; 2346 __le16 cookie; 2347 __le16 flags; 2348 u8 resp_size; 2349 u8 reserved8; 2350 u8 enable_cc; 2351 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL 2352 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL 2353 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 2354 u8 tos_dscp_tos_ecn; 2355 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL 2356 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 2357 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL 2358 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 2359 u8 g; 2360 u8 num_phases_per_state; 2361 __le16 init_cr; 2362 __le16 init_tr; 2363 u8 alt_vlan_pcp; 2364 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL 2365 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 2366 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL 2367 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 2368 u8 alt_tos_dscp; 2369 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2370 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 2371 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL 2372 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 2373 u8 cc_mode; 2374 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL 2375 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL 2376 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\ 2377 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 2378 u8 tx_queue; 2379 __le16 rtt; 2380 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL 2381 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 2382 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL 2383 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 2384 __le16 tcp_cp; 2385 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL 2386 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 2387 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL 2388 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 2389 __le16 inactivity_th; 2390 u8 pkts_per_phase; 2391 u8 time_per_phase; 2392 __le32 reserved32; 2393}; 2394 2395/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ 2396struct creq_query_roce_cc_gen1_resp_sb_tlv { 2397 __le16 cmd_discr; 2398 u8 reserved_8b; 2399 u8 tlv_flags; 2400 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2401 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2402 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2403 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2404 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2405 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2406 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2407 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2408 __le16 tlv_type; 2409 __le16 length; 2410 __le64 reserved64; 2411 __le16 inactivity_th_hi; 2412 __le16 min_time_between_cnps; 2413 __le16 init_cp; 2414 u8 tr_update_mode; 2415 u8 tr_update_cycles; 2416 u8 fr_num_rtts; 2417 u8 ai_rate_increase; 2418 __le16 reduction_relax_rtts_th; 2419 __le16 additional_relax_cr_th; 2420 __le16 cr_min_th; 2421 u8 bw_avg_weight; 2422 u8 actual_cr_factor; 2423 __le16 max_cp_cr_th; 2424 u8 cp_bias_en; 2425 u8 cp_bias; 2426 u8 cnp_ecn; 2427 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL 2428 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL 2429 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL 2430 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \ 2431 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 2432 u8 rtt_jitter_en; 2433 __le16 link_bytes_per_usec; 2434 __le16 reset_cc_cr_th; 2435 u8 cr_width; 2436 u8 quota_period_min; 2437 u8 quota_period_max; 2438 u8 quota_period_abs_max; 2439 __le16 tr_lower_bound; 2440 u8 cr_prob_factor; 2441 u8 tr_prob_factor; 2442 __le16 fairness_cr_th; 2443 u8 red_div; 2444 u8 cnp_ratio_th; 2445 __le16 exp_ai_rtts; 2446 u8 exp_ai_cr_cp_ratio; 2447 u8 use_rate_table; 2448 __le16 cp_exp_update_th; 2449 __le16 high_exp_ai_rtts_th1; 2450 __le16 high_exp_ai_rtts_th2; 2451 __le16 actual_cr_cong_free_rtts_th; 2452 __le16 severe_cong_cr_th1; 2453 __le16 severe_cong_cr_th2; 2454 __le32 link64B_per_rtt; 2455 u8 cc_ack_bytes; 2456 u8 reduce_init_en; 2457 __le16 reduce_init_cong_free_rtts_th; 2458 u8 random_no_red_en; 2459 u8 actual_cr_shift_correction_en; 2460 u8 quota_period_adjust_en; 2461 u8 reserved[5]; 2462}; 2463 2464/* cmdq_modify_roce_cc (size:448b/56B) */ 2465struct cmdq_modify_roce_cc { 2466 u8 opcode; 2467 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL 2468 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 2469 u8 cmd_size; 2470 __le16 flags; 2471 __le16 cookie; 2472 u8 resp_size; 2473 u8 reserved8; 2474 __le64 resp_addr; 2475 __le32 modify_mask; 2476 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL 2477 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL 2478 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2479 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL 2480 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL 2481 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL 2482 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL 2483 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2484 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2485 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL 2486 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL 2487 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL 2488 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL 2489 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2490 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2491 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2492 u8 enable_cc; 2493 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL 2494 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL 2495 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 2496 u8 g; 2497 u8 num_phases_per_state; 2498 u8 pkts_per_phase; 2499 __le16 init_cr; 2500 __le16 init_tr; 2501 u8 tos_dscp_tos_ecn; 2502 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL 2503 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 2504 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL 2505 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 2506 u8 alt_vlan_pcp; 2507 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL 2508 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 2509 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL 2510 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 2511 __le16 alt_tos_dscp; 2512 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL 2513 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 2514 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL 2515 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 2516 __le16 rtt; 2517 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL 2518 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 2519 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL 2520 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 2521 __le16 tcp_cp; 2522 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL 2523 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 2524 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL 2525 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 2526 u8 cc_mode; 2527 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL 2528 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2529 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 2530 u8 tx_queue; 2531 __le16 inactivity_th; 2532 u8 time_per_phase; 2533 u8 reserved8_1; 2534 __le16 reserved16; 2535 __le32 reserved32; 2536 __le64 reserved64; 2537}; 2538 2539/* cmdq_modify_roce_cc_tlv (size:640b/80B) */ 2540struct cmdq_modify_roce_cc_tlv { 2541 __le16 cmd_discr; 2542 u8 reserved_8b; 2543 u8 tlv_flags; 2544 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL 2545 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2546 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2547 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL 2548 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2549 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2550 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \ 2551 CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES 2552 __le16 tlv_type; 2553 __le16 length; 2554 u8 total_size; 2555 u8 reserved56[7]; 2556 u8 opcode; 2557 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL 2558 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 2559 u8 cmd_size; 2560 __le16 flags; 2561 __le16 cookie; 2562 u8 resp_size; 2563 u8 reserved8; 2564 __le64 resp_addr; 2565 __le32 modify_mask; 2566 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL 2567 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL 2568 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2569 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL 2570 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL 2571 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL 2572 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL 2573 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2574 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2575 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL 2576 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL 2577 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL 2578 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL 2579 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2580 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2581 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2582 u8 enable_cc; 2583 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL 2584 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL 2585 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 2586 u8 g; 2587 u8 num_phases_per_state; 2588 u8 pkts_per_phase; 2589 __le16 init_cr; 2590 __le16 init_tr; 2591 u8 tos_dscp_tos_ecn; 2592 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL 2593 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 2594 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL 2595 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 2596 u8 alt_vlan_pcp; 2597 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL 2598 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 2599 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL 2600 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 2601 __le16 alt_tos_dscp; 2602 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2603 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 2604 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL 2605 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 2606 __le16 rtt; 2607 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL 2608 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 2609 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL 2610 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 2611 __le16 tcp_cp; 2612 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL 2613 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 2614 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL 2615 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 2616 u8 cc_mode; 2617 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL 2618 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2619 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\ 2620 CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 2621 u8 tx_queue; 2622 __le16 inactivity_th; 2623 u8 time_per_phase; 2624 u8 reserved8_1; 2625 __le16 reserved16; 2626 __le32 reserved32; 2627 __le64 reserved64; 2628 __le64 reservedtlvpad; 2629}; 2630 2631/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ 2632struct cmdq_modify_roce_cc_gen1_tlv { 2633 __le16 cmd_discr; 2634 u8 reserved_8b; 2635 u8 tlv_flags; 2636 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL 2637 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2638 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2639 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL 2640 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2641 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2642 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\ 2643 CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES 2644 __le16 tlv_type; 2645 __le16 length; 2646 __le64 reserved64; 2647 __le64 modify_mask; 2648 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL 2649 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL 2650 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL 2651 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL 2652 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL 2653 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL 2654 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL 2655 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL 2656 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL 2657 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL 2658 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL 2659 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL 2660 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL 2661 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL 2662 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL 2663 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL 2664 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL 2665 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL 2666 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL 2667 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL 2668 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL 2669 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL 2670 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL 2671 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL 2672 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL 2673 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL 2674 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL 2675 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL 2676 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL 2677 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL 2678 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL 2679 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL 2680 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL 2681 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL 2682 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL 2683 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL 2684 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL 2685 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL 2686 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL 2687 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL 2688 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \ 2689 0x10000000000ULL 2690 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL 2691 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \ 2692 0x40000000000ULL 2693 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL 2694 __le16 inactivity_th_hi; 2695 __le16 min_time_between_cnps; 2696 __le16 init_cp; 2697 u8 tr_update_mode; 2698 u8 tr_update_cycles; 2699 u8 fr_num_rtts; 2700 u8 ai_rate_increase; 2701 __le16 reduction_relax_rtts_th; 2702 __le16 additional_relax_cr_th; 2703 __le16 cr_min_th; 2704 u8 bw_avg_weight; 2705 u8 actual_cr_factor; 2706 __le16 max_cp_cr_th; 2707 u8 cp_bias_en; 2708 u8 cp_bias; 2709 u8 cnp_ecn; 2710 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL 2711 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL 2712 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL 2713 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 2714 u8 rtt_jitter_en; 2715 __le16 link_bytes_per_usec; 2716 __le16 reset_cc_cr_th; 2717 u8 cr_width; 2718 u8 quota_period_min; 2719 u8 quota_period_max; 2720 u8 quota_period_abs_max; 2721 __le16 tr_lower_bound; 2722 u8 cr_prob_factor; 2723 u8 tr_prob_factor; 2724 __le16 fairness_cr_th; 2725 u8 red_div; 2726 u8 cnp_ratio_th; 2727 __le16 exp_ai_rtts; 2728 u8 exp_ai_cr_cp_ratio; 2729 u8 use_rate_table; 2730 __le16 cp_exp_update_th; 2731 __le16 high_exp_ai_rtts_th1; 2732 __le16 high_exp_ai_rtts_th2; 2733 __le16 actual_cr_cong_free_rtts_th; 2734 __le16 severe_cong_cr_th1; 2735 __le16 severe_cong_cr_th2; 2736 __le32 link64B_per_rtt; 2737 u8 cc_ack_bytes; 2738 u8 reduce_init_en; 2739 __le16 reduce_init_cong_free_rtts_th; 2740 u8 random_no_red_en; 2741 u8 actual_cr_shift_correction_en; 2742 u8 quota_period_adjust_en; 2743 u8 reserved[5]; 2744}; 2745 2746/* creq_modify_roce_cc_resp (size:128b/16B) */ 2747struct creq_modify_roce_cc_resp { 2748 u8 type; 2749 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2750 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 2751 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2752 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 2753 u8 status; 2754 __le16 cookie; 2755 __le32 reserved32; 2756 u8 v; 2757 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL 2758 u8 event; 2759 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL 2760 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 2761 u8 reserved48[6]; 2762}; 2763 2764/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ 2765struct cmdq_set_link_aggr_mode_cc { 2766 u8 opcode; 2767 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 2768 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \ 2769 CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 2770 u8 cmd_size; 2771 __le16 flags; 2772 __le16 cookie; 2773 u8 resp_size; 2774 u8 reserved8; 2775 __le64 resp_addr; 2776 __le32 modify_mask; 2777 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL 2778 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL 2779 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL 2780 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL 2781 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL 2782 u8 aggr_enable; 2783 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL 2784 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL 2785 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 2786 u8 active_port_map; 2787 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL 2788 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 2789 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL 2790 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 2791 u8 member_port_map; 2792 u8 link_aggr_mode; 2793 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL 2794 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL 2795 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL 2796 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL 2797 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 2798 __le16 stat_ctx_id[4]; 2799 __le64 rsvd1; 2800}; 2801 2802/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ 2803struct creq_set_link_aggr_mode_resources_resp { 2804 u8 type; 2805 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL 2806 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 2807 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL 2808 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 2809 u8 status; 2810 __le16 cookie; 2811 __le32 reserved32; 2812 u8 v; 2813 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL 2814 u8 event; 2815 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2816 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\ 2817 CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 2818 u8 reserved48[6]; 2819}; 2820 2821/* creq_func_event (size:128b/16B) */ 2822struct creq_func_event { 2823 u8 type; 2824 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 2825 #define CREQ_FUNC_EVENT_TYPE_SFT 0 2826 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 2827 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 2828 u8 reserved56[7]; 2829 u8 v; 2830 #define CREQ_FUNC_EVENT_V 0x1UL 2831 u8 event; 2832 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 2833 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 2834 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 2835 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 2836 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 2837 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 2838 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 2839 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 2840 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2841 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 2842 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 2843 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 2844 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 2845 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 2846 u8 reserved48[6]; 2847}; 2848 2849/* creq_qp_event (size:128b/16B) */ 2850struct creq_qp_event { 2851 u8 type; 2852 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 2853 #define CREQ_QP_EVENT_TYPE_SFT 0 2854 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 2855 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT 2856 u8 status; 2857 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL 2858 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL 2859 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL 2860 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL 2861 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL 2862 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL 2863 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL 2864 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL 2865 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 2866 __le16 cookie; 2867 __le32 reserved32; 2868 u8 v; 2869 #define CREQ_QP_EVENT_V 0x1UL 2870 u8 event; 2871 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 2872 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 2873 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 2874 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 2875 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 2876 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 2877 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 2878 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 2879 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 2880 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 2881 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 2882 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 2883 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 2884 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 2885 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 2886 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 2887 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 2888 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 2889 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 2890 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 2891 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 2892 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 2893 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 2894 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 2895 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 2896 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 2897 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 2898 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL 2899 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 2900 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 2901 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 2902 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 2903 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL 2904 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2905 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL 2906 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2907 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 2908 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 2909 u8 reserved48[6]; 2910}; 2911 2912/* creq_qp_error_notification (size:128b/16B) */ 2913struct creq_qp_error_notification { 2914 u8 type; 2915 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 2916 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 2917 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 2918 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 2919 u8 status; 2920 u8 req_slow_path_state; 2921 u8 req_err_state_reason; 2922 __le32 xid; 2923 u8 v; 2924 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 2925 u8 event; 2926 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2927 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \ 2928 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 2929 u8 res_slow_path_state; 2930 u8 res_err_state_reason; 2931 __le16 sq_cons_idx; 2932 __le16 rq_cons_idx; 2933}; 2934 2935/* creq_cq_error_notification (size:128b/16B) */ 2936struct creq_cq_error_notification { 2937 u8 type; 2938 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 2939 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 2940 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL 2941 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 2942 u8 status; 2943 u8 cq_err_reason; 2944 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL 2945 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL 2946 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL 2947 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL 2948 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL 2949 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL 2950 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \ 2951 CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 2952 u8 reserved8; 2953 __le32 xid; 2954 u8 v; 2955 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL 2956 u8 event; 2957 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 2958 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \ 2959 CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 2960 u8 reserved48[6]; 2961}; 2962 2963/* sq_base (size:64b/8B) */ 2964struct sq_base { 2965 u8 wqe_type; 2966 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 2967 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 2968 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 2969 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 2970 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 2971 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 2972 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 2973 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 2974 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 2975 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 2976 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 2977 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL 2978 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR 2979 u8 unused_0[7]; 2980}; 2981 2982/* sq_sge (size:128b/16B) */ 2983struct sq_sge { 2984 __le64 va_or_pa; 2985 __le32 l_key; 2986 __le32 size; 2987}; 2988 2989/* sq_psn_search (size:64b/8B) */ 2990struct sq_psn_search { 2991 __le32 opcode_start_psn; 2992 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 2993 #define SQ_PSN_SEARCH_START_PSN_SFT 0 2994 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 2995 #define SQ_PSN_SEARCH_OPCODE_SFT 24 2996 __le32 flags_next_psn; 2997 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 2998 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 2999 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 3000 #define SQ_PSN_SEARCH_FLAGS_SFT 24 3001}; 3002 3003/* sq_psn_search_ext (size:128b/16B) */ 3004struct sq_psn_search_ext { 3005 __le32 opcode_start_psn; 3006 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 3007 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 3008 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 3009 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 3010 __le32 flags_next_psn; 3011 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 3012 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 3013 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 3014 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 3015 __le16 start_slot_idx; 3016 __le16 reserved16; 3017 __le32 reserved32; 3018}; 3019 3020/* sq_send (size:1024b/128B) */ 3021struct sq_send { 3022 u8 wqe_type; 3023 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 3024 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3025 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 3026 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID 3027 u8 flags; 3028 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3029 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3030 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 3031 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3032 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 3033 #define SQ_SEND_FLAGS_SE 0x8UL 3034 #define SQ_SEND_FLAGS_INLINE 0x10UL 3035 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL 3036 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL 3037 u8 wqe_size; 3038 u8 reserved8_1; 3039 __le32 inv_key_or_imm_data; 3040 __le32 length; 3041 __le32 q_key; 3042 __le32 dst_qp; 3043 #define SQ_SEND_DST_QP_MASK 0xffffffUL 3044 #define SQ_SEND_DST_QP_SFT 0 3045 __le32 avid; 3046 #define SQ_SEND_AVID_MASK 0xfffffUL 3047 #define SQ_SEND_AVID_SFT 0 3048 __le32 reserved32; 3049 __le32 timestamp; 3050 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL 3051 #define SQ_SEND_TIMESTAMP_SFT 0 3052 __le32 data[24]; 3053}; 3054 3055/* sq_send_hdr (size:256b/32B) */ 3056struct sq_send_hdr { 3057 u8 wqe_type; 3058 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL 3059 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3060 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL 3061 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 3062 u8 flags; 3063 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3064 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3065 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3066 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3067 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL 3068 #define SQ_SEND_HDR_FLAGS_SE 0x8UL 3069 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL 3070 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL 3071 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3072 u8 wqe_size; 3073 u8 reserved8_1; 3074 __le32 inv_key_or_imm_data; 3075 __le32 length; 3076 __le32 q_key; 3077 __le32 dst_qp; 3078 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL 3079 #define SQ_SEND_HDR_DST_QP_SFT 0 3080 __le32 avid; 3081 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL 3082 #define SQ_SEND_HDR_AVID_SFT 0 3083 __le32 reserved32; 3084 __le32 timestamp; 3085 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL 3086 #define SQ_SEND_HDR_TIMESTAMP_SFT 0 3087}; 3088 3089/* sq_send_raweth_qp1 (size:1024b/128B) */ 3090struct sq_send_raweth_qp1 { 3091 u8 wqe_type; 3092 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 3093 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 3094 u8 flags; 3095 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \ 3096 0xffUL 3097 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \ 3098 0 3099 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 3100 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3101 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 3102 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 3103 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 3104 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL 3105 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL 3106 u8 wqe_size; 3107 u8 reserved8; 3108 __le16 lflags; 3109 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3110 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 3111 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 3112 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 3113 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 3114 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 3115 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 3116 __le16 cfa_action; 3117 __le32 length; 3118 __le32 reserved32_1; 3119 __le32 cfa_meta; 3120 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 3121 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 3122 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 3123 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 3124 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 3125 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 3126 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 3127 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3128 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3129 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3130 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3131 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3132 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3133 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\ 3134 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 3135 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3136 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 3137 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 3138 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 3139 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 3140 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3141 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 3142 __le32 reserved32_2; 3143 __le32 reserved32_3; 3144 __le32 timestamp; 3145 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL 3146 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 3147 __le32 data[24]; 3148}; 3149 3150/* sq_send_raweth_qp1_hdr (size:256b/32B) */ 3151struct sq_send_raweth_qp1_hdr { 3152 u8 wqe_type; 3153 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL 3154 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 3155 u8 flags; 3156 #define \ 3157 SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3158 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3159 0 3160 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL 3161 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3162 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL 3163 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL 3164 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL 3165 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL 3166 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL 3167 u8 wqe_size; 3168 u8 reserved8; 3169 __le16 lflags; 3170 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3171 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL 3172 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL 3173 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL 3174 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL 3175 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL 3176 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL 3177 __le16 cfa_action; 3178 __le32 length; 3179 __le32 reserved32_1; 3180 __le32 cfa_meta; 3181 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL 3182 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 3183 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL 3184 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL 3185 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 3186 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL 3187 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 3188 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3189 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3190 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3191 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3192 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3193 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3194 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\ 3195 SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG 3196 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3197 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 3198 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL 3199 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 3200 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28) 3201 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3202 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\ 3203 SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG 3204 __le32 reserved32_2; 3205 __le32 reserved32_3; 3206 __le32 timestamp; 3207 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL 3208 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 3209}; 3210 3211/* sq_rdma (size:1024b/128B) */ 3212struct sq_rdma { 3213 u8 wqe_type; 3214 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 3215 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3216 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 3217 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE 3218 u8 flags; 3219 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3220 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3221 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 3222 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3223 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 3224 #define SQ_RDMA_FLAGS_SE 0x8UL 3225 #define SQ_RDMA_FLAGS_INLINE 0x10UL 3226 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL 3227 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL 3228 u8 wqe_size; 3229 u8 reserved8; 3230 __le32 imm_data; 3231 __le32 length; 3232 __le32 reserved32_1; 3233 __le64 remote_va; 3234 __le32 remote_key; 3235 __le32 timestamp; 3236 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL 3237 #define SQ_RDMA_TIMESTAMP_SFT 0 3238 __le32 data[24]; 3239}; 3240 3241/* sq_rdma_hdr (size:256b/32B) */ 3242struct sq_rdma_hdr { 3243 u8 wqe_type; 3244 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL 3245 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3246 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL 3247 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE 3248 u8 flags; 3249 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3250 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3251 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL 3252 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3253 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL 3254 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL 3255 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL 3256 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL 3257 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL 3258 u8 wqe_size; 3259 u8 reserved8; 3260 __le32 imm_data; 3261 __le32 length; 3262 __le32 reserved32_1; 3263 __le64 remote_va; 3264 __le32 remote_key; 3265 __le32 timestamp; 3266 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL 3267 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 3268}; 3269 3270/* sq_atomic (size:1024b/128B) */ 3271struct sq_atomic { 3272 u8 wqe_type; 3273 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 3274 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 3275 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 3276 u8 flags; 3277 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3278 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3279 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 3280 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3281 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 3282 #define SQ_ATOMIC_FLAGS_SE 0x8UL 3283 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 3284 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL 3285 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL 3286 __le16 reserved16; 3287 __le32 remote_key; 3288 __le64 remote_va; 3289 __le64 swap_data; 3290 __le64 cmp_data; 3291 __le32 data[24]; 3292}; 3293 3294/* sq_atomic_hdr (size:256b/32B) */ 3295struct sq_atomic_hdr { 3296 u8 wqe_type; 3297 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL 3298 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL 3299 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 3300 u8 flags; 3301 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3302 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3303 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL 3304 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3305 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL 3306 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL 3307 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL 3308 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL 3309 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL 3310 __le16 reserved16; 3311 __le32 remote_key; 3312 __le64 remote_va; 3313 __le64 swap_data; 3314 __le64 cmp_data; 3315}; 3316 3317/* sq_localinvalidate (size:1024b/128B) */ 3318struct sq_localinvalidate { 3319 u8 wqe_type; 3320 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 3321 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 3322 u8 flags; 3323 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\ 3324 0xffUL 3325 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3326 0 3327 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 3328 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3329 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 3330 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 3331 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 3332 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL 3333 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL 3334 __le16 reserved16; 3335 __le32 inv_l_key; 3336 __le64 reserved64; 3337 u8 reserved128[16]; 3338 __le32 data[24]; 3339}; 3340 3341/* sq_localinvalidate_hdr (size:256b/32B) */ 3342struct sq_localinvalidate_hdr { 3343 u8 wqe_type; 3344 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL 3345 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 3346 u8 flags; 3347 #define \ 3348 SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3349 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3350 0 3351 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL 3352 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3353 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL 3354 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL 3355 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL 3356 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL 3357 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL 3358 __le16 reserved16; 3359 __le32 inv_l_key; 3360 __le64 reserved64; 3361 u8 reserved128[16]; 3362}; 3363 3364/* sq_fr_pmr (size:1024b/128B) */ 3365struct sq_fr_pmr { 3366 u8 wqe_type; 3367 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 3368 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR 3369 u8 flags; 3370 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 3371 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3372 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 3373 #define SQ_FR_PMR_FLAGS_SE 0x8UL 3374 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 3375 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL 3376 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL 3377 u8 access_cntl; 3378 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3379 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 3380 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3381 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3382 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3383 u8 zero_based_page_size_log; 3384 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 3385 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 3386 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3387 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3388 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3389 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3390 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3391 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3392 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3393 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3394 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3395 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3396 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3397 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3398 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3399 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3400 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3401 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3402 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3403 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3404 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3405 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3406 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3407 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3408 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3409 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3410 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3411 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3412 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3413 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3414 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3415 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3416 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3417 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3418 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 3419 #define SQ_FR_PMR_ZERO_BASED 0x20UL 3420 __le32 l_key; 3421 u8 length[5]; 3422 u8 reserved8_1; 3423 u8 reserved8_2; 3424 u8 numlevels_pbl_page_size_log; 3425 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3426 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 3427 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3428 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3429 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3430 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3431 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3432 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3433 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3434 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3435 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3436 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3437 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3438 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3439 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3440 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3441 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3442 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3443 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3444 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3445 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3446 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3447 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3448 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3449 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3450 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3451 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3452 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3453 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3454 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3455 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3456 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3457 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3458 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3459 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3460 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 3461 #define SQ_FR_PMR_NUMLEVELS_SFT 6 3462 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3463 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 3464 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 3465 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 3466 __le64 pblptr; 3467 __le64 va; 3468 __le32 data[24]; 3469}; 3470 3471/* sq_fr_pmr_hdr (size:256b/32B) */ 3472struct sq_fr_pmr_hdr { 3473 u8 wqe_type; 3474 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL 3475 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 3476 u8 flags; 3477 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL 3478 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3479 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL 3480 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL 3481 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL 3482 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL 3483 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL 3484 u8 access_cntl; 3485 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3486 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3487 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3488 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3489 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3490 u8 zero_based_page_size_log; 3491 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL 3492 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 3493 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3494 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3495 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3496 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3497 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3498 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3499 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3500 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3501 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3502 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3503 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3504 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3505 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3506 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3507 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3508 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3509 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3510 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3511 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3512 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3513 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3514 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3515 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3516 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3517 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3518 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3519 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3520 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3521 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3522 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3523 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3524 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3525 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 3526 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL 3527 __le32 l_key; 3528 u8 length[5]; 3529 u8 reserved8_1; 3530 u8 reserved8_2; 3531 u8 numlevels_pbl_page_size_log; 3532 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3533 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 3534 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3535 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3536 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3537 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3538 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3539 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3540 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3541 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3542 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3543 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3544 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3545 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3546 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3547 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3548 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3549 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3550 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3551 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3552 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3553 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3554 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3555 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3556 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3557 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3558 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3559 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3560 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3561 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3562 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3563 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3564 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3565 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3566 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3567 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL 3568 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 3569 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3570 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6) 3571 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6) 3572 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 3573 __le64 pblptr; 3574 __le64 va; 3575}; 3576 3577/* sq_bind (size:1024b/128B) */ 3578struct sq_bind { 3579 u8 wqe_type; 3580 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 3581 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND 3582 u8 flags; 3583 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3584 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3585 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 3586 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3587 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 3588 #define SQ_BIND_FLAGS_SE 0x8UL 3589 #define SQ_BIND_FLAGS_INLINE 0x10UL 3590 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL 3591 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL 3592 u8 access_cntl; 3593 #define \ 3594 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3595 0xffUL 3596 #define \ 3597 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 3598 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3599 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 3600 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3601 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3602 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 3603 u8 reserved8_1; 3604 u8 mw_type_zero_based; 3605 #define SQ_BIND_ZERO_BASED 0x1UL 3606 #define SQ_BIND_MW_TYPE 0x2UL 3607 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 3608 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 3609 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 3610 u8 reserved8_2; 3611 __le16 reserved16; 3612 __le32 parent_l_key; 3613 __le32 l_key; 3614 __le64 va; 3615 u8 length[5]; 3616 u8 reserved24[3]; 3617 __le32 data[24]; 3618}; 3619 3620/* sq_bind_hdr (size:256b/32B) */ 3621struct sq_bind_hdr { 3622 u8 wqe_type; 3623 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL 3624 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND 3625 u8 flags; 3626 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3627 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3628 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3629 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3630 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL 3631 #define SQ_BIND_HDR_FLAGS_SE 0x8UL 3632 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL 3633 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL 3634 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3635 u8 access_cntl; 3636 #define \ 3637 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3638 0xffUL 3639 #define \ 3640 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \ 3641 0 3642 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3643 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3644 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3645 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3646 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3647 u8 reserved8_1; 3648 u8 mw_type_zero_based; 3649 #define SQ_BIND_HDR_ZERO_BASED 0x1UL 3650 #define SQ_BIND_HDR_MW_TYPE 0x2UL 3651 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1) 3652 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1) 3653 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 3654 u8 reserved8_2; 3655 __le16 reserved16; 3656 __le32 parent_l_key; 3657 __le32 l_key; 3658 __le64 va; 3659 u8 length[5]; 3660 u8 reserved24[3]; 3661}; 3662 3663/* rq_wqe (size:1024b/128B) */ 3664struct rq_wqe { 3665 u8 wqe_type; 3666 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 3667 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV 3668 u8 flags; 3669 u8 wqe_size; 3670 u8 reserved8; 3671 __le32 reserved32; 3672 __le32 wr_id[2]; 3673 #define RQ_WQE_WR_ID_MASK 0xfffffUL 3674 #define RQ_WQE_WR_ID_SFT 0 3675 u8 reserved128[16]; 3676 __le32 data[24]; 3677}; 3678 3679/* rq_wqe_hdr (size:256b/32B) */ 3680struct rq_wqe_hdr { 3681 u8 wqe_type; 3682 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL 3683 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV 3684 u8 flags; 3685 u8 wqe_size; 3686 u8 reserved8; 3687 __le32 reserved32; 3688 __le32 wr_id[2]; 3689 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL 3690 #define RQ_WQE_HDR_WR_ID_SFT 0 3691 u8 reserved128[16]; 3692}; 3693 3694/* cq_base (size:256b/32B) */ 3695struct cq_base { 3696 __le64 reserved64_1; 3697 __le64 reserved64_2; 3698 __le64 reserved64_3; 3699 u8 cqe_type_toggle; 3700 #define CQ_BASE_TOGGLE 0x1UL 3701 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 3702 #define CQ_BASE_CQE_TYPE_SFT 1 3703 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 3704 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 3705 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 3706 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 3707 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 3708 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1) 3709 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 3710 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 3711 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF 3712 u8 status; 3713 __le16 reserved16; 3714 __le32 reserved32; 3715}; 3716 3717/* cq_req (size:256b/32B) */ 3718struct cq_req { 3719 __le64 qp_handle; 3720 __le16 sq_cons_idx; 3721 __le16 reserved16_1; 3722 __le32 reserved32_2; 3723 __le64 reserved64; 3724 u8 cqe_type_toggle; 3725 #define CQ_REQ_TOGGLE 0x1UL 3726 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 3727 #define CQ_REQ_CQE_TYPE_SFT 1 3728 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 3729 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ 3730 #define CQ_REQ_PUSH 0x20UL 3731 u8 status; 3732 #define CQ_REQ_STATUS_OK 0x0UL 3733 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 3734 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 3735 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 3736 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 3737 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3738 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3739 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 3740 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 3741 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 3742 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 3743 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 3744 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 3745 __le16 reserved16_2; 3746 __le32 reserved32_1; 3747}; 3748 3749/* cq_res_rc (size:256b/32B) */ 3750struct cq_res_rc { 3751 __le32 length; 3752 __le32 imm_data_or_inv_r_key; 3753 __le64 qp_handle; 3754 __le64 mr_handle; 3755 u8 cqe_type_toggle; 3756 #define CQ_RES_RC_TOGGLE 0x1UL 3757 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 3758 #define CQ_RES_RC_CQE_TYPE_SFT 1 3759 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 3760 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC 3761 u8 status; 3762 #define CQ_RES_RC_STATUS_OK 0x0UL 3763 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3764 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 3765 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3766 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3767 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3768 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3769 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3770 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 3771 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR 3772 __le16 flags; 3773 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 3774 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL 3775 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL 3776 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 3777 #define CQ_RES_RC_FLAGS_IMM 0x2UL 3778 #define CQ_RES_RC_FLAGS_INV 0x4UL 3779 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 3780 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 3781 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 3782 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 3783 __le32 srq_or_rq_wr_id; 3784 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3785 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 3786}; 3787 3788/* cq_res_ud (size:256b/32B) */ 3789struct cq_res_ud { 3790 __le16 length; 3791 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 3792 #define CQ_RES_UD_LENGTH_SFT 0 3793 __le16 cfa_metadata; 3794 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 3795 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 3796 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 3797 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 3798 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 3799 __le32 imm_data; 3800 __le64 qp_handle; 3801 __le16 src_mac[3]; 3802 __le16 src_qp_low; 3803 u8 cqe_type_toggle; 3804 #define CQ_RES_UD_TOGGLE 0x1UL 3805 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 3806 #define CQ_RES_UD_CQE_TYPE_SFT 1 3807 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 3808 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD 3809 u8 status; 3810 #define CQ_RES_UD_STATUS_OK 0x0UL 3811 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3812 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3813 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3814 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3815 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3816 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3817 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 3818 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR 3819 __le16 flags; 3820 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 3821 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL 3822 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL 3823 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 3824 #define CQ_RES_UD_FLAGS_IMM 0x2UL 3825 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 3826 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 3827 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 3828 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 3829 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3830 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3831 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3832 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 3833 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 3834 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 3835 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3836 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 3837 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3838 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3839 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3840 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 3841 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 3842 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 3843 __le32 src_qp_high_srq_or_rq_wr_id; 3844 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3845 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 3846 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 3847 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 3848}; 3849 3850/* cq_res_ud_v2 (size:256b/32B) */ 3851struct cq_res_ud_v2 { 3852 __le16 length; 3853 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL 3854 #define CQ_RES_UD_V2_LENGTH_SFT 0 3855 __le16 cfa_metadata0; 3856 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL 3857 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 3858 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL 3859 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL 3860 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 3861 __le32 imm_data; 3862 __le64 qp_handle; 3863 __le16 src_mac[3]; 3864 __le16 src_qp_low; 3865 u8 cqe_type_toggle; 3866 #define CQ_RES_UD_V2_TOGGLE 0x1UL 3867 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL 3868 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 3869 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1) 3870 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD 3871 u8 status; 3872 #define CQ_RES_UD_V2_STATUS_OK 0x0UL 3873 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3874 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3875 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3876 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3877 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3878 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3879 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL 3880 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 3881 __le16 flags; 3882 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL 3883 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL 3884 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL 3885 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ 3886 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL 3887 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL 3888 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 3889 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 3890 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 3891 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3892 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3893 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3894 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 3895 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 3896 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 3897 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3898 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 3899 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3900 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3901 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3902 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET 3903 __le32 src_qp_high_srq_or_rq_wr_id; 3904 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3905 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 3906 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL 3907 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 3908 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 3909 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 3910 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 3911 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 3912 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 3913 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 3914 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 3915 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 3916 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 3917 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL 3918 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL 3919 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 3920}; 3921 3922/* cq_res_ud_cfa (size:256b/32B) */ 3923struct cq_res_ud_cfa { 3924 __le16 length; 3925 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL 3926 #define CQ_RES_UD_CFA_LENGTH_SFT 0 3927 __le16 cfa_code; 3928 __le32 imm_data; 3929 __le32 qid; 3930 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL 3931 #define CQ_RES_UD_CFA_QID_SFT 0 3932 __le32 cfa_metadata; 3933 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL 3934 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 3935 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL 3936 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL 3937 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 3938 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL 3939 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 3940 __le16 src_mac[3]; 3941 __le16 src_qp_low; 3942 u8 cqe_type_toggle; 3943 #define CQ_RES_UD_CFA_TOGGLE 0x1UL 3944 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL 3945 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 3946 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 3947 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA 3948 u8 status; 3949 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL 3950 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3951 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3952 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3953 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3954 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3955 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3956 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL 3957 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 3958 __le16 flags; 3959 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL 3960 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL 3961 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL 3962 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 3963 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL 3964 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL 3965 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 3966 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL 3967 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 3968 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3969 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3970 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3971 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 3972 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL 3973 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 3974 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3975 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 3976 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3977 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3978 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3979 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET 3980 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 3981 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 3982 __le32 src_qp_high_srq_or_rq_wr_id; 3983 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3984 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 3985 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL 3986 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 3987}; 3988 3989/* cq_res_ud_cfa_v2 (size:256b/32B) */ 3990struct cq_res_ud_cfa_v2 { 3991 __le16 length; 3992 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL 3993 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 3994 __le16 cfa_metadata0; 3995 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL 3996 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 3997 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL 3998 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL 3999 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 4000 __le32 imm_data; 4001 __le32 qid; 4002 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL 4003 #define CQ_RES_UD_CFA_V2_QID_SFT 0 4004 __le32 cfa_metadata2; 4005 __le16 src_mac[3]; 4006 __le16 src_qp_low; 4007 u8 cqe_type_toggle; 4008 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL 4009 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL 4010 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 4011 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4012 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA 4013 u8 status; 4014 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL 4015 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4016 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4017 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4018 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4019 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4020 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4021 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL 4022 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 4023 __le16 flags; 4024 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL 4025 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL 4026 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL 4027 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 4028 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL 4029 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL 4030 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 4031 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4032 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 4033 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4034 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4035 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4036 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 4037 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4038 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 4039 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4040 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4041 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4042 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4043 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4044 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \ 4045 CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET 4046 __le32 src_qp_high_srq_or_rq_wr_id; 4047 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4048 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 4049 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL 4050 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 4051 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4052 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 4053 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4054 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4055 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4056 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4057 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4058 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4059 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \ 4060 CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4061 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL 4062 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL 4063 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 4064}; 4065 4066/* cq_res_raweth_qp1 (size:256b/32B) */ 4067struct cq_res_raweth_qp1 { 4068 __le16 length; 4069 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 4070 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 4071 __le16 raweth_qp1_flags; 4072 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4073 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 4074 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 4075 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4076 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4077 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4078 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4079 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4080 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4081 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4082 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4083 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4084 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4085 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4086 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4087 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4088 __le16 raweth_qp1_errors; 4089 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4090 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4091 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4092 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4093 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4094 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4095 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4096 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4097 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4098 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4099 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4100 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4101 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4102 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4103 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4104 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4105 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4106 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4107 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4108 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4109 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4110 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4111 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4112 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4113 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4114 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 4115 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 4116 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4117 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4118 __le16 raweth_qp1_cfa_code; 4119 __le64 qp_handle; 4120 __le32 raweth_qp1_flags2; 4121 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 4122 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 4123 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 4124 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 4125 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4126 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4127 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4128 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4) 4129 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4130 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4131 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4132 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4133 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4134 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4135 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4136 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL 4137 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 4138 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4139 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4140 __le32 raweth_qp1_metadata; 4141 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL 4142 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 4143 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 4144 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 4145 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 4146 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 4147 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 4148 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 4149 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 4150 u8 cqe_type_toggle; 4151 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 4152 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 4153 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 4154 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4155 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 4156 u8 status; 4157 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 4158 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4159 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4160 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4161 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4162 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4163 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4164 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 4165 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 4166 __le16 flags; 4167 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 4168 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 4169 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 4170 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 4171 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4172 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4173 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 4174 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4175 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4176}; 4177 4178/* cq_res_raweth_qp1_v2 (size:256b/32B) */ 4179struct cq_res_raweth_qp1_v2 { 4180 __le16 length; 4181 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL 4182 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 4183 __le16 raweth_qp1_flags; 4184 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4185 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 4186 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL 4187 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4188 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4189 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4190 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4191 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4192 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4193 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4194 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4195 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4196 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4197 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4198 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4199 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4200 __le16 raweth_qp1_errors; 4201 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4202 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4203 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4204 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4205 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4206 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4207 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4208 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4209 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4210 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4211 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4212 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4213 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4214 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4215 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4216 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4217 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4218 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4219 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4220 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4221 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4222 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4223 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4224 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4225 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4226 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ 4227 (0x7UL << 12) 4228 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 4229 (0x8UL << 12) 4230 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4231 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4232 __le16 cfa_metadata0; 4233 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL 4234 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 4235 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL 4236 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4237 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 4238 __le64 qp_handle; 4239 __le32 raweth_qp1_flags2; 4240 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL 4241 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4242 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4243 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4244 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 4245 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4246 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4247 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4248 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4249 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4250 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4251 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4252 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL 4253 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 4254 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4255 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4256 __le32 cfa_metadata2; 4257 u8 cqe_type_toggle; 4258 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL 4259 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL 4260 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 4261 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4262 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 4263 u8 status; 4264 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL 4265 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4266 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4267 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4268 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4269 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4270 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4271 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL 4272 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 4273 __le16 flags; 4274 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL 4275 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL 4276 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL 4277 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 4278 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4279 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4280 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 4281 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL 4282 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 4283 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4284 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 4285 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4286 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4287 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4288 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4289 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4290 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4291 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \ 4292 CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4293 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL 4294 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4295 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4296}; 4297 4298/* cq_terminal (size:256b/32B) */ 4299struct cq_terminal { 4300 __le64 qp_handle; 4301 __le16 sq_cons_idx; 4302 __le16 rq_cons_idx; 4303 __le32 reserved32_1; 4304 __le64 reserved64_3; 4305 u8 cqe_type_toggle; 4306 #define CQ_TERMINAL_TOGGLE 0x1UL 4307 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 4308 #define CQ_TERMINAL_CQE_TYPE_SFT 1 4309 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 4310 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL 4311 u8 status; 4312 #define CQ_TERMINAL_STATUS_OK 0x0UL 4313 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK 4314 __le16 reserved16; 4315 __le32 reserved32_2; 4316}; 4317 4318/* cq_cutoff (size:256b/32B) */ 4319struct cq_cutoff { 4320 __le64 reserved64_1; 4321 __le64 reserved64_2; 4322 __le64 reserved64_3; 4323 u8 cqe_type_toggle; 4324 #define CQ_CUTOFF_TOGGLE 0x1UL 4325 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 4326 #define CQ_CUTOFF_CQE_TYPE_SFT 1 4327 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 4328 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF 4329 u8 status; 4330 #define CQ_CUTOFF_STATUS_OK 0x0UL 4331 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK 4332 __le16 reserved16; 4333 __le32 reserved32; 4334}; 4335 4336/* nq_base (size:128b/16B) */ 4337struct nq_base { 4338 __le16 info10_type; 4339 #define NQ_BASE_TYPE_MASK 0x3fUL 4340 #define NQ_BASE_TYPE_SFT 0 4341 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 4342 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 4343 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 4344 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 4345 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 4346 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT 4347 #define NQ_BASE_INFO10_MASK 0xffc0UL 4348 #define NQ_BASE_INFO10_SFT 6 4349 __le16 info16; 4350 __le32 info32; 4351 __le32 info63_v[2]; 4352 #define NQ_BASE_V 0x1UL 4353 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 4354 #define NQ_BASE_INFO63_SFT 1 4355}; 4356 4357/* nq_cn (size:128b/16B) */ 4358struct nq_cn { 4359 __le16 type; 4360 #define NQ_CN_TYPE_MASK 0x3fUL 4361 #define NQ_CN_TYPE_SFT 0 4362 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 4363 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 4364 #define NQ_CN_TOGGLE_MASK 0xc0UL 4365 #define NQ_CN_TOGGLE_SFT 6 4366 __le16 reserved16; 4367 __le32 cq_handle_low; 4368 __le32 v; 4369 #define NQ_CN_V 0x1UL 4370 __le32 cq_handle_high; 4371}; 4372 4373/* nq_srq_event (size:128b/16B) */ 4374struct nq_srq_event { 4375 u8 type; 4376 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 4377 #define NQ_SRQ_EVENT_TYPE_SFT 0 4378 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 4379 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT 4380 u8 event; 4381 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 4382 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 4383 __le16 reserved16; 4384 __le32 srq_handle_low; 4385 __le32 v; 4386 #define NQ_SRQ_EVENT_V 0x1UL 4387 __le32 srq_handle_high; 4388}; 4389 4390/* nq_dbq_event (size:128b/16B) */ 4391struct nq_dbq_event { 4392 u8 type; 4393 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 4394 #define NQ_DBQ_EVENT_TYPE_SFT 0 4395 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 4396 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT 4397 u8 event; 4398 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 4399 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 4400 __le16 db_pfid; 4401 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 4402 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 4403 __le32 db_dpi; 4404 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 4405 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 4406 __le32 v; 4407 #define NQ_DBQ_EVENT_V 0x1UL 4408 __le32 db_type_db_xid; 4409 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 4410 #define NQ_DBQ_EVENT_DB_XID_SFT 0 4411 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 4412 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 4413}; 4414 4415/* xrrq_irrq (size:256b/32B) */ 4416struct xrrq_irrq { 4417 __le16 credits_type; 4418 #define XRRQ_IRRQ_TYPE 0x1UL 4419 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 4420 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 4421 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ 4422 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 4423 #define XRRQ_IRRQ_CREDITS_SFT 11 4424 __le16 reserved16; 4425 __le32 reserved32; 4426 __le32 psn; 4427 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 4428 #define XRRQ_IRRQ_PSN_SFT 0 4429 __le32 msn; 4430 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 4431 #define XRRQ_IRRQ_MSN_SFT 0 4432 __le64 va_or_atomic_result; 4433 __le32 rdma_r_key; 4434 __le32 length; 4435}; 4436 4437/* xrrq_orrq (size:256b/32B) */ 4438struct xrrq_orrq { 4439 __le16 num_sges_type; 4440 #define XRRQ_ORRQ_TYPE 0x1UL 4441 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 4442 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 4443 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ 4444 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 4445 #define XRRQ_ORRQ_NUM_SGES_SFT 11 4446 __le16 reserved16; 4447 __le32 length; 4448 __le32 psn; 4449 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 4450 #define XRRQ_ORRQ_PSN_SFT 0 4451 __le32 end_psn; 4452 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 4453 #define XRRQ_ORRQ_END_PSN_SFT 0 4454 __le64 first_sge_phy_or_sing_sge_va; 4455 __le32 single_sge_l_key; 4456 __le32 single_sge_size; 4457}; 4458 4459/* ptu_pte (size:64b/8B) */ 4460struct ptu_pte { 4461 __le32 page_next_to_last_last_valid[2]; 4462 #define PTU_PTE_VALID 0x1UL 4463 #define PTU_PTE_LAST 0x2UL 4464 #define PTU_PTE_NEXT_TO_LAST 0x4UL 4465 #define PTU_PTE_UNUSED_MASK 0xff8UL 4466 #define PTU_PTE_UNUSED_SFT 3 4467 #define PTU_PTE_PAGE_MASK 0xfffff000UL 4468 #define PTU_PTE_PAGE_SFT 12 4469}; 4470 4471/* ptu_pde (size:64b/8B) */ 4472struct ptu_pde { 4473 __le32 page_valid[2]; 4474 #define PTU_PDE_VALID 0x1UL 4475 #define PTU_PDE_UNUSED_MASK 0xffeUL 4476 #define PTU_PDE_UNUSED_SFT 1 4477 #define PTU_PDE_PAGE_MASK 0xfffff000UL 4478 #define PTU_PDE_PAGE_SFT 12 4479}; 4480 4481#endif /* ___BNXT_RE_HSI_H__ */ 4482