1/* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39#define dev_fmt(fmt) "QPLIB: " fmt 40 41#include <linux/interrupt.h> 42#include <linux/spinlock.h> 43#include <linux/sched.h> 44#include <linux/pci.h> 45 46#include "roce_hsi.h" 47 48#include "qplib_res.h" 49#include "qplib_rcfw.h" 50#include "qplib_sp.h" 51#include "qplib_tlv.h" 52 53const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56/* Device */ 57 58static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59{ 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67} 68 69static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 70 char *fw_ver) 71{ 72 struct creq_query_version_resp resp = {}; 73 struct bnxt_qplib_cmdqmsg msg = {}; 74 struct cmdq_query_version req = {}; 75 int rc; 76 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 78 CMDQ_BASE_OPCODE_QUERY_VERSION, 79 sizeof(req)); 80 81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 83 if (rc) 84 return; 85 fw_ver[0] = resp.fw_maj; 86 fw_ver[1] = resp.fw_minor; 87 fw_ver[2] = resp.fw_bld; 88 fw_ver[3] = resp.fw_rsvd; 89} 90 91int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 struct bnxt_qplib_dev_attr *attr) 93{ 94 struct creq_query_func_resp resp = {}; 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 struct creq_query_func_resp_sb *sb; 97 struct bnxt_qplib_rcfw_sbuf sbuf; 98 struct cmdq_query_func req = {}; 99 u8 *tqm_alloc; 100 int i, rc; 101 u32 temp; 102 103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 104 CMDQ_BASE_OPCODE_QUERY_FUNC, 105 sizeof(req)); 106 107 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 108 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 109 &sbuf.dma_addr, GFP_KERNEL); 110 if (!sbuf.sb) 111 return -ENOMEM; 112 sb = sbuf.sb; 113 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 114 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 115 sizeof(resp), 0); 116 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 117 if (rc) 118 goto bail; 119 120 /* Extract the context from the side buffer */ 121 attr->max_qp = le32_to_cpu(sb->max_qp); 122 /* max_qp value reported by FW doesn't include the QP1 */ 123 attr->max_qp += 1; 124 attr->max_qp_rd_atom = 125 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 126 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 127 attr->max_qp_init_rd_atom = 128 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 130 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 131 /* 132 * 128 WQEs needs to be reserved for the HW (8916). Prevent 133 * reporting the max number 134 */ 135 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 136 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx) ? 137 6 : sb->max_sge; 138 attr->max_cq = le32_to_cpu(sb->max_cq); 139 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 140 attr->max_cq_sges = attr->max_qp_sges; 141 attr->max_mr = le32_to_cpu(sb->max_mr); 142 attr->max_mw = le32_to_cpu(sb->max_mw); 143 144 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 145 attr->max_pd = 64 * 1024; 146 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 147 attr->max_ah = le32_to_cpu(sb->max_ah); 148 149 attr->max_srq = le16_to_cpu(sb->max_srq); 150 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 151 attr->max_srq_sges = sb->max_srq_sge; 152 attr->max_pkey = 1; 153 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 154 attr->l2_db_size = (sb->l2_db_space_size + 1) * 155 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 156 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 157 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 158 159 bnxt_qplib_query_version(rcfw, attr->fw_ver); 160 161 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 162 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 163 tqm_alloc = (u8 *)&temp; 164 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 165 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 166 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 167 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 168 } 169 170 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 171 attr->max_dpi = le32_to_cpu(sb->max_dpi); 172 173 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 174bail: 175 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 176 sbuf.sb, sbuf.dma_addr); 177 return rc; 178} 179 180int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 181 struct bnxt_qplib_rcfw *rcfw, 182 struct bnxt_qplib_ctx *ctx) 183{ 184 struct creq_set_func_resources_resp resp = {}; 185 struct cmdq_set_func_resources req = {}; 186 struct bnxt_qplib_cmdqmsg msg = {}; 187 int rc; 188 189 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 190 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 191 sizeof(req)); 192 193 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 194 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 195 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 196 req.number_of_cq = cpu_to_le32(ctx->cq_count); 197 198 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 199 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 200 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 201 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 202 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 203 204 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 205 sizeof(resp), 0); 206 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 207 if (rc) { 208 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 209 } 210 return rc; 211} 212 213/* SGID */ 214int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 215 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 216 struct bnxt_qplib_gid *gid) 217{ 218 if (index >= sgid_tbl->max) { 219 dev_err(&res->pdev->dev, 220 "Index %d exceeded SGID table max (%d)\n", 221 index, sgid_tbl->max); 222 return -EINVAL; 223 } 224 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 225 return 0; 226} 227 228int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 229 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 230{ 231 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 232 struct bnxt_qplib_res, 233 sgid_tbl); 234 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 235 int index; 236 237 /* Do we need a sgid_lock here? */ 238 if (!sgid_tbl->active) { 239 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 240 return -ENOMEM; 241 } 242 for (index = 0; index < sgid_tbl->max; index++) { 243 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 244 vlan_id == sgid_tbl->tbl[index].vlan_id) 245 break; 246 } 247 if (index == sgid_tbl->max) { 248 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 249 return 0; 250 } 251 /* Remove GID from the SGID table */ 252 if (update) { 253 struct creq_delete_gid_resp resp = {}; 254 struct bnxt_qplib_cmdqmsg msg = {}; 255 struct cmdq_delete_gid req = {}; 256 int rc; 257 258 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 259 CMDQ_BASE_OPCODE_DELETE_GID, 260 sizeof(req)); 261 if (sgid_tbl->hw_id[index] == 0xFFFF) { 262 dev_err(&res->pdev->dev, 263 "GID entry contains an invalid HW id\n"); 264 return -EINVAL; 265 } 266 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 267 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 268 sizeof(resp), 0); 269 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 270 if (rc) 271 return rc; 272 } 273 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 274 sizeof(bnxt_qplib_gid_zero)); 275 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 276 sgid_tbl->vlan[index] = 0; 277 sgid_tbl->active--; 278 dev_dbg(&res->pdev->dev, 279 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 280 index, sgid_tbl->hw_id[index], sgid_tbl->active); 281 sgid_tbl->hw_id[index] = (u16)-1; 282 283 /* unlock */ 284 return 0; 285} 286 287int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 288 struct bnxt_qplib_gid *gid, const u8 *smac, 289 u16 vlan_id, bool update, u32 *index) 290{ 291 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 292 struct bnxt_qplib_res, 293 sgid_tbl); 294 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 295 int i, free_idx; 296 297 /* Do we need a sgid_lock here? */ 298 if (sgid_tbl->active == sgid_tbl->max) { 299 dev_err(&res->pdev->dev, "SGID table is full\n"); 300 return -ENOMEM; 301 } 302 free_idx = sgid_tbl->max; 303 for (i = 0; i < sgid_tbl->max; i++) { 304 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 305 sgid_tbl->tbl[i].vlan_id == vlan_id) { 306 dev_dbg(&res->pdev->dev, 307 "SGID entry already exist in entry %d!\n", i); 308 *index = i; 309 return -EALREADY; 310 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 311 sizeof(bnxt_qplib_gid_zero)) && 312 free_idx == sgid_tbl->max) { 313 free_idx = i; 314 } 315 } 316 if (free_idx == sgid_tbl->max) { 317 dev_err(&res->pdev->dev, 318 "SGID table is FULL but count is not MAX??\n"); 319 return -ENOMEM; 320 } 321 if (update) { 322 struct creq_add_gid_resp resp = {}; 323 struct bnxt_qplib_cmdqmsg msg = {}; 324 struct cmdq_add_gid req = {}; 325 int rc; 326 327 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 328 CMDQ_BASE_OPCODE_ADD_GID, 329 sizeof(req)); 330 331 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 332 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 333 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 334 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 335 /* 336 * driver should ensure that all RoCE traffic is always VLAN 337 * tagged if RoCE traffic is running on non-zero VLAN ID or 338 * RoCE traffic is running on non-zero Priority. 339 */ 340 if ((vlan_id != 0xFFFF) || res->prio) { 341 if (vlan_id != 0xFFFF) 342 req.vlan = cpu_to_le16 343 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 344 req.vlan |= cpu_to_le16 345 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 346 CMDQ_ADD_GID_VLAN_VLAN_EN); 347 } 348 349 /* MAC in network format */ 350 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 351 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 352 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 353 354 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 355 sizeof(resp), 0); 356 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 357 if (rc) 358 return rc; 359 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 360 } 361 /* Add GID to the sgid_tbl */ 362 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 363 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 364 sgid_tbl->active++; 365 if (vlan_id != 0xFFFF) 366 sgid_tbl->vlan[free_idx] = 1; 367 368 dev_dbg(&res->pdev->dev, 369 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 370 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 371 372 *index = free_idx; 373 /* unlock */ 374 return 0; 375} 376 377int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 378 struct bnxt_qplib_gid *gid, u16 gid_idx, 379 const u8 *smac) 380{ 381 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 382 struct bnxt_qplib_res, 383 sgid_tbl); 384 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 385 struct creq_modify_gid_resp resp = {}; 386 struct bnxt_qplib_cmdqmsg msg = {}; 387 struct cmdq_modify_gid req = {}; 388 int rc; 389 390 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 391 CMDQ_BASE_OPCODE_MODIFY_GID, 392 sizeof(req)); 393 394 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 395 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 396 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 397 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 398 if (res->prio) { 399 req.vlan |= cpu_to_le16 400 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 401 CMDQ_ADD_GID_VLAN_VLAN_EN); 402 } 403 404 /* MAC in network format */ 405 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 406 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 407 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 408 409 req.gid_index = cpu_to_le16(gid_idx); 410 411 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 412 sizeof(resp), 0); 413 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 414 return rc; 415} 416 417/* AH */ 418int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 419 bool block) 420{ 421 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 422 struct creq_create_ah_resp resp = {}; 423 struct bnxt_qplib_cmdqmsg msg = {}; 424 struct cmdq_create_ah req = {}; 425 u32 temp32[4]; 426 u16 temp16[3]; 427 int rc; 428 429 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 430 CMDQ_BASE_OPCODE_CREATE_AH, 431 sizeof(req)); 432 433 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 434 req.dgid[0] = cpu_to_le32(temp32[0]); 435 req.dgid[1] = cpu_to_le32(temp32[1]); 436 req.dgid[2] = cpu_to_le32(temp32[2]); 437 req.dgid[3] = cpu_to_le32(temp32[3]); 438 439 req.type = ah->nw_type; 440 req.hop_limit = ah->hop_limit; 441 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 442 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 443 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 444 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 445 req.pd_id = cpu_to_le32(ah->pd->id); 446 req.traffic_class = ah->traffic_class; 447 448 /* MAC in network format */ 449 memcpy(temp16, ah->dmac, 6); 450 req.dest_mac[0] = cpu_to_le16(temp16[0]); 451 req.dest_mac[1] = cpu_to_le16(temp16[1]); 452 req.dest_mac[2] = cpu_to_le16(temp16[2]); 453 454 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 455 sizeof(resp), block); 456 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 457 if (rc) 458 return rc; 459 460 ah->id = le32_to_cpu(resp.xid); 461 return 0; 462} 463 464int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 465 bool block) 466{ 467 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 468 struct creq_destroy_ah_resp resp = {}; 469 struct bnxt_qplib_cmdqmsg msg = {}; 470 struct cmdq_destroy_ah req = {}; 471 int rc; 472 473 /* Clean up the AH table in the device */ 474 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 475 CMDQ_BASE_OPCODE_DESTROY_AH, 476 sizeof(req)); 477 478 req.ah_cid = cpu_to_le32(ah->id); 479 480 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 481 sizeof(resp), block); 482 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 483 return rc; 484} 485 486/* MRW */ 487int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 488{ 489 struct creq_deallocate_key_resp resp = {}; 490 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 491 struct cmdq_deallocate_key req = {}; 492 struct bnxt_qplib_cmdqmsg msg = {}; 493 int rc; 494 495 if (mrw->lkey == 0xFFFFFFFF) { 496 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 497 return 0; 498 } 499 500 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 501 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 502 sizeof(req)); 503 504 req.mrw_flags = mrw->type; 505 506 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 507 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 508 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 509 req.key = cpu_to_le32(mrw->rkey); 510 else 511 req.key = cpu_to_le32(mrw->lkey); 512 513 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 514 sizeof(resp), 0); 515 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 516 if (rc) 517 return rc; 518 519 /* Free the qplib's MRW memory */ 520 if (mrw->hwq.max_elements) 521 bnxt_qplib_free_hwq(res, &mrw->hwq); 522 523 return 0; 524} 525 526int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 527{ 528 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 529 struct creq_allocate_mrw_resp resp = {}; 530 struct bnxt_qplib_cmdqmsg msg = {}; 531 struct cmdq_allocate_mrw req = {}; 532 unsigned long tmp; 533 int rc; 534 535 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 536 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 537 sizeof(req)); 538 539 req.pd_id = cpu_to_le32(mrw->pd->id); 540 req.mrw_flags = mrw->type; 541 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 542 mrw->flags & BNXT_QPLIB_FR_PMR) || 543 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 544 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 545 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 546 tmp = (unsigned long)mrw; 547 req.mrw_handle = cpu_to_le64(tmp); 548 549 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 550 sizeof(resp), 0); 551 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 552 if (rc) 553 return rc; 554 555 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 556 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 557 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 558 mrw->rkey = le32_to_cpu(resp.xid); 559 else 560 mrw->lkey = le32_to_cpu(resp.xid); 561 return 0; 562} 563 564int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 565 bool block) 566{ 567 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 568 struct creq_deregister_mr_resp resp = {}; 569 struct bnxt_qplib_cmdqmsg msg = {}; 570 struct cmdq_deregister_mr req = {}; 571 int rc; 572 573 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 574 CMDQ_BASE_OPCODE_DEREGISTER_MR, 575 sizeof(req)); 576 577 req.lkey = cpu_to_le32(mrw->lkey); 578 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 579 sizeof(resp), block); 580 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 581 if (rc) 582 return rc; 583 584 /* Free the qplib's MR memory */ 585 if (mrw->hwq.max_elements) { 586 mrw->va = 0; 587 mrw->total_size = 0; 588 bnxt_qplib_free_hwq(res, &mrw->hwq); 589 } 590 591 return 0; 592} 593 594int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 595 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 596{ 597 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 598 struct bnxt_qplib_hwq_attr hwq_attr = {}; 599 struct bnxt_qplib_sg_info sginfo = {}; 600 struct creq_register_mr_resp resp = {}; 601 struct bnxt_qplib_cmdqmsg msg = {}; 602 struct cmdq_register_mr req = {}; 603 int pages, rc; 604 u32 pg_size; 605 u16 level; 606 607 if (num_pbls) { 608 pages = roundup_pow_of_two(num_pbls); 609 /* Allocate memory for the non-leaf pages to store buf ptrs. 610 * Non-leaf pages always uses system PAGE_SIZE 611 */ 612 /* Free the hwq if it already exist, must be a rereg */ 613 if (mr->hwq.max_elements) 614 bnxt_qplib_free_hwq(res, &mr->hwq); 615 hwq_attr.res = res; 616 hwq_attr.depth = pages; 617 hwq_attr.stride = sizeof(dma_addr_t); 618 hwq_attr.type = HWQ_TYPE_MR; 619 hwq_attr.sginfo = &sginfo; 620 hwq_attr.sginfo->umem = umem; 621 hwq_attr.sginfo->npages = pages; 622 hwq_attr.sginfo->pgsize = buf_pg_size; 623 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 624 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 625 if (rc) { 626 dev_err(&res->pdev->dev, 627 "SP: Reg MR memory allocation failed\n"); 628 return -ENOMEM; 629 } 630 } 631 632 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 633 CMDQ_BASE_OPCODE_REGISTER_MR, 634 sizeof(req)); 635 636 /* Configure the request */ 637 if (mr->hwq.level == PBL_LVL_MAX) { 638 /* No PBL provided, just use system PAGE_SIZE */ 639 level = 0; 640 req.pbl = 0; 641 pg_size = PAGE_SIZE; 642 } else { 643 level = mr->hwq.level; 644 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 645 } 646 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 647 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 648 ((ilog2(pg_size) << 649 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 650 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 651 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 652 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 653 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 654 req.access = (mr->flags & 0xFFFF); 655 req.va = cpu_to_le64(mr->va); 656 req.key = cpu_to_le32(mr->lkey); 657 req.mr_size = cpu_to_le64(mr->total_size); 658 659 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 660 sizeof(resp), 0); 661 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 662 if (rc) 663 goto fail; 664 665 return 0; 666 667fail: 668 if (mr->hwq.max_elements) 669 bnxt_qplib_free_hwq(res, &mr->hwq); 670 return rc; 671} 672 673int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 674 struct bnxt_qplib_frpl *frpl, 675 int max_pg_ptrs) 676{ 677 struct bnxt_qplib_hwq_attr hwq_attr = {}; 678 struct bnxt_qplib_sg_info sginfo = {}; 679 int pg_ptrs, pages, rc; 680 681 /* Re-calculate the max to fit the HWQ allocation model */ 682 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 683 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 684 if (!pages) 685 pages++; 686 687 if (pages > MAX_PBL_LVL_1_PGS) 688 return -ENOMEM; 689 690 sginfo.pgsize = PAGE_SIZE; 691 sginfo.nopte = true; 692 693 hwq_attr.res = res; 694 hwq_attr.depth = pg_ptrs; 695 hwq_attr.stride = PAGE_SIZE; 696 hwq_attr.sginfo = &sginfo; 697 hwq_attr.type = HWQ_TYPE_CTX; 698 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 699 if (!rc) 700 frpl->max_pg_ptrs = pg_ptrs; 701 702 return rc; 703} 704 705int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 706 struct bnxt_qplib_frpl *frpl) 707{ 708 bnxt_qplib_free_hwq(res, &frpl->hwq); 709 return 0; 710} 711 712int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 713 struct bnxt_qplib_roce_stats *stats) 714{ 715 struct creq_query_roce_stats_resp resp = {}; 716 struct creq_query_roce_stats_resp_sb *sb; 717 struct cmdq_query_roce_stats req = {}; 718 struct bnxt_qplib_cmdqmsg msg = {}; 719 struct bnxt_qplib_rcfw_sbuf sbuf; 720 int rc; 721 722 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 723 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 724 sizeof(req)); 725 726 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 727 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 728 &sbuf.dma_addr, GFP_KERNEL); 729 if (!sbuf.sb) 730 return -ENOMEM; 731 sb = sbuf.sb; 732 733 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 734 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 735 sizeof(resp), 0); 736 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 737 if (rc) 738 goto bail; 739 /* Extract the context from the side buffer */ 740 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 741 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 742 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 743 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 744 stats->missing_resp = le64_to_cpu(sb->missing_resp); 745 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 746 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 747 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 748 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 749 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 750 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 751 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 752 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 753 stats->dup_req = le64_to_cpu(sb->dup_req); 754 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 755 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 756 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 757 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 758 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 759 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 760 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 761 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 762 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 763 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 764 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 765 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 766 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 767 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 768 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 769 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 770 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 771 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 772 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 773 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 774 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 775 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 776 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 777 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 778 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 779 if (!rcfw->init_oos_stats) { 780 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 781 rcfw->init_oos_stats = 1; 782 } else { 783 stats->res_oos_drop_count += 784 (le64_to_cpu(sb->res_oos_drop_count) - 785 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 786 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 787 } 788 789bail: 790 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 791 sbuf.sb, sbuf.dma_addr); 792 return rc; 793} 794 795int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 796 struct bnxt_qplib_ext_stat *estat) 797{ 798 struct creq_query_roce_stats_ext_resp resp = {}; 799 struct creq_query_roce_stats_ext_resp_sb *sb; 800 struct cmdq_query_roce_stats_ext req = {}; 801 struct bnxt_qplib_cmdqmsg msg = {}; 802 struct bnxt_qplib_rcfw_sbuf sbuf; 803 int rc; 804 805 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 806 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 807 &sbuf.dma_addr, GFP_KERNEL); 808 if (!sbuf.sb) 809 return -ENOMEM; 810 811 sb = sbuf.sb; 812 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 813 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 814 sizeof(req)); 815 816 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 817 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 818 req.function_id = cpu_to_le32(fid); 819 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 820 821 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 822 sizeof(resp), 0); 823 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 824 if (rc) 825 goto bail; 826 827 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 828 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 829 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 830 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 831 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 832 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 833 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 834 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 835 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 836 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 837 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 838 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 839 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 840 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 841 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 842 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 843 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 844 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 845 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 846 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 847 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 848 849bail: 850 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 851 sbuf.sb, sbuf.dma_addr); 852 return rc; 853} 854 855static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 856 struct bnxt_qplib_cc_param_ext *cc_ext) 857{ 858 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 859 cc_ext->ext_mask = 0; 860 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 861 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 862 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 863 ext_req->tr_update_mode = cc_ext->tr_update_mode; 864 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 865 ext_req->fr_num_rtts = cc_ext->fr_rtt; 866 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 867 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 868 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 869 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 870 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 871 ext_req->actual_cr_factor = cc_ext->cr_factor; 872 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 873 ext_req->cp_bias_en = cc_ext->cp_bias_en; 874 ext_req->cp_bias = cc_ext->cp_bias; 875 ext_req->cnp_ecn = cc_ext->cnp_ecn; 876 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 877 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 878 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 879 ext_req->cr_width = cc_ext->cr_width; 880 ext_req->quota_period_min = cc_ext->min_quota; 881 ext_req->quota_period_max = cc_ext->max_quota; 882 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 883 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 884 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 885 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 886 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 887 ext_req->red_div = cc_ext->red_div; 888 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 889 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 890 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 891 ext_req->use_rate_table = cc_ext->low_rate_en; 892 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 893 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 894 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 895 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 896 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 897 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 898 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 899 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 900} 901 902int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 903 struct bnxt_qplib_cc_param *cc_param) 904{ 905 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 906 struct creq_modify_roce_cc_resp resp = {}; 907 struct bnxt_qplib_cmdqmsg msg = {}; 908 struct cmdq_modify_roce_cc *req; 909 int req_size; 910 void *cmd; 911 int rc; 912 913 /* Prepare the older base command */ 914 req = &tlv_req.base_req; 915 cmd = req; 916 req_size = sizeof(*req); 917 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 918 sizeof(*req)); 919 req->modify_mask = cpu_to_le32(cc_param->mask); 920 req->enable_cc = cc_param->enable; 921 req->g = cc_param->g; 922 req->num_phases_per_state = cc_param->nph_per_state; 923 req->time_per_phase = cc_param->time_pph; 924 req->pkts_per_phase = cc_param->pkts_pph; 925 req->init_cr = cpu_to_le16(cc_param->init_cr); 926 req->init_tr = cpu_to_le16(cc_param->init_tr); 927 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 928 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 929 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 930 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 931 req->rtt = cpu_to_le16(cc_param->rtt); 932 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 933 req->cc_mode = cc_param->cc_mode; 934 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 935 936 /* For chip gen P5 onwards fill extended cmd and header */ 937 if (bnxt_qplib_is_chip_gen_p5(res->cctx)) { 938 struct roce_tlv *hdr; 939 u32 payload; 940 u32 chunks; 941 942 cmd = &tlv_req; 943 req_size = sizeof(tlv_req); 944 /* Prepare primary tlv header */ 945 hdr = &tlv_req.tlv_hdr; 946 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 947 payload = sizeof(struct cmdq_modify_roce_cc); 948 __roce_1st_tlv_prep(hdr, chunks, payload, true); 949 /* Prepare secondary tlv header */ 950 hdr = (struct roce_tlv *)&tlv_req.ext_req; 951 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 952 sizeof(struct roce_tlv); 953 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 954 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 955 } 956 957 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 958 sizeof(resp), 0); 959 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 960 return rc; 961} 962