1/*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses.  You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in
21 *    the documentation and/or other materials provided with the
22 *    distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: QPLib resource manager (header)
37 */
38
39#ifndef __BNXT_QPLIB_RES_H__
40#define __BNXT_QPLIB_RES_H__
41
42extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
43
44#define CHIP_NUM_57508		0x1750
45#define CHIP_NUM_57504		0x1751
46#define CHIP_NUM_57502		0x1752
47
48struct bnxt_qplib_drv_modes {
49	u8	wqe_mode;
50	bool db_push;
51	bool dbr_pacing;
52};
53
54struct bnxt_qplib_chip_ctx {
55	u16	chip_num;
56	u8	chip_rev;
57	u8	chip_metal;
58	u16	hw_stats_size;
59	u16	hwrm_cmd_max_timeout;
60	struct bnxt_qplib_drv_modes modes;
61	u64	hwrm_intf_ver;
62	u32     dbr_stat_db_fifo;
63};
64
65struct bnxt_qplib_db_pacing_data {
66	u32 do_pacing;
67	u32 pacing_th;
68	u32 alarm_th;
69	u32 fifo_max_depth;
70	u32 fifo_room_mask;
71	u32 fifo_room_shift;
72	u32 grc_reg_offset;
73};
74
75#define BNXT_QPLIB_DBR_PF_DB_OFFSET     0x10000
76#define BNXT_QPLIB_DBR_VF_DB_OFFSET     0x4000
77
78#define PTR_CNT_PER_PG		(PAGE_SIZE / sizeof(void *))
79#define PTR_MAX_IDX_PER_PG	(PTR_CNT_PER_PG - 1)
80#define PTR_PG(x)		(((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
81#define PTR_IDX(x)		((x) & PTR_MAX_IDX_PER_PG)
82
83#define HWQ_CMP(idx, hwq)	((idx) & ((hwq)->max_elements - 1))
84
85#define HWQ_FREE_SLOTS(hwq)	(hwq->max_elements - \
86				((HWQ_CMP(hwq->prod, hwq)\
87				- HWQ_CMP(hwq->cons, hwq))\
88				& (hwq->max_elements - 1)))
89enum bnxt_qplib_hwq_type {
90	HWQ_TYPE_CTX,
91	HWQ_TYPE_QUEUE,
92	HWQ_TYPE_L2_CMPL,
93	HWQ_TYPE_MR
94};
95
96#define MAX_PBL_LVL_0_PGS		1
97#define MAX_PBL_LVL_1_PGS		512
98#define MAX_PBL_LVL_1_PGS_SHIFT		9
99#define MAX_PBL_LVL_1_PGS_FOR_LVL_2	256
100#define MAX_PBL_LVL_2_PGS		(256 * 512)
101#define MAX_PDL_LVL_SHIFT               9
102
103enum bnxt_qplib_pbl_lvl {
104	PBL_LVL_0,
105	PBL_LVL_1,
106	PBL_LVL_2,
107	PBL_LVL_MAX
108};
109
110#define ROCE_PG_SIZE_4K		(4 * 1024)
111#define ROCE_PG_SIZE_8K		(8 * 1024)
112#define ROCE_PG_SIZE_64K	(64 * 1024)
113#define ROCE_PG_SIZE_2M		(2 * 1024 * 1024)
114#define ROCE_PG_SIZE_8M		(8 * 1024 * 1024)
115#define ROCE_PG_SIZE_1G		(1024 * 1024 * 1024)
116
117enum bnxt_qplib_hwrm_pg_size {
118	BNXT_QPLIB_HWRM_PG_SIZE_4K	= 0,
119	BNXT_QPLIB_HWRM_PG_SIZE_8K	= 1,
120	BNXT_QPLIB_HWRM_PG_SIZE_64K	= 2,
121	BNXT_QPLIB_HWRM_PG_SIZE_2M	= 3,
122	BNXT_QPLIB_HWRM_PG_SIZE_8M	= 4,
123	BNXT_QPLIB_HWRM_PG_SIZE_1G	= 5,
124};
125
126struct bnxt_qplib_reg_desc {
127	u8		bar_id;
128	resource_size_t	bar_base;
129	unsigned long	offset;
130	void __iomem	*bar_reg;
131	size_t		len;
132};
133
134struct bnxt_qplib_pbl {
135	u32				pg_count;
136	u32				pg_size;
137	void				**pg_arr;
138	dma_addr_t			*pg_map_arr;
139};
140
141struct bnxt_qplib_sg_info {
142	struct ib_umem			*umem;
143	u32				npages;
144	u32				pgshft;
145	u32				pgsize;
146	bool				nopte;
147};
148
149struct bnxt_qplib_hwq_attr {
150	struct bnxt_qplib_res		*res;
151	struct bnxt_qplib_sg_info	*sginfo;
152	enum bnxt_qplib_hwq_type	type;
153	u32				depth;
154	u32				stride;
155	u32				aux_stride;
156	u32				aux_depth;
157};
158
159struct bnxt_qplib_hwq {
160	struct pci_dev			*pdev;
161	/* lock to protect qplib_hwq */
162	spinlock_t			lock;
163	struct bnxt_qplib_pbl		pbl[PBL_LVL_MAX + 1];
164	enum bnxt_qplib_pbl_lvl		level;		/* 0, 1, or 2 */
165	/* ptr for easy access to the PBL entries */
166	void				**pbl_ptr;
167	/* ptr for easy access to the dma_addr */
168	dma_addr_t			*pbl_dma_ptr;
169	u32				max_elements;
170	u32				depth;
171	u16				element_size;	/* Size of each entry */
172	u16				qe_ppg;	/* queue entry per page */
173
174	u32				prod;		/* raw */
175	u32				cons;		/* raw */
176	u8				cp_bit;
177	u8				is_user;
178	u64				*pad_pg;
179	u32				pad_stride;
180	u32				pad_pgofft;
181};
182
183struct bnxt_qplib_db_info {
184	void __iomem		*db;
185	void __iomem		*priv_db;
186	struct bnxt_qplib_hwq	*hwq;
187	u32			xid;
188	u32			max_slot;
189};
190
191/* Tables */
192struct bnxt_qplib_pd_tbl {
193	unsigned long			*tbl;
194	u32				max;
195};
196
197struct bnxt_qplib_sgid_tbl {
198	struct bnxt_qplib_gid_info	*tbl;
199	u16				*hw_id;
200	u16				max;
201	u16				active;
202	void				*ctx;
203	u8				*vlan;
204};
205
206enum {
207	BNXT_QPLIB_DPI_TYPE_KERNEL      = 0,
208	BNXT_QPLIB_DPI_TYPE_UC          = 1,
209	BNXT_QPLIB_DPI_TYPE_WC          = 2
210};
211
212struct bnxt_qplib_dpi {
213	u32				dpi;
214	u32				bit;
215	void __iomem			*dbr;
216	u64				umdbr;
217	u8				type;
218};
219
220struct bnxt_qplib_dpi_tbl {
221	void				**app_tbl;
222	unsigned long			*tbl;
223	u16				max;
224	struct bnxt_qplib_reg_desc	ucreg; /* Hold entire DB bar. */
225	struct bnxt_qplib_reg_desc	wcreg;
226	void __iomem			*priv_db;
227};
228
229struct bnxt_qplib_stats {
230	dma_addr_t			dma_map;
231	void				*dma;
232	u32				size;
233	u32				fw_id;
234};
235
236struct bnxt_qplib_vf_res {
237	u32 max_qp_per_vf;
238	u32 max_mrw_per_vf;
239	u32 max_srq_per_vf;
240	u32 max_cq_per_vf;
241	u32 max_gid_per_vf;
242};
243
244#define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE	448
245#define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE	64
246#define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE	64
247#define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE	128
248
249#define MAX_TQM_ALLOC_REQ               48
250#define MAX_TQM_ALLOC_BLK_SIZE          8
251struct bnxt_qplib_tqm_ctx {
252	struct bnxt_qplib_hwq           pde;
253	u8                              pde_level; /* Original level */
254	struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
255	u8                              qcount[MAX_TQM_ALLOC_REQ];
256};
257
258struct bnxt_qplib_ctx {
259	u32				qpc_count;
260	struct bnxt_qplib_hwq		qpc_tbl;
261	u32				mrw_count;
262	struct bnxt_qplib_hwq		mrw_tbl;
263	u32				srqc_count;
264	struct bnxt_qplib_hwq		srqc_tbl;
265	u32				cq_count;
266	struct bnxt_qplib_hwq		cq_tbl;
267	struct bnxt_qplib_hwq		tim_tbl;
268	struct bnxt_qplib_tqm_ctx	tqm_ctx;
269	struct bnxt_qplib_stats		stats;
270	struct bnxt_qplib_vf_res	vf_res;
271};
272
273struct bnxt_qplib_res {
274	struct pci_dev			*pdev;
275	struct bnxt_qplib_chip_ctx	*cctx;
276	struct bnxt_qplib_dev_attr      *dattr;
277	struct net_device		*netdev;
278	struct bnxt_qplib_rcfw		*rcfw;
279	struct bnxt_qplib_pd_tbl	pd_tbl;
280	/* To protect the pd table bit map */
281	struct mutex			pd_tbl_lock;
282	struct bnxt_qplib_sgid_tbl	sgid_tbl;
283	struct bnxt_qplib_dpi_tbl	dpi_tbl;
284	/* To protect the dpi table bit map */
285	struct mutex                    dpi_tbl_lock;
286	bool				prio;
287	bool                            is_vf;
288	struct bnxt_qplib_db_pacing_data *pacing_data;
289};
290
291static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
292{
293	return (cctx->chip_num == CHIP_NUM_57508 ||
294		cctx->chip_num == CHIP_NUM_57504 ||
295		cctx->chip_num == CHIP_NUM_57502);
296}
297
298static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
299{
300	return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
301					HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
302}
303
304static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
305{
306	return bnxt_qplib_is_chip_gen_p5(cctx) ?
307	       RING_ALLOC_REQ_RING_TYPE_NQ :
308	       RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
309}
310
311static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
312{
313	u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
314	struct bnxt_qplib_pbl *pbl;
315
316	pbl = &hwq->pbl[PBL_LVL_0];
317	switch (pbl->pg_size) {
318	case ROCE_PG_SIZE_4K:
319		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
320		break;
321	case ROCE_PG_SIZE_8K:
322		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
323		break;
324	case ROCE_PG_SIZE_64K:
325		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
326		break;
327	case ROCE_PG_SIZE_2M:
328		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
329		break;
330	case ROCE_PG_SIZE_8M:
331		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
332		break;
333	case ROCE_PG_SIZE_1G:
334		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
335		break;
336	default:
337		break;
338	}
339
340	return pg_size;
341}
342
343static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
344				      u32 indx, u64 *pg)
345{
346	u32 pg_num, pg_idx;
347
348	pg_num = (indx / hwq->qe_ppg);
349	pg_idx = (indx % hwq->qe_ppg);
350	if (pg)
351		*pg = (u64)&hwq->pbl_ptr[pg_num];
352	return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
353}
354
355static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
356{
357	idx += hwq->prod;
358	if (idx >= hwq->depth)
359		idx -= hwq->depth;
360	return bnxt_qplib_get_qe(hwq, idx, NULL);
361}
362
363#define to_bnxt_qplib(ptr, type, member)	\
364	container_of(ptr, type, member)
365
366struct bnxt_qplib_pd;
367struct bnxt_qplib_dev_attr;
368
369void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
370			 struct bnxt_qplib_hwq *hwq);
371int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
372			      struct bnxt_qplib_hwq_attr *hwq_attr);
373int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res,
374			struct bnxt_qplib_pd *pd);
375int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
376			  struct bnxt_qplib_pd_tbl *pd_tbl,
377			  struct bnxt_qplib_pd *pd);
378int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res,
379			 struct bnxt_qplib_dpi *dpi,
380			 void *app, u8 type);
381int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
382			   struct bnxt_qplib_dpi *dpi);
383void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
384int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
385void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
386int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
387			 struct net_device *netdev,
388			 struct bnxt_qplib_dev_attr *dev_attr);
389void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
390			 struct bnxt_qplib_ctx *ctx);
391int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
392			 struct bnxt_qplib_ctx *ctx,
393			 bool virt_fn, bool is_p5);
394int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res);
395void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res);
396
397int bnxt_qplib_determine_atomics(struct pci_dev *dev);
398
399static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
400{
401	hwq->prod = (hwq->prod + cnt) % hwq->depth;
402}
403
404static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
405					    u32 cnt)
406{
407	hwq->cons = (hwq->cons + cnt) % hwq->depth;
408}
409
410static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
411					bool arm)
412{
413	u32 key;
414
415	key = info->hwq->cons & (info->hwq->max_elements - 1);
416	key |= (CMPL_DOORBELL_IDX_VALID |
417		(CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
418	if (!arm)
419		key |= CMPL_DOORBELL_MASK;
420	writel(key, info->db);
421}
422
423static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
424				      u32 type)
425{
426	u64 key = 0;
427
428	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
429	key <<= 32;
430	key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
431		DBC_DBC_INDEX_MASK;
432	writeq(key, info->db);
433}
434
435static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
436					   u32 type)
437{
438	u64 key = 0;
439
440	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
441	key <<= 32;
442	key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
443	writeq(key, info->db);
444}
445
446static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
447				       u32 type)
448{
449	u64 key = 0;
450
451	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
452	key <<= 32;
453	writeq(key, info->priv_db);
454}
455
456static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
457					 u32 th)
458{
459	u64 key = 0;
460
461	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
462	key <<= 32;
463	key |=  th & DBC_DBC_INDEX_MASK;
464	writeq(key, info->priv_db);
465}
466
467static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
468					 struct bnxt_qplib_chip_ctx *cctx,
469					 bool arm)
470{
471	u32 type;
472
473	type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
474	if (bnxt_qplib_is_chip_gen_p5(cctx))
475		bnxt_qplib_ring_db(info, type);
476	else
477		bnxt_qplib_ring_db32(info, arm);
478}
479
480static inline bool _is_ext_stats_supported(u16 dev_cap_flags)
481{
482	return dev_cap_flags &
483		CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;
484}
485
486static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx)
487{
488	return cctx->modes.dbr_pacing;
489}
490
491#endif /* __BNXT_QPLIB_RES_H__ */
492